A data storage processing method and apparatus for iterative decoders

Abstract

This invention provides a data storage processing method and apparatus for an iterative decoder. The method includes a cache memory for receiving and caching data to be decoded, and an arithmetic memory for participating in intermediate calculations of the decoding arithmetic logic unit and caching related data. A data path is provided between the two memories for writing the data to be decoded stored in the cache memory into the arithmetic memory. Decoding begins after the arithmetic memory receives data of a code length. When the decoding is completed or the maximum number of iterations is reached, the data cached in the cache memory is written in parallel into the arithmetic memory for subsequent decoding operations. Using the technical solution provided by this invention, storage space can be saved, more data to be decoded can be cached, the storage structure is simple and easily expandable, and the data processing efficiency is no less than that of a ping-pong storage structure.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, and particularly relates to a data storage processing method and apparatus for an iterative decoder. Background Technology

[0002] Codecs and decoders are essential components of communication systems. In ASIC implementations, due to efficiency and area considerations, decoders typically employ iterative decoding, often using a core decoding arithmetic logic unit with a ping-pong memory structure. Common iterative decoder architectures and their processing flows are as follows: Figure 1 As shown. The steps of a common iterative decoder processing flow are as follows:

[0003] a) During initialization, the reference signals in_end, flag, dec_busy, and dec_suc_flag of the ping-pong control logic are all 0. The ping-pong control logic uses flag to determine which RAM to fill with the data to be decoded. When a RAM is filled with one code length of data, in_end is set to 1, indicating that the RAM is full of one code length of data; flag = ! flag, indicating that subsequent data needs to be filled into another ping-pong RAM.

[0004] b) When the core decoding arithmetic logic unit sees the in_end instruction, it starts iterative decoding, reads data from the corresponding RAM, and sets dec_busy=1, indicating that the core decoder is in a busy state.

[0005] c) The core decoding arithmetic logic unit writes the intermediate decoding results into the corresponding RAM, which is the RAM that was previously filled with data of one code length to be decoded. This is managed by the ping-pong control logic.

[0006] e) After each iteration, the core decoding arithmetic logic unit sends the decision condition to the iteration termination decision unit.

[0007] f) The iteration termination decision unit notifies the core decoding arithmetic logic unit of the decision result. If the decision passes, dec_suc_flag = 1, indicating that the decoding is successful. The core decoding arithmetic logic unit stops decoding after completing this decoding. Otherwise, it continues decoding until the preset maximum number of iterations is reached. At this time, dec_busy = 0 is set to indicate that the core decoder is in an idle state.

[0008] g) At the end of this iteration, the decoding result is written to RAM2; the decoding result after receiving the message dec_suc_flag=1 will not be written to RAM2 to avoid introducing error information through additional iterations.

[0009] h)dec_suc_flag = 1 and after the current iteration ends or the maximum number of iterations is reached, dec_sel = !dec_sel, and the decoding result is output.

[0010] Figure 1 The primary purpose of using ping-pong RAM is to buffer the second code block to be decoded during the iterative decoding process of the core decoding arithmetic logic unit. Therefore, the size of both RAMs is designed to accommodate the longest code block. Furthermore, the structure of ping-pong RAM dictates that, regardless of the code length, only two code blocks can be buffered at a time. In OFDMA systems, the receiver needs to process data from multiple subbands simultaneously. In this case, the decoding unit often encounters situations where it needs to process more than two code blocks of data to be decoded during iterative decoding. Following this structure would require expanding the ping-pong structure to three RAMs. However, this expansion introduces problems such as increased area, control complexity, and deterioration of RAM interface timing. Furthermore, the core decoding arithmetic logic unit uses signed number operations. In ASIC implementations, a three-sign-bit approach is generally used (for overflow or underflow detection). For example, [-31, 31] can be represented by only one sign bit and five value bits. However, in a three-sign-bit system, the sign bit needs to be copied three times to become three sign bits and five value bits, for a total of eight bits (assuming the highest bit is S and the second highest bit is C, then calculate S^C. When the result is 1, it indicates that an overflow has occurred; S is 1, indicating the maximum negative value; S is 0, indicating the maximum positive value; when the result is 0, it indicates that there is no overflow). Thus, the bit width of the ping-pong RAM is a multiple of eight bits.

[0011] In existing wireless communication protocols, the main parameters of LDPC are code length (N), code rate (R), and cyclic submatrix size (T). The correspondence between the three is shown in Table 1 below.

[0012] Table 1 LDPC coding parameters in existing wireless communication systems

[0013] Code length (N) Bitrate (R) Size of the cyclic submatrix (T) 5376 1 / 2,5 / 8,3 / 4，7 / 8 112 2688 1 / 2,5 / 8,3 / 4，5 / 6 112 1344 1 / 2,5 / 8,3 / 4 56 1344 7 / 8 42 448 1 / 2 28 448 4 / 7 32

[0014] In the classic LDPC decoder architecture, the ping-pong RAM storage unit must be able to store data to be decoded with a maximum code length. For ease of hardware implementation, each piece of data to be decoded is represented by 5 bits, with the sign bit extended to 3 bits. The selection scheme for each storage unit in the EUHT is shown in Table 2:

[0015] Table 2 EUHT LDPC Memory Unit Information

[0016]

[0017] As can be seen from Table 2, each row of the sub-storage unit needs to store 16 or 14 points, so using 48 rows of RAM with 16 points per row as the sub-storage unit is the most suitable.

[0018] Figure 2 The image shows a traditional ping-pong RAM storage structure, such as... Figure 2 As shown, the processing flow is as follows:

[0019] 1. When initializing RAMa / b, 16 data are written at a time, so only one of the write enable signals, wra0~wra6 or wrb0~wrb6, is valid each time.

[0020] 2. When the data received in RAMa / b reaches a LDPC code block, the core decoding arithmetic logic unit begins decoding. When it reads from or writes back to RAMa / b, all seven sub-RAMs can operate simultaneously.

[0021] 3. The number of RAM data pairs selected at one time is determined by the number of sub-cells stored in Table 2.

[0022] The theoretical maximum number of iterations for an LDPC decoder is closely related to bandwidth, MCS (Mean Cross Section), and the time required for a single iteration. In OFDMA systems, because the receiver needs to process data from multiple users simultaneously, and the LDPC decoder has a large area, decoder resources are generally allocated to each user on an average basis. This can easily lead to excessive latency due to a large number of LDPC decoder iterations, filling up both ping-pong RAMs, especially with high bandwidth and low-order MCS. If more data arrives at this point, it's necessary to add a new RAM block to modify the ping-pong structure, or prematurely terminate the LDPC iteration, which reduces the probability of successful decoding.

[0023] To address the issue of the ping-pong RAM storage structure used in the iterative decoder described above, a new solution is needed. Summary of the Invention

[0024] In view of this, the technical problem to be solved by the present invention is to provide a new data storage and processing scheme for iterative decoders, which adopts a new easily expandable storage structure, is simple and easy to implement, and does not reduce decoding efficiency.

[0025] This invention provides a data processing method for an iterative decoder, comprising:

[0026] Set up two memory units, where...

[0027] The first memory (ldpc_buffer) is used to receive and buffer the data to be decoded;

[0028] The second memory (ldpc_rama) is used to participate in intermediate calculations of the decoding arithmetic logic unit and to cache related data;

[0029] A data path is provided between the first memory and the second memory for writing the data to be decoded stored in the first memory into the second memory.

[0030] Decoding begins once the second memory receives data of one code length.

[0031] When the decoding is completed or the maximum number of iterations is reached, the data cached in the first memory is written in parallel to the second memory for subsequent decoding operations.

[0032] More appropriately, when writing data cached in the first memory to the second memory in parallel, each time the data is written to the second memory in parallel according to the number of cyclic submatrices T.

[0033] If the data in the second memory is not full, and there are more than or equal to T data to be decoded in the first memory, then the data is written into the second memory.

[0034] More appropriately, when the decoder needs to expand its storage capacity, this can be achieved by increasing the storage space of the first memory as needed.

[0035] This iterative decoder is a low-density parity-check (LDPC) decoder.

[0036] The present invention provides a data storage and processing apparatus for an iterative decoder, comprising:

[0037] The first memory (ldpc_buffer) is used to receive and buffer the data to be decoded;

[0038] The second memory (ldpc_rama) is used to participate in intermediate calculations of the decoding arithmetic logic unit and to cache related data;

[0039] A data path is provided between the first memory and the second memory for writing the data to be decoded stored in the first memory into the second memory;

[0040] Decoding begins once the second memory (ldpc_rama) receives data of a code length.

[0041] When the decoding is completed or the maximum number of iterations is reached, the data cached in the first memory is written in parallel to the second memory for subsequent decoding operations.

[0042] When writing data cached in the first memory (ldpc_buffer) to the second memory in parallel, each time a number of data in the cyclic submatrix T are written to the second memory (ldpc_rama) in parallel.

[0043] When the data in the second memory is not full, and there are more than or equal to T data to be decoded in the first memory, the data in the first memory is written into the second memory.

[0044] More preferably, the storage space of the first memory can be adjusted as needed to meet the needs of the decoder for expanding its storage capacity.

[0045] The iterative decoder is a low-density parity-check (LDPC) decoder.

[0046] The technical solution provided by this invention can save storage space, cache more data to be decoded, and has a simple and easily expandable storage structure. Its data processing efficiency is no less than that of the ping-pong storage structure.

[0047] For the foregoing and related purposes, one or more embodiments include features that will be described in detail below and particularly pointed out in the claims. The following description and accompanying drawings detail certain exemplary aspects and indicate only a few of the various ways in which the principles of the various embodiments can be utilized. Other benefits and novel features will become apparent upon consideration of the following detailed description in conjunction with the accompanying drawings, and the disclosed embodiments are intended to include all such aspects and their equivalents. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of the structure and data processing flow of an iterative decoder in the prior art;

[0049] Figure 2 This is a schematic diagram of a traditional ping-pong RAM storage structure in the prior art;

[0050] Figure 3 This is a schematic diagram of the easily expandable storage structure used in the LDPC decoder in Example 1 of the present invention;

[0051] Figure 4 This is a timing diagram of the early termination of LDPC decoding in an embodiment of the present invention;

[0052] Figure 5 This is the timing diagram of the LDPC decoder reaching its maximum decoding count under poor channel conditions in this embodiment.

[0053] Figure 6 This is a schematic diagram of the traditional ping-pong storage structure used in existing WIFI technology for implementing LDPC decoding;

[0054] Figure 7 This is a schematic diagram of the structure when a flexible and easily expandable storage mode is used in Embodiment 2 of the present invention;

[0055] Figure 8This is a schematic diagram of the LDPC decoder with an easily expandable storage structure in Embodiment 3 of the present invention. Detailed Implementation

[0056] The following description and accompanying drawings fully illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Some portions and features of some embodiments may be included in or replace portions and features of other embodiments. The scope of embodiments of the invention includes the entire scope of the claims and all available equivalents thereof.

[0057] To address the problem of existing iterative decoders using a ping-pong RAM storage structure, this invention provides a solution by proposing a new, easily expandable storage structure.

[0058] like Figure 3 As shown, the present invention provides a decoding implementation apparatus for an iterative decoder, comprising:

[0059] The buffer (ldpc_buffer) is used to receive and buffer data to be decoded;

[0060] The operational memory (ldpc_rama) is used for intermediate calculations in the decoding arithmetic logic unit and for caching related data.

[0061] A data path is provided between the cache memory (ldpc_buffer) and the computation memory (ldpc_rama) for writing the data to be decoded stored in the cache memory (ldpc_buffer) into the computation memory (ldpc_rama);

[0062] Decoding begins once the computational memory (ldpc_rama) receives data of one code length.

[0063] When the decoding is completed or the maximum number of iterations is reached, the data cached in the cache memory is written in parallel to the computation memory (ldpc_rama) for subsequent decoding operations.

[0064] When writing data cached in the buffer memory (ldpc_buffer) into the operation memory in parallel, each time data of the number of cyclic submatrices T is written into the operation memory (ldpc_rama) in parallel.

[0065] When the data in the computation memory (ldpc_rama) is not full, and the depth in the cache memory (ldpc_buffer) is 0, the data in the cache memory (ldpc_buffer) is written into the computation memory (ldpc_rama).

[0066] The storage space of the cache memory (ldpc_buffer) can be adjusted as needed to meet the requirements of the decoder to expand its storage capacity.

[0067] The iterative decoder is a low-density parity-check (LDPC) decoder.

[0068] This invention provides a decoding implementation method for an iterative decoder, comprising:

[0069] Set up two memory units, where...

[0070] The buffer (ldpc_buffer) is used to receive and buffer data to be decoded;

[0071] The operational memory (ldpc_rama) is used for intermediate calculations in the decoding arithmetic logic unit and for caching related data.

[0072] A data path is provided between the cache memory (ldpc_buffer) and the computation memory (ldpc_rama) for writing the data to be decoded stored in the cache memory (ldpc_buffer) into the computation memory (ldpc_rama);

[0073] Decoding begins once the computational memory (ldpc_rama) receives data of one code length.

[0074] When the decoding is completed or the maximum number of iterations is reached, the data cached in the cache memory is written in parallel to the computation memory (ldpc_rama) for subsequent decoding operations.

[0075] The specific implementation scheme of the present invention is described below using an LDPC decoder as an example.

[0076] LDPC decoders are the most commonly used iterative decoders in modern communication systems such as WIFI, WiMAX, DVB-S2, and ultra-high-speed wireless communication. To facilitate understanding of the intent and principles of this invention, the RAM storage structure in an LDPC decoder within a wireless communication system is used as an example; however, the method described in this invention is not limited to the implementation of an LDPC decoder.

[0077] Example 1

[0078] Figure 3This is a schematic diagram of the easily expandable storage structure used in the LDPC decoder in Example 1 of the present invention. Figure 3 As shown, the data processing flow of the LDPC decoder is as follows:

[0079] During initialization, the data to be decoded in S301 is first written to the buffer ldpc_buffer, which consists of 7 sub-RAMs. Since the data in this RAM is only temporarily stored and does not participate in mathematical operations, each point is raw data, represented by one sign bit and five value bits. Therefore, each sub-RAM is 64 x 6 * 16. Since 32 bits can be saved per row, the sub-RAM depth can be increased to 64 bits for the same capacity.

[0080] S302, ldpc_buffer uses in_wr, in_ring[6:0] to control which sub-RAM to write to. After the number of data to be decoded, which reaches the number of circular sub-matrix T, is written to ldpc_buffer, the write address will increase by one unit. At the same time, ldpc_buffer has already added T data to be decoded (depth++).

[0081] S303, when the operational memory ldpc_rama still has storage space and the buffer ldpc_buffer contains greater than or equal to T data items to be decoded (depth != 0), the data to be decoded will be immediately written to the operational memory ldpc_rama. The data is written in parallel, that is, T numbers of data items to be decoded are written to the circular submatrix at a time, and each data item is extended to eight bits by three sign bits. In this way, the address of the operational memory ldpc_rama increases by one unit, while the buffer ldpc_buffer has released the space of T data items to be decoded.

[0082] S304, when depth == max, it means that ldpc_buffer is full and no more data can be written. This max value can be set to different values ​​according to the specific situation. The max value will be smaller for data path utilization that is high and larger for low utilization. Of course, the depth of the entire ldpc_buffer will also increase at this time. In the example, since the depth of ldpc_buffer is 64, max is set to 64.

[0083] After the computational memory `ldpc_rama` receives data of one code length, decoding begins (at this point, `ldpc_busy = 1`). Subsequent new data is buffered in `ldpc_buffer`. When can data in `ldpc_buffer` be written back to `ldpc_rama`? The conditions are successful decoding (`dec_suc_flag = 1`) or reaching the maximum number of iterations (`ldpc_busy = 0`). At this point, the data buffered in `ldpc_buffer` is written back to `ldpc_rama` in parallel according to the size of the cyclic submatrix `T`. Table 3 below shows the time required to write one code length:

[0084] Table 3 shows the maximum time required to convert from ldpc_buffer to ldpc_rama.

[0085]

[0086] According to the LDPC decoding algorithm, the time for one iteration (which is closely related to the parity check matrix) definitely exceeds the time for writing from the buffer ldpc_buffer to the operational memory ldpc_rama.

[0087] Figure 4 The diagram shows the timing sequence for early termination of LDPC decoding in an embodiment of the present invention. Figure 4 The steps, in chronological order, are as follows:

[0088] S4a. Initialize the computation memory ldpc_rama. At this time, data is written directly from the buffer ldpc_buffer to ldpc_rama. ldpc_buffer buffers no more than one cyclic submatrix T of data. Because the information to be decoded is generated slowly, filling ldpc_rama takes a long time.

[0089] The S4b.LDPC decoder performs iterative decoding. After each iteration, it checks whether the decoding was successful (this is determined by the LDPC algorithm and is beyond the scope of this patent). At this time, ldpc_busy = 1, indicating that the decoder is in a busy state.

[0090] S4c. Suppose that after iterx's iteration, the decoding is successful, but the preset maximum number of iterations has not yet been reached. At this time, dec_suc_flag = 1, indicating that the decoding is successful. However, what is special is that the data of the next iterx iteration will not be written back to the arithmetic memory ldpc_rama (to avoid write conflicts in the arithmetic memory ldpc_rama), and the extra iteration results will not be written back to the decoding result RAM.

[0091] S4d. Output the decoding result, at which point dec_suc_flag = 0;

[0092] S4e. When ldpc_busy=1&dec_suc_flag=0, the newly arrived data to be decoded is cached in ldpc_buffer. In the worst case, ldpc_buffer caches more than one code block of data to be decoded.

[0093] S4f. When ldpc_busy = 1 & dec_suc_flag = 1, the data buffered in ldpc_buffer begins to be written to ldpc_rama. Because this is done in T-times at a time, the process is very fast. ldpc_rama is then quickly initialized.

[0094] S4g. Repeat the process of S4b, S4c, and S4d above, which is the iterative decoding and output of the second code block. When the data to be decoded for the third code block arrives, the process of e and f will be executed again. In fact, the entire LDPC iterative decoder will work repeatedly according to this timing sequence.

[0095] Therefore, it can be seen that the time for writing data from the buffer ldpc_buffer to the arithmetic memory ldpc_rama at this time utilizes the time of this iteration after the successful decoding decision, so it will not take up any extra time.

[0096] Figure 5 The diagram shows the timing sequence of an LDPC decoder that fails to decode even after reaching its maximum decoding count under poor channel conditions. The specific steps are as follows:

[0097] S5a. Initialize the computation memory ldpc_rama. At this time, data is written directly from the buffer ldpc_buffer to ldpc_rama. ldpc_buffer buffers no more than one cyclic submatrix T of data. Because the information to be decoded is generated slowly, filling ldpc_rama takes a long time.

[0098] The S5b.LDPC decoder performs iterative decoding. After each iteration, it checks whether the decoding was successful (this is determined by the LDPC algorithm and is not within the scope of this patent). At this time, ldpc_busy = 1, indicating that the decoder is in a busy state.

[0099] S5c. If decoding still fails when the preset maximum number of iterations (iterm) is reached, decoding terminates, ldpc_busy = 0, indicating that the decoder is in an idle state, and the LDPC decoder starts outputting the decoding result of this iteration.

[0100] S5d. When ldpc_busy=1, the newly arrived data to be decoded is cached in ldpc_buffer. Considering the worst case, at this time ldpc_buffer has already cached more than one code block of data to be decoded.

[0101] S5e. When ldpc_busy = 0, data buffered in ldpc_buffer begins to be written to ldpc_rama. Because this is done in T-times at a time, the speed is very fast. The operational memory ldpc_rama is quickly filled with one code length of data, and initialization is complete. At this moment, ldpc_busy = 1 is set, indicating that the decoder is in a busy state.

[0102] S5f. Repeat the operations of S5b and S5c above, which is the iterative decoding and output of the new code block. The entire LDPC iterative decoder will work repeatedly according to this timing sequence.

[0103] It is important to emphasize that when the LDPC iterative decoder decodes consecutive code blocks, the first code block may be decoded successfully but the second code block may fail, or the first may fail but the second may succeed, or both may succeed or fail. However, in any of these cases, it is a combination of the two timing sequences described above, which will not be elaborated upon here.

[0104] from Figure 5As shown in the timing diagram, when decoding terminates at the maximum number of iterations, the extra iteration time of the `idpc_rama` memory for filling the computational memory cannot be utilized when the decoding decision is successful. In this case, an additional time period (S5e) will occur between the two decoding operations. The maximum value of this time period is the same as the 'fill time' in Table 3. Because this time is much smaller than the time of one iteration, and even smaller than the time of an unsuccessful LDPC decoding (iteratio to the maximum preset number of iterations), it has almost no performance impact. Theoretically analyzing the maximum possible number of iterations, let's assume the maximum number of LDPC iterations is IterMax, the bandwidth is 80MHz (including 224 effective sampling points in the 20MHz subband), 256QAM coding is used, there are 4 streams, the time for one iteration is t (which is several times the time of (S5e)), the LDPC code length is 5376, and the time of one frame is 14.4us. Then, IterMax = 14.4 / (224 * 4 * 8 * 4 / 5376) / t. The theoretical maximum number of iterations calculated using this formula is generally a decimal. However, when setting the configurable maximum number of iterations, integers are used. Therefore, the extra time (e) is easily taken into account and will not reduce the maximum number of iterations. Furthermore, in the actual design of LDPC decoders, because there are many units in the data path, it is impossible for each unit to reach the highest throughput. Therefore, the actual preset maximum number of iterations will be smaller than the theoretically calculated maximum number of iterations.

[0105] Figure 4 and Figure 5 The structure and scheme described herein consider the scenario where the next code block is filled into the ldpc_buffer before the previous code block has been fully decoded. This is the worst-case scenario. Otherwise, whether the next code block arrives before the previous code block has finished decoding or the ldpc_buffer is not full, it will not put pressure on the ldpc_buffer. The additional time added during the decoding of two consecutive code blocks will not exceed the data in Table 3.

[0106] Table 4 compares the number of LDPC code blocks that can be cached using the easily expandable structure of this invention and the traditional ping-pong RAM storage structure.

[0107] Table 4

[0108]

[0109] The data in Table 4 shows that this easily expandable structure has advantages for every code length and code rate, and these advantages are more obvious for short codes.

[0110] In this embodiment of the invention, there is a direct write data path from the buffer ldpc_buffer to the operational memory ldpc_rama. Note the one-to-one correspondence between the sub-RAMs within the two. In chip implementation, these one-to-one corresponding sub-RAMs need to be placed closer together during layout and routing. This way, there will be no setup time issues during timing analysis of this RAM-to-RAM data path.

[0111]

Example 2

[0112] 802.11n / ac / ax is currently the most popular indoor LAN solution. This protocol also uses LDPC encoding. The following uses LDPC from the WIFI protocol to illustrate this technical solution. However, this solution is not only applicable to this protocol.

[0113] The main parameters of LDPC in the Wi-Fi protocol are code length (N), code rate (R), and cyclic submatrix size (T). These parameters differ somewhat from those of LDPC in EUHT, primarily in that the cyclic submatrix size T does not have a multiple relationship between the maximum code length and the secondary code length. For ease of hardware implementation, each piece of data to be decoded uses 5 bits to represent the numerical bits, with the sign bit extended to 3 bits. The selection scheme for each memory unit in 802.11AC is shown in Table 5 below.

[0114] Table 5 802.11AC LDPC Encoding Parameters and Storage Unit Information

[0115]

[0116] As can be seen from Table 5, the sub-storage unit sizes in the LDPC of the WIFI protocol are the same due to the special nature of the T value (which has a common divisor of 9).

[0117] Figure 6 This is a schematic diagram of the traditional ping-pong storage structure used in existing WIFI technology for LDPC decoding:

[0118] S601 writes 9 data at a time when initializing RAMa / b, so only one of the write enable signals from wra0 to wra8 or wrb0 to wrb8 is valid each time.

[0119] In S602, when the data received in RAMa / b reaches a LDPC code block, the core decoding arithmetic logic unit begins decoding. When reading from or writing back to RAMa / b, all nine sub-RAMs can operate simultaneously.

[0120] Therefore, it can be seen that using this ping-pong storage structure, the LDPC decoder of WIFI can process the data of up to two code blocks at the same time. If redundancy is required, more ping-pong RAM needs to be added.

[0121] Figure 7 This is a schematic diagram of the structure when a flexible and easily expandable storage mode is used in Embodiment 2 of the present invention.

[0122] The processing flow in Example 2 is as follows:

[0123] During initialization, the S701 first writes data to the buffer ldpc_buffer, which consists of nine sub-RAMs, each 32x6x9. Since the data in this RAM is only temporarily stored, it doesn't participate in mathematical operations; each point represents raw data, with one sign bit and five value bits. Because each row saves 18 bits, the depth is increased to 32 for the same area.

[0124] S702, ldpc_buffer uses in_wr,in_ring[8:0] to control which sub-RAM to write to. When the number of data to be decoded reaches T in the circular sub-matrix is ​​written to ldpc_buffer, the write address will increase by one unit, and depth++ will indicate that ldpc_buffer has cached an additional T number of data to be decoded.

[0125] S703: When the computational memory ldpc_rama is not full and depth in ldpc_buffer is 0, data will be written to ldpc_rama immediately. The data is written in parallel, meaning that T units of data to be decoded are written to the circular submatrix at a time, and each data item is extended to eight bits using three sign bits. This increases the address of ldpc_rama by one unit, while ldpc_buffer.depth-- indicates that T units of storage space have been released in the buffer ldpc_buffer.

[0126] S704, when depth == max, it means that ldpc_buffer is full and no more data can be written. Depending on the design, this max will be different. The max will be smaller for data path utilization that is high and larger for utilization that is low. Of course, the depth of the entire ldpc_buffer will also increase at this time.

[0127] After the computational memory `ldpc_rama` receives data of one code length, decoding begins (at this point, `ldpc_busy = 1`). Subsequent new data is buffered in `ldpc_buffer`. When can data in `ldpc_buffer` be written back to `ldpc_rama`? The condition is successful decoding (`dec_suc_flag = 1`) or reaching the maximum number of iterations (`ldpc_busy = 0`). At this point, the data buffered in `ldpc_buffer` is written back to `ldpc_rama` in parallel according to the size of the cyclic submatrix `T`. The table below shows the time required for WIFI's LDPC to write a full code length, as shown in Table 6:

[0128] Table 6 shows the maximum time required to convert from ldpc_buffer to ldpc_rama.

[0129]

[0130]

[0131] In LDPC decoding implementations, due to considerations of storage space and performance, a row (column) information scheduling decoding algorithm is generally adopted. The typical time value for one iteration in Table 6 above is obtained based on this decoding algorithm, and its value is closely related to the size of the LDPC parity-check matrix. Of course, this invention is not concerned with the specific decoding algorithm; this invention focuses on... Figure 1 The improved storage logic structure of this type of iterative decoding algorithm is shown in Table 6. As can be seen from Table 6, the time for one iteration definitely exceeds the time required to write from the buffer `ldpc_buffer` to the operational memory `ldpc_rama`. Regarding the timing impact of this improved, easily expandable storage structure on the WIFI LDPC decoder when it terminates prematurely or reaches the maximum number of iterations, this has already been analyzed in the aforementioned Example 1 and will not be repeated here. The number of LDPC code blocks that can be cached by the improved, easily expandable storage structure for WIFI LDPC is shown in Table 7 below.

[0132] Table 7 compares the number of code blocks accommodated by LDPC scalable memory structure and ping-pong RAM structure in WIFI within the same area.

[0133]

[0134] The table shows that the expandable structure can accommodate 0.33 more code blocks without increasing the total RAM capacity.

[0135] If the time to write data from ldpc_buffer to ldpc_rama can be increased by three times to 72 clock cycles, then this easily expandable storage structure can be changed to the following embodiment three. The essence of this modification is still the idea of ​​the easily expandable structure in this invention.

[0136]

Example 3

[0137] This solution is a derivative of Embodiment 1 and Embodiment 2 above. Its core idea remains the same: an arithmetic memory ldpc_rama participates in the intermediate operations of the iterative decoding arithmetic logic unit, and another buffer ldpc_buffer is used to buffer the data to be decoded.

[0138] Figure 8 The diagram shows a variation of the WIFI LDPC decoder in Embodiment 3, employing an easily expandable storage structure. Its workflow is as follows:

[0139] During initialization, the S801 first writes data to ldpc_buffer, which consists of 3 sub-RAMs, each of which is 96x6*9. Since the data in this RAM is only temporarily stored, it does not need to participate in mathematical operations. Each point is raw data, with one sign bit plus five value bits representing one point.

[0140] S802, the buffer ldpc_buffer uses in_wr, in_ring[2:0], and in_sel to control which sub-RAM is written to. in_sel is generated by the code length and code rate. For example, when the code length is 1944, 81 points need to be generated. When in_sel=0, addr of RAM0, RAM1, and RAM2 are written respectively. When in_sel=1, these three RAMs are also written respectively, but addr++ and depth++. When in_sel=2, these three RAMs are still written, but addr++ and depth++.

[0141] In S803, when the operational memory `ldpc_rama` is not full and `ldpc_buffer.depth` is 0, data is immediately written to `ldpc_rama`. Data is written in parallel at 27 points. This means that with a code length of 1944, it takes three clock cycles to write T points: the first cycle writes to sub-RAMs `a0 / 1 / 2`, the second to `a3 / 4 / 5`, and the third to `a6 / 7 / 8`, and so on. With a code length of 1296, it takes two clock cycles to write T points: the first cycle writes to sub-RAMs `a0 / 1 / 2`, the second to `a3 / 4 / 5`, and so on. With a code length of 648, it only takes one clock cycle, directly writing to sub-RAMs `a0 / 1 / 2`. Each point is extended to eight bits using three sign bits. After writing one clock cycle of data, `ldpc_buffer.depth` is decremented. After writing T points, the address of `ldpc_rama` is incremented.

[0142] S804, when depth == max, it means that the buffer ldpc_buffer is full and no more data can be written. Depending on the design, this max will be different. The max will be smaller for high data path utilization and larger for low utilization. Of course, the depth of the entire ldpc_buffer will also increase at this time.

[0143] Figure 8The ldpc_buffer adds a 27*6-bit register resource to address the issue that the three sub-RAMs 0 / 1 / 2 of the ldpc_buffer and the nine sub-RAMs in the ldpc_rama memory do not correspond one-to-one in this structure. This makes it difficult to handle the timing of the direct RAM-to-RAM data path during back-end placement and routing. If the actual timing meets the requirements, these additional register resources can be omitted. This modified easily expandable memory structure is slightly more complex to control, as it must consider different cyclic submatrix sizes and how to allocate the RAM inside the ldpc_buffer. The solution in this invention is to allow the three sub-RAMs to be used in turn, with the address incremented uniformly after every 27 points are written, and ldpc_buffer.depth also incremented. When writing from the buffer ldpc_buffer to the operational memory ldpc_rama, internal register resources (27*6 bits) are simultaneously written to ldpc_rama. At T=81, the order is as follows: In the first clock cycle, RAMa0, RAMa1, and RAMa2 are written simultaneously; in the second clock cycle, RAMa3, RAMa4, and RAMa5 are written simultaneously; and in the third clock cycle, RAMa6, RAMa7, and RAMa8 are written simultaneously. At T=54, the order is as follows: In the first clock cycle, RAMa0, RAMa1, and RAMa2 are written simultaneously; and in the second clock cycle, RAMa3, RAMa4, and RAMa5 are written simultaneously. At T=27, RAMa0, RAMa1, and RAMa2 are written simultaneously in a single clock cycle. One advantage of this easily expandable memory structure variant is that it can accommodate more code block resources, fully utilizing the three RAMs in ldpc_buffer. The table below shows the corresponding data.

[0144] Table 8: Comparison of the number of code blocks accommodated in the same area between the WIFI LDPC deformable scalable memory structure and the ping-pong RAM structure.

[0145]

[0146] The drawback of this modified structure is that when the LDPC decoder terminates decoding at the maximum number of iterations, there will be a delay of 72 clock cycles in the worst case for a code length of 1944, a delay of 48 clock cycles for a code length of 1296, and a delay of 24 clock cycles for a code length of 648. Of course, these delays will not exceed the time of one iteration. Therefore, whether to adopt this modified scheme requires analysis in a real system using simulations to see if a balance can be achieved between the maximum number of iterations and allowing for more code blocks.

[0147] The above three schemes all illustrate how this easily expandable storage structure is implemented during iterative decoding. Compared with the traditional ping-pong storage structure, it has the advantages of easy structural expansion and the ability to accommodate more code blocks to be decoded.

[0148] Compared with existing solutions, the present invention has the following advantages:

[0149] Compared to the ping-pong RAM storage structure, this invention can accommodate more code blocks to be decoded at low code lengths without increasing the total RAM capacity, and also provides a certain gain at the longest code lengths. Furthermore, the greatest advantage of this invention lies in its convenient structural expansion. There is only one single write data path from the buffer ldpc_buffer to the operational memory ldpc_rama, making the control of ldpc_buffer very simple and increasing the buffer depth very easy. The reason for achieving this effect is mainly due to:

[0150] 1. The ldpc_buffer is just a regular buffer and does not participate in the storage and retrieval of intermediate data during the LDPC core arithmetic logic unit iteration. Therefore, each piece of data to be decoded in the ldpc_buffer does not need to be sign-extended, which can save 25% of the space for such data. This saved space can then be used to cache more data to be decoded.

[0151] 2. In the ping-pong RAM storage structure, the size of each RAM is designed according to the maximum code length. However, with short code lengths, this ping-pong RAM structure inherently limits it to storing only two code blocks of data. The ldpc_buffer, on the other hand, does not directly participate in the storage and retrieval of intermediate data in the LDPC core arithmetic logic unit. Therefore, it can store more than two code blocks of data to be decoded, regardless of whether the code length is long or short. This is why this structure can cache more code blocks.

[0152] 3. Because there is a unidirectional data path between ldpc_buffer and ldpc_rama, the control is very simple. In the ping-pong RAM structure, the control of the two ping-pong RAMs is symmetrical, and there is always a need for switching, making the control naturally more complex than this unidirectional structure. If another RAM is added because the two RAMs are not enough, then firstly, a RAM of the same size must be added, and secondly, controlling the switching between the three RAMs becomes even more complex.

[0153] 4. The ldpc_buffer buffer only buffers the raw data to be decoded. Therefore, when the buffer size needs to be expanded, it is not necessary to increase the number of code blocks at once; only a small margin needs to be added according to the actual simulation conditions. Furthermore, the control logic of the ldpc_buffer buffer after increasing its depth is almost exactly the same as before. This is the scalability of this structure.

[0154] In the technical solution provided by this invention, a buffer ldpc_buffer is used to store the data to be decoded, while only the arithmetic memory ldpc_rama participates in caching the intermediate calculation results of the LDPC core decoding arithmetic logic unit. This is the biggest difference from the ping-pong RAM structure, in which both ping-pong RAMs participate fairly in caching the intermediate calculation results of the core decoding arithmetic logic unit.

[0155] Because the buffer ldpc_buffer does not participate in arithmetic logic calculations, it can store the raw data to be decoded without the need for sign bit extension to prevent overflow or underflow. This saves storage resources for each piece of data to be decoded. Sign bit extension is performed when the data to be decoded is written from the buffer ldpc_buffer to the arithmetic memory ldpac_rama.

[0156] During LDPC initialization, once the data accumulated in the ldpc_buffer is sufficient for a cyclic submatrix of size T, it is immediately written to the ldpc_rama within one clock cycle. The reason why T data items can be written in one clock cycle is that there is a one-to-one correspondence between the sub-RAM of the ldpc_buffer and the sub-RAM in the operational memory ldpc_rama.

[0157] During LDPC decoding, subsequent data to be decoded is stored in the buffer ldpc_buffer; the decoder busy / idle flag ldpc_busy signal and the decoding success / failure flag ldpc_suc_flag signal are used to control when data in the buffer ldpc_buffer can be written to the operational memory ldpc_rama.

[0158] To avoid write data conflicts, during the additional iteration after successful decoding, the intermediate calculation results are not written to the computation memory ldpc_rama. Instead, the data to be decoded cached in the buffer ldpc_buffer is written to the computation memory ldpc_rama.

[0159] To avoid introducing unnecessary errors through additional iterations, the decoding result of the extra iteration after successful decoding is not written to the result memory.

[0160] When the storage structure needs to be expanded, only the area of ​​the buffer ldpc_buffer needs to be increased, without modifying the area of ​​the computation memory ldpc_rama. This fully guarantees the scalability of this storage structure.

[0161] Although this invention uses a typical iterative decoding algorithm, LDPC decoding, as an example to illustrate the principle of the invention, this principle is also applicable to other iterative decoders that employ a core decoding arithmetic logic unit plus a ping-pong RAM structure.

[0162] Considering the unique characteristics of communication systems, different data packet formats of varying lengths are inevitable. If a ping-pong RAM structure is used to buffer these data packet formats, each RAM must be configured according to the largest data packet format. However, the inherent limitation of ping-pong RAM means it can only buffer two packets at a time, regardless of size. The structure of this invention, consisting of a buffer and a computational memory, easily allows for buffering more packets when small, and expansion is only required by increasing the buffer size, while the computational memory only needs to maintain its capacity to hold the maximum packet length. Of course, systems using this structure must meet two conditions: first, the system must need to accommodate more than two data packets; second, the system must be able to tolerate the increased latency in parallel writes from the buffer (ldpc_buffer) to the computational memory (ldpc_rama) when processing the second packet.

[0163] Those skilled in the art will understand that the various exemplary method steps and apparatus units described herein in conjunction with the disclosed embodiments can be implemented in electronic hardware, software, or a combination of both. To clearly illustrate the interchangeability between hardware and software, the various exemplary steps and units have been generally described above in their functional form. Whether this functionality is implemented in hardware or software depends on the specific application and the design constraints implemented by the entire system. Those skilled in the art can implement the described functionality in various ways for each specific application, but the result of such implementation should not be construed as departing from the scope of the invention.

[0164] Based on the disclosed embodiments, those skilled in the art can implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can also be applied to other embodiments without departing from the scope and spirit of the invention. The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A data storage processing method for an iterative decoder, characterized in that, include: Set up two memory units, where... The first memory, ldpc_buffer, is used to receive and buffer data to be decoded. The second memory, ldpc_rama, is used to participate in intermediate calculations of the decoding arithmetic logic unit and to cache related data. A data path is provided between the first memory ldpc_buffer and the second memory ldpc_rama for writing the data to be decoded stored in the first memory ldpc_buffer into the second memory ldpc_rama. The first memory ldpc_buffer has multiple RAM units, and the second memory ldpc_rama has multiple RAM units. There is a one-to-one correspondence between each RAM unit of the first memory ldpc_buffer and each RAM unit of the second memory ldpc_rama, and there is a data path between each RAM unit of the first memory ldpc_buffer and each RAM unit of the second memory ldpc_rama. When the decoder needs to expand its storage capacity, it is achieved by increasing the storage space of the first memory ldpc_buffer as needed. Decoding begins once the second memory ldpc_rama receives data of one code length. When the decoding is completed or the maximum number of iterations is reached, the data cached in the first memory ldpc_buffer is written in parallel to the second memory ldpc_rama for subsequent decoding operations; when writing the data cached in the first memory ldpc_buffer in parallel to the second memory ldpc_rama, each time the data of the cyclic submatrix T is written in parallel to the second memory ldpc_rama.

2. The data storage processing method as described in claim 1, characterized in that, When the data in the second memory ldpc_rama is not full, and there are more than or equal to T data to be decoded in the first memory ldpc_buffer, the data in the first memory ldpc_buffer is written into the second memory ldpc_rama.

3. The data storage processing method according to any one of claims 1 to 2, characterized in that, The iterative decoder is a low-density parity-check (LDPC) decoder.

4. A data storage and processing apparatus for an iterative decoder, characterized in that, include: The first memory, ldpc_buffer, is used to receive and buffer data to be decoded. The second memory, ldpc_rama, is used to participate in intermediate calculations of the decoding arithmetic logic unit and to cache related data. A data path is provided between the first memory ldpc_buffer and the second memory ldpc_rama for writing the data to be decoded stored in the first memory ldpc_buffer into the second memory ldpc_rama. The first memory ldpc_buffer has multiple RAM units, and the second memory ldpc_rama has multiple RAM units. There is a one-to-one correspondence between each RAM unit of the first memory ldpc_buffer and each RAM unit of the second memory ldpc_rama, and there is a data path between each RAM unit of the first memory ldpc_buffer and each RAM unit of the second memory ldpc_rama. When the decoder needs to expand its storage capacity, it is achieved by increasing the storage space of the first memory ldpc_buffer as needed. Decoding begins once the second memory ldpc_rama receives data of one code length. When the decoding is completed or the maximum number of iterations is reached, the data cached in the first memory ldpc_buffer is written in parallel to the second memory ldpc_rama for subsequent decoding operations.

5. The data storage processing apparatus as described in claim 4, characterized in that, When the data in the second memory ldpc_rama is not full, and there are more than or equal to T data to be decoded in the first memory ldpc_buffer, the data in the first memory ldpc_buffer will be written into the second memory ldpc_rama.

6. The data storage processing apparatus as described in any one of claims 4 to 5, characterized in that, The iterative decoder is a low-density parity-check (LDPC) decoder.

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