Memory device generating improved write voltage according to size of memory cell

Abstract

A memory device including magnetic memory elements is disclosed. The memory device includes an array of memory cells including a first region and a second region, the second region configured to store a value of a write voltage, the write voltage based on a value of a reference resistor used to determine whether a programmed memory cell is in a parallel state or an anti-parallel state; a voltage generator configured to generate a code value based on the value of the write voltage; and a write driver configured to drive a write current based on the code value, the write current being a current used to store data in the first region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0101344, filed on August 12, 2020, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Some example embodiments relate to semiconductor devices, and more specifically, to memory devices including magnetic tunnel junction elements and / or methods for testing and operating the semiconductor device. Background Technology

[0004] Today, various types of electronic devices are in use. Due to the expectation of high-speed, low-power electronic devices, these devices require memory devices that meet at least some of the following requirements: high reliability, high speed, and low power consumption. To meet these expectations, magnetic memory elements have been proposed as storage elements for memory devices. Because magnetic memory elements operate at high speeds and are non-volatile, they have attracted attention as next-generation semiconductor memory elements.

[0005] Generally, magnetic memory elements can include magnetic tunnel junctions (MTJs), such as MTJ elements. An MTJ element can include two magnetic materials and an insulating layer interposed therebetween. The resistance of an MTJ element can vary depending on the magnetization directions of the two magnetic materials. For example, when the magnetization directions of the two magnetic materials are antiparallel to each other, the MTJ element can have a large resistance value; when the magnetization directions of the two magnetic materials are parallel to each other, the MTJ element can have a small resistance value. Data can be written to or read from the source by using the difference in resistance values.

[0006] Furthermore, regarding the expected reliability and / or durability of magnetic memory components, the durability of the memory device may be problematic when written using excessively large voltages and / or currents, while its viability may be questionable when written using insufficient voltages and / or currents. In particular, because the values ​​of the write voltage and / or current are stored in the memory device by the memory vendor / supplier during testing (e.g., wafer testing), these values, once determined, can significantly impact the performance of the memory device. Summary of the Invention

[0007] Some example embodiments provide devices and / or methods for determining an improved (e.g., optimal) value of a reference resistor through a small number (e.g., minimal) number of write operations and for determining an improved (e.g., optimal) value of a write voltage based on the value of the reference resistor thus determined.

[0008] According to some example embodiments, a memory device includes: a memory cell array including a first region and a second region, the second region being configured to store a write voltage value based on the value of a reference resistor used to determine whether a programmed memory cell is in a parallel or antiparallel state; a voltage generator configured to generate a code value based on the write voltage value; and a write driver configured to drive a write current based on the code value, the write current being a current used to store data in the first region.

[0009] According to some example embodiments, a method of operating a memory device includes: writing the memory device to a first state; counting fault bits of the memory device programmed to the first state using a first plurality of resistors having different values, the first plurality of resistors corresponding to each of a plurality of reference resistors; writing the memory device to a second state; counting fault bits of the memory device programmed to the second state using the first plurality of resistors; selecting a selected reference resistor from the first plurality of resistors based on (A) a counting result associated with the first state and (B) a counting result associated with the second state; and determining a value of a write voltage for the memory device based on the value of the selected reference resistor.

[0010] According to some example embodiments, a memory device includes: a memory cell array including a first region and a second region, the second region being configured to store the value of the reference resistor and the value of a write voltage, the value of the write voltage being determined based on the value of the reference resistor, the value of the reference resistor being determined based on: (A) a first result of counting the number of fault bits of the first region programmed to a first state for each of a plurality of resistance values, and (B) a second result of counting the number of fault bits of the first region programmed to a second state for each of the plurality of resistance values; a column decoder configured to select a bit line connected to a memory cell selected from memory cells in the first region; a row decoder configured to drive a word line connected to the selected memory cell; a voltage generator configured to generate a code value based on the value of the write voltage; and a write driver configured to drive a write current and provide the driven write current to the selected memory cell through the selected bit line, the write current being a current for storing data in the selected memory cell, the write current being based on the code value. Attached Figure Description

[0011] The above and other objects and features of the exemplary embodiments will become apparent from the detailed description of their embodiments with reference to the accompanying drawings.

[0012] Figure 1 A substrate in which a memory device according to some example embodiments of the inventive concept is integrated is shown.

[0013] Figure 2 It shows Figure 1 The configuration of the memory device.

[0014] Figure 3 It is shown Figure 2 A circuit diagram showing the configuration of the memory cell array.

[0015] Figure 4 It is shown Figure 2 Circuit diagram of the configuration of the memory cell array

[0016] Figure 5 and Figure 6 It shows Figure 3 The configuration of the memory cells.

[0017] Figure 7 It is shown that... Figure 4 A conceptual diagram of the configuration associated with the memory cells.

[0018] Figure 8 It shows the relationship with Figure 5 or Figure 6 A graph relating the write status of memory cells.

[0019] Figure 9 The invention conceptually illustrates some example embodiments of how to determine the optimal value of a reference resistor for a memory device, based on the inventive concept.

[0020] Figure 10 This conceptually illustrates the relationship between the value of the optimal reference resistor and its corresponding optimal write voltage, determined during test operations for a memory device.

[0021] Figure 11 The invention conceptually illustrates some example embodiments of how to test a memory device based on the inventive concept.

[0022] Figure 12 The invention conceptually illustrates some example embodiments of how to perform test operations on a memory device according to the inventive concept.

[0023] Figure 13 The invention conceptually illustrates some example embodiments of how to test a memory device based on the inventive concept.

[0024] Figure 14 It shows Figure 11The configuration of the driver.

[0025] Figure 15 and Figure 16 It shows the basis from Figure 14 The operation of the driver is based on the code value output by the voltage generator.

[0026] Figure 17 This is a flowchart illustrating a test method for a memory device according to some example embodiments of the inventive concept.

[0027] Figure 18 A test system based on some example embodiments of the inventive concept is shown. Specific Implementation

[0028] Below, some exemplary embodiments of the inventive concept will be described in detail and clearly to the extent that those skilled in the art can readily implement some exemplary embodiments.

[0029] Some components and / or functional blocks shown in the figures described in the detailed description using terms such as “unit,” “module,” “block,” “circuit,” “device,” “component,” “table,” “device,” “area,” etc., may be implemented using software, hardware, or a combination thereof. For example, software may be or include machine code, firmware, embedded code, or application software, and may be stored in a temporary or non-temporary manner. Hardware may include processing circuitry such as electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, FPGAs, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or combinations thereof.

[0030] Figure 1 A substrate 1 is shown in which a memory device according to some example embodiments of the inventive concept is integrated. The substrate 1 may include a plurality of dies or devices (such as a memory device including a first memory device C1 and a second memory device C2) and scribe lines 3 between the memory devices. The memory devices may be arranged two-dimensionally in a first direction D1 and a second direction D2. Each memory device may be surrounded by the scribe lines 3. For example, the scribe lines 3 may be defined between adjacent memory devices along the first direction D1 and between adjacent memory devices along the second direction D2. Additionally, although in Figure 1 A number of dies are shown, but the example embodiments are not limited to these. Figure 1 The quantity shown can be more or less than the quantity indicated. Figure 1 The quantity shown. Furthermore, although the die is shown as square, the example embodiment is not limited to this, and the die shape can be another shape, such as another rectangular shape.

[0031] In some exemplary embodiments, substrate 1 may be or include a semiconductor substrate such as a semiconductor wafer. Substrate 1 may be or include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, and / or a substrate of an epitaxial thin film formed by selective epitaxial growth (SEG). For example, substrate 1 may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or mixtures thereof. Substrate 1 may have a single-crystal structure. Substrate 1 may be doped, for example, lightly doped with p-type impurities; however, the exemplary embodiments are not limited thereto. Furthermore, although substrate 1 is shown as circular, the exemplary embodiments are not limited thereto. For example, substrate 1 may have, for example, flat edges, and / or may have notched locations on the circumference of a circle. Furthermore, substrate 1 may have a diameter of 100 mm, 150 mm, 200 mm, 300 mm, or 450 mm; however, the exemplary embodiments are not limited thereto.

[0032] In some example embodiments, a first memory device C1 may refer to a memory device formed in a region relatively close to the edge (such as the periphery of substrate 1), and a second memory device C2 may refer to a memory device formed relatively close to the center of substrate 1.

[0033] Meanwhile, the write characteristics and / or reference resistor characteristics of the memory device can vary, for example, depending on the location on the substrate 1 where the memory device is formed. For example, if the memory device formed on the substrate 1 includes an MRAM cell, the size of the MRAM cell can vary depending on the location of the memory device in the substrate 1.

[0034] For example, due to manufacturing processes, the size of the MRAM cell of the first memory device C1, which is placed relatively close to the periphery of the substrate 1, can be relatively small. Conversely, due to manufacturing processes, the size of the MRAM cell of the second memory device C2, which is placed relatively close to the center of the substrate 1, can be relatively large. According to some exemplary embodiments of the inventive concept, the write voltage level, such as an improved or optimal write voltage level for the memory device (or chip), can be determined taking into account the relative position of the memory devices in the substrate 1. For example, the write voltage level can be determined based on the radial and / or angular position of the memory devices in the substrate 1 and / or the number of adjacent devices. Therefore, as described more fully below, a memory device with improved reliability and durability can be provided.

[0035] Figure 2 It shows Figure 1 The configuration of memory devices C1 and C2. In some example embodiments, Figure 2The memory device 100 can be an implementation Figure 1 Examples of memory devices C1 and C2. Memory device 100 may include a memory cell array 110, a row decoder 120, a column decoder 130, a write driver 140, sensing circuitry 150, a source line driver 160, input / output circuitry 170, control logic circuitry, and a voltage generator 180.

[0036] The memory cell array 110 may include a plurality of memory cells, each configured to store data. For example, each memory cell may include a variable resistive element, and the value of the data stored in the variable resistive element may be determined based on the resistance value of the variable resistive element. For example, each memory cell may include at least one of an MRAM (magnetoresistive RAM) cell, an STT-MRAM (spin-transfer torque MRAM) cell, a PRAM (phase-change RAM) cell, a ReRAM (resistive RAM) cell, etc. In the following description, the description will be given under the assumption that each memory cell includes an MRAM cell; however, the exemplary embodiments are not limited thereto.

[0037] The memory cells constituting the memory cell array 110 / including the memory cells in the memory cell array 110 can be connected to the source line SL, the bit line BL, and the word line WL. For example, memory cells arranged along a row can be connected together to the word line corresponding to that row, and memory cells arranged along a column can be connected together to the source line and the bit line corresponding to that column.

[0038] The row decoder 120 can select (or drive) the word line WL connected to the memory cell targeted by the read or write operation. The row decoder 120 can drive a specific word line WL based on the row address RA and the row control signal R_CTRL. The row decoder 120 can provide the selected word line with a drive voltage received from the control logic circuitry and the voltage generator 180.

[0039] The column decoder 130 can select the bit line BL and / or source line SL connected to the memory cell targeted by the read or write operation based on the column address CA and the column control signal C_CTRL.

[0040] During a write operation, the write driver 140 can drive a write voltage and / or a write current to store the write data in a memory cell selected by the row decoder 120 and the column decoder 130. For example, in a write operation of the memory device 100, the write driver 140 can store the write data in a selected memory cell by controlling the voltage of the data line DL based on the write data provided from the input / output circuit 170 via the write input / output line WIO.

[0041] Meanwhile, for the sake of convenience and the simplicity of the accompanying drawings, the data line DL is shown, but the data line DL can be understood as corresponding to the bit line BL and the source line SL selected by the column decoder 130.

[0042] During a read operation, sensing circuit 150 can sense the signal output via data line DL to determine the value of the data stored in the selected memory cell. Sensing circuit 150 can be connected to column decoder 130 via data line DL and to input / output circuit 170 via read input / output line RIO. Sensing circuit 150 can output the sensed read data to input / output circuit 170 via read input / output line RIO.

[0043] The source line driver 160 can drive the source line SL to a specific voltage level under the control of the control logic circuitry and the voltage generator 180. For example, a voltage for driving the source line SL can be supplied to the source line driver 160 from the control logic circuitry and the voltage generator 180. For example, the value of the voltage applied to the source line SL from the source line driver 160 can be variable in the case of a write operation, resulting in a large resistance value for the memory cell (e.g., antiparallel state), or variable in the case of a write operation, resulting in a small resistance value for the memory cell (e.g., parallel state).

[0044] At the same time, although not in Figure 2 As shown, however, memory device 100 may also include other memories, such as fuse arrays and / or antifuse arrays. Fuse arrays may be arranged along rows and columns and may include fuses, for example, that are fused by a laser. Antifuse arrays may include antifuses arranged along rows and columns. For example, the fuse array or antifuses, as an once-programmable (OTP) memory, may be non-volatile. Information about memory device 100 may be written into the antifuse array. For example, information about the manufacturing process, a specific batch and / or a specific substrate 1, a specific location of memory device 100 within substrate 1, information about fault addresses of memory cell array 110, information about the internal voltages of memory device 100 (e.g., write voltage and / or read voltage), etc., may be written into the antifuse array. In particular, according to some exemplary embodiments of the inventive concept, information about the value of the write voltage (such as an optimal write voltage determined during testing of memory device 100 after its manufacture) may be written into the antifuse array.

[0045] Figure 3 It is shown Figure 2A circuit diagram illustrating the configuration of the memory cell array 110a. The memory cell array 110a may include a plurality of memory cells arranged in the row and column directions. Each memory cell may include a magnetic tunnel junction (MTJ) element and a cell transistor (CT). As an example, each memory cell may be a 1T1MTJ memory cell; however, the example embodiment is not limited thereto. When the MTJ element of each memory cell is written to have a specific resistance value, data corresponding to that specific resistance value can be stored in each memory cell. In some example embodiments, the memory cell indicated by the dashed box among the plurality of memory cells is marked with "MC1".

[0046] The plurality of memory cells can be connected to word lines WL1 to WLm, bit lines BL1 to BLn, and source lines SL1 to SLn. In the first memory cell MC1, the first terminal of the MTJ element can be connected to or directly connected to the first bit line BL1, and the second terminal of the MTJ element can be connected to or directly connected to the first terminal of the cell transistor CT. The MTJ element can be arranged in series between the cell transistor CT and the bit line BL. The second terminal of the cell transistor CT can be connected to the source line SL1, and the gate electrode of the cell transistor CT can be connected to the first word line WL1.

[0047] Figure 4 It is shown Figure 2 A circuit diagram illustrating the configuration of the memory cell array 110b. The memory cell array 110b may include multiple memory cells arranged in the row and column directions. Each memory cell may include an MTJ element and two unit transistors. For example, a memory cell may be a 2T1MTJ memory cell. Figure 4 Some example embodiments shown include a first memory cell MC1, indicated by a dashed box, which comprises an MTJ element, a first unit transistor CT1, and a second unit transistor CT2.

[0048] The first memory cell MC1 may have a structure in which two cell transistors CT1 and CT2 share a single MTJ element. In the first memory cell MC1, the first terminal of the MTJ element may be connected to the first bit line BL1, for example, in direct series connection, and the second terminal of the MTJ element may be connected to the first terminals of the first and second cell transistors CT1 and CT2, for example, in direct series connection. The second terminals of cell transistors CT1 and CT2 may be connected to or directly connected to the first source line SL1. The gate electrode of the first cell transistor CT1 may be connected to or directly connected to the first word line WL1, and the gate electrode of the second cell transistor CT2 may be connected to the first sub-word line WL1'. Each of the cell transistors CT1 and CT2 may be turned on or off by a signal (or voltage) provided via the first word line WL1 or the first sub-word line WL1'.

[0049] Example embodiments are not limited to Figure 3 and Figure 4 Those shown, Figure 3 and Figure 4 The characteristics do not necessarily imply mutual exclusion. For example, memory device 100 may include, as referenced... Figure 3 The first memory cell array 110 described and as follows Figure 4 The second memory cell array 110b is described in the document.

[0050] Figure 5 and Figure 6 It shows Figure 3 The configuration of the memory cells.

[0051] Reference Figure 5 and Figure 6 The MTJ element may include a first magnetic layer L1, a second magnetic layer L2, and a barrier layer BL (or tunneling layer) interposed between the first magnetic layer L1 and the second magnetic layer L2. The barrier layer BL may be composed of at least one or a combination of magnesium (Mg) oxide, titanium (terminal) oxide, aluminum (Al) oxide, magnesium-zinc (Mg-Zn) oxide, or magnesium-boron (Mg-B) oxide, or may include at least one or a combination of magnesium (Mg) oxide, titanium (terminal) oxide, aluminum (Al) oxide, magnesium-zinc (Mg-Zn) oxide, or magnesium-boron (Mg-B) oxide. Each of the first magnetic layer L1 and the second magnetic layer L2 may include at least one magnetic layer.

[0052] Specifically, the first magnetic layer L1 may include a reference layer (e.g., a pinned layer PL) having a magnetization direction fixed (e.g., pinned) in a specific direction, and the second magnetic layer L2 may include a free layer FL having a magnetization direction that can be changed to be parallel or antiparallel to the magnetization direction of the reference layer. However, Figure 5 and Figure 6 The example discloses a scenario where the first magnetic layer L1 includes a reference layer PL and the second magnetic layer L2 includes a free layer FL, but the example embodiment is not limited thereto. For example, with Figure 5 and Figure 6 The embodiments shown differ; the first magnetic layer L1 may include a free layer, and the second magnetic layer L2 may include a pinning layer.

[0053] In some example embodiments, such as Figure 5 As shown, the magnetization direction can be generally parallel to the interface between the barrier layer BL and the first magnetic layer L1. In this case, each of the reference layer PL and the free layer FL can be composed of or include ferromagnetic materials, and can include the same or different materials. For example, the reference layer PL can also include an antiferromagnetic material to pin the magnetization direction of the ferromagnetic material.

[0054] In some example embodiments, such as Figure 6 As shown, the magnetization direction can be substantially perpendicular to the interface between the barrier layer BL and the first magnetic layer L1. In this case, each of the reference layer PL and the free layer FL can be composed of at least one or a combination of a vertical magnetic material (e.g., CoFeTb, CoFeGd, or CoFeDy), a vertical magnetic material with an L10 structure, a CoPt-based material with a hexagonal close-packed lattice structure, and a vertical magnetic structure, or include at least one or a combination of a vertical magnetic material (e.g., CoFeTb, CoFeGd, or CoFeDy), a vertical magnetic material with an L10 structure, a CoPt-based material with a hexagonal close-packed lattice structure, and a vertical magnetic structure. The vertical magnetic material with an L10 structure can include at least one or a combination of FePt, FePd, CoPd, or CoPt with an L10 structure. The vertical magnetic structure can include alternating and repeatedly stacked magnetic and non-magnetic layers. For example, the vertical magnetic structure may include at least one or a combination of (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n, or (CoCr / Pd)n (where n is the number of stacked paired layers). Here, the thickness of the reference layer PL may be greater than the thickness of the free layer FL, or the coercivity of the reference layer PL may be greater than the coercivity of the free layer FL.

[0055] In some example embodiments, write current I1 can flow when a relatively high voltage is applied to bit line BL1 and a relatively low voltage is applied to source line SL1. In this case, the magnetization direction of the second magnetic layer L2 can be the same as that of the first magnetic layer L1, and the MTJ element can have a low resistance value (i.e., parallel state).

[0056] Conversely, when a relatively high voltage is applied to the source line SL1 and a relatively low voltage is applied to the bit line BL1, the write current I2 can flow. In this case, the magnetization direction of the second magnetic layer L2 can be opposite to that of the first magnetic layer L1, and the MTJ element can have a large resistance value (i.e., antiparallel state).

[0057] In some example embodiments, when the MTJ elements are in a parallel state, the memory cell MC can be considered as storing data with a first value (e.g., logic "0"). Conversely, when the MTJ elements are in an antiparallel state, the memory cell MC can be considered as storing data with a second value (e.g., logic "1").

[0058] At the same time, Figure 5 and Figure 6 Only one unit transistor CT is shown, but Figure 5 and Figure 6 The components shown can also be applied to Figure 4 The memory cell. In this case, unit transistors CT1 and CT2 can be connected to one end of the MTJ element. Except that the current path changes depending on which unit transistor CT1 or CT2 is conducting, the basic principles and operation of the MTJ element can be applied in the same way. Figure 4 Memory units.

[0059] Example embodiments are not limited to Figure 5 and Figure 6 Those shown, Figure 5 and Figure 6 The characteristics of these features do not necessarily imply mutual exclusion. For example, memory device 100 may include references. Figure 5 The first memory cell MC and such Figure 6 The second memory unit MC is described in the text.

[0060] Figure 7 It is shown that... Figure 4 A conceptual diagram of the configuration associated with the memory cells.

[0061] The unit transistor CT may include a body substrate 111, a gate electrode 112, and junctions 113 and 114. Junction 113 may be formed on the body substrate 111 and may be connected to the source line SL1. Junction 114 may be formed on the body substrate 111 and may be connected to the bit line BL1 via an MTJ element. The gate electrode 112 may be formed on the body substrate 111 between junctions 113 and 114 and may be connected to the word line WL1. Meanwhile, Figure 7 The configuration is exemplary. See reference... Figure 4 As described in the example embodiments, in the case where two unit transistors share a single MTJ element, the following can be employed: Figure 7 The modified version of the configuration shown. Furthermore, although... Figure 7 The example shown is a planar cell transistor CT, but the example embodiment is not limited to planar transistors.

[0062] Figure 8 It shows the relationship with Figure 5 or Figure 6 A graph relating the write status of memory cells.

[0063] As referenced above Figure 1As mentioned, the write characteristics of the memory device can vary depending on the location of the memory device on the substrate 1. For example, the resistance profile corresponding to the first memory device C1 can be different from the resistance profile corresponding to the second memory device C2. For example, the resistance value of the first memory device C1 can be substantially smaller than the resistance value of the second memory device C2. This difference could be due to the fact that the size of the MRAM cell belonging to the first memory device C1 is substantially smaller than the size of the MRAM cell belonging to the second memory device C2.

[0064] First, referring to the graph corresponding to the first memory device C1, the resistance distribution Rp1 of memory cells written in a parallel state and the resistance distribution Rap1 of memory cells written in an anti-parallel state can be distinguished by the value of the first reference resistor Rref1. For example, the first reference resistor Rref1 can be used as a reference for determining the data value stored in the MRAM cell. For example, a memory cell with a resistance value smaller than that of the first reference resistor Rref1 can be considered as storing a first value, and a memory cell with a resistance value larger than that of the first reference resistor Rref1 can be considered as storing a second value.

[0065] Next, referring to the graph corresponding to the second memory device C2, the resistance distribution Rp2 of memory cells written in a parallel state and the resistance distribution Rap2 of memory cells written in an antiparallel state can be distinguished by the value of the second reference resistor Rref2. For example, the second reference resistor Rref2 can be used as a reference for determining the data value stored in the MRAM cell. For example, a memory cell with a resistance value smaller than that of the second reference resistor Rref2 can be considered as storing a first value, and a memory cell with a resistance value larger than that of the second reference resistor Rref2 can be considered as storing a second value.

[0066] Based on the above, when the same write conditions are applied to memory devices C1 and C2 provided from the same substrate 1, errors may occur during the write operation. For example, assuming a write operation is performed under the condition that a second reference resistor Rref2 is applied to the first memory device C1, a memory cell written with a resistance value of Rap1 in an antiparallel state (specifically, belonging to...) Figure 8 The memory cell in region "A" can be considered to have a parallel state Rp1, rather than the expected antiparallel state. Instead, assuming a write operation is performed with the first reference resistor Rref1 applied to the second memory device C2, the memory cell written to have a resistance value with a parallel state Rp1 (specifically, belonging to...) Figure 8The memory cells in region "B" can be considered to have an antiparallel state Rap2, rather than the expected parallel state. For example, unexpected write errors may occur when the same reference resistor value is applied to all memory devices that are separate from the same substrate 1.

[0067] Figure 9 The invention conceptually illustrates how some example embodiments of the invention can determine an improved (e.g., optimal) value for a reference resistor for a memory device.

[0068] Reference Figure 9 In testing operations for memory devices, a pre-write operation can be performed. Here, a pre-write operation can represent or correspond to a write operation during the testing of the memory device that searches for the optimal reference resistor to distinguish between parallel and antiparallel states, rather than a write operation that stores data. For example, the write voltage level applied to the memory device during a pre-write operation can be higher than the write voltage level used in normal write operations after product shipment. This can be associated with preventing or reducing the possibility of write failures for the purpose of accurately performing test operations.

[0069] First, all or a subset of the memory cells of the memory device can be written into a parallel state using a test device (e.g., an automated test equipment (ATE)). The test device can test the memory device on substrate 1; alternatively, the test device can test the memory device after it has been diced and packaged. (Refer to...) Figure 9 “Rp” indicates the distribution of resistance values ​​of memory cells written to a parallel state. The number of fault bits in the memory device can then be counted using a testing device. For example, when counting fault bits using a relatively small reference resistor (e.g., a first reference resistor Rref1), memory cells with resistance values ​​larger than the first reference resistor Rref1 can be treated as write faults. Therefore, the number of fault bits can be very large. As the value of the reference resistor increases, the number of fault bits in the memory device can decrease. The graph indicated by G1 shows the trend of the counted number of fault bits.

[0070] All or a subset of the memory cells of a memory device can be written into an antiparallel state using a test device. Figure 9In the graph, "Rap" indicates the distribution of resistance values ​​written to memory cells in an antiparallel state. The number of fault bits in the memory device can then be counted using a testing device. For example, the number of fault bits can be very small when counting fault bits using a relatively small reference resistor (e.g., the first reference resistor Rref1). However, as the value of the reference resistor increases (e.g., to a point between the values ​​of the second reference resistor Rref2 and the third reference resistor Rref3), the number of fault bits in the memory device can increase. The graph indicated by G2 shows the trend in the number of counted fault bits.

[0071] Subsequently, the test equipment can determine the improved or optimal reference resistor value by using the number of counted fault bits. For example, the test equipment can sum a graph G1 indicating the number of fault bits measured in the parallel (P) state and a graph G2 indicating the number of fault bits measured in the anti-parallel (AP) state. The graph indicated by G3 can be plotted as the summation result. In the graph indicated by G3, the value of the reference resistor (i.e., Rref2) corresponding to a low number (e.g., the minimum number or very close to the minimum number) of fault bits can be the value of the optimal reference resistor for the memory device.

[0072] Subsequently, the test equipment can determine an improved (e.g., optimal) write voltage for the memory device based on the value of the optimal reference resistor (e.g., Rref2). The write voltage value can be derived from the pre-measured trend of the MRAM cell size, the reference resistor value based on the MRAM cell size, and the write voltage value based on the reference resistor value.

[0073] In some example embodiments, a relatively small value for the improved / optimal reference resistor (e.g., Rref1) may correspond to or indicate a relatively large size of the MRAM cell in the memory device, which may indicate the need for a relatively large write voltage value. Conversely, a relatively large value for the improved / optimal reference resistor (e.g., Rref3) may correspond to or indicate a relatively small size of the MRAM cell in the memory device, which may mean the need for a relatively small write voltage value.

[0074] Assuming the above interoperability is applied to Figure 1Given a first memory device C1 and a second memory device C2, it can be concluded that the improved / optimal reference resistor value for the first memory device C1 is relatively large (e.g., Rref3), therefore a relatively small write voltage is used or required in the write operation of the first memory device C1. As described above, it can be concluded that the improved / optimal reference resistor value for the second memory device C2 is relatively small (e.g., Rref1), therefore a relatively large write voltage is used or required in the write operation of the second memory device C2.

[0075] Finally, the test equipment can store the measured reference resistor value and its corresponding write voltage value in the memory device. After the memory device is used by the end user, the improved / optimal write voltage value stored in the memory device can be used in normal write operations. According to some example embodiments, the improved / optimal reference resistor value and its corresponding write voltage value can be determined by performing only two pre-write operations on the memory device, thus reducing the time and / or cost required to perform test operations to determine the write voltage value. Alternatively or additionally, since the improved / optimal write voltage (or current) value is selected based on the location on substrate 1 where the memory device is formed after product shipment, the reliability of the memory device during write operations can be improved, and / or the durability of the memory device can be improved.

[0076] Figure 10 This conceptually illustrates the relationship between the improved / optimal reference resistor value determined during test operations for a memory device and the corresponding improved / optimal write voltage value.

[0077] In some example embodiments, the value of the reference resistor for the memory device may be inversely proportional to the improved / optimal write voltage (or current) of the memory device corresponding to that reference resistor value. However, the reference resistor value of the memory device may not be precisely inversely proportional to the optimal write voltage value of the memory device. It should be understood that the write voltage value may decrease as the value of the reference resistor increases.

[0078] Figure 10 The diagram conceptually shows that the relatively large value of the first reference resistor Rref1 corresponds to the relatively close... Figure 1 A first memory device C1 is formed on the periphery of the substrate 1, and the corresponding improved / optimal write voltage value is a relatively small "V1". This is because the MRAM cell of the first memory device C1 has a relatively small size, which requires a relatively small write voltage.

[0079] on the contrary, Figure 10The diagram conceptually shows that the relatively small value of the second reference resistor Rref2 corresponds to the relatively close... Figure 1 The second memory device C2 is formed at the center of the substrate 1, and the corresponding improved / optimal write voltage value is a relatively large "V2". This is because the relatively large size of the MRAM cell of the second memory device C2 requires a relatively large write voltage.

[0080] Simultaneously, the relationship between the improved / optimal reference resistor value and the write voltage value of the memory device can be managed in tabular form. In some example embodiments, the reference resistor value and the write voltage (or current) value can be represented by 4 bits, but the example embodiments are not limited to this. When the reference resistor value is represented by 4 bits, for each of the fault bit counting operation for the parallel state and the fault bit counting operation for the antiparallel state, the reference... Figure 9 The described fault bit counting operation can be performed up to 16 times or less. For example, the write voltage (or current) can be variable between a first value corresponding to "1111" and a second value corresponding to "0000".

[0081] During the testing of a memory device, an improved / optimal reference resistor value (e.g., "1001") and its corresponding write voltage value (e.g., "0110") can be stored in the memory device. Alternatively or additionally, Figure 10 The table shown can be stored in the memory device. In this case, when the memory device is used by an end user, the improved / optimal reference resistor value (e.g., "1001") and the corresponding write voltage value (e.g., "0110") can be specified in a write operation. For example, the improved / optimal reference resistor value, the corresponding write voltage value, and / or the table can be stored in the antifuse array of the memory device, etc., but this disclosure is not limited thereto.

[0082] Figure 11 The invention conceptually illustrates some example embodiments of how to test a memory device based on the inventive concept. In detail, Figure 11 It can be associated with write-before operations performed on the memory device during testing.

[0083] The memory cell array 110 may include multiple memory cells, each memory cell including an MTJ element and a cell transistor. A write driver 140, a source line driver 160, and a voltage generator 182 are shown together with the memory cell array 110. For example, the voltage generator 182 may be... Figure 2The control logic circuit and voltage generator 180 are part of it. For ease of description and brevity of the figures, only “n” memory cells connected to the first bit line BL1 and the first source line SL1 are shown.

[0084] First, voltage generator 182 can be configured to generate a voltage for a pre-write operation to be performed on memory cell array 110. Here, the expression "voltage for pre-write operation" can correspond to a voltage whose level is high enough to prevent write failures at memory cells. For example, the value of the voltage for pre-write operation can be greater than the value of the write voltage used in a normal (or ordinary) write operation that can be performed by an end user, but the example embodiment is not limited thereto. For example, the value of the voltage for performing the pre-write operation can be implemented by code values ​​CV for turning on / off the various elements (e.g., various transistors) constituting write driver 140.

[0085] The write driver 140 can perform a pre-write operation on a memory cell based on a code value CV. The pre-write operation can include writing the memory cell to a parallel state and writing the memory cell to an anti-parallel state. For example, the write driver 140 can output a write current "I" corresponding to the code value CV. For example, the write driver 140 can include driver circuitry configured to generate the write current "I" for the purpose of performing a pre-write operation on a memory cell.

[0086] Figure 12 The invention conceptually illustrates some example embodiments of how test operations can be performed on a memory device according to the inventive concept. In detail, Figure 12 Implementations can be associated with determining the improved / optimal value of a reference resistor, performed during the testing of a memory device. For example, the reference resistor value can be... Figure 11 The test operation described will be executed according to the following instructions. Figure 12 The test operations are described, and for the sake of simplicity, we assume... Figure 12 The memory cells are written into a parallel state.

[0087] The memory cell array 110 may include multiple memory cells connected to multiple bit lines and multiple source lines. Each memory cell may include an MTJ element and at least one cell transistor. For simplicity, only the memory cells connected to the first bit line BL1 and the first source line SL1 are shown. The first bit line BL1 may be connected to the first node N1, and the first source line SL1 may be connected to the source line driver 160.

[0088] The reference resistor Rref can be associated with the reference voltage Vref used / necessary to read data stored in the memory cells of the memory cell array 110. For example, during the production / manufacturing of the memory device 100, the reference resistor Rref can be implemented using gate polysilicon (e.g., serpentine polysilicon) used in the gate electrode of a transistor (e.g., a single-cell transistor CT). In this case, the value of the reference resistor Rref can be easily changed by adjusting the length of the implemented gate polysilicon, the dopant concentration, etc., thus, as a reference... Figure 9 and Figure 10 The fault bits can be counted based on the value of the reference resistor Rref.

[0089] The sensing circuit 150 can be configured to read data stored in a memory cell connected to the first bit line BL1. For example, the sensing circuit 150 may include a current source that generates a first read current IRD1 and a second read current IRD2, and a sensing amplifier 152.

[0090] The first read current IRD1 can be used to sense the voltage drop in a selected memory cell of the first word line BL1. For example, the first read current IRD1 can be input to a word line (i.e., WL2) that is connected to / to the first word line BL1. As a result, a voltage drop will occur at the MTJ element that is connected to / to the second word line WL2.

[0091] The second read current IRD2 can be used to determine the voltage drop across the reference resistor Rref, which is connected to the second node N2 via the reference bit line Rref BL. For example, the second read current IRD2 can flow through the reference resistor Rref, thus causing a voltage drop at the reference resistor Rref. Figure 12 The reference current Iref is shown to indicate the current flowing through the reference resistor Rref, but the reference current Iref can be considered to be essentially the same as the second read current IRD2.

[0092] The sensing amplifier 152 can sense the voltage difference between the first node N1 and the second node N2, and can amplify the sensed voltage difference. For example, the voltage level of the first node N1 may be different from the voltage level of the second node N2. The amplified voltage difference can be output as an output voltage Vout and can be used to determine the data read from the memory cell. The sensing amplifier 152 can be implemented using a cross-coupled inverter; however, the example embodiment is not limited thereto.

[0093] In some example embodiments, during the testing of memory device 100, the number of fault bits in at least a portion of the memory cells in memory cell array 110 can be counted whenever the value of reference resistor Rref changes. For example, when at least a portion of the memory cells in memory cell array 110 are written in a parallel state, the number of fault bits based on the value of reference resistor Rref can have a similar count as... Figure 9 The trend corresponding to curve G1; when memory cells in memory cell array 110 are written in an antiparallel state, the number of fault bits can have a similar trend to the value of reference resistor Rref. Figure 9 The trend corresponding to curve G2. The testing equipment can be based on... Figure 9 The curves G1 and G2 obtain (or plot) curve G3 and / or can determine the improved / optimal value of the reference resistor corresponding to a low number (e.g., minimum number or very close to minimum number) of fault bits and the corresponding improved / optimal value of the write voltage.

[0094] Figure 13 The invention conceptually illustrates some example embodiments of how to test a memory device based on the inventive concept. In detail, Figure 13 Implementations may be associated with determining an improved (e.g., optimal) reference resistor value during the testing of a memory device. Figure 13 The embodiments are generally similar to Figure 12 Examples of implementations.

[0095] The memory cell array may include a first region 110a and a second region 110b. The memory cell array may include multiple memory cells, each memory cell including an MTJ element and a unit transistor.

[0096] The first region 110a, which serves as the area for storing data, may include memory cells connected to multiple bit lines and multiple source lines. However, for the sake of simplicity in the figures, the memory cells of the first region 110a are shown as connected to the first bit line BL1 and the first source line SL1.

[0097] The second region 110b may include components or elements necessary for generating a reference voltage Vref, which is used to read data stored in a memory cell of the first region 110a. For example, the second region 110b may include a plurality of memory cells connected to a reference bit line Ref BL and a reference source line Ref SL, as well as a resistor “R”.

[0098] In some example embodiments, the memory cells of the first region 110a and the second region 110b can be substantially the same, for example, identical in structure and electrical characteristics. The reference bit line Ref BL can be structurally substantially the same as the first bit line BL1, and the reference source line Ref SL can be structurally substantially the same as the first source line SL1. That is, the first region 110a and the second region 110b can be provided using the same manufacturing process. However, depending on the example embodiment, a resistor "R" may or may not be provided.

[0099] Sensing circuit 150 can be configured to read data stored in a memory cell connected to the first bit line BL1. Sensing circuit 150 may include at least one current source generating a first read current IRD1 and a second read current IRD2, and a sensing amplifier 152. Sensing circuit 150 can determine the voltage drop in a selected memory cell of the first bit line BL1 using the first read current IRD1.

[0100] Alternatively or additionally, the sensing circuit 150 can determine the voltage drop in the memory cell connected to the reference bit line Ref BL by using the second read current IRD2. For example, the second read current IRD2 can be input to the memory cell selected when the cell transistor CT is turned on via the reference bit line RefBL. Therefore, the voltage drop in the second region 110b can be considered as the voltage drop caused by the reference resistor Rref.

[0101] According to some example embodiments, it may not be necessary or expected to include, as referenced Figure 12 As described in the embodiment, fault bit counting is performed in the first region 110a for each reference resistor while replacing the reference resistor Rref. Alternatively, by appropriately controlling the on / off state of the cell transistor CT in the second region 110b, fault bit counting in the first region 110a can be performed while changing the value of the reference resistor Rref.

[0102] Alternatively or additionally, even if only one reference bit line Ref BL is in Figure 13 The line shown is connected to the second node N2, but more reference bit lines can be connected to the second node N2. For example, connected to a line with... Figure 13 The reference bit lines of memory cells with the same structure as the second region 110b shown can also be connected to the second node N2.

[0103] As referenced above Figure 12 and Figure 13In some of the example embodiments described, the improved / optimal value of the write voltage can be determined using the value of an improved / optimal reference resistor. The value of the reference resistor and the value of the write voltage determined therefrom can be stored in a specific area of ​​the memory device 100 (e.g., an antifuse array or other OTP area).

[0104] Figure 14 It shows Figure 11 The configuration of the driver. In detail, Figure 14 Some example embodiments may be associated with performing write operations depending on the value of the improved / optimal write voltage determined during the testing of the memory device.

[0105] Driver 140 may include (PMOS) transistors PU1 to PUp and (NMOS) transistors PD1 to PDp. Transistors PU1 to PUp may be connected between the first bit line BL1 and the first power supply voltage VDD. Transistors PD1 to PDp may be connected between the first bit line BL1 and the second power supply voltage VSS. For example, the level of the first power supply voltage VDD may be higher than the level of the second power supply voltage VSS, and the level of the voltage on the source line SL1 may be between the level of the first power supply voltage VDD and the level of the second power supply voltage VDD. For example, the power supply voltages VDD and VSS may be provided from voltage generator 182 or from a separate voltage generator.

[0106] Driver 140 can be accessed by column decoder 130 (see reference). Figure 2 The selected first bit line BL1 is connected to the memory cell MC. In some example embodiments, additional drivers, implemented in the same way as driver 140, may be provided for each bit line different from the first bit line BL1. However, for the sake of brevity in the drawings, the description associated with the additional drivers will be omitted.

[0107] Voltage generator 182 can generate code value CV for controlling driver 140. Code value CV can be based on a mapping table (e.g., a reference table) that defines the values ​​of an improved / optimal reference resistor and an improved / optimal write voltage for the memory device. Figure 10 (Described in the table). A code value CV may include a first code value CVU and a second code value CVD. The first code value CVU and the second code value CVD can be implemented using a single code value CV, or they can be provided independently of each other. Examples are provided in... Figure 14 The first code value CVU and the second code value CVD are shown as separate code values.

[0108] Each of transistors PU1 to PUp can be turned on or off based on a first code value CVU. For example, if each of transistors PU1 to Pup is a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET), each of transistors PU1 to Pup can be turned on in response to a logic "0" bit and turned off in response to a logic "1" bit.

[0109] Each of transistors PD1 through PDp can be turned on or off based on a second code value CVD. For example, in the case where each of transistors PD1 through PDp is an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET), each of transistors PD1 through PDp can be turned on in response to a logic "1" bit and turned off in response to a logic "0" bit. However, Figure 14 The configuration of drive 140 can be one configuration, and it is understood that the configuration of drive 140 can be modified or changed in various ways to be different. Figure 14 Configuration.

[0110] The conducting transistors can provide a current path for the write current I1 / I2. Therefore, transistors PU1 to Pup and transistors PD1 to PDp can drive the write current I1 / I2 based on the first code value CVU and the second code value CVD.

[0111] For example, when one or more transistors PU1 to PUp are turned on and transistors PD1 to PDp are turned off, the voltage of the first bit line BL1 can be pulled up to the first supply voltage VDD. In this case, a write current I1 can be supplied from the first bit line BL1 to the first source line SL1.

[0112] Conversely, with transistors PU1 through Pup off and one or more transistors PD1 through PDp on, the voltage of the first bit line BL1 can be pulled down to the second supply voltage VSS. In this case, a write current I2 can be supplied from the first source line SL1 to the second bit line BL1. The data state of the memory cell MC can depend on the write current I1 / I2.

[0113] The number of transistors to be turned on among transistors PU1 to Pup can vary depending on the bits of the first code value CVU. The number of transistors to be turned on among transistors PD1 to PDp can vary depending on the bits of the second code value CVD. The intensity of the write current I1 / I2 can vary depending on the number of transistors turned on.

[0114] As the number of conducting transistors increases, the intensity of the write current I1 / I2 can be increased. The intensity of the write current I1 / I2 can correspond to the sum of the currents driven by the conducting transistors. Therefore, the intensity of the write current I1 / I2 can be adjusted based on the first code value CVU and the second code value CVD.

[0115] Based on the above description, the write driver 140 can be configured to drive write currents with different amplitudes / intensities. The values ​​of the write currents I1 / I2 flowing through the memory cell MC can be adjusted to have one of the different intensities provided by the write driver 140.

[0116] Figure 15 and Figure 16 It shows the basis from Figure 14 The voltage generator 182 outputs the code value CV, which is used to operate the driver 140.

[0117] Reference Figure 15 and Figure 16 The driver 140 may include transistors PU1 to PU4 and transistors PD1 to PD4. For example, each of transistors PU1 and PD1 may have a channel width for driving a current of 40 μA, and each of transistors PU2 to PU4 and PD2 to PD4 may have a channel width for driving a current of 10 μA.

[0118] In some example embodiments, Figure 15 This can be associated with the scenario where driver 140 pulls up the voltage of the first bit line BL1 to the first supply voltage VDD. Figure 15 In one embodiment, the voltage generator 182 (see reference 182) can be used. Figure 14 The driver 140 is supplied with a voltage corresponding to the first code value CVU "0011" and a voltage corresponding to the second code value CVD "0000".

[0119] Reference Figure 15 Transistors PD1 through PD4 can be turned off in response to the second code value CVD. Transistors PU1 and PU2 can be turned on in response to a bit with logic "0" in the first code value CVU, and transistors PU3 and PU4 can be turned off in response to a bit with logic "1" in the first code value CVU. Therefore, a write current of 50μA can be driven by the turned-on transistors PU1 and PU2.

[0120] In some example embodiments, Figure 16 This can be associated with the scenario where driver 140 pulls down the voltage of the first line BL1 to the second supply voltage VSS. Figure 16In one embodiment, a first code value CVU "1111" and a second code value CVD "1100" can be provided from the voltage generator 182 to the driver 140.

[0121] Reference Figure 16 Transistors PU1 through PU4 can be turned off in response to the first code value CVU. Transistors PD1 and PD2 can be turned on in response to a bit with logic "1" in the second code value CVD, and transistors PD3 and PD4 can be turned off in response to a bit with logic "0" in the second code value CVD. Therefore, a write current of 50μA can be driven by the turned-on transistors PD1 and PD2.

[0122] In some example embodiments, Figure 15 The example implementation can be associated with the case of storing data with logic "0" in the memory cell MC. Figure 16 The embodiments can be associated with the case of storing logical "1" data in a memory cell MC. For example, in order to... Figure 10 The code values ​​of the mapping table shown are provided to the transistors PU1 to PU4 and PD1 to PD4 that constitute driver 140, and voltage generator 182 may include components such as switches and multiplexers.

[0123] For reference Figures 14 to 16 The occurrence of faulty bits can be reduced by performing write operations using an improved / optimal write voltage (or current) determined during the testing of the memory device. As a result, the reliability of the memory device can be improved. Alternatively or additionally, the durability of the memory device can be improved by preventing or reducing the likelihood of performing write operations using excessively high write voltages (or currents).

[0124] Figure 17 This is a flowchart illustrating a test method for a memory device according to some example embodiments of the inventive concept.

[0125] In operation S105, a write operation can be performed on the memory device. For example, the test device can write the memory cells constituting the memory device to have... Figure 9 The resistance distribution Rp in the parallel state.

[0126] In operation S110, a fault bit count can be performed on the memory device. In some example embodiments, the test device can count the number of fault bits of the memory cell while changing the value of the reference resistor Rref. For example, the initial value of the reference resistor Rref being "1" may simply indicate the order in which the reference resistors will be used in the test operation and may not be associated with detailed reference resistor values. For example, the value of the first selected reference resistor Rref may not indicate a low value (e.g., the minimum or very close to the minimum) of the reference resistor value to be used to perform the test operation and may be any value selected by the memory manufacturer / supplier.

[0127] Subsequently, the test equipment can count the number of fault bits in the memory cell while changing the value of the reference resistor Rref (i.e., operations S110, S115, and S120 can be repeatedly executed). When the fault bit counting operation using all the reference resistors provided for the test operation is completed, the fault bit counting operation associated with the parallel state can end.

[0128] In operation S125, a write operation can be performed on the memory device. For example, the test device can write the memory cells constituting the memory device to have... Figure 9 The resistance distribution Rap in the antiparallel state.

[0129] In operation S130, a fault bit count can be performed on the memory device. In some example embodiments, the test device can count the number of fault bits in the memory cell while changing the value of the reference resistor Rref. As in the fault bit count associated with a parallel state, the value of the reference resistor Rref selected in the fault bit count can be randomly selected from the provided reference resistor values, regardless of the order of the reference resistor values.

[0130] The test equipment can count the number of fault bits in the memory cell while changing the value of the reference resistor Rref (i.e., operations S130, S135, and S140 can be performed repeatedly); when the fault bit counting operation using all the reference resistor values ​​provided for the test operation is completed, the fault bit counting operation associated with the antiparallel state can end.

[0131] In operation S145, the improved / optimal reference resistor value can be determined based on the fault bit count results. For example, for each reference resistor value, the test equipment can add the number of fault bits counted in the parallel state and the number of fault bits counted in the antiparallel state, and can select the lower of the addition results (e.g., the minimum addition result or very close to the minimum addition result (e.g., + / - 10% of the minimum addition result)) as the improved / optimal reference resistor value.

[0132] In operation S150, an improved or optimal write voltage (or current) value corresponding to the value of the optimal reference resistor can be determined. In some example embodiments, the value of the reference resistor and the value of the write voltage can have, for example, […]. Figure 10 The trend shown in the graph is as described (e.g., an inverse proportional relationship or a reciprocal relationship). Therefore, a relatively small write voltage (or current) may be required relative to substrate 1 (refer to...). Figure 1 The memory device formed on the periphery of ) (e.g., Figure 1 Write to C1). Conversely, a relatively large write voltage (or current) may be required for memory devices formed relatively close to the center of substrate 1 (e.g., C1). Figure 1 Write to C2).

[0133] In operation S155, the value of the optimal write voltage (or current) can be stored in the memory device. In some example embodiments, the value of the optimal reference resistor and the value of the optimal write voltage (or current) can be stored in the memory device. Alternatively or additionally, such as Figure 10 As shown, a mapping table defining the write voltage values ​​corresponding to the values ​​of each reference resistor can be stored in the memory device. In this case, the values ​​of the reference resistors and the write voltage values ​​corresponding to the memory device provided to the end user can be specified during a write operation. In some example embodiments, the values ​​of the optimal reference resistors, the corresponding write voltage values, and / or the table can be stored in the antifuse array, etc., of the memory device, but this disclosure is not limited thereto.

[0134] Figure 18 A test system according to some example embodiments of the inventive concept is shown. The test system 1000 may include a memory device 1100 and a test device 1200.

[0135] Memory device 1100 includes a memory cell array 1110. In some example embodiments, memory device 1100 may be a reference... Figures 1 to 17An implementation example of the described memory device 100. The memory cell array 1110 may include a first region 1112 and a second region 1114. For example, the first region 1112, as a user region, may be an area where data intended by the user is stored. The second region 1114, as a supplier region, may be an area where data intended by the memory manufacturer / supplier is stored. For example, refer to... Figures 1 to 17 The improved / optimal reference resistor value and the improved / optimal write voltage value described can be stored in the second region 1114.

[0136] Test device 1200 can perform various test operations on memory device 1100. To do this, test device 1200 can send the command CMD to memory device 1100.

[0137] In some example embodiments, the command CMD may include a command for writing a first region 1112 of the memory cell array 1110 to a specific write state (e.g., parallel or antiparallel). The test device 1200 may send dummy write data DATA_DW along with the command CMD for writing the first region 1112 to a parallel or antiparallel state.

[0138] In some example embodiments, the command CMD can instruct a read operation to count the number of fault bits for each reference resistor for a specific write state (e.g., parallel or antiparallel). Read data DATA_RD can be received from memory device 1100 as the read result.

[0139] In some example embodiments, test device 1200 may count the number of fault bits for each reference resistor based on read data DATA_RD received from memory device 1100, determine the improved / optimal value of reference resistor Rref based on the counting result, and determine the improved / optimal value of write voltage (or current) based on the value of optimal reference resistor Rref.

[0140] In some example embodiments, test device 1200 may store the improved / optimal reference resistor Rref value and the improved / optimal write voltage (or current) value in a table in memory device 1100. For example, this table may be stored in a second region 1114 of memory cell array 110. For example, the second region 1114 may include an antifuse cell array.

[0141] Meanwhile, some example embodiments are described as performing pre-write operations, fault bit counting operations, operations to determine the value of an improved / optimal reference resistor, and operations to determine the value of an improved / optimal write voltage on a unit basis of memory device (e.g., semiconductor chip). However, in some example embodiments, the value of the improved / optimal write voltage may be determined based on different references rather than memory device (i.e., semiconductor chip) cells. For example, in a memory device, because the memory cells are at different distances from the center of substrate 1, the memory cells can be classified into multiple regions, and the value of the improved / optimal write voltage can be determined for each region.

[0142] According to some example embodiments, the improved / optimal values ​​of the reference resistor and the write voltage (or current) of the memory device can be determined by performing only two pre-write operations on the memory device (e.g., associated with parallel and antiparallel states, respectively). Therefore, the time and / or cost required to determine the improved / optimal write voltage value can be reduced. Alternatively or additionally, the reliability and durability of the memory device can be improved because programming operations are performed by determining / optimizing the write voltage (or current) based on the characteristics of the memory device (e.g., the size of the MRAM cell).

[0143] According to some example embodiments, it is possible to determine the improved / optimal value of a reference resistor by a small number / minimal number of write operations, and to determine the improved / optimal value of the write voltage based on the value of the resistor thus determined.

[0144] In this case, the durability of the memory device is improved by preventing the memory device from being written to by excessive voltage (or current) or reducing the likelihood of the memory device being written to by excessive voltage (or current).

[0145] Alternatively or additionally, the memory device is prevented from being written to by insufficient voltage (or current) or the likelihood of the memory device being written to by insufficient voltage (or current) is reduced, thereby improving the reliability of the memory device.

[0146] While some exemplary embodiments have been described with reference to their embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A memory device, comprising: The memory cell array includes a first region and a second region, the second region being configured to store the value of a write voltage based on the value of a reference resistor used to determine whether the programmed memory cell is in a parallel or antiparallel state. A voltage generator configured to generate code values ​​based on the write voltage value; as well as The write driver is configured to drive the write current based on a code value; the write current is the current used to store data in the first region. The value of the reference resistor is determined based on the minimum value obtained by summing the first and second results for each of a plurality of resistance values. The first result is obtained by counting the number of fault bits in the first region programmed to the first state for each of the plurality of resistance values. The second result is obtained by counting the number of fault bits in the first region programmed into the second state for each of the plurality of resistance values.

2. The memory device of claim 1, wherein the memory cell array comprises a plurality of memory cells, and Each of the plurality of memory units includes: A unit transistor includes a first terminal, a second terminal, and a gate electrode, the first terminal being connected to a source line and the gate electrode being connected to a word line; as well as A magnetic tunnel junction includes a first end and a second end. The first end of the magnetic tunnel junction is connected to the second end of the unit transistor, and the second end of the magnetic tunnel junction is connected to a bit line.

3. The memory device according to claim 1, further comprising: A current source is configured to generate a first read current and a second read current. as well as The sensing circuit includes a sensing amplifier configured to amplify the difference between a first voltage drop and a second voltage drop, the first voltage drop being at a first node based on the application of a first read current to a first bit line, the first bit line being connected to a selected memory cell, and the second voltage drop being at a second node based on the application of a second read current to a reference bit line.

4. The memory device according to claim 3, further comprising: A resistor having the value of a reference resistor connected to a reference bit line.

5. The memory device of claim 4, wherein the gate electrode of the transistor included in the memory cell array corresponds to gate polysilicon, and Resistors with a reference resistor value include gate polysilicon.

6. The memory device according to claim 3, further comprising: At least one first memory cell, wherein the at least one first memory cell is connected to a reference bit line, and the at least one first memory cell is structurally identical to the selected memory cell.

7. The memory device of claim 1, wherein the write driver comprises: At least one transistor of a first type, each of the at least one transistor of the first type includes a first terminal connected to a first power supply voltage and a second terminal connected to an output node; as well as At least one transistor of the second type, each of the at least one transistor of the second type including a first terminal connected to a second power supply voltage and a second terminal connected to an output node.

8. The memory device of claim 7, wherein the code value includes a first code value and a second code value. The at least one transistor of the first type is configured to receive bits of a first code value from a voltage generator, and The at least one transistor of the second type is configured to receive bits of the second code value from the voltage generator, respectively.

9. The memory device of claim 1, wherein the second region comprises an antifuse cell array.

10. A method of operating a memory device, the method comprising: Write the memory device to the first state; The number of fault bits in a memory device programmed to the first state is counted by using each of the resistance values ​​of a plurality of resistors with different values. Write the memory device to the second state; The number of fault bits in the memory device programmed to the second state is counted by using the plurality of resistors. For each of the multiple resistance values, sum the number of fault bits associated with the first state and the number of fault bits associated with the second state; Select the resistor corresponding to the minimum value among the summation results as the reference resistor; as well as The memory device determines the write voltage value based on the value of the reference resistor.

11. The method of claim 10, further comprising: The value of the reference resistor is stored in a memory device, and The determined write voltage value is stored in the memory device.

12. The method of claim 11, wherein storing the value of the reference resistor and storing the value of the determined write voltage comprises: The value of the reference resistor is stored in the antifuse array of the memory device, and The determined write voltage value is stored in the antifuse array of the memory device.

13. The method of claim 10, wherein the memory device comprises a memory cell array, the memory cell array comprising magnetic random access memory (MRAM) cells.

14. A memory device, comprising: A memory cell array includes a first region and a second region, the second region being configured to store the value of a reference resistor and the value of a write voltage, the value of which is determined based on the value of the reference resistor, which is determined based on: a first result of counting the number of fault bits of the first region programmed to a first state for each of a plurality of resistor values, and a second result of counting the number of fault bits of the first region programmed to a second state for each of the plurality of resistor values. The column decoder is configured to select bit lines connected to memory cells, which are selected from memory cells in a first region. The line decoder is configured to drive the word lines connected to the selected memory cells; A voltage generator configured to generate a code value based on the value of the written voltage; as well as The write driver is configured to drive the write current and provide the driven write current to the selected memory cell through the selected bit line. The write current is the current used to store data in the selected memory cell and is based on the code value.

15. The memory device of claim 14, wherein each memory cell in the first region comprises: A unit transistor includes a first terminal, a second terminal, and a gate electrode, the first terminal being connected to a source line and the gate electrode being connected to a first word line among word lines; as well as A magnetic tunnel junction includes a first end and a second end. The first end of the magnetic tunnel junction is connected to the second end of the unit transistor, and the second end of the magnetic tunnel junction is connected to the first bit line among the bit lines.

16. The memory device of claim 14, further comprising: The sensing circuit is configured to perform a read operation on the selected memory cell. The sensing circuit includes: The first current source is configured to generate the first read current. The second current source is configured to generate the second read current, and A sensing amplifier configured to amplify the difference between a first voltage drop at a first node applied to a bit line connected to a selected memory cell according to a first read current and a second voltage drop at a second node applied to a reference bit line according to a second read current.

17. The memory device of claim 14, wherein the write driver comprises: At least one transistor of a first type, each of the at least one transistor of the first type includes a first terminal connected to a first power supply voltage and a second terminal connected to an output node; as well as At least one transistor of the second type, each of the at least one transistor of the second type including a first terminal connected to a second power supply voltage and a second terminal connected to an output node.

18. The memory device of claim 17, wherein the code value includes a first code value and a second code value. The at least one transistor of the first type is configured to receive bits of a first code value from a voltage generator, and The at least one transistor of the second type is configured to receive bits of the second code value from the voltage generator, respectively.

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