Graph data pre-fetching method, processor and electronic device

Abstract

The embodiment of the present invention provides a graph data prefetching method, a processor and an electronic device, and relates to the computer field. The method includes: obtaining a memory access address sent by a processor core to a private cache, and obtaining memory access data through the memory access address by the private cache. When the memory access address is located in an edge array, determining that the memory access data includes multiple vertex numbers, and determining multiple target vertex numbers in the edge array based on the multiple vertex numbers. The storage position of the vertex to which the target vertex number belongs in the vertex array is used as the first prefetch address, so that the private cache pre-stores the attribute value of the vertex to which the target vertex number belongs in the private cache. When the processor core accesses the data in the edge array, the data in the vertex array that the processor core is about to access is determined, and the data is pre-stored in the private cache. When the processor core accesses the data in the vertex array, the private cache can quickly provide the processor core with the data, thereby improving the efficiency of graph calculation.

Description

Technical Field

[0001] The present invention relates to the field of computers, and in particular to a graph data pre-fetching method, a processor and an electronic device. Background Art

[0002] A graph is an abstract data structure used to represent the relationship between objects. It is described using vertices and edges. Vertices represent objects, and edges represent the relationship between objects. Data that can be abstracted into graphs is called graph data. Usually, graph data is stored in the format of Compressed Sparse Row (CSR). The CSR format uses offset arrays, edge arrays, and vertex arrays to store graph data. The offset array stores a position data corresponding to each vertex. The edge array stores the destination vertex numbers corresponding to all connected edges when each vertex is used as a source vertex in vertex order. The vertex array stores the attribute values ​​of each vertex.

[0003] Graph computing is the process of expressing and solving problems with graph data. Graph computing usually adopts a vertex-centric computing mode. When calculating the attribute value of each vertex, it is necessary to read the attribute values ​​of the vertices adjacent to the vertex. Therefore, when performing graph computing, the processor (Central Processing Unit, CPU) accesses the graph data randomly, making it impossible for the cache to pre-read the graph data that the CPU is about to access into the cache. The CPU needs to read data from the memory frequently, resulting in low efficiency of graph computing. Summary of the invention

[0004] In view of the above problems, an embodiment of the present invention is proposed to provide a graph data pre-fetching method that overcomes the above problems or at least partially solves the above problems, so as to solve the problem of low efficiency in the graph calculation process.

[0005] Correspondingly, the embodiment of the present invention also provides a processor and an electronic device to ensure the implementation and application of the above method.

[0006] In order to solve the above problems, an embodiment of the present invention discloses a graph data prefetching method, which is applied to a prefetcher, wherein the prefetcher is arranged in a processor, and the processor also includes a processor core and a private cache corresponding to the prefetcher; the method includes:

[0007] Acquire a memory access address sent by the processor core to the private cache, and memory access data acquired by the private cache through the memory access address;

[0008] In the case where the access address is within the storage range of the edge array, determining that the access data includes a plurality of vertex numbers stored in the edge array; the edge array is used to store the numbers of destination vertices corresponding to the vertices in the graph data as source vertices;

[0009] Based on the multiple vertex numbers, determining multiple target vertex numbers in the edge array;

[0010] Using the storage position of the vertex to which the target vertex number belongs in the vertex array as the first pre-fetch address; the vertex array is used to store the attribute values ​​of the vertices in the graph data;

[0011] The first pre-fetch address is sent to the private cache, so that the private cache pre-stores the attribute value of the vertex to which the target vertex number belongs in the private cache through the first pre-fetch address.

[0012] Optionally, the private cache includes a first-level cache;

[0013] The determining a plurality of target vertex numbers in the edge array based on the plurality of vertex numbers comprises: using the plurality of vertex numbers as the target vertex numbers;

[0014] The sending the first pre-fetch address to the private cache so that the private cache stores the attribute value of the vertex to which the target vertex number belongs in advance in the private cache through the first pre-fetch address includes:

[0015] The first prefetch address is sent to the first-level cache, so that the first-level cache pre-stores the attribute value of the vertex to which the target vertex number belongs in the first-level cache through the first prefetch address.

[0016] Optionally, the private cache includes a secondary cache;

[0017] The step of determining a plurality of target vertex numbers in the edge array based on the plurality of vertex numbers comprises: in the case where it is determined that a plurality of vertices to which the plurality of vertex numbers belong are densely stored, determining a preset number of vertex numbers starting from the vertex number with the largest number as the target vertex numbers;

[0018] The sending the first pre-fetch address to the private cache so that the private cache stores the attribute value of the vertex to which the target vertex number belongs in advance in the private cache through the first pre-fetch address includes:

[0019] The first pre-fetch address is sent to the secondary cache, so that the secondary cache stores the attribute value of the vertex to which the target vertex number belongs in advance in the secondary cache through the first pre-fetch address.

[0020] Optionally, the memory access address is obtained by adding a starting address offset value to the starting address of the edge array; the processor core obtains the starting address offset value and the ending address offset value corresponding to the currently processed vertex from the offset array of the graph data in advance;

[0021] Before taking the storage position of the vertex to which the target vertex number belongs in the vertex array as the first pre-fetch address, the method further includes:

[0022] Determine a termination offset address corresponding to the memory access address; the termination offset address is obtained by adding the termination address offset value to the start address of the edge array;

[0023] The vertex numbers whose storage locations are after the end offset address are removed from the plurality of target vertex numbers.

[0024] Optionally, the method further comprises: when the access address is within the storage range of an offset array, determining that the access data includes a starting address offset value corresponding to a currently processed vertex; the offset array is used to store the starting address offset values ​​corresponding to the vertices in the graph data;

[0025] Using multiple addresses after the first address in the edge data group as second pre-fetch addresses; the first address is obtained by adding the starting address offset value to the starting address of the edge array;

[0026] The second prefetch address is sent to the private cache, so that the private cache pre-stores the vertex number stored in the second prefetch address in the private cache through the second prefetch address.

[0027] Optionally, the method further comprises:

[0028] In the case where the memory access address is within the storage range of the edge array, a preset number of addresses after the memory access address are used as second pre-fetch addresses;

[0029] The second prefetch address is sent to the private cache, so that the private cache pre-stores the vertex number stored in the second prefetch address in the private cache through the second prefetch address.

[0030] Optionally, before sending the second prefetch address to the private cache, the method further includes:

[0031] The second prefetch address located after the second address is deleted from the multiple second prefetch addresses; the second address is obtained by adding the end address offset value to the start address of the edge array, and the end address offset value is included in the memory access data and corresponds to the current processing vertex.

[0032] Optionally, before sending the second prefetch address to the private cache, the method further includes:

[0033] The second prefetch address located after the second address is deleted from the multiple second prefetch addresses; the second address is obtained by adding the end address offset value to the start address of the edge array, and the end address offset value is included in the memory access data and corresponds to the current processing vertex.

[0034] The embodiment of the present invention further discloses a processor, comprising at least one processor core, and a prefetcher and a private cache corresponding to the processor core;

[0035] The processor core is connected to the private cache and is used to send a memory access address to the private cache so that the private cache obtains memory access data through the memory access address;

[0036] The prefetcher is connected to the private cache, and is used to obtain the access address and the access data from the private cache, and when the access address is within the storage range of the edge array, determine that the access data includes a plurality of vertex numbers stored in the edge array, and determine a plurality of target vertex numbers in the edge array based on the plurality of vertex numbers, use the storage position of the vertex to which the target vertex number belongs in the vertex array as a first prefetch address, and send the first prefetch address to the private cache;

[0037] The private cache is used to receive the first pre-fetch address, and pre-store the attribute value of the vertex to which the target vertex number belongs in the private cache through the first pre-fetch address;

[0038] The vertex array is used to store the attribute values ​​of the vertices in the graph data, and the edge array is used to store the numbers of the corresponding destination vertices when the vertices in the graph data are used as source vertices.

[0039] The embodiment of the present invention further discloses an electronic device, including the processor as described above. The embodiment of the present invention has the following advantages:

[0040] In an embodiment of the present invention, the prefetcher obtains the memory access address sent by the processor core to the private cache, and the memory access data obtained by the private cache through the memory access address. When the memory access address is within the storage range of the edge array, it is determined that the memory access data includes multiple vertex numbers stored in the edge array, and based on the multiple vertex numbers, multiple target vertex numbers in the edge array are determined. The storage position of the vertex to which the target vertex number belongs in the vertex array is used as the first prefetch address, and the first prefetch address is sent to the private cache, so that the private cache pre-stores the attribute value of the vertex to which the target vertex number belongs in the private cache through the first prefetch address. During the graph calculation process, when the processor core accesses the data in the edge array, the data in the vertex array that the processor core is about to access is determined, and the data is pre-stored in the private cache. When the processor core accesses the data in the vertex array, the private cache can quickly provide the processor core with the data, which can shorten the access delay of the processor core, thereby improving the efficiency of graph calculation. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of the structure of graph data in an embodiment of the present invention is shown;

[0042] Figure 2 A schematic diagram of storing graph data in an embodiment of the present invention is shown;

[0043] Figure 3 A flowchart showing a method for pre-fetching graph data according to an embodiment of the present invention is shown;

[0044] Figure 4 A schematic diagram of a partial structure of a processor in an embodiment of the present invention is shown;

[0045] Figure 5 A schematic diagram of the structure of a prefetcher in an embodiment of the present invention is shown;

[0046] Figure 6 A logic schematic diagram of a vertex array address generator in an embodiment of the present invention is shown;

[0047] Figure 7 A logical schematic diagram of an edge array address generator in an embodiment of the present invention is shown;

[0048] Figure 8 A structural block diagram of an electronic device in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0049] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] In order to introduce the present invention in more detail, firstly, the graph data and the method of reading the graph data are briefly introduced.

[0051] Graph data consists of a set of vertices and a set of edges between vertices. A vertex in graph data can represent an object in the real or virtual world. The attribute value of the vertex represents the characteristics of the object. The edges between vertices can represent the relationship between objects. For example, a vertex can represent a person. The attribute value of the vertex includes characteristics such as age, gender, and preferences. The edge connecting two vertices can represent the relationship between the two people, such as father and son, colleagues, or friends. Figure 1 A schematic diagram of the structure of a graph data in an embodiment of the present invention is shown, wherein the graph data includes vertices 0 to 4. Figure 1 Each circle in the graph represents a vertex. The number in the circle represents the object corresponding to the vertex and also represents the number of the vertex. Each vertex is directly or indirectly connected by an edge. The edge has a direction. The vertex from which the edge starts is the source vertex, and the vertex to which the edge points is the destination vertex. For example, edge 101 points from vertex 0 to vertex 1. Vertex 0 is the source vertex corresponding to vertex 1, and vertex 1 is the destination vertex corresponding to vertex 0 as the source vertex.

[0052] like Figure 2 As shown, Figure 2 The diagram of graph data storage in the embodiment of the present invention is shown. When the graph data is stored in CSR format, the graph data is stored together by the offset array, the edge array and the vertex array. The vertex array 203 stores the attribute value of each vertex in sequence according to the vertex numbering order, that is, it stores each vertex in the graph data; the edge array 202 stores the number of the destination vertex corresponding to each vertex as the source vertex in sequence according to the vertex numbering order. The corresponding relationship between the source vertex and the destination vertex can represent the edge between the vertices, that is, the edge array 202 can store the edge in the graph data; the offset array 201 stores the position information corresponding to each vertex in the vertex array 203 in sequence, and the position information includes the starting address offset value and the ending address offset value ( Figure 2 Only the starting address offset value is shown in the figure), the starting address offset value and the ending address offset value define the storage location of the numbers of all destination vertices corresponding to the vertex as the source vertex in the edge array 202. For example, Figure 1 The attribute values ​​of vertices 0 to 4 in the vertex array 203 are stored in sequence. The symbols D0, D1, D2, D3 and D4 in the vertex array 203 represent vertex 0, vertex 1, vertex 2, vertex 3 and vertex 4 respectively. The first position in the offset array 201 stores the starting address offset value and the ending address offset value corresponding to vertex 0. The starting address offset value is Figure 2The number 0 shown, the end address offset value 2, the start address offset value 0 and the end address offset value 2 define a storage area in the edge array 202, that is, the start address offset value 0 is added to the start address X of the edge array 202 to obtain the start offset address (X+0), the start offset address is the first bit in the edge array 202, and the end address offset value 2 is added to the start address X of the edge array 202 to obtain the end offset address (X+2), the end offset address is the third bit in the edge array 202. Figure 2 As shown, the first bit of edge array 202 stores the number of vertex 1, the second bit stores the number of vertex 2, and the third bit stores the number of vertex 3. Vertex 1, vertex 2, and vertex 3 are all corresponding destination vertices when vertex 0 is used as the source vertex. Similarly, the second bit of offset array 201 stores the starting address offset value and the ending address offset value corresponding to vertex 1.

[0053] In the embodiments of the present invention, the graph computing framework adopts a vertex-centric computing mode. In this computing mode, when the CPU calculates the attribute value of a vertex, it first reads the position data corresponding to the vertex from the offset array, that is, the position data, that is, the position information, obtains the starting address offset value and the ending address offset value, and then determines a storage range in the edge array according to the starting address offset value and the ending address offset value, reads the corresponding destination vertex number from the storage range, and finally reads the attribute value of the vertex to which the destination vertex number belongs from the vertex array according to the destination vertex number. For example, when calculating the attribute value of vertex 0 (vertex 0 is the currently processed vertex), first read the first position data in offset array 201 corresponding to vertex 0 from offset array 201, including the starting address offset value 0 and the ending address offset value 2, then determine the starting offset address (i.e., the first bit in edge array 202) from edge array 202 based on the starting address offset value 0 and the starting address of edge array 202, and determine the ending offset address (i.e., the third bit in edge array 202) from edge array 201 based on the ending address offset value 2 and the starting address of edge array 202, then read the vertex numbers from the first to the third digits from edge array 202, i.e., the number of vertex 1, the number of vertex 2, and the number of vertex 3, finally read the attribute value of vertex 1, the attribute value of vertex 2, and the attribute value of vertex 3 from vertex array 203 based on the number of vertex 1, the number of vertex 2, and the number of vertex 3, to calculate the attribute value of vertex 0.

[0054] The specific process of graph calculation is implemented by the processor core in the processor. When performing graph calculation, the processor core first reads the graph data from the private cache. If the private cache does not store the corresponding graph data, the private cache reads the corresponding graph data from the shared cache (the shared cache can also be called the third-level cache) and sends it to the private cache. If the shared cache does not store the corresponding graph data, the shared cache reads the corresponding graph data from the memory and sends it to the private cache. Figure 1 and Figure 2 As shown, when the processor core calculates the attribute value of vertex 2 (vertex 2 is the current processing vertex), the destination vertices corresponding to vertex 2 as the source vertex include vertex 3 and vertex 4. The processor core can first send a memory access request including a memory access address to the private cache. The memory access address corresponds to the third bit in the offset array 201 (the third bit corresponds to the storage position of vertex 2 in the vertex array 203), and the position data corresponding to vertex 2 is stored. After the private cache returns the position data to the processor core, the processor core can calculate the starting offset address and the ending offset address according to the position data and the starting address of the edge array 202. The starting offset address is the fifth bit in the edge array 202, and the ending offset address is the sixth bit in the edge array 202. The fifth bit stores the number of vertex 3, and the sixth bit stores the number of vertex 4. At this time, the processor core needs to obtain the vertex numbers stored in the fifth and sixth bits in the edge array 202 according to the starting offset address. The processor core can send a memory access request including a memory access address to the private cache, and the memory access address is the calculated starting offset address. If the private cache stores number 3 corresponding to the starting offset address, number 3 is returned to the CPU. If number 3 is not stored, number 3 is obtained from the shared cache through the above process.

[0055] One of the core concepts of an embodiment of the present invention is that, based on the storage and reading method of graph data, after reading the vertex number from the edge array, the attribute value of the corresponding vertex in the vertex array is pre-read and stored in a private cache based on the vertex number, avoiding reading the attribute value of the vertex from the memory, thereby shortening the memory access delay of the processing core and improving the efficiency of graph calculation.

[0056] Reference Figure 3 , shows a flowchart of a method for pre-fetching graph data in an embodiment of the present invention, the method may include the following steps:

[0057] Step 301: Obtain a memory access address sent by a processor core to a private cache, and memory access data obtained by the private cache through the memory access address.

[0058] Step 302: When the memory access address is within the storage range of the edge array, determine that the memory access data includes multiple vertex numbers stored in the edge array.

[0059] The edge array is used to store the numbers of the destination vertices corresponding to the vertices in the graph data as source vertices.

[0060] In this embodiment, the graph data prefetching process can be implemented by a prefetcher (Graph Structure Prefetcher, GSP), which is set in a processor, and the processor also includes a processor core and a private cache corresponding to the prefetcher. Figure 4 As shown, Figure 4 A schematic diagram of the local structure of a processor in an embodiment of the present invention is shown. The CPU includes one or more processor cores. A corresponding prefetcher and a corresponding private cache are respectively set for each processor core in the processor. The private cache can be composed of a first-level cache and a second-level cache. The processor core is connected to the corresponding prefetcher and the corresponding first-level cache. The first-level cache is connected to the second-level cache. The first-level cache is a first-level data cache, which is used to store data read from the second-level cache for the processor core to read. The second-level cache is used to store data read from the shared cache for the first-level cache to read. The shared cache is set outside the CPU. The shared cache is used to read data from the memory for the second-level cache to read. When the processor core processes a vertex, the vertex is the current processing vertex. The processor core first sends a memory access request to the private cache to read the corresponding data from the private cache for graph calculation. After receiving the memory access request sent by the processor core, the private cache can obtain the data stored in the memory access address from the shared cache according to the memory access address included in the memory access request, and send the obtained data to the processor core, or send the data corresponding to the memory access address that has been stored in the private cache to the processor core. Among them, the private cache is connected to the prefetcher. After receiving the memory access request sent by the processor core, the private cache can also send the memory access address included in the memory access request to the prefetcher, and after obtaining the memory access data according to the memory access address, send the memory access data to the prefetcher.

[0061] In this embodiment, the private cache is composed of a first-level cache and a second-level cache. When the processor core processes a certain vertex, it can first send a memory access request to the first-level cache to read the corresponding data from the first-level cache for graph calculation. After receiving the memory access request sent by the processor core, the first-level cache can obtain the data stored in the memory access address from the second-level cache according to the memory access address included in the memory access request, and send the obtained data to the processor core, or send the data corresponding to the memory access address already stored in the first-level cache to the processor core. The first-level cache is connected to the prefetcher. After receiving the memory access request sent by the processor core, the first-level cache can also send the memory access address included in the memory access request to the prefetcher, and after obtaining the memory access data according to the memory access address, send the memory access data to the prefetcher. The specific process of the prefetcher obtaining the memory access address and memory access data from the first-level cache can be set according to demand, and this embodiment does not limit this.

[0062] Correspondingly, after receiving the access address sent by the first-level cache, the prefetcher first determines whether the access address is within the storage range of the edge array. If the access address is within the storage range of the edge array, it can be determined that the access data obtained by the prefetcher according to the access address stores the vertex number in the edge data. Figure 5 As shown, Figure 5 The schematic diagram of the structure of a prefetcher in an embodiment of the present invention is shown. The prefetcher includes an address register, an address generator and a cache unit. The address register and Figure 4 The first-level cache in the processor core is connected, and the address register can be configured as a register that can be read and written by the user state. Before performing graph calculation, the processor core can write the starting address and ending address of the offset array 201, the starting address and ending address of the edge array 202, and the starting address and ending address of the vertex array 203 into the address register. After the address register receives the memory access address sent by the first-level cache, it can compare the memory access address with the pre-written starting address and ending address. If it is determined that the memory access address is within the storage range defined by the starting address and ending address of the edge array 202, it can be determined that the memory access address is within the storage range of the edge array 202. Further, it can be determined that the memory access data obtained by the first-level cache through the memory access address is the data stored in the edge array 202, including multiple vertex numbers stored in the edge array 202.

[0063] In the process of obtaining data, the first-level cache obtains the data amount of one cache line each time. For example, if 64 bytes of binary data can be stored in a cache line, and the data amount of each vertex number is 4 bytes, then the first-level cache can obtain 16 vertex numbers from the second-level cache each time, that is, 64 bytes of binary data. After receiving the access data sent by the first-level cache and determining that multiple vertex numbers are stored in the access data, the prefetcher can determine that the vertex number of the destination vertex corresponding to the current processing vertex as the source vertex is stored in the multiple vertex numbers. Combined with the above example, if the current processing vertex is vertex 2, the processor core needs to obtain the number of the destination vertex corresponding to vertex 2 from the edge array 202. At this time, the access address sent by the processor core to the first-level cache is the address of the 5th bit in the edge array 202, and the data amount of one cache line can be obtained from the second-level cache, including 16 vertex numbers, that is, the access data includes 16 vertex numbers, and the 16 vertex numbers include the vertex numbers of vertex 3 and vertex 4. In actual applications, the number of destination vertices corresponding to each vertex as a source vertex is uncertain, so the number of vertex numbers of the destination vertices corresponding to the currently processed vertex may be less than the number of vertex numbers that can be accommodated in a cache line, or it may be greater than the number of vertex numbers that can be accommodated in a cache line. The specific size of the cache line can be set according to demand, and the amount of data for each vertex number is determined according to the type of graph data, which is not specifically limited in this embodiment.

[0064] It should be noted that when the processor core sends the memory access address to the first-level cache, it can first send the memory access address to the Data Translation Lookaside Buffer (DTLB) in the processor. The memory access address is a virtual address. After the DTLB converts the virtual address into a physical address, it sends the converted physical address to the first-level cache. The first-level cache obtains data from the second-level cache according to the received physical address. Figure 4 As shown, the processor also includes a DTLB, which is connected to the processor core, the first-level cache and the prefetcher respectively. The memory access address sent by the first-level cache to the prefetcher is also a physical address. The start address and the end address pre-written in the address register can be virtual addresses. The address register can determine whether the received physical address is within the storage range of the edge array according to the corresponding relationship between the virtual address and the physical address. Alternatively, the address register can convert the received physical address into a virtual address to determine whether the received physical address is within the storage range of the edge array.

[0065] Step 303: Based on the multiple vertex numbers, determine multiple target vertex numbers in the edge array.

[0066] Step 304: Use the storage location of the vertex to which the target vertex number belongs in the vertex array as the first pre-fetch address.

[0067] Among them, the vertex array is used to store the attribute values ​​of the vertices in the graph data.

[0068] Optionally, step 303 may include: using multiple vertex numbers as target vertex numbers.

[0069] In one embodiment, after determining that the access data includes multiple vertex numbers stored in the edge array, the prefetcher can determine that the processor core is about to access the attribute value of the vertex to which the vertex number belongs, and can directly use the determined vertex number as the target vertex number. Combined with the above example, when the processor core calculates the attribute value of vertex 2, if the vertex number of the destination vertex corresponding to vertex 2 as the source vertex is obtained from the first-level cache, that is, the number of vertex 3 and vertex 4, then the processor core needs to obtain the attribute value of vertex 3 and the attribute value of vertex 4 from vertex array 203 in the next step to calculate the attribute value of vertex 2. At this time, the prefetcher can use the vertex number of vertex 3 and the vertex number of vertex 4 as the target vertex number, and determine the storage position of vertex 3 in vertex array 203, as well as the storage position of vertex 4 in vertex array 203, and use the determined storage position as the first prefetch address.

[0070] like Figure 5 As shown, the address generator is connected to the address register. After determining that the access data includes the vertex number, the address register can send the access data sent by the first-level cache to the address generator, that is, send the vertex number to the address generator. The address generator includes a vertex array address generator, which can determine the storage location of the vertex to which the vertex number belongs in the vertex array 203 according to the vertex number. Figure 6 As shown, Figure 6 The logic diagram of a vertex array address generator in an embodiment of the present invention is shown. The access data obtained by the prefetcher from the first-level cache includes V0 to V n Since the vertex array 203 stores the attribute value of each vertex in sequence according to the vertex number, the storage position of the vertex to which the vertex number belongs in the vertex array 203 can be determined by adding the product of the data amount of each vertex number and the vertex number to the starting address of the vertex array 203. Figure 2 As shown, vertex 3 is stored in the fourth position of vertex array 203, vertex 3 is numbered 3, and the data size of each vertex is 4 bytes. Then, the storage position of vertex 3 in vertex array 203 can be obtained by adding (3×4) to the starting address of vertex array 203. Figure 6The symbol "<<2" means shifting 2 bits to the left, which means that each binary vertex number is multiplied by 4, the "starting address" is the starting address of the vertex array 203, and the symbol "+" means addition. The first prefetch address corresponding to each vertex number can be calculated by the formula: PV = vertex_begin + 4 × vertex_id. Among them, the symbol PV represents the first prefetch address, the symbol vertex_begin represents the starting address of the vertex array 203, and the symbol vertex_id represents the vertex number. For vertex number V0, V0 is multiplied by 4 and added to the starting address of the vertex array 203, which is the storage position of the vertex to which the vertex number V0 belongs in the vertex array 203. For V0 to V n The storage address corresponding to each vertex number can be determined by calculating the (n+1) vertex numbers, that is, the first pre-fetch address. After the vertex array address generator calculates the first pre-fetch address, it can send Figure 5 The cache unit shown sends a first pre-fetch address and stores the first pre-fetch address in the cache unit.

[0071] Optionally, step 303 may include: in a case where it is determined that the multiple vertices to which the multiple vertex numbers respectively belong are densely stored, determining a preset number of vertex numbers starting from the vertex number with the largest number as target vertex numbers.

[0072] In one embodiment, after determining that the accessed data includes multiple vertex numbers stored in the edge array, the prefetcher may also determine that a preset number of vertex numbers starting from the vertex number with the largest number are target vertex numbers when it is determined that the multiple vertices to which the multiple vertex numbers belong are stored densely. Exemplarily, the prefetcher may determine that the multiple vertices to which the multiple vertex numbers belong are stored densely when it is determined that the actual difference between the upper limit and the lower limit of the number among the multiple vertex numbers is less than the preset difference. The preset difference may be 48, the upper limit of the number may be the largest vertex number among the multiple vertex numbers, and the lower limit of the number may be the smallest vertex number among the multiple vertex numbers. Figure 6 As shown, the prefetcher determines the V0 to V nAfter n+1 vertices are numbered, the vertex number with the largest number can be determined from the multiple vertex numbers as the upper limit of the number, and the vertex number with the smallest number can be determined as the lower limit of the number, and then the actual difference between the upper limit of the number and the lower limit of the number is calculated, and the size between the actual difference and the preset difference is compared. If the actual difference is less than the preset difference 48, it is determined that the storage of the multiple vertices to which the multiple vertex numbers belong is relatively dense. On the contrary, when the actual difference is greater than or equal to the preset difference 48, it is determined that the multiple vertices to which the multiple vertex numbers belong are sparsely distributed and the storage is relatively dispersed. In practical applications, the upper limit of the number and the lower limit of the number can also be other vertex numbers among the multiple vertex numbers, and the specific value of the preset difference can be set according to demand, which is not limited in this embodiment.

[0073] Among them, the vertices in the graph data have a community structure, and multiple vertices with high association form a community structure. The attribute values ​​of multiple vertices in the same community structure are stored in multiple cache lines that are close. In graph data containing more community structures, when only multiple vertex numbers in the access data are used as target vertex numbers, the amount of pre-fetched data is small, and the memory bandwidth cannot be fully utilized, resulting in poor timeliness of data pre-fetching. Combined with the above example, when the CSR format is used to store graph data, the attribute value of each vertex in the graph data is stored in the vertex array 203 in sequence according to the vertex number, and multiple vertices belonging to the same community structure are stored in close cache lines. The smaller the difference between the vertex numbers, the denser the vertex storage. When the actual difference between the upper limit and the lower limit of the number in the multiple vertex numbers is less than the preset difference 48, it means that the vertex storage in the community structure where the current processing vertex is located is relatively dense, and is distributed in one to three cache lines that are close. At this time, the attribute values ​​of multiple vertices with relatively dense storage and high association can be pre-stored in the private cache. The method for determining the dense storage of multiple vertices may include but is not limited to the above example, and this embodiment does not limit this.

[0074] In one embodiment, the corresponding preset quantity can be determined according to the actual difference, and different actual differences can correspond to different preset quantities. Figure 6 As shown, the selector is used to determine the size of the preset number according to the actual difference after determining that the actual difference is less than the preset difference 48. When the actual difference is greater than or equal to 32 and less than 48, the preset number can be selected as 16, that is, a cache line, 64 bytes of data. At this time, the vertex number V with the largest number can be selected. n The next 16 numbers are used as the target vertex numbers. Accordingly, the vertex array address generator first determines the vertex number V with the largest number. n The storage address of V nThe storage address of 64 bytes after the storage address of is used as the first prefetch address. Similarly, when the actual difference is greater than or equal to 16 and less than 32, the preset number can be 32, that is, 2 cache lines and 128 bytes of data, and the vertex number V can be selected. n The next 32 numbers are used as the target vertex numbers, and V n The storage address 128 bytes after the storage address of is used as the first prefetch address. Similarly, when the actual difference is less than 16, the preset number can be 48, that is, 3 cache lines and 192 bytes of data, and the vertex number V can be selected. n The next 48 numbers are used as the target vertex numbers, and V n The storage address 192 bytes after the storage address is used as the first prefetch address.

[0075] Step 305: Send a first pre-fetch address to the private cache, so that the private cache stores the attribute value of the vertex to which the target vertex number belongs in advance in the private cache through the first pre-fetch address.

[0076] In this embodiment, after determining the first prefetch address, the prefetcher may send the first prefetch address to the private cache, and the private cache may pre-store the attribute value of the vertex to which the target vertex number belongs in the private cache through the first prefetch address.

[0077] Optionally, when the target vertex number is a vertex number in the access data, step 305 may be implemented as follows:

[0078] The first pre-fetch address is sent to the first-level cache, so that the first-level cache stores the attribute value of the vertex to which the target vertex number belongs in advance in the first-level cache through the first pre-fetch address.

[0079] In one embodiment, if the vertex number in the accessed data is directly used as the target vertex number, the attribute value of the vertex to which the target vertex number belongs can be pre-stored in the first-level cache. Figure 4 and Figure 5As shown, the cache unit in the prefetcher is connected to the DTLB, and the cache unit can send a first prefetch address to the DTLB, which converts the first prefetch address into a physical address and sends it to the first-level cache. The cache unit can send the first prefetch address to the first-level cache when the processor core is idle. After receiving the first prefetch address (physical address) sent by the prefetcher, the first-level cache can send a memory access request including the first prefetch address to the second-level cache, and obtain the data stored in the first prefetch address from the second-level cache, that is, the attribute value of the vertex stored in the vertex array. Combined with the above example, for the current processing vertex 2, after receiving the first prefetch addresses corresponding to vertices 3 and vertices 4 sent by the prefetcher, the first-level cache can send the corresponding first prefetch address to the second-level cache, obtain the attribute value of vertex 3 and the attribute value of vertex 4 stored in the vertex array 203 from the second-level cache, and store them. If the attribute value of vertex 3 and the attribute value of vertex 4 are stored in the second-level cache, the second-level cache can obtain the attribute value of vertex 3 and the attribute value of vertex 4 from the shared cache based on the first prefetch address, and then send them to the first-level cache for storage. At this time, the attribute values ​​of vertex 3 and vertex 4 are pre-stored in the first-level cache. When the first-level cache receives the memory access request sent by the processor core for vertex 3 and vertex 4, it can directly send the pre-stored attribute values ​​of vertex 3 and vertex 4 to the processor core, which can shorten the waiting time of the processor core, thereby shortening the memory access delay and improving computing efficiency.

[0080] In another embodiment, when the vertex number in the accessed data is directly used as the target vertex number, the attribute value of the vertex to which the target vertex number belongs can also be pre-stored in the secondary cache. Figure 4 As shown, the DTLB is connected to the secondary cache, and the DTLB can also send the first pre-fetch address to the secondary cache, and the secondary cache pre-stores the attribute value of vertex 3 and the attribute value of vertex 4 in the secondary cache through the first pre-fetch address.

[0081] Optionally, before using the storage position of the vertex to which the target vertex number belongs in the vertex array as the first pre-fetch address, the method further includes:

[0082] Determine the end offset address corresponding to the memory access address; the end offset address is obtained by adding the end address offset value to the start address of the edge array;

[0083] The vertex numbers whose storage locations are after the ending offset address are removed from the plurality of target vertex numbers.

[0084] In one embodiment, after determining the target vertex number, the vertex numbers of vertices that are not related to the currently processed vertex can be removed from the multiple target vertex numbers. Combined with the above example, since the first-level cache reads the amount of data of a cache line each time, when the first-level cache reads the vertex number corresponding to vertex 2 from the edge array 202, 16 vertex numbers can be read. Among the 16 vertex numbers, only the vertex numbers of vertex 3 and vertex 4 are related to vertex 2, which are the vertex numbers of the corresponding destination vertices when vertex 2 is used as the source vertex. The other vertex numbers are not the destination vertex numbers corresponding to vertex 2. At this time, if the attribute values ​​of the vertices belonging to other vertex numbers are read into the first-level cache, this part of the data will not be used when calculating the attribute value of vertex 2, and this part of the data read into the first-level cache will replace other valid data already stored in the first-level cache, which will cause cache pollution.

[0085] In combination with the above example, after the prefetcher obtains the position data corresponding to vertex 2 from offset array 201, it can determine the end offset address according to the end address offset value in the position data and the start address of edge array 202, that is, the storage position of the vertex number of destination vertex 4 corresponding to vertex 2 as the source vertex in edge array 202, and then remove the vertex numbers whose storage positions are after the end offset address, that is, remove vertex number 0, vertex number 1 and vertex number 3 whose storage positions are after the storage position of vertex number 4 in edge array 202. At this time, in the process of determining the first prefetch address, the first prefetch address only includes the storage positions of vertex 3 and vertex 4 in vertex array 203.

[0086] In the embodiment of the present invention, the vertex numbers of vertices irrelevant to the currently processed vertex are removed according to the termination offset address corresponding to the currently processed vertex, and when the pre-fetch address is determined according to the remaining vertex numbers, the attribute values ​​of the vertices stored in the pre-fetch address are all the attribute values ​​of the destination vertex corresponding to the currently processed vertex. In the data pre-fetch process, it is possible to avoid reading irrelevant data into the first-level cache, thereby achieving more accurate data pre-fetching and avoiding cache pollution.

[0087] In another embodiment, after determining the plurality of vertex numbers, duplicate numbers among the plurality of vertex numbers may be removed. Figure 2 As shown, the first-level cache can read 16 vertex numbers at a time, and there may be duplicate vertex numbers among the 16 vertex numbers. After determining the 16 vertex numbers, the prefetcher can first delete the duplicate numbers among the 16 vertex numbers, and then determine the first prefetch address based on the remaining vertex numbers. In practical applications, deduplication of vertices in multiple vertex numbers can avoid repeatedly reading the attribute values ​​of the same vertex into the first-level cache, thereby improving the efficiency of data prefetching.

[0088] Optionally, when the target vertex number is a vertex number in the access data, step 305 may be implemented as follows:

[0089] The first pre-fetch address is sent to the secondary cache, so that the secondary cache stores the attribute value of the vertex to which the target vertex number belongs in advance in the secondary cache through the first pre-fetch address.

[0090] In one embodiment, when a preset number of vertex numbers after the vertex number with the largest number is determined as the target vertex number, the attribute values ​​of the vertices to which the target vertex number belongs can be pre-stored in the secondary cache. Figure 4 As shown, DTLB is connected to the secondary cache, and after determining the first prefetch address, the vertex array generator can store the first prefetch address in the cache unit. When the processor core is idle, the cache unit can send the first prefetch address to DTLB, and DTLB converts the first prefetch address into a physical address and sends it to the secondary cache. Correspondingly, the secondary cache can obtain the attribute value of the vertex to which the target vertex number belongs from the shared cache through the first prefetch address, and store it in the secondary cache. When the processor core needs to obtain the attribute value of the vertex to which the target vertex number belongs, the first-level cache can quickly obtain data from the secondary cache after receiving the memory access request, avoiding obtaining data from the shared cache or memory, thereby shortening the waiting time of the processor core and improving computing efficiency.

[0091] In one embodiment, before the storage location of the vertex to which the target vertex number belongs in the vertex array is used as the first pre-fetch address, the end offset address corresponding to the access address can also be determined, and the vertex numbers whose storage locations are after the end offset address are removed from the multiple target vertex numbers. In combination with the above example, after determining the target vertex number, the end offset address corresponding to the currently processed vertex 2 can also be determined, and the vertex numbers whose storage locations are after the end offset address are deleted, and the storage addresses of the vertices to which the remaining target vertex numbers belong in the vertex array are used as the first pre-fetch address.

[0092] In an embodiment of the present invention, by utilizing the community structure of graph data, when the vertex storage is relatively dense, multiple vertices with a high degree of association with the current vertex that are densely stored are pre-read into the secondary cache, which can shorten the access delay of the processor and improve the efficiency of graph calculation. In addition, since the data is stored in the secondary cache, it can be avoided to be directly stored in the primary cache, reducing the pollution of cached data in the primary cache. At the same time, pre-fetching is performed when it is determined that the vertex storage is dense, which can avoid pre-fetching data when the vertex storage is relatively scattered, thereby avoiding pollution of the data in the cache.

[0093] In the prior art, the prefetcher is usually set outside the processor, and the prefetcher uses streaming prefetching to pre-read the data that the processor core is about to access from the memory into the cache. Since the processor's access to graph data during graph calculation is random, when streaming prefetching is used, the prefetched data is not accurate, resulting in the processor needing to frequently read data from the memory, and the memory access delay is long, resulting in low efficiency of graph calculation. In an embodiment of the present invention, the prefetcher is set inside the processor, and the graph data to be accessed is determined based on the graph data currently accessed by the processor core, and the data to be accessed is pre-stored in the cache, which can achieve accurate prefetching of graph data, thereby shortening the memory access delay of the processor core, improving the efficiency of graph calculation, and avoiding reading invalid data into the cache, which pollutes the data in the cache.

[0094] It should be noted that before the graph calculation starts, the processor can turn off the prefetcher located outside the processor to avoid the prefetcher located outside the processor reading unnecessary data into the cache during the graph calculation process, replacing the data read into the cache by the prefetcher inside the processor, causing cache pollution.

[0095] In summary, in an embodiment of the present invention, the prefetcher obtains the memory access address sent by the processor core to the private cache, and the memory access data obtained by the private cache through the memory access address. When the memory access address is within the storage range of the edge array, it is determined that the memory access data includes multiple vertex numbers stored in the edge array, and based on the multiple vertex numbers, multiple target vertex numbers in the edge array are determined. The storage position of the vertex to which the target vertex number belongs in the vertex array is used as the first prefetch address, and the first prefetch address is sent to the private cache, so that the private cache pre-stores the attribute value of the vertex to which the target vertex number belongs in the private cache through the first prefetch address. In the graph calculation process, when the processor core accesses the data in the edge array, the data in the vertex array that the processor core is about to access is determined, and the data is pre-stored in the private cache. When the processor core accesses the data in the vertex array, the private cache can quickly provide the processor core with the data, which can shorten the access delay of the processor core, thereby improving the efficiency of graph calculation.

[0096] The prefetching method provided in this embodiment can achieve a performance improvement of 65% to 176% compared to the case without prefetching; it can achieve a performance improvement of 6% to 21% compared to a streaming prefetcher arranged outside the processor, and it can achieve a performance improvement of 4% to 18% compared to a traditional prefetcher. At the same time, since the data pre-read into the private cache is determined according to the currently accessed data, the probability of being accessed by the processor core is relatively high, and it can be avoided that data with a low access probability is read into the private cache, causing pollution to the data in the private cache. In addition, since the prefetcher is arranged inside the processor, in the process of converting physical addresses and virtual addresses, the conversion between virtual addresses and physical addresses can be realized by the DTLB inside the processor, which can avoid setting up a separate DTLB for the prefetcher, thereby avoiding additional DTLB design overhead.

[0097] Optionally, the method may further include:

[0098] In the case where the access address is within the storage range of the offset array, it is determined that the access data includes the starting address offset value corresponding to the currently processed vertex; the offset array is used to store the starting address offset value corresponding to the vertex in the graph data;

[0099] Using multiple addresses after the first address in the edge data group as second pre-fetch addresses; the first address is obtained by adding the starting address offset value to the starting address of the edge array;

[0100] The second prefetch address is sent to the private cache, so that the private cache pre-stores the vertex number stored in the second prefetch address in the private cache through the second prefetch address.

[0101] In this embodiment, during the graph calculation process, the vertex numbers stored in the edge array can also be pre-fetched. In combination with the above example, the address register also stores the starting address and the ending address of the offset array 201. After the pre-fetcher receives the memory access address sent by the private cache, if it is determined that the memory access address is between the starting address and the ending address of the offset array 201, it can be determined that the memory access data read by the private cache through the memory access address is the data in the offset array, that is, the memory access data includes the position data corresponding to the currently processed vertex, including the starting address offset value and the ending address offset value. Further, it can be determined that the processor core will access the data in the edge array 202 in the next step.

[0102] like Figure 7 As shown, Figure 7A logical schematic diagram of an edge array address generator in an embodiment of the present invention is shown, and the prefetch address generator also includes an edge array address generator. The first-level cache obtains the data amount of a cache line each time. When the first-level cache reads the data in the offset array 201, the data obtained each time includes m position data, that is, the position data corresponding to m vertices. If the current processing vertex is vertex 2, then among the m position data obtained, the first position data U1 is the position data corresponding to vertex 2, including the starting address offset value and the ending address offset value. At this time, the edge array address generator can only use the starting offset address corresponding to vertex 2 as the second prefetch address. The second prefetch address can be calculated by the formula: PE=offset+edge_begin, where the symbol PE represents the second prefetch address, offset represents the starting address offset value in the position data, and edge_begin is the starting address of the edge array 202 (pre-stored in the address register). For vertex 2, offset is the starting address offset value in the position data corresponding to the vertex. When the prefetcher determines that the access address is an address in the offset array 201, the access address and the access data may be stored, and the access address is used to determine the corresponding position data from the access data. Figure 7 As shown, after determining the memory access address corresponding to vertex 2, the multiplexer can select and determine the position data U1 corresponding to vertex 2 from the 64 bytes of data based on the memory access address, and extract the starting address offset value from the position data U1, and then add the starting address offset value to the starting address of the edge array 202 to obtain the second prefetch address.

[0103] In another embodiment, the address of one or more cache line capacities after the start offset address may be used as the second pre-fetch address. Figure 7 As shown, after determining the starting offset address corresponding to vertex 2, the storage address of 64 bytes after the address can be used as the second pre-fetch address, or the storage address of 128 bytes after the address can be used as the second pre-fetch address, or the storage address of 192 bytes after the address can be used as the second pre-fetch address. The specific number of the second pre-fetch addresses can be set according to demand, and this embodiment does not limit this.

[0104] In one embodiment, the data in the second prefetch address may be pre-stored by the first-level cache. Specifically, after determining the second prefetch address, the edge array address generator may store the second prefetch address in the cache unit, and send the second prefetch address to the DTLB when the processor core is idle, and the DTLB converts the second prefetch address into a physical address and then sends it to the first-level cache. At this time, the first-level cache may read the data stored in the second prefetch address from the second-level cache based on the second prefetch address, that is, the vertex numbers stored in the edge array 202 are pre-stored in the first-level cache. Alternatively, the data in the second prefetch address may also be pre-stored by the second-level cache.

[0105] In an embodiment of the present invention, during a graph calculation process, when a processor core accesses an offset array, data in an edge array that the processor core is about to access is determined, and the data is pre-stored in a first-level cache. When the processor core accesses the data in the edge array, the first-level cache can quickly provide the processor core with the data, thereby shortening the access delay of the processor core and improving the efficiency of graph calculation.

[0106] Optionally, before sending the second prefetch address to the private cache, the method may further include:

[0107] The second pre-fetch address after the second address is deleted from the plurality of second pre-fetch addresses; the second address is obtained by adding the end address offset value to the start address of the edge array, the end address offset value is included in the access data and corresponds to the current processing vertex.

[0108] Among them, the second address is the end offset address corresponding to the currently processed vertex. Combined with the above example, for the currently processed vertex 2, when the access data includes the position data corresponding to vertex 2, the start offset address and the end offset address corresponding to vertex 2 can be calculated according to the start address of edge array 202 and the start address offset value in the position data, the start offset address is the storage address of number 3 corresponding to vertex 2 in edge array 202, and the end offset address is the storage location of number 4 corresponding to vertex 2. When the determined second prefetch address includes the capacity of multiple cache lines, the second prefetch address after the end offset address can be deleted, that is, multiple second prefetch addresses after the storage location of number 4 can be deleted.

[0109] In the embodiment of the present invention, in the process of prefetching data in the edge array, for the currently processed vertex, only the vertex number corresponding to the currently processed vertex can be prefetched. For example, when the second prefetch address located after the second address is removed, the second prefetch address only includes the storage addresses of number 3 and number 4 in the edge array, and does not include the storage addresses corresponding to other vertices. Since the prefetching of the edge array is only for the currently processed vertex, the edge array can be prefetched more accurately.

[0110] Optionally, the method may further include:

[0111] When the access address is within the storage range of the edge array, a preset number of addresses after the access address are used as the third pre-fetch address;

[0112] The third prefetch address is sent to the private cache, so that the private cache pre-stores the vertex number stored in the third prefetch address in the private cache through the third prefetch address.

[0113] In one embodiment, the data in the edge array may be pre-fetched in a streaming pre-fetching manner. Figure 5 and Figure 7 As shown, after receiving the access address sent by the first-level cache, the prefetcher can first compare the access address with the start address and the end address of the edge array 202 stored in advance. When the access address is within the storage range defined by the start address and the end address of the edge array 202, it is determined that the access address belongs to the edge array 202. At this time, the storage address of 4 cache line capacities and 256 bytes after the access address can be used as the third prefetch address. After determining the third prefetch address, the edge array address generator can send the third prefetch address to the cache unit for storage, and send the third prefetch address to the DTLB when the processor core is idle. After the DTLB converts the third prefetch address into a physical address, it sends it to at least one of the first-level cache or the second-level cache. The first-level cache or the second-level cache pre-stores the data stored in the third prefetch address through the third prefetch address, that is, the data in the edge array is pre-stored in the first-level cache or the second-level cache.

[0114] In an embodiment of the present invention, when the access address received by the first-level cache belongs to an edge array, a streaming pre-fetch method can be used to determine multiple pre-fetch addresses after the access address, and the data stored in the pre-fetch address is pre-stored in the first-level cache or the second-level cache. When the processing core is accessing the data, the data can be quickly provided to the processor core, shortening the access delay of the processor core and improving the efficiency of graph computing.

[0115] Optionally, before sending the third prefetch address to the private cache, the method further includes:

[0116] The third prefetch address after the second address is deleted from the plurality of third prefetch addresses; the second address is obtained by adding the end address offset value to the start address of the edge array, the end address offset value is included in the access data and corresponds to the current processing vertex.

[0117] The process of deleting the third pre-fetch address located after the second address is the same as the process of deleting the second pre-fetch address located after the second address, which will not be described in detail in this embodiment.

[0118] An embodiment of the present invention further provides a processor, comprising: at least one processor core, and a prefetcher and a private cache corresponding to the processor core;

[0119] The processor core is connected to the private cache and is used to send a memory access address to the private cache so that the private cache obtains memory access data through the memory access address;

[0120] The prefetcher is connected to the private cache, and is used to obtain the access address and the access data from the private cache, and when the access address is located in the storage range of the edge array, determine that the access data includes multiple vertex numbers stored in the edge array, and based on the multiple vertex numbers, determine multiple target vertex numbers in the edge array, use the storage position of the vertex to which the target vertex number belongs in the vertex array as the first prefetch address, and send the first prefetch address to the private cache;

[0121] The private cache is used to receive the first pre-fetch address, and pre-store the attribute value of the vertex to which the target vertex number belongs in the private cache through the first pre-fetch address;

[0122] Among them, the vertex array is used to store the attribute values ​​of the vertices in the graph data, and the edge array is used to store the corresponding destination vertex number when the vertex in the graph data is used as the source vertex.

[0123] Optionally, the private cache includes a first-level cache.

[0124] The prefetcher is specifically used to use multiple vertex numbers as target vertex numbers and send a first prefetch address to the first-level cache.

[0125] The first-level cache is used to pre-store the attribute value of the vertex to which the target vertex number belongs in the first-level cache through the first pre-fetch address.

[0126] Optionally, the private cache includes a secondary cache.

[0127] The prefetcher is specifically used to determine a preset number of vertex numbers starting from the vertex number with the largest number as target vertex numbers when it is determined that the multiple vertices to which the multiple vertex numbers belong are densely stored, and send a first prefetch address to the secondary cache.

[0128] The secondary cache is used to pre-store the attribute value of the vertex to which the target vertex number belongs in the secondary cache through the first pre-fetch address.

[0129] Optionally, the memory access address is obtained by adding the starting address offset value to the starting address of the edge array; the processor core obtains the starting address offset value and the ending address offset value corresponding to the currently processed vertex from the offset array of the graph data in advance; the prefetcher is also used to determine the ending offset address corresponding to the memory access address; the ending offset address is obtained by adding the ending address offset value to the starting address of the edge array; and the vertex numbers whose storage locations are after the ending offset address are removed from multiple target vertex numbers.

[0130] Optionally, the prefetcher is further used to determine that the accessed data includes a starting address offset value corresponding to the currently processed vertex when the accessed address is within the storage range of the offset array; the offset array is used to store the starting address offset value corresponding to the vertex in the graph data; multiple addresses after the first address in the edge data group are used as the second prefetch address; the first address is obtained by adding the starting address offset value to the starting address of the edge array; and the second prefetch address is sent to the private cache;

[0131] The private cache is further used to pre-store the vertex number stored in the second pre-fetch address in the private cache through the second pre-fetch address.

[0132] Optionally, the prefetcher is further configured to, when the memory access address is within the storage range of the edge array, use a preset number of addresses after the memory access address as third prefetch addresses; and send the third prefetch address to the private cache.

[0133] The private cache is further used to pre-store the vertex number stored in the third pre-fetch address in the private cache through the third pre-fetch address.

[0134] Optionally, the prefetcher is also used to delete the second prefetch address located after the second address from multiple second prefetch addresses before sending the second prefetch address to the private cache; the second address is obtained by adding the ending address offset value to the starting address of the edge array, and the ending address offset value is included in the memory access data and corresponds to the currently processed vertex.

[0135] Optionally, the prefetcher is also used to delete a third prefetch address located after the second address from multiple third prefetch addresses before sending the third prefetch address to the private cache; the second address is obtained by adding the ending address offset value to the starting address of the edge array, and the ending address offset value is included in the memory access data and corresponds to the currently processed vertex.

[0136] For an understanding of the processor and the prefetcher, please refer to the above examples, which will not be elaborated in this embodiment.

[0137] An embodiment of the present invention further provides an electronic device, comprising the processor as described above.

[0138] Figure 8The electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a message transceiver, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0139] Reference Figure 8 , the electronic device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output (I / O) interface 812 , a sensor component 814 , and a communication component 816 .

[0140] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0141] The memory 804 is configured to store various types of data to support operations on the device 700. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0142] The power supply component 806 provides power to the various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 800.

[0143] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0144] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), and when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 804 or sent via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0145] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: home button, volume button, start button, and lock button.

[0146] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the electronic device 800. For example, the sensor assembly 814 can detect the open / closed state of the device 700, the relative positioning of the components, such as the display and keypad of the electronic device 800, and the sensor assembly 814 can also detect the position change of the electronic device 800 or a component of the electronic device 800, the presence or absence of contact between the user and the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and the temperature change of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0147] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0148] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above methods.

[0149] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the instructions can be executed by a processor 820 of an electronic device 800 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0150] A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform a graph data pre-fetching method, the method comprising:

[0151] Obtaining a memory access address sent by the processor core to the private cache, and memory access data obtained by the private cache through the memory access address;

[0152] In the case where the access address is within the storage range of the edge array, it is determined that the access data includes multiple vertex numbers stored in the edge array; the edge array is used to store the numbers of the destination vertices corresponding to the vertices in the graph data as the source vertices;

[0153] Based on the multiple vertex numbers, determine multiple target vertex numbers in the edge array;

[0154] The storage position of the vertex to which the target vertex number belongs in the vertex array is used as the first pre-fetch address; the vertex array is used to store the attribute values ​​of the vertices in the graph data;

[0155] The first pre-fetch address is sent to the private cache, so that the private cache stores the attribute value of the vertex to which the target vertex number belongs in advance in the private cache through the first pre-fetch address.

[0156] Optionally, the private cache includes a first-level cache.

[0157] The method of determining a plurality of target vertex numbers in the edge array based on a plurality of vertex numbers includes: using the plurality of vertex numbers as target vertex numbers.

[0158] The method of sending the first prefetch address to the private cache so that the private cache pre-stores the attribute values ​​of the vertices to which the target vertex number belongs in the private cache through the first prefetch address includes: sending the first prefetch address to the first-level cache so that the first-level cache pre-stores the attribute values ​​of the vertices to which the target vertex number belongs in the first-level cache through the first prefetch address.

[0159] Optionally, the private cache includes a secondary cache.

[0160] Based on the multiple vertex numbers, determining multiple target vertex numbers in the edge array includes: when it is determined that the multiple vertices to which the multiple vertex numbers belong are densely stored, determining a preset number of vertex numbers starting from the vertex number with the largest number as the target vertex numbers;

[0161] Sending a first prefetch address to a private cache so that the private cache pre-stores the attribute value of the vertex to which the target vertex number belongs in the private cache through the first prefetch address, including: sending the first prefetch address to a secondary cache so that the secondary cache pre-stores the attribute value of the vertex to which the target vertex number belongs in the secondary cache through the first prefetch address.

[0162] Optionally, the memory access address is obtained by adding the starting address offset value to the starting address of the edge array; the processor core obtains the starting address offset value and the ending address offset value corresponding to the currently processed vertex from the offset array of the graph data in advance;

[0163] Before using the storage location of the vertex to which the target vertex number belongs in the vertex array as the first pre-fetch address, the method further includes:

[0164] Determine the end offset address corresponding to the memory access address; the end offset address is obtained by adding the end address offset value to the start address of the edge array;

[0165] The vertex numbers whose storage locations are after the ending offset address are removed from the plurality of target vertex numbers.

[0166] Optionally, it also includes:

[0167] In the case where the access address is within the storage range of the offset array, it is determined that the access data includes the starting address offset value corresponding to the currently processed vertex; the offset array is used to store the starting address offset value corresponding to the vertex in the graph data;

[0168] Using multiple addresses after the first address in the edge data group as second pre-fetch addresses; the first address is obtained by adding the starting address offset value to the starting address of the edge array;

[0169] The second prefetch address is sent to the private cache, so that the private cache pre-stores the vertex number stored in the second prefetch address in the private cache through the second prefetch address.

[0170] Optionally, it also includes:

[0171] When the access address is within the storage range of the edge array, a preset number of addresses after the access address are used as the third pre-fetch address;

[0172] The third prefetch address is sent to the private cache, so that the private cache pre-stores the vertex number stored in the third prefetch address in the private cache through the third prefetch address.

[0173] Optionally, before sending the second prefetch address to the private cache, the method further includes:

[0174] The second pre-fetch address located after the second address is deleted from the plurality of second pre-fetch addresses; the second address is obtained by adding the end address offset value to the start address of the edge array, the end address offset value is included in the access data and corresponds to the current processing vertex.

[0175] Optionally, before sending the third prefetch address to the private cache, the method further includes:

[0176] The third prefetch address after the second address is deleted from the plurality of third prefetch addresses; the second address is obtained by adding the end address offset value to the start address of the edge array, the end address offset value is included in the access data and corresponds to the current processing vertex.

[0177] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0178] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0179] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0180] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0181] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0182] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0183] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0184] The above is a detailed introduction to a graph data pre-fetching method and device, an electronic device and a storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A graph data pre-fetching method, characterized in that: Applied to a prefetcher, the prefetcher is arranged in a processor, and the processor also includes a processor core and a private cache corresponding to the prefetcher; the method includes: Acquire a memory access address sent by the processor core to the private cache, and memory access data acquired by the private cache through the memory access address; In the case where the access address is within the storage range of the edge array, it is determined that the access data includes multiple vertex numbers stored in the edge array; the edge array is used to store the numbers of destination vertices corresponding to the vertices in the graph data as source vertices; the graph data is composed of a set of vertices and a set of edges between vertices, a vertex in the graph data represents an object in the real or virtual world, the attribute value of the vertex represents the characteristics of the object, and the edges between vertices represent the relationship between the objects; Based on the multiple vertex numbers, determining multiple target vertex numbers in the edge array; Using the storage position of the vertex to which the target vertex number belongs in the vertex array as the first pre-fetch address; the vertex array is used to store the attribute values ​​of the vertices in the graph data; The first pre-fetch address is sent to the private cache, so that the private cache pre-stores the attribute value of the vertex to which the target vertex number belongs in the private cache through the first pre-fetch address.

2. The method according to claim 1, characterized in that The private cache includes a first-level cache; The determining a plurality of target vertex numbers in the edge array based on the plurality of vertex numbers comprises: using the plurality of vertex numbers as the target vertex numbers; The sending the first pre-fetch address to the private cache so that the private cache stores the attribute value of the vertex to which the target vertex number belongs in advance in the private cache through the first pre-fetch address includes: The first prefetch address is sent to the first-level cache, so that the first-level cache pre-stores the attribute value of the vertex to which the target vertex number belongs in the first-level cache through the first prefetch address.

3. The method according to claim 1, characterized in that The private cache includes a secondary cache; The step of determining a plurality of target vertex numbers in the edge array based on the plurality of vertex numbers comprises: in the case where it is determined that a plurality of vertices to which the plurality of vertex numbers belong are densely stored, determining a preset number of vertex numbers starting from the vertex number with the largest number as the target vertex numbers; The sending the first pre-fetch address to the private cache so that the private cache stores the attribute value of the vertex to which the target vertex number belongs in advance in the private cache through the first pre-fetch address includes: The first pre-fetch address is sent to the secondary cache, so that the secondary cache stores the attribute value of the vertex to which the target vertex number belongs in advance in the secondary cache through the first pre-fetch address.

4. The method according to claim 2, characterized in that: The memory access address is obtained by adding a starting address offset value to the starting address of the edge array; the processor core obtains the starting address offset value and the ending address offset value corresponding to the current processing vertex from the offset array of the graph data in advance; Before taking the storage position of the vertex to which the target vertex number belongs in the vertex array as the first pre-fetch address, the method further includes: Determine a termination offset address corresponding to the memory access address; the termination offset address is obtained by adding the termination address offset value to the start address of the edge array; The vertex numbers whose storage locations are after the end offset address are removed from the plurality of target vertex numbers.

5. The method according to any one of claims 1 to 4, characterized in that: Also includes: In the case where the access address is within the storage range of the offset array, determining that the access data includes a starting address offset value corresponding to the currently processed vertex; the offset array is used to store the starting address offset values ​​corresponding to the vertices in the graph data; Using multiple addresses after the first address in the edge array as second pre-fetch addresses; the first address is obtained by adding the starting address offset value to the starting address of the edge array; The second prefetch address is sent to the private cache, so that the private cache pre-stores the vertex number stored in the second prefetch address in the private cache through the second prefetch address.

6. The method according to any one of claims 1 to 4, characterized in that: Also includes: In the case where the memory access address is within the storage range of the edge array, a preset number of addresses after the memory access address are used as third pre-fetch addresses; The third prefetch address is sent to the private cache, so that the private cache pre-stores the vertex number stored in the third prefetch address in the private cache through the third prefetch address.

7. The method according to claim 5, characterized in that Before sending the second prefetch address to the private cache, the method further includes: The second prefetch address located after the second address is deleted from the multiple second prefetch addresses; the second address is obtained by adding the end address offset value to the start address of the edge array, and the end address offset value is included in the memory access data and corresponds to the current processing vertex.

8. The method according to claim 6, characterized in that Before sending the third prefetch address to the private cache, the method further includes: The third prefetch address located after the second address is deleted from the plurality of third prefetch addresses; the second address is obtained by adding the end address offset value to the start address of the edge array, and the end address offset value is included in the memory access data and corresponds to the current processing vertex.

9. A processor, characterized in that: include: at least one processor core, and a prefetcher and a private cache corresponding to the processor core; The processor core is connected to the private cache and is used to send a memory access address to the private cache so that the private cache obtains memory access data through the memory access address; The prefetcher is connected to the private cache, and is used to obtain the access address and the access data from the private cache, and when the access address is within the storage range of the edge array, determine that the access data includes a plurality of vertex numbers stored in the edge array, and determine a plurality of target vertex numbers in the edge array based on the plurality of vertex numbers, use the storage position of the vertex to which the target vertex number belongs in the vertex array as a first prefetch address, and send the first prefetch address to the private cache; The private cache is used to receive the first pre-fetch address, and pre-store the attribute value of the vertex to which the target vertex number belongs in the private cache through the first pre-fetch address; The vertex array is used to store the attribute values ​​of the vertices in the graph data, and the edge array is used to store the numbers of the corresponding destination vertices when the vertices in the graph data are used as source vertices; The graph data consists of a set of vertices and a set of edges between vertices. A vertex in the graph data represents an object in the real or virtual world, the attribute value of the vertex represents the characteristics of the object, and the edges between vertices represent the relationship between objects.

10. An electronic device, characterized in that: Comprising a processor as claimed in claim 9.

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