Display panel and manufacturing method thereof, chip-on-film, and display device

Abstract

The present application provides a display panel, a method for manufacturing the same, a COF, and a display device, relating to the field of display technology. The display panel is electrically connected to the COF; the display panel includes a display area and a peripheral area adjacent to the display area; the peripheral area includes a substrate and a plurality of binding electrodes located on the substrate, the binding electrodes being electrically connected to connection electrodes on the COF; wherein the orthographic projection of the connection electrodes on the substrate is within the orthographic projection of the binding electrodes on the substrate, and the area of ​​the surface of the connection electrodes close to the binding electrodes is smaller than the area of ​​the surface of the binding electrodes away from the substrate. The display panel can improve the problem of poor binding caused by misalignment between the binding electrodes on the display panel and the connection electrodes on the COF, thereby improving product reliability.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, a chip-on-film, and a display device. Background Art

[0002] Display products typically include a display panel and a chip-on-film (COF). Currently, the display panel and COF are electrically connected through a bonding process. Specifically, the bonding electrodes on the display panel and the connecting electrodes on the COF are aligned and pre-pressed, and then the connection is secured using a pressing process.

[0003] However, there are problems of inaccurate alignment during the pre-pressing process, and uneven pressure applied by the pressing head of the pressing equipment during the pressing process, which will cause the connecting electrodes on the COF and the binding electrodes on the display panel to be misaligned, thereby causing poor binding between the COF and the display panel. Summary of the Invention

[0004] Embodiments of the present application provide a display panel and a method for manufacturing the same, a COF film, and a display device. The display panel can improve the poor binding problem caused by misalignment between the binding electrodes on the display panel and the connecting electrodes on the COF film, thereby improving product reliability.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a display panel electrically connected to a chip-on-film; the display panel includes a display area and a peripheral area adjacent to the display area;

[0007] The peripheral area includes a substrate and a plurality of binding electrodes located on the substrate, wherein the binding electrodes are electrically connected to the connection electrodes on the chip-on-film;

[0008] The orthographic projection outline of the connecting electrode on the substrate is located within the orthographic projection outline of the binding electrode on the substrate, and the area of ​​the surface of the connecting electrode close to the binding electrode is smaller than the area of ​​the surface of the binding electrode away from the substrate.

[0009] In an exemplary embodiment, the peripheral area includes a first binding area, and the first binding area is located on one side of the display area;

[0010] The display panel further includes a plurality of data lines arranged along a first direction and extending along a second direction, wherein the data lines extend from the display area to the first binding area, and the first direction and the second direction intersect;

[0011] The width of a portion of the data line located in the first binding area along the first direction is greater than the width of a portion of the data line located in the display area along the first direction.

[0012] In an exemplary embodiment, the binding electrode located in the first binding area is a first binding electrode;

[0013] The first binding area includes the substrate, and a plurality of the data lines, a first dielectric layer, a second dielectric layer, a plurality of the first binding electrodes, and a plurality of first openings located on the substrate;

[0014] The first opening penetrates the first dielectric layer and the second dielectric layer in a direction perpendicular to the substrate and exposes a partial area of ​​the data line; the first binding electrode is located in the first opening and is electrically connected to the data line.

[0015] In an exemplary embodiment, a distance between a surface of the first binding electrode away from the substrate and the substrate in a direction perpendicular to the substrate is smaller than a distance between a surface of the second dielectric layer away from the substrate and the substrate in a direction perpendicular to the substrate.

[0016] In an exemplary embodiment, the peripheral area further includes a second binding area, the second binding area is located on the other side of the display area, and the second binding area is connected to the first binding area;

[0017] The display panel further includes a plurality of scan lines arranged along the second direction and extending along the first direction, the scan lines intersecting and insulated from the data lines, and the scan lines extending from the display area to the second binding area;

[0018] The width of the portion of the scan line located in the second binding area along the second direction is greater than the width of the portion of the scan line located in the display area along the second direction.

[0019] In an exemplary embodiment, the binding electrode located in the second binding area is a second binding electrode;

[0020] The second binding region includes the substrate, and a plurality of the scanning lines, a first gate insulating layer, a second gate insulating layer, a first dielectric layer, a plurality of the second binding electrodes, and a plurality of second openings located on the substrate;

[0021] The second opening penetrates the first gate insulating layer, the second gate insulating layer and the first dielectric layer in a direction perpendicular to the substrate and exposes a partial area of ​​the scan line; the second binding electrode is located in the second opening and is electrically connected to the scan line.

[0022] In an exemplary embodiment, a distance between the second binding electrode and the substrate in a direction perpendicular to the substrate and away from the surface of the substrate is smaller than a distance between the first dielectric layer and the substrate in a direction perpendicular to the substrate and away from the surface of the substrate.

[0023] In an exemplary embodiment, the second binding region further includes a second dielectric layer, the second dielectric layer covers the first dielectric layer, and the second opening further penetrates the second dielectric layer;

[0024] The distance between the surface of the second binding electrode away from the substrate and the substrate in a direction perpendicular to the substrate is smaller than the distance between the surface of the second dielectric layer away from the substrate and the substrate in a direction perpendicular to the substrate.

[0025] In an exemplary embodiment, a maximum width of the first binding electrodes along the first direction is greater than a distance between two adjacent first binding electrodes.

[0026] In an exemplary embodiment, the display area includes a plurality of pixel units arranged in an array, and the scan lines and the data lines define an area where the pixel units are located;

[0027] In the case where one of the scan lines is connected to a row of the pixel units, the maximum width of the second binding electrodes along the second direction is greater than the distance between two adjacent second binding electrodes.

[0028] In an exemplary embodiment, a width of a portion of the data line located in the first binding area along the first direction is 5%-20% greater than a width of a portion of the data line located in the display area along the first direction.

[0029] In a second aspect, an embodiment of the present application provides a chip-on-chip film electrically connected to the display panel as described above; the chip-on-chip film includes a plurality of connecting electrodes; the peripheral area of ​​the display panel includes a plurality of binding electrodes; the binding electrodes are electrically connected to the connecting electrodes; wherein the orthographic projection outline of the connecting electrode on the substrate of the display panel is located within the orthographic projection outline of the binding electrode on the substrate, and the area of ​​the surface of the connecting electrode close to the binding electrode is smaller than the area of ​​the surface of the binding electrode away from the substrate.

[0030] In a third aspect, an embodiment of the present application provides a display device, comprising the display panel and the chip-on-film as described above, wherein the display panel and the chip-on-film are bound together.

[0031] In a fourth aspect, an embodiment of the present application provides a method for manufacturing the display panel as described above, the method comprising:

[0032] Providing a substrate; dividing the substrate into a display area and a peripheral area adjacent to the display area;

[0033] A plurality of binding electrodes are formed on a portion of the substrate located in the peripheral area; wherein the binding electrodes are electrically connected to the connecting electrodes on the flip chip film, the orthographic projection outline of the connecting electrodes on the substrate is located within the orthographic projection outline of the binding electrodes on the substrate, and the area of ​​the surface of the connecting electrodes close to the binding electrodes is smaller than the area of ​​the surface of the binding electrodes away from the substrate.

[0034] Embodiments of the present application provide a display panel and a preparation method thereof, a chip-on-chip film, and a display device, wherein the display panel is electrically connected to the chip-on-chip film; the display panel includes a display area and a peripheral area adjacent to the display area; the peripheral area includes a substrate and a plurality of binding electrodes located on the substrate, and the binding electrodes are electrically connected to the connecting electrodes on the chip-on-chip film; wherein the orthographic projection outline of the connecting electrode on the substrate is located within the orthographic projection outline of the binding electrode on the substrate, and the area of ​​the surface of the connecting electrode close to the binding electrode is smaller than the area of ​​the surface of the binding electrode away from the substrate.

[0035] In the embodiments of the present application, the orthographic projection outline of the connecting electrode on the substrate is positioned within the orthographic projection outline of the binding electrode on the substrate, and the area of ​​the surface of the connecting electrode close to the binding electrode is smaller than the area of ​​the surface of the binding electrode away from the substrate. Since the area of ​​the surface provided by the binding electrode for binding is larger than the area of ​​the surface provided by the connecting electrode for binding, even if the connecting electrode on the chip-on-film is misaligned, the orthographic projection outline of the connecting electrode on the substrate can still be positioned within the orthographic projection outline of the binding electrode on the substrate, so that there is still sufficient contact area between the connecting electrode and the binding electrode to complete the binding connection. This greatly improves the problem of poor binding between the binding electrode on the display panel and the connecting electrode on the chip-on-film due to misalignment, thereby improving product quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1a A schematic structural diagram of a display panel in a related technology provided in an embodiment of the present application;

[0038] Figure 1b for Figure 1aCross-sectional view along direction A1A2;

[0039] Figure 1c for Figure 1a Cross-sectional view along direction B1B2;

[0040] Figure 2a-2c Schematic diagram of the structure of poor binding between the display panel and the chip-on-film in three related technologies provided in the embodiments of the present application;

[0041] Figure 3-6b Schematic diagrams of the structures of six display panels provided in the embodiments of the present application;

[0042] Figure 7a-Figure 8 A schematic diagram of the binding structure of a display panel and a chip-on-film provided in an embodiment of the present application;

[0043] Figure 9 A flow chart of a method for manufacturing a display panel is provided for an embodiment of the present application;

[0044] Figure 10-12a Provides an intermediate structural diagram of a display panel manufacturing process for an embodiment of the present application;

[0045] Figure 13 A schematic structural diagram of a display area of ​​a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0047] In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings represent the same or similar structures, and their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0048] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0049] In the embodiments of the present application, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0050] In the embodiments of the present application, the terms "upper" and "lower" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0051] Display products usually include display panels and Chip On Film (COF), combined with Figure 1a 、 Figure 1b and Figure 1c As shown, the binding electrodes (5 or 6) on the display panel are bound together with the connecting electrodes on the chip-on-chip film to electrically connect the display panel and the chip-on-chip film, and then the electrical signal is transmitted to the data line 3 or the scan line 1 of the display panel through the chip-on-chip film to realize the picture display. However, in the related art, the contactable surface size of the binding electrode (5 or 6) on the display panel and the connecting electrode on the chip-on-chip film for binding is the same, which can also be understood as the binding surface size of the binding electrode of the display panel and the connecting electrode of the COF is the same. And the binding electrode (5 or 6) of the display panel is set to be "convex". It should be noted that the "convex" binding electrode is a relative concept compared to the "concave" type. For details, refer to Figure 1b As shown, the distance between the binding electrode 5 electrically connected to the scanning line 1 and the substrate 100 along the direction perpendicular to the substrate 100 is almost the same as the distance between the dielectric layer (PVX) 8 and the substrate 100 along the direction perpendicular to the substrate 100; Figure 1c As shown, the distance between the bonding electrode 6 electrically connected to the data line 2 and the substrate 100 along the direction perpendicular to the substrate 100 is almost the same as the distance between the dielectric layer (PVX) 8 and the substrate 100 along the direction perpendicular to the substrate 100. Figure 1b for Figure 1a Cross-sectional view along the A1A1 direction, Figure 1c for Figure 1a Cross-sectional view along the C1C2 direction.

[0052] Thus, during the bonding process, poor bonding is very likely to occur. First, when the connection electrode 103 of the COF film 104 is pre-pressed and aligned with the bonding electrode (5 or 6) of the display panel, the pressure head 102 of the bonding device may be Figure 2a The alignment deviation shown in the figure causes misalignment between the binding surface of the binding electrode (Panel Lead) and the binding surface of the connecting electrode 103 (COF Lead), resulting in poor binding. Figure 2bAs shown, the pressure applied by the pressure head 102 of the binding device to the flexible film 101 of the COF 104 is uneven, so that the vertical force F1 is not perpendicular to the horizontal force F2 (or the pressure head 102 is not parallel to the flexible film 101 of the COF 104), causing the connection electrode 103 to deviate with the pressure head 102, thereby causing the binding surface of the binding electrode (Panel Lead) and the binding surface of the connection electrode 103 (COFLead) to be misaligned, resulting in poor binding. Third, refer to Figure 2c As shown, during the bonding process, the connecting electrodes 103 and the bonding electrodes (5 or 6) need to be fixed together through heating. However, during heating, the flexible film 101 of the chip-on-film 104 is prone to expansion. If the chip-on-film expands too much, the bonding surface of some bonding electrodes (panel leads) and the bonding surface of the connecting electrodes 103 (COF leads) may be misaligned, which can also cause poor bonding. Because the bonding surfaces of the display panel bonding electrodes and the COF connecting electrodes are the same size, any misalignment will highly likely cause a short circuit due to poor bonding, thereby reducing the quality of the display product.

[0053] Based on this, the embodiment of the present application provides a display panel electrically connected to the chip-on-film; Figure 3 As shown, the display panel includes a display area AA and a peripheral area adjacent to the display area AA (including Figure 3 The area where the markers B1 and B2 are shown);

[0054] The peripheral region includes a substrate 100 and a plurality of bonding electrodes (5 or 6) located on the substrate 100, wherein the bonding electrodes (5 or 6) are electrically connected to the connection electrodes 103 on the COF film 104;

[0055] In which, the orthographic projection outline of the connecting electrode 103 on the substrate 100 is located within the orthographic projection outline of the binding electrode (5 or 6) on the substrate 100, and the area of ​​the surface of the connecting electrode 103 close to the binding electrode (5 or 6) is smaller than the area of ​​the surface of the binding electrode (5 or 6) away from the substrate 100.

[0056] In an exemplary embodiment, referring to Figure 7a or Figure 7bAs shown, by setting the positive projection outline of the connecting electrode 103 on the substrate 100 to be within the positive projection outline of the binding electrode (5 or 6) on the substrate 100, and the area of ​​the surface of the connecting electrode 103 close to the binding electrode (5 or 6) is smaller than the area of ​​the surface of the binding electrode (5 or 6) away from the substrate 100, when the binding electrode (5 or 6) and the connecting electrode 103 are misaligned due to alignment deviation or excessive expansion of the flexible film 101 of the flip chip film 104, since the binding electrode (5 or 6) provides a binding surface of sufficiently large size, when the connecting electrode 103 is misaligned to a certain extent, the binding electrode (5 or 6) and the connecting electrode 103 still have sufficient contact surface for binding, which greatly reduces the probability of poor binding between the binding electrode (5 or 6) and the connecting electrode 103, thereby improving the reliability of the display product composed of the display panel and the flip chip film and improving the quality of the product.

[0057] It should be noted that the binding surface of the binding electrode ( 5 or 6 ) refers to the surface of the binding electrode ( 5 or 6 ) that is away from the substrate 100 and is used for binding with the connecting electrode 103 .

[0058] In an exemplary embodiment, the material of the binding electrode ( 5 or 6 ) may be any one of gold (Au), copper (Cu), and indium tin oxide (ITO).

[0059] The specific type of the display panel is not limited here. For example, the display panel can be an LCD (Liquid Crystal Display) display panel, an OLED (Organic Light-Emitting Diode) display panel, or a Mini / Micro LED (micro display panel) display panel, and the specific type can be determined according to actual conditions.

[0060] In an exemplary embodiment, referring to Figure 3 As shown, the peripheral area includes a first binding area B1, and the first binding area B1 is located on one side of the display AA;

[0061] The display panel further includes a plurality of data lines 3 arranged along a first direction OA and extending along a second direction OB, the data lines 3 extending from the display area AA to the first binding area B1, and the first direction OA and the second direction OB intersect;

[0062] The width d4 of the portion of the data line 3 located in the first binding area B1 along the first direction OA is greater than the width d3 of the portion of the data line 3 located in the display area AA along the first direction OA.

[0063] For example, the width d3 of the portion of the data line 3 located in the display area AA along the first direction OA may be 20 μm, and the width d4 of the portion of the data line 3 located in the first binding area B1 along the first direction OA may be 24 μm.

[0064] In practical applications, in order to set the positive projection outline of the connecting electrode 103 on the substrate 100 to be within the positive projection outline of the binding electrode (5 or 6) on the substrate 100, and the area of ​​the surface of the connecting electrode 103 close to the binding electrode (5 or 6) is smaller than the area of ​​the surface of the binding electrode (5 or 6) away from the substrate 100, for the binding electrode in the first binding area B1, it is necessary to simultaneously increase the size of the data line 3 and the size of the binding electrode 6 located in the first binding area B1.

[0065] Specifically, the width of the data line 3 along the first direction can be directly increased. However, since the width of the data line 3 located in the display area AA affects the aperture ratio of the display area A, and thus affects the display effect, the width of the data line 3 located in the display area AA is set to remain unchanged, and the width d4 of the portion of the data line 3 located in the first binding area B1 along the first direction OA is set to be greater than the width d3 of the portion of the data line 3 located in the display area AA along the first direction OA.

[0066] In an exemplary embodiment, after the width of the portion of the data line 3 located in the first binding area B1 along the first direction OA is increased, the width of the binding electrode 6 along the first direction OA can be appropriately increased, thereby increasing the size of the binding surface of the binding electrode 6, so that when there is a certain degree of misalignment of the connecting electrode 103, the binding electrode 6 and the connecting electrode 103 still have sufficient contact surface for binding, which greatly reduces the probability of poor binding between the binding electrode 6 and the connecting electrode 103, thereby improving the reliability of the display product composed of the display panel and the flip chip film, and improving the quality of the product.

[0067] It should be noted that, in order to ensure better electrical connection between the binding electrode 6 and the data line 3 , the orthographic projection of the binding electrode 6 on the substrate 100 is located within the orthographic projection of the data line 3 on the substrate 100 .

[0068] Exemplarily, the width of the binding surface of the binding electrode 6 along the first direction OA may be greater than the width of the portion of the data line 3 located in the display area AA along the first direction OA.

[0069] For example, the width of the binding surface of the binding electrode 6 along the first direction OA may be increased by 5%-20% compared with the width in the related art.

[0070] Exemplarily, the size of the binding surface of the binding electrode 6 may also be increased by increasing the width of the binding surface of the binding electrode 6 along the second direction OB.

[0071] In an exemplary embodiment, referring to Figure 3 As shown, the binding electrode located in the first binding area B1 is the first binding electrode 6;

[0072] refer to Figure 4a or Figure 4b As shown, the first binding area B1 includes a substrate 100, and a plurality of data lines 3, a first dielectric layer 8, a second dielectric layer 201, a plurality of first binding electrodes 6 and a plurality of first openings 61 located on the substrate 100;

[0073] The first opening 61 penetrates the first dielectric layer 8 and the second dielectric layer 201 in a direction perpendicular to the substrate 100 and exposes a portion of the data line 3 . The first binding electrode 6 is located in the first opening 61 and is electrically connected to the data line 3 .

[0074] In an exemplary embodiment, the thickness of the first dielectric layer 8 and the second dielectric layer 201 along a direction perpendicular to the substrate 100 is in a range of 0.4 μm to 0.6 μm.

[0075] Exemplarily, the first dielectric layer 8 and the second dielectric layer 201 have the same thickness along the direction perpendicular to the substrate 100. For example, the thickness along the direction perpendicular to the substrate 100 is 0.4 μm, 0.5 μm or 0.6 μm.

[0076] It should be noted that Figure 4a and Figure 4b In the figure, a first binding electrode 6, a first opening 61 and a data line 3 are drawn as examples for description.

[0077] In an exemplary embodiment, in the first binding region B1 , a first gate insulating layer 7 is further disposed between the substrate 100 and the data line 3 .

[0078] In an exemplary embodiment, referring to Figure 4b As shown, the distance h1 between the surface of the first binding electrode 6 away from the substrate 100 and the substrate 100 along the direction perpendicular to the substrate 100 is smaller than the distance h2 between the surface of the second dielectric layer 201 away from the substrate 100 and the substrate along the direction perpendicular to the substrate 100.

[0079] In an exemplary embodiment, the second dielectric layer 201 may not be provided, and the depth of the first opening 61 in the direction perpendicular to the substrate 100 may be increased by increasing the thickness of the first dielectric layer 8 in the direction perpendicular to the substrate 100, so that the distance between the surface of the first binding electrode 6 away from the substrate 100 and the substrate 100 in the direction perpendicular to the substrate 100 is smaller than the distance between the surface of the first dielectric layer 8 away from the substrate 100 and the substrate 100 in the direction perpendicular to the substrate 100.

[0080] In an exemplary embodiment, the material of the first dielectric layer 8 and the second dielectric layer 201 may be any one of silicon oxide, silicon nitride, or silicon oxynitride.

[0081] In an exemplary embodiment, the first dielectric layer 8 and the second dielectric layer 201 may be made of the same material.

[0082] In an exemplary embodiment, referring to Figure 4a As shown, both ends of the first binding electrode 6 may extend from the first opening 61 to the surface of the second dielectric layer 201 , so that the first binding electrode 6 covers the sidewalls of the first opening 61 and the upper edge of the first opening 61 .

[0083] In practical applications, no matter the first binding electrode 6 is Figure 4b As shown, the first binding electrode 6 is located inside the first opening 61; or, the first binding electrode 6 is as shown Figure 4a As shown, the first bonding electrode 6 extends from the first opening 61 to the surface of the second dielectric layer 201, so that the first bonding electrode 6 covers the sidewalls of the first opening 61 and the upper edge of the first opening 61. During the bonding process between the display panel and the chip-on-film, the surface of the first bonding electrode 6 that is bonded and in contact with the connecting electrode 103 is mainly located in the first opening 61 and away from the substrate 100.

[0084] In an embodiment of the present application, the orthographic projection outline of the connecting electrode 103 on the substrate 100 is set to be within the orthographic projection outline of the binding electrode (5 or 6) on the substrate 100, and the area of ​​the surface of the connecting electrode 103 close to the binding electrode (5 or 6) is smaller than the area of ​​the surface of the binding electrode (5 or 6) away from the substrate 100, and the distance h1 between the surface of the first binding electrode 6 away from the substrate 100 and the substrate 100 along the direction perpendicular to the substrate 100 is set to be smaller than the distance h2 between the surface of the second dielectric layer 201 away from the substrate 100 and the substrate along the direction perpendicular to the substrate 100.

[0085] Thus, during the bonding process, even if the connection electrodes 103 of the flip chip film are offset or misaligned, the reference electrode 103 can be used to connect the flip chip to the flip chip. Figure 8 As shown, the side wall 62 of the first opening 61 limits the movement of the connecting electrode 103, so that the offset range of the connecting electrode 103 is located within the area where the first opening 61 is located, thereby effectively reducing the possibility of a larger offset of the connecting electrode 103, and greatly reducing the probability of poor binding between the first binding electrode 6 and the connecting electrode 103, thereby improving the reliability of the display product composed of the display panel and the flip chip film, and improving the quality of the product.

[0086] In an exemplary embodiment, referring to Figure 3As shown, the peripheral area further includes a second binding area B2, the second binding area B1 is located on the other side of the display area AA, and the second binding area B2 is connected to the first binding area B1;

[0087] The display panel further includes a plurality of scan lines 1 arranged along the second direction OB and extending along the first direction OA. The scan lines 1 intersect and are insulated from the data lines 3. The scan lines 1 extend from the display area AA to the second binding area B2.

[0088] The width d1 of the portion of the scan line 3 located in the second binding area B2 along the second direction OB is greater than the width d2 of the portion of the scan line 3 located in the display area AA along the second direction OB.

[0089] For example, the width d2 of the portion of the scan line 3 located in the display area AA along the second direction OB may be 32.5 μm, and the width d1 of the portion of the scan line 3 located in the second binding area B2 along the second direction OB may be 39 μm.

[0090] In an exemplary embodiment, after the width d1 of the portion of the scan line 1 located in the second binding area B2 along the second direction OB is increased, the width of the binding electrode 5 along the second direction OB can be appropriately increased, thereby increasing the size of the binding surface of the binding electrode 5. In this way, when there is a certain degree of misalignment of the connecting electrode 103, the binding electrode 5 and the connecting electrode 103 still have sufficient contact surface for binding, which greatly reduces the probability of poor binding between the binding electrode 5 and the connecting electrode 103, thereby improving the reliability of the display product composed of the display panel and the flip chip film and improving the quality of the product.

[0091] It should be noted that, in order to ensure better electrical connection between the binding electrode 5 and the scan line 1 , the orthographic projection of the binding electrode 5 on the substrate 100 is located within the orthographic projection of the scan line 1 on the substrate 100 .

[0092] Exemplarily, the width of the binding surface of the binding electrode 5 along the second direction OB may be greater than the width of the portion of the scan line 1 located in the display area AA along the second direction OB.

[0093] For example, the width of the binding surface of the binding electrode 5 along the second direction OB may be increased by 5%-20% compared with the width in the related art.

[0094] Exemplarily, the size of the binding surface of the binding electrode 5 may also be increased by increasing the width of the binding surface of the binding electrode 5 along the second direction OB.

[0095] In an exemplary embodiment, in combination with Figure 3 、 Figure 6a and Figure 6b As shown, the binding electrode located in the second binding area B2 is the second binding electrode 5;

[0096] The second binding region B2 includes a substrate 100, and a plurality of scanning lines 1, a first gate insulating layer 7, a second gate insulating layer 200, a first dielectric layer 8, a plurality of second binding electrodes 5 and a plurality of second openings 51 located on the substrate 100;

[0097] The second opening 51 penetrates the first gate insulating layer 7 , the second gate insulating layer 200 and the first dielectric layer 8 in a direction perpendicular to the substrate 100 and exposes a portion of the scanning line 1 ; the second binding electrode 5 is located in the second opening 51 and is electrically connected to the scanning line 1 .

[0098] In an exemplary embodiment, referring to Figure 6b As shown, the distance h3 between the surface of the second binding electrode 5 away from the substrate 100 and the substrate 100 along the direction perpendicular to the substrate 100 is smaller than the distance h4 between the surface of the first dielectric layer 8 away from the substrate 100 and the substrate 100 along the direction perpendicular to the substrate 100.

[0099] In an exemplary embodiment, the second gate insulating layer 200 may not be provided, and by increasing the thickness of the first gate insulating layer 7 in a direction perpendicular to the substrate 100, the distance between the surface of the second binding electrode 5 away from the substrate 100 and the substrate 100 in the direction perpendicular to the substrate 100 is made smaller than the distance between the surface of the first dielectric layer 8 away from the substrate 100 and the substrate 100 in the direction perpendicular to the substrate 100.

[0100] In an exemplary embodiment, in Figure 6b On the basis of the structure shown, the second binding area B1 further includes a second dielectric layer 201, the second dielectric layer 201 covers the first dielectric layer 8, and the second opening 51 also penetrates the second dielectric layer 201; wherein, the distance between the surface of the second binding electrode 5 away from the substrate 100 and the substrate 100 along the direction perpendicular to the substrate 100 is smaller than the distance between the surface of the second dielectric layer 8 away from the substrate 100 and the substrate 100 along the direction perpendicular to the substrate 100.

[0101] In an exemplary embodiment, the second binding region B2 may include: Figure 5 The substrate 100, the scan line 1, the gate insulating layer 7, the first dielectric layer 8 and the second dielectric layer 201 are shown, and the second opening 51 penetrates the gate insulating layer 7, the first dielectric layer 8 and the second dielectric layer 201 and exposes a partial area of ​​the scan line 1; the second binding electrode 5 is located in the second opening 51 and is electrically connected to the scan line 1.

[0102] In an exemplary embodiment, referring to Figure 6a As shown, both ends of the second binding electrode 5 may extend from the second opening 51 to the surface of the first dielectric layer 8 , so that the second binding electrode 5 covers the sidewalls and the upper edge of the second opening 51 .

[0103] In an embodiment of the present application, the orthographic projection outline of the connecting electrode 103 on the substrate 100 is set to be within the orthographic projection outline of the binding electrode (5 or 6) on the substrate 100, and the area of ​​the surface of the connecting electrode 103 close to the binding electrode (5 or 6) is smaller than the area of ​​the surface of the binding electrode (5 or 6) away from the substrate 100, and the distance h3 between the surface of the second binding electrode 5 away from the substrate 100 and the substrate 100 along the direction perpendicular to the substrate 100 is smaller than the distance h4 between the surface of the first dielectric layer 8 away from the substrate 100 and the substrate 100 along the direction perpendicular to the substrate 100.

[0104] Thus, during the bonding process, even if the connection electrodes 103 of the flip chip film are offset or misaligned, the reference electrode 103 can be used to connect the flip chip to the flip chip. Figure 8 As shown, the side wall 52 of the second opening 51 limits the movement of the connecting electrode 103, so that the offset range of the connecting electrode 103 is located within the area where the second opening 51 is located, thereby effectively reducing the possibility of a larger offset of the connecting electrode 103, and greatly reducing the probability of poor binding between the second binding electrode 5 and the connecting electrode 103, thereby improving the reliability of the display product composed of the display panel and the flip chip film, and improving the quality of the product.

[0105] In practical applications, to simplify the manufacturing process, the first binding region B1 can be configured to include a substrate 100, and multiple data lines 3, a first dielectric layer 8, a second dielectric layer 201, multiple first binding electrodes 6, and multiple first openings 61 located on the substrate 100. The first openings 61 penetrate the first dielectric layer 8 and the second dielectric layer 201 in a direction perpendicular to the substrate 100 and expose portions of the data lines 3. The first binding electrodes 6 are located within the first openings 61 and are electrically connected to the data lines 3. The second binding region B2 can be configured to include the substrate 100, the scan lines 1, the gate insulating layer 7, the first dielectric layer 8, and the second dielectric layer 201. The second openings 51 penetrate the gate insulating layer 7, the first dielectric layer 8, and the second dielectric layer 201 and expose portions of the scan lines 1. The second binding electrodes 5 are located within the second openings 51 and are electrically connected to the scan lines 1.

[0106] In an exemplary embodiment, the maximum width of the first binding electrodes 6 along the first direction OA is greater than the distance between two adjacent first binding electrodes 6 .

[0107] In practical applications, in order to increase the maximum width of the first binding electrode 6 along the first direction OA, it is necessary to appropriately reduce the distance between two adjacent first binding electrodes 6 to ensure that the size change of the data line 3 located in the first binding area B1 and the size change of the first binding electrode 6 do not affect the design and arrangement of other structures of the display panel.

[0108] In an exemplary embodiment, referring to Figure 3 As shown, the display area AA includes a plurality of pixel units arranged in an array, and the scan line 1 and the data line 3 define the area where the pixel units are located;

[0109] In the case where one scan line 1 is connected to a row of pixel units, the maximum width of the second binding electrodes 5 along the second direction OB is greater than the distance between two adjacent second binding electrodes 5 .

[0110] It should be noted that a scan line 1 connecting a row of pixel units means that a scan line 1 scans only one row of pixel units within a time period. In this case, by reducing the distance between two adjacent second binding electrodes 5 and increasing the width of the second binding electrode 5 along the second direction OB, the size of the binding surface of the second binding electrode 5 can be increased without affecting the design and arrangement of other structures in the display panel. This ensures that even if the connecting electrode 103 is misaligned to a certain extent, the binding electrode 6 and the connecting electrode 103 still have sufficient contact surface for bonding, greatly reducing the probability of poor bonding between the second binding electrode 5 and the connecting electrode 103.

[0111] In an exemplary embodiment, referring to Figure 3 As shown, the width of the portion of the data line 3 located in the first binding area B1 along the first direction OA is 5%-20% greater than the width of the portion of the data line 3 located in the display area AA along the first direction OA.

[0112] In an exemplary embodiment, referring to Figure 3 As shown, the width of the portion of the scan line 1 located in the second binding area B2 along the second direction OB is 5%-20% greater than the width of the portion of the scan line 1 located in the display area AA along the second direction OB.

[0113] The display panel provided in the embodiment of the present application also includes the following Figure 3 The thin film transistor 2 shown, of course, the display panel also includes other components and structures, here only the structure related to the invention point is introduced, the other structures included in the display panel can be obtained according to relevant technologies or common knowledge, and will not be repeated here.

[0114] The embodiment of the present application provides a chip-on-film 104 electrically connected to the display panel as described above; the chip-on-film 104 includes a plurality of connecting electrodes 103; the peripheral area of ​​the display panel includes a plurality of binding electrodes (5 or 6); the binding electrodes (5 or 6) are electrically connected to the connecting electrodes 103;

[0115] In which, the orthographic projection outline of the connecting electrode 103 on the substrate 100 of the display panel is located within the orthographic projection outline of the binding electrode (5 or 6) on the substrate 100, and the area of ​​the surface of the connecting electrode 103 close to the binding electrode (5 or 6) is smaller than the area of ​​the surface of the binding electrode (5 or 6) away from the substrate 100.

[0116] In an exemplary embodiment, the chip on film (COF) 104 can be divided into a tape-on-reel packaging substrate (TAB substrate, whose manufacturing process is called TCP), a flexible board-connected chip assembly, and a flexible IC carrier packaging substrate (Tape BGA / CSP).

[0117] In the embodiment of the present application, the orthographic projection outline of the connecting electrode 103 on the substrate 100 is arranged to be located within the orthographic projection outline of the binding electrode (5 or 6) on the substrate 100, and the area of ​​the surface of the connecting electrode 103 close to the binding electrode (5 or 6) is made smaller than the area of ​​the surface of the binding electrode (5 or 6) away from the substrate 100. Since the area of ​​the surface provided by the binding electrode (5 or 6) for binding is larger than the area of ​​the surface provided by the connecting electrode 103 for binding, even if the connecting electrode 103 on the chip-on-film is misaligned, the orthographic projection outline of the connecting electrode 103 on the substrate 100 can still be located within the orthographic projection outline of the binding electrode (5 or 6) on the substrate 100, so that there is still sufficient contact area between the connecting electrode 103 and the binding electrode (5 or 6) to complete the binding connection, thereby greatly improving the problem of poor binding between the binding electrode (5 or 6) on the display panel and the connecting electrode 103 on the chip-on-film due to misalignment, thereby improving product quality.

[0118] An embodiment of the present application provides a display device, including the display panel and the chip-on-film as described above, wherein the display panel and the chip-on-film are bound together.

[0119] The display device may be any one of an LCD display device, an OLED display device, a Micro OLED micro-display device, and a Mini LED micro-display device. If the display device is a liquid crystal display device, the liquid crystal display device may be a TN (Twisted Nematic) type, a VA (Vertical Alignment) type, an IPS (In-Plane Switching) type, or an ADS (Advanced Super Dimension Switch) type liquid crystal display device.

[0120] In addition, the display device may be a display device such as an LCD display device, as well as any product or component with a display function, such as a television, a digital camera, a mobile phone, a tablet computer, etc. that includes these display devices.

[0121] In the display device provided in the embodiment of the present application, the orthographic projection outline of the connecting electrode 103 on the substrate 100 is arranged to be located within the orthographic projection outline of the binding electrode (5 or 6) on the substrate 100, and the area of ​​the surface of the connecting electrode 103 close to the binding electrode (5 or 6) is made smaller than the area of ​​the surface of the binding electrode (5 or 6) away from the substrate 100. Because the area of ​​the surface provided by the binding electrode (5 or 6) for binding is larger than the area of ​​the surface provided by the connecting electrode 103 for binding, even if the connecting electrode 103 on the chip-on-film is misaligned, the orthographic projection outline of the connecting electrode 103 on the substrate 100 can still be located within the orthographic projection outline of the binding electrode (5 or 6) on the substrate 100, so that there is still sufficient contact area between the connecting electrode 103 and the binding electrode (5 or 6) to complete the bonding connection. This greatly improves the problem of poor bonding between the binding electrode (5 or 6) on the display panel and the connecting electrode 103 on the chip-on-film due to misalignment, thereby improving product quality.

[0122] The embodiment of the present application provides a method for preparing the display panel as described above, referring to Figure 9 As shown, the method includes:

[0123] Providing a substrate 100; dividing the substrate 100 into a display area AA and a peripheral area adjacent to the display area AA (including Figure 3 The area where the markers B1 and B2 are shown);

[0124] A plurality of binding electrodes (5 or 6) are formed on a portion of the substrate 100 located in the peripheral area; wherein the binding electrodes (5 or 6) are electrically connected to the connecting electrodes 103 on the flip chip film 104, the orthographic projection outline of the connecting electrodes 103 on the substrate 100 is located within the orthographic projection outline of the binding electrodes (5 or 6) on the substrate 100, and the area of ​​the surface of the connecting electrode 103 close to the binding electrode (5 or 6) is smaller than the area of ​​the surface of the binding electrode (5 or 6) away from the substrate 100.

[0125] The display panel prepared by the preparation method provided in the embodiment of the present application is configured such that the orthographic projection outline of the connecting electrode 103 on the substrate 100 is located within the orthographic projection outline of the binding electrode (5 or 6) on the substrate 100, and the area of ​​the surface of the connecting electrode 103 close to the binding electrode (5 or 6) is smaller than the area of ​​the surface of the binding electrode (5 or 6) away from the substrate 100. Because the area of ​​the surface provided by the binding electrode (5 or 6) for binding is larger than the area of ​​the surface provided by the connecting electrode 103 for binding, even if the connecting electrode 103 on the chip-on-film is misaligned, the orthographic projection outline of the connecting electrode 103 on the substrate 100 can still be located within the orthographic projection outline of the binding electrode (5 or 6) on the substrate 100, so that there is still sufficient contact area between the connecting electrode 103 and the binding electrode (5 or 6) to complete the bonding connection. This greatly improves the problem of poor bonding between the binding electrode (5 or 6) on the display panel and the connecting electrode 103 on the chip-on-film due to misalignment, thereby improving product quality.

[0126] Below Figure 3 Taking the structure shown in FIG. 1 as an example, the method for preparing the display panel is described in detail.

[0127] S1. Reference Figure 10 As shown, a substrate 100 is provided, and a gate line 1 and a gate 21 (Gate) of a thin film transistor 2 are formed on the substrate 100 .

[0128] The process of forming the gate 21 includes the steps of film formation, photoresist coating, exposure, development, etching and photoresist stripping, and the details can be referred to the relevant technology.

[0129] The width d1 of the portion of the scan line 3 located in the second binding area B2 along the second direction OB is greater than the width d2 of the portion of the scan line 3 located in the display area AA along the second direction OB.

[0130] S2. Form a gate insulating layer 7 (GI).

[0131] The material of the gate insulating layer 7 can be any one of silicon nitride, silicon oxide or silicon oxynitride.

[0132] S3. Reference Figure 11a As shown, an active layer 22 is formed.

[0133] The active layer 22 is made of amorphous silicon (a-Si) and N-type doped amorphous silicon (n-Si). + a-Si).

[0134] Among them, Figure 11a The structure of the gate insulating layer 7 is not shown in the top view of the display panel. Figure 11b for Figure 11aCross-sectional view along the E1E2 direction, Figure 11c for Figure 11a Cross-sectional view along the F1F1 direction.

[0135] S4. References Figure 12a As shown, the data line 3 and the source electrode and the drain electrode of the thin film transistor 2 are formed.

[0136] The width d4 of the portion of the data line 3 located in the first binding area B1 along the first direction OA is greater than the width d3 of the portion of the data line 3 located in the display area AA along the first direction OA.

[0137] S5. Forming a first dielectric layer 8.

[0138] S6. Forming a second dielectric layer 201.

[0139] S7, patterning process, so as to simultaneously obtain the first opening 61, the second opening 51 and the Figure 12d The via hole on the drain electrode 24 of the thin film transistor 2 is shown.

[0140] Specifically, the first dielectric layer 8 and the second dielectric layer 201 located in the first binding area B1 are patterned to obtain the following Figure 12c The gate insulating layer 7, the first dielectric layer 8 and the second dielectric layer 201 located in the second binding region B2 are patterned to obtain the following Figure 12b The first dielectric layer 8 and the second dielectric layer 201 located in the display area AA are patterned to obtain the second opening 51 shown in FIG. Figure 12d vias shown.

[0141] in, Figure 12c for Figure 12a Cross-sectional view along the G1G2 direction, Figure 12b for Figure 12a Cross-sectional view along the H1H2 direction, Figure 12d for Figure 12a Cross-sectional view along the I1I2 direction.

[0142] S8, forming a conductive film layer and performing patterning, and obtaining Figure 13 The pixel electrode 4 shown in the display area AA is Figure 3 As shown, a first binding electrode 6 is located in the first binding area B1 and a second binding electrode 5 is located in the second binding area B2.

[0143] The pixel electrode 4 is electrically connected to the drain electrode 24 of the thin film transistor 2 through a via hole, and the source electrode 23 of the thin film transistor 2 is electrically connected to the data line 3 .

[0144] In an exemplary embodiment, by providing the second dielectric layer 201, the distance between the surface of the first binding electrode 6 away from the substrate 100 and the substrate 100 along the direction perpendicular to the substrate 100 is smaller than the distance between the surface of the second dielectric layer 201 away from the substrate 100 and the substrate 100 along the direction perpendicular to the substrate 100; and the distance between the surface of the second binding electrode 5 away from the substrate 100 and the substrate 100 along the direction perpendicular to the substrate 100 is smaller than the distance between the surface of the second dielectric layer 201 away from the substrate 100 and the substrate along the direction perpendicular to the substrate 100.

[0145] In this way, the depth of the first opening 61 and the second opening 51 in the direction perpendicular to the substrate 100 is increased, so that the first bonding electrode 6 is located in the first opening 61 and the second bonding electrode 5 is located in the second opening 51, forming a "recessed" bonding electrode (5 and 6). During the bonding process, even if the connection electrode 103 of the flip chip film is offset or misaligned, the first bonding electrode 6 is located in the first opening 61 and the second bonding electrode 5 is located in the second opening 51. Figure 8 As shown, the side wall 62 of the first opening 61 will limit the movement of the connecting electrode 103, so that the offset range of the connecting electrode 103 is located within the area where the first opening 61 is located, and the side wall 52 of the second opening 51 will also limit the movement of the connecting electrode 103 bound thereto; thereby effectively reducing the possibility of a larger offset of the connecting electrode 103, and greatly reducing the probability of poor binding between the binding electrodes (5 and 6) and the connecting electrode 103, thereby improving the reliability of the display product composed of the display panel and the flip chip film, and improving the quality of the product.

[0146] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a peripheral area adjacent to the display area. The peripheral area includes a substrate and a plurality of binding electrodes located on the substrate, wherein the binding electrodes are electrically connected to the connection electrodes on the chip-on-film; The orthographic projection outline of the connecting electrode on the substrate is located within the orthographic projection outline of the binding electrode on the substrate, and the area of ​​the surface of the connecting electrode close to the binding electrode is smaller than the area of ​​the surface of the binding electrode away from the substrate; Among them, the multiple binding electrodes include a first binding electrode and a second binding electrode, the peripheral area includes a first binding area and a second binding area, the first binding area includes the first binding electrode, a first dielectric layer, a second dielectric layer, multiple first binding electrodes and multiple first openings, the first opening passes through the first dielectric layer and the second dielectric layer, the first binding electrode is located in the first opening, and the sidewall of the first opening limits the movement of the connecting electrode; the second binding area includes the second binding electrode, the first dielectric layer and multiple second openings, the second opening passes through the first dielectric layer, the second binding electrode is located in the second opening, and the sidewall of the second opening limits the movement of the connecting electrode.

2. The display panel according to claim 1, wherein: The peripheral area includes a first binding area, and the first binding area is located on one side of the display area; The display panel further includes a plurality of data lines arranged along a first direction and extending along a second direction, wherein the data lines extend from the display area to the first binding area, and the first direction and the second direction intersect; The width of a portion of the data line located in the first binding area along the first direction is greater than the width of a portion of the data line located in the display area along the first direction.

3. The display panel according to claim 2, wherein: The first binding area further includes the substrate and a plurality of data lines located on the substrate; The first opening penetrates the first dielectric layer and the second dielectric layer in a direction perpendicular to the substrate and exposes a partial area of ​​the data line; The first binding electrode is located in the first opening and is electrically connected to the data line.

4. The display panel according to claim 3, wherein: The distance between the surface of the first binding electrode away from the substrate and the substrate along a direction perpendicular to the substrate is smaller than the distance between the surface of the second dielectric layer away from the substrate and the substrate along a direction perpendicular to the substrate.

5. The display panel according to claim 2, wherein: The second binding area is located on the other side of the display area, and the second binding area is connected to the first binding area; The display panel further includes a plurality of scan lines arranged along the second direction and extending along the first direction, the scan lines intersecting and insulated from the data lines, and the scan lines extending from the display area to the second binding area; The width of the portion of the scan line located in the second binding area along the second direction is greater than the width of the portion of the scan line located in the display area along the second direction.

6. The display panel according to claim 5, wherein: The second binding region further includes the substrate, and a plurality of the scan lines, a first gate insulating layer, and a second gate insulating layer located on the substrate; The second opening penetrates the first gate insulating layer, the second gate insulating layer and the first dielectric layer in a direction perpendicular to the substrate and exposes a partial area of ​​the scan line; the second binding electrode is located in the second opening and is electrically connected to the scan line.

7. The display panel according to claim 6, wherein: The distance between the surface of the second binding electrode away from the substrate and the substrate in a direction perpendicular to the substrate is smaller than the distance between the surface of the first dielectric layer away from the substrate and the substrate in a direction perpendicular to the substrate.

8. The display panel according to claim 6, wherein: The second binding area further includes a second dielectric layer, the second dielectric layer covers the first dielectric layer, and the second opening also penetrates the second dielectric layer; The distance between the surface of the second binding electrode away from the substrate and the substrate in a direction perpendicular to the substrate is smaller than the distance between the surface of the second dielectric layer away from the substrate and the substrate in a direction perpendicular to the substrate.

9. The display panel according to claim 3, wherein: The maximum width of the first binding electrode along the first direction is greater than the distance between two adjacent first binding electrodes.

10. The display panel according to claim 6, wherein: The display area includes a plurality of pixel units arranged in an array, and the scan lines and the data lines define an area where the pixel units are located; In the case where one of the scan lines is connected to a row of the pixel units, the maximum width of the second binding electrodes along the second direction is greater than the distance between two adjacent second binding electrodes.

11. The display panel according to claim 2, wherein: A width of a portion of the data line located in the first binding area along the first direction is 5%-20% greater than a width of a portion of the data line located in the display area along the first direction.

12. A chip-on-film, characterized in that: electrically connected to the display panel according to any one of claims 1 to 11; The chip-on-film includes a plurality of connecting electrodes; the peripheral area of ​​the display panel includes a plurality of binding electrodes; the binding electrodes are electrically connected to the connecting electrodes; The orthographic projection outline of the connecting electrode on the substrate of the display panel is located within the orthographic projection outline of the binding electrode on the substrate, and the area of ​​the surface of the connecting electrode close to the binding electrode is smaller than the area of ​​the surface of the binding electrode away from the substrate.

13. A display device, characterized in that: The device comprises the display panel according to any one of claims 1 to 11 and the chip-on-film according to claim 12, wherein the display panel and the chip-on-film are bound together.

14. A method for preparing a display panel according to any one of claims 1 to 11, characterized in that: The method comprises: Providing a substrate; dividing the substrate into a display area and a peripheral area adjacent to the display area; forming a plurality of binding electrodes on a portion of the substrate located in the peripheral region; wherein the binding electrodes are electrically connected to connection electrodes on the chip-on-film, an orthographic projection outline of the connection electrodes on the substrate is located within an orthographic projection outline of the binding electrodes on the substrate, and an area of ​​a surface of the connection electrodes close to the binding electrodes is smaller than an area of ​​a surface of the binding electrodes away from the substrate; Among them, the multiple binding electrodes include a first binding electrode and a second binding electrode, the peripheral area includes a first binding area and a second binding area, the first binding area includes the first binding electrode, a first dielectric layer, a second dielectric layer, multiple first binding electrodes and multiple first openings, the first opening passes through the first dielectric layer and the second dielectric layer, the first binding electrode is located in the first opening, and the sidewall of the first opening limits the movement of the connecting electrode; the second binding area includes the second binding electrode, the first dielectric layer and multiple second openings, the second opening passes through the first dielectric layer, the second binding electrode is located in the second opening, and the sidewall of the second opening limits the movement of the connecting electrode.

Images