Management of the Unmapped Allocation Unit of the Memory Subsystem

Abstract

An indication that an allocation unit of a memory subsystem has become unmapped is received. In response to receiving the indication that the allocation unit of the memory subsystem has become unmapped, the allocation unit may be programmed with a data pattern. Data to be written to the unmapped allocation unit may be received. The received data may be programmed at the unmapped allocation unit by performing a write operation using a read voltage based on the data pattern.

Description

Technical Field

[0001] The present disclosure generally relates to a memory subsystem, and more particularly, to the management of an unmap-allocated unit of a memory subsystem. Background Art

[0002] A memory subsystem can be a storage system, a memory module, or a combination of a storage device and a memory module. The memory subsystem can include one or more memory components that store data. The memory components can be, for example, non-volatile memory components and volatile memory components. Generally, a host system can utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the Invention

[0003] In one exemplary embodiment, a method for operating a memory system includes: receiving an indication that an allocated unit of a memory subsystem has become unmapped; in response to receiving the indication that the allocated unit of the memory subsystem has become unmapped, programming the allocated unit by a processing device with a data pattern based on a voltage change direction of a threshold voltage distribution of the allocated unit; receiving data to be written to the unmapped allocated unit; and performing a write operation by using a read voltage based on the data pattern to program the received data at the unmapped allocated unit.

[0004] In another exemplary embodiment, a non-transitory computer-readable medium includes instructions that, when executed by a processing device, cause the processing device to perform operations including: receiving an indication that an allocated unit of a memory subsystem has become unmapped; in response to receiving the indication that the allocated unit of the memory subsystem has become unmapped, programming the allocated unit with a data pattern based on a voltage change direction of a threshold voltage distribution of the allocated unit; receiving data to be written to the unmapped allocated unit; and performing a write operation by using a read voltage based on the data pattern to program the received data at the unmapped allocated unit.

[0005] In yet another exemplary embodiment, a memory system includes a memory component and a processing device operatively coupled to the memory component, wherein the processing device is configured to: receive an indication to remove a group of memory cells of the memory subsystem from a logical address space for accessing the memory subsystem; in response to receiving the indication, remove the group of memory cells of the memory subsystem from the logical address space; and program the group of memory cells removed from the logical address space with a voltage state, wherein the voltage state is based on a voltage change direction of a threshold voltage distribution of the group of memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the disclosure.

[0007] Figure 1 Illustrate an example computing environment that includes a memory subsystem in accordance with some embodiments of the present disclosure.

[0008] Figure 2 is a flowchart of an example method for programming a high voltage state at an unmapped allocation unit and performing a write operation using a lowest prefetch voltage in accordance with some embodiments.

[0009] Figure 3 Illustrate voltage states associated with data patterns and prefetch voltages in accordance with some embodiments of the present disclosure.

[0010] Figure 4 is a flowchart of an example method for managing an unmapped allocation unit based on data patterns and prefetch voltages in accordance with some embodiments.

[0011] Figure 5A Illustrate a transformation between an unmapped allocation unit and a mapped allocation unit in accordance with some embodiments of the present disclosure.

[0012] Figure 5B Illustrate a transformation between an unmapped allocation unit and a mapped allocation unit based on a host system command in accordance with some embodiments of the present disclosure.

[0013] Figure 5C Illustrate a transformation between an unmapped allocation unit and a mapped allocation unit based on a wear leveling operation in accordance with some embodiments of the present disclosure.

[0014] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure relate to the management of an unmapped allocation unit of a memory subsystem. The memory subsystem can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices and memory modules are described below in conjunction with Figure 1 In general, a host system can utilize a memory subsystem that includes one or more memory components. The host system can provide data to be stored at the memory subsystem and can request retrieval of data from the memory subsystem.

[0016] A conventional memory subsystem can store data at an allocation unit. The allocation unit can be an individual section or portion of the memory subsystem that can be accessed independently by the host system. For example, the allocation unit can be used to store the smallest amount of data that can be retrieved or written to the memory subsystem independently. In some embodiments, the allocation unit can be one or more memory cells of a memory component included in the memory subsystem. The allocation unit can be mapped or unmapped. A mapped allocation unit can refer to an allocation unit that has been assigned to a logical address space used by the host system. For example, a mapped allocation unit can be currently used to store and retrieve data for the host system. An unmapped allocation unit can refer to an allocation unit that is not currently assigned to a logical address space used by the host system. For example, an unmapped allocation unit can be a group of over-provisioned data blocks that are currently inaccessible to the host system in the memory subsystem. In some embodiments, when the allocation unit is placed in an erased state, the allocation unit can become unmapped.

[0017] The allocation unit can switch between being mapped and unmapped. For example, the allocation unit can be unmapped during an initial operational lifetime of the memory subsystem and can subsequently be assigned to be accessible by the host system and become mapped. In some embodiments, the allocation unit can be mapped and can become unmapped in response to a host command (e.g., a trim command) or a wear leveling operation performed by the memory subsystem. Later, the unmapped allocation unit can return to being mapped in response to another host command or wear leveling operation.

[0018] A write operation performed by the memory subsystem can utilize a pre-read sub-operation. For example, the memory subsystem can utilize a cross-point array memory where the write operation can be an in-place write operation that can program the memory cells of the cross-point array memory without erasing the memory cells. In such an in-place write operation, the pre-read sub-operation can retrieve the current state (e.g., value) of the memory cell and can change the value of the memory cell if the value to be written is different from the current value of the memory cell. For example, if the memory cell currently stores the value '1' and the value '1' is to be written, the value '1' will not be reprogrammed into the memory cell because the stored value matches the requested value.

[0019] Memory cells can represent different bit values using a low voltage (LV) state and a high voltage (HV) state. For example, the LV state can represent the bit value '0', and the HV state can represent the bit value '1' (or vice versa). The presence of the LV state or the HV state (i.e., the threshold voltage distribution) can be detected at the memory cell by applying a voltage (i.e., the read threshold voltage) to the memory cell. However, due to the physical characteristics of the memory cell, the threshold voltage distribution of the memory cell changes or migrates over time. Therefore, as part of a pre-read operation, applying the read threshold voltage to the memory cell can result in retrieving an incorrect value. For example, for a type of media component where the threshold voltage distribution migrates towards a higher voltage over time, it may be incorrectly determined that the memory cell is in the HV state instead of the originally programmed LV state. Thus, since the pre-read operation may return an incorrect value, the memory subsystem may determine not to program the memory cell with a new value in the case where the new value to be programmed matches the value represented by the incorrect HV state. Therefore, the number of errors stored at the memory subsystem may increase.

[0020] Aspects of the present disclosure address the above and other deficiencies by managing the unmapped allocation units of the memory subsystem. For example, when an allocation unit becomes unmapped, the memory subsystem can perform a write operation at the allocation unit. The write operation can place the memory cells of the allocation unit in a certain state. For example, based on the characteristics of the media component (i.e., the direction of threshold voltage migration), a data pattern (e.g., a high voltage state) can be programmed into each memory cell of the allocation unit. Subsequently, when the allocation unit is to become mapped, data from the host system can be programmed into the allocation unit. For example, the data can be written to the allocation unit based on a pre-read voltage that is lower than the data pattern or the high voltage state. For example, the read threshold voltage used during the pre-read operation can utilize the lowest or a lower read threshold voltage available for the memory subsystem.

[0021] Advantages of the present disclosure include, but are not limited to, improving the performance of a memory subsystem because data retrieved from the memory subsystem can contain fewer errors. For example, for a media component type where the threshold voltage distribution migrates to a higher voltage, when an allocation unit is unmapped, a data pattern corresponding to a high voltage state can be programmed into the memory cells of the allocation unit. Thus, fewer errors can be retrieved for a prefetch sub-operation using a lower read threshold voltage because the lower read threshold voltage can more accurately detect the presence of the high voltage state of the data pattern applied to the unmapped allocation unit. Thus, a write operation using the result of the prefetch sub-operation can accurately program the data because the result of the prefetch sub-operation is used to determine whether to program the memory cells of the allocation unit. Thus, the performance of the memory subsystem can be improved because fewer error correction operations can be performed. For example, fewer read retry operations will be performed to retrieve data from the allocation unit. Thus, more read operations and write operations can be performed by the memory subsystem.

[0022] Figure 1 Illustrate an example computing environment 100 that includes a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 can include media, such as memory components 112A to 112N. The memory components 112A to 112N can be volatile memory components, non-volatile memory components, or a combination of such components. The memory subsystem 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMCs) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0023] The computing environment 100 can include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 Illustrate an example of a host system 120 coupled to a memory subsystem 110. The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intervening component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0024] The host system 120 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, an embedded computer (e.g., a computer included in a vehicle, an industrial device, or a networked commercial device), or such a computing device that includes a memory and a processing device. The host system 120 can include or be coupled to the memory subsystem 110 such that the host system 120 can read data from or write data to the memory subsystem. The host system 120 can be coupled to the memory subsystem 110 through a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 can also utilize the Non-Volatile Memory Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface can provide an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0025] Memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory. Each of memory components 112A to 112N may include one or more arrays of memory cells, such as single-level cells (SLCs) or multi-level cells (MLCs) (e.g., triple-level cells (TLCs) or quad-level cells (QLCs)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of memory cells. Each of the memory cells may store one or more bits of data (e.g., data blocks) used by host system 120. Although non-volatile memory components such as NAND-type flash memory are described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory may perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-gridded data access array. Additionally, compared to many flash-based memories, cross-point non-volatile memory may perform in-place write operations, where non-volatile memory cells may be programmed without first erasing the non-volatile memory cells. Further, the memory cells of memory components 112A to 112N may be grouped into memory pages or data blocks, which may refer to the units of the memory components used to store data.

[0026] A memory system controller 115 (hereinafter referred to as "controller") can communicate with memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at the memory components 112A to 112N, and other such operations. The controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 can include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines to control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 can include memory registers for storing memory pointers, fetched data, etc. The local memory 119 can also include a read only memory (ROM) for storing microcode. Although the Figure 1 illustrated example memory subsystem 110 is shown as including a controller 115, in another embodiment of the present disclosure, the memory subsystem 110 may not include a controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0027] Generally, the controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. The controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between the logical block addresses and the physical block addresses associated with the memory components 112A to 112N. The controller 115 can also include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access the memory components 112A to 112N, and convert responses associated with the memory components 112A to 112N into information for the host system 120.

[0028] Memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that may receive an address from controller 115 and decode the address to access memory components 112A through 112N.

[0029] Memory subsystem 110 includes allocation unit component 113 that can be used to manage an allocation unit for memory subsystem 110. In some embodiments, controller 115 includes at least a portion of allocation unit component 113. For example, controller 115 may include processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, allocation unit component 113 is part of host system 120, an application, or an operating system. In the same or alternative embodiments, a portion of allocation unit component 113 is part of host system 120 while other portions of allocation unit component 113 execute at controller 115.

[0030] Allocation unit component 113 can be used to manage an allocation unit of the memory subsystem. The allocation unit may include one or more memory cells (i.e., a group of memory cells). The allocation unit may become unmapped by an operation from the host system or by an operation performed by the memory subsystem (e.g., wear leveling, garbage collection). In response to the allocation unit changing from being mapped to being unmapped, a write operation may program a data pattern at the allocation unit. For example, each memory cell of the allocation unit may be programmed with a data pattern (e.g., a high voltage state). Subsequently, when host data is to be programmed to the allocation unit, as part of the write operation, a pre-read sub-operation may be performed at a lower or lowest available read threshold voltage. Other details regarding the operation of allocation unit component 113 are described below.

[0031] Figure 2 is a flowchart of an example method 200 for programming a high voltage state at an unmapped allocation unit and performing a write operation with a lowest pre-read voltage according to some embodiments. Method 200 may be executed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 200 is performed by Figure 1is performed by the allocation component 113. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Accordingly, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order and some processes may be performed in parallel. Additionally, one or more of the processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0032] As Figure 2 shown, at operation 210, the processing logic receives an indication that an allocation unit is unmapped. For example, the allocation unit may be unmapped during an initial operational lifetime of the memory subsystem that includes the allocation unit. In some embodiments, the allocation unit may transition from being mapped to becoming unmapped. For example, the allocation unit may be assigned a logical address of a logical address space used by the host system. The allocation unit may be unmapped using a wear leveling operation or a host command (i.e., a trim command). The wear leveling operation may remove the allocation unit from the logical address space and assign another currently unmapped allocation unit to the logical address of the removed allocation unit. For example, when a threshold number of write operations have been performed at the allocation unit, the allocation unit may be removed from the logical address space. The trim command may be an instruction from the host system to remove the allocation unit from the logical address space. For example, the allocation unit may be removed such that it is not accessible via the logical address used by the host system. At operation 220, the processing logic performs a write operation at the allocation unit to program the allocation unit to a high voltage state. For example, a certain data pattern may be written to one or more memory cells of the allocation unit. The data pattern may be the high voltage state stored at each memory cell of the allocation unit. At operation 230, the processing logic receives data to be written to the allocation unit that has been programmed to the high voltage state. For example, the data may be received from the host system. In some embodiments, the allocation unit may become available to the host system when the allocation unit becomes mapped to the logical address space of the host system. For example, the wear leveling operation may remove another allocation unit from the logical address space and may add the allocation unit to the logical address space.

[0033] In addition, at operation 240, the processing logic writes the received data at the allocation unit based on a pre-read voltage that is lower than the voltage of the high voltage state. For example, a write operation for programming the received data at the allocation unit can utilize a pre-read sub-operation that reads or retrieves the value of a memory cell of the allocation unit and compares the retrieved value with the value to be written to the memory cell. If the values match, the write operation will not program the memory cell because the intended value is already stored at the memory cell. Thus, no voltage signal is applied to the memory cell to change the stored value. Otherwise, if the values do not match, the write operation will program the memory cell to update or change the value at the memory cell to match the intended value of the received data. Thus, a voltage signal is applied to the memory cell to change the stored value. As previously discussed, the pre-read voltage can be lower than the voltage of the high voltage state. In some embodiments, the memory subsystem can perform the pre-read sub-operation using multiple different pre-read voltages. The lowest available pre-read voltage can be selected for the pre-read sub-operation. In some embodiments, a lower but not the lowest available pre-read voltage can be selected for the pre-read sub-operation. When performing the pre-read sub-operation, using a lower pre-read voltage can result in fewer errors, such that the determination of whether to change the value stored at the memory cell can be more accurate.

[0034] As described above, the data pattern can be the high voltage state and a lower pre-read voltage can be utilized during the pre-read sub-operation. In some embodiments, the data pattern can be the low voltage state and a higher pre-read voltage can be utilized during the pre-read sub-operation. The higher pre-read voltage can be higher than the voltage level of the low voltage state. The data pattern used can be based on or depend on the type of media component. For example, the threshold voltage distribution between different types of media components can change or shift in different directions with respect to voltage. In some embodiments, the threshold voltage distribution of one type of media component can change or shift over time towards higher voltages, while the threshold voltage distribution of another type of media component can change or shift over time towards lower voltages. The data pattern can be the high voltage state or the low voltage state based on the direction of change or shift of the threshold voltage distribution for the type of media component. For example, if the threshold voltage distribution (e.g., LV state and HV state) of a certain type of media component changes or shifts towards higher voltages over time, the data pattern can correspond to the high voltage state. Otherwise, if the threshold voltage distribution (e.g., LV state and HV state) of a certain type of media component changes or shifts towards lower voltages over time, the data pattern can correspond to the low voltage state. Thus, the data pattern can be based on the characteristics of the media component (i.e., the direction of threshold voltage shift).

[0035] Figure 3Describe the voltage states associated with data patterns and pre-read voltages according to some embodiments of the present disclosure. In some embodiments, a memory cell may be placed at a specific voltage, and a specific pre-read voltage may be selected by the Figure 1 allocation component 113.

[0036] As Figure 3 shown, the memory cell may be programmed to a low voltage (LV) state or a high voltage (HV) state to represent different bit values (e.g., '0' or '1', or vice versa). Additionally, the memory subsystem may perform a pre-read sub-operation using multiple pre-read voltages. For example, as shown, the memory subsystem may utilize a lower pre-read voltage 310, two medium pre-read voltages, and a higher pre-read voltage 320. If the memory cell is programmed to the high voltage state, more errors may occur when using the higher pre-read voltage 320 compared to using the lower pre-read voltage 310. Alternatively, if the memory cell is programmed to the low voltage state, more errors may occur when using the lower pre-read voltage 310 compared to using the higher pre-read voltage 320.

[0037] Figure 4 is a flowchart of an example method 400 for managing unmapped allocation units based on data patterns and pre-read voltages according to some embodiments. Method 400 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, method 400 is executed by the Figure 1 allocation component 113. Although shown in a specific order or sequence, the order of the process may be modified unless otherwise specified. Thus, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in a different order, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0038] As Figure 4As shown, at operation 410, the processing logic receives an indication that the allocation unit has become unmapped from the logical address space of the host system. In some embodiments, in response to a wear leveling operation or a trim command from the host system, the allocation unit may become unmapped. For example, the allocation unit may be removed from the logical address space of the host system and replaced with another allocation unit as part of a wear leveling operation, or the allocation unit may be removed from the logical address space in response to a trim command from the host system. At operation 420, the processing logic programs the memory cells of the allocation unit with a certain data pattern in response to receiving the indication that the allocation unit has become unmapped. As previously described, based on the type of media component, the data pattern may be a high voltage state or a low voltage state. For example, each memory cell of the allocation unit may be programmed to be in a higher voltage state if the threshold voltage distribution of the memory cell migrates or changes towards a higher voltage, or each memory cell of the allocation unit may be programmed to be in a low voltage state if the threshold voltage distribution of the memory cell migrates or changes towards a lower voltage. At operation 430, the processing logic receives a subsequent notification that the allocation unit will be remapped with data. For example, the allocation unit may be added to the logical address space to replace another allocation unit that will become unmapped and be removed from the logical address space. For example, the allocation unit may be added to the logical address space when a wear leveling operation has unmapped another allocation unit and the data of the unmapped allocation unit will be stored at the new allocation unit. In some embodiments, the allocation unit may be added to the logical address space to replace a previous allocation unit that has undergone a trim command from the host system.

[0039] As Figure 4 shown, at operation 440, the processing logic performs a write operation at the allocation unit by using a pre-read voltage based on the data pattern to write data. For example, the write operation may include a pre-read sub-operation as previously described. The pre-read voltage for the pre-read sub-operation may be based on the voltage state of the data pattern. For example, if the data pattern programmed into the memory cells of the allocation unit is a low voltage state (e.g., based on the type of media component), a higher or highest pre-read voltage may be selected for the pre-read sub-operation. Otherwise, if the data pattern programmed into the memory cells of the allocation unit is a high voltage state (e.g., based on another type of media component), a lower or lowest pre-read voltage may be selected for the pre-read sub-operation.

[0040] Figure 5A Illustrates the transformation between an unmapped allocation unit and a mapped allocation unit according to some embodiments of the present disclosure. In some embodiments, the management of the allocation unit may be performed by Figure 1 the allocation component 113.

[0041] AsFigure 5A As shown, at the time of memory subsystem initialization, the allocation unit may be unmapped. For example, at state 510 during the initial operating life of the memory subsystem, the allocation unit may be unmapped because the memory subsystem has not been used by any host system. In some embodiments, the allocation units of the memory subsystem may be programmed to a high voltage state or a low voltage state at manufacturing time using a data pattern based on the type of media component used in the memory subsystem. When the allocation unit transitions to state 511 to become a mapped allocation unit, the lowest pre-read voltage (or the highest pre-read voltage depending on the type of media component) may be used. For example, when an allocation unit is first added to the logical address space, the lowest pre-read voltage may be selected for the first write operation that will write data at the allocation unit.

[0042] Figure 5B Illustrate the transformation between unmapped allocation units and mapped allocation units based on host system commands according to some embodiments of the present disclosure. In some embodiments, the management of the allocation units may be performed by Figure 1 the allocation component 113.

[0043] As Figure 5B shown, the allocation unit may be mapped at state 520. For example, the allocation unit has previously been added to the logical address space of the host system. Subsequently, the host system may issue a trim command to remove the allocation unit from the logical address space. For example, the trim command instructs to unmapped the allocation unit. In response to removing the allocation unit from the logical address space, a write operation may be performed on the allocation unit to place the allocation unit in a high voltage state (or a low voltage state depending on the type of media component). Thus, at state 521, the allocation unit may be unmapped and in a high voltage state. Subsequently, when the allocation unit is to return to the logical address space, the data to be stored at the allocation unit may be written to the allocation unit by using the lowest pre-read voltage (or the highest pre-read voltage depending on the type of media component). Thus, at stage 522, the allocation unit may become mapped to the logical address space and may store data from the host system.

[0044] Figure 5C Illustrate the transformation between unmapped allocation units and mapped allocation units based on wear leveling operations according to some embodiments of the present disclosure. In some embodiments, the management of the allocation units may be performed by Figure 1 the allocation component 113.

[0045] As Figure 5CAs shown, at state 530, since the allocation unit is added to the host system dynamic logical address space, the allocation unit can be mapped. Subsequently, the memory subsystem can perform an wear leveling operation to remove the allocation unit from the logical address space. For example, the wear leveling operation can remove the allocation unit from the logical address space, add a new allocation unit to the logical address space, and store the data from the removed allocation unit at the new allocation unit. At state 531, when the allocation unit is unmapped, the allocation unit can be programmed to be in a high voltage state (or a low voltage state depending on the media component type). Subsequently, at state 532, when the allocation unit returns to the logical address space (e.g., due to being added in response to a subsequent wear leveling operation), and then when the allocation unit becomes mapped, data can be written to the allocation unit by using the lowest prefetch voltage (or the highest prefetch voltage depending on the media component type).

[0046] Figure 6 An example machine of computer system 600 is illustrated, within which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 600 can correspond to a host system (e.g., Figure 1 host system 120), which includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or can be used to perform the operations of a controller (e.g., execute an operating system to perform operations corresponding to Figure 1 allocation unit component 113). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine can operate as a server or client machine in a client-server network environment or as a peer machine in a peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment.

[0047] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch or bridge, digital or non-digital circuitry, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by that machine. Further, although a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0048] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0049] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 602 can also be one or more dedicated processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 may also include a network interface device 608 to communicate via a network 620.

[0050] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during their execution by the computer system 600, and the main memory 604 and the processing device 602 also constitute machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 the memory subsystem 110.

[0051] In one embodiment, the instructions 626 include instructions for implementing the functionality corresponding to an allocation unit component (e.g., Figure 1 the allocation unit component 113 corresponding to). Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid state memories, optical media, and magnetic media.

[0052] Some parts of the foregoing have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts can most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived as a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has sometimes proven convenient, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0053] However, it should be borne in mind that all such and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. This disclosure may refer to the action and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memories or registers of the computer system or other such information storage systems.

[0054] This disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0055] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. The structure of various of these systems will be presented as will be set forth in the description below. In addition, no specific programming language has been referred to in describing this disclosure. It will be understood that a variety of programming languages may be used to implement the teachings of this disclosure as described herein.

[0056] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as a read only memory (“ROM”), a random access memory (“RAM”), a magnetic disk storage medium, an optical storage medium, a flash memory component, and the like.

[0057] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method for operating a memory system, comprising: Receiving an indication that an allocation unit of the memory subsystem has become unmapped; In response to receiving the indication that the allocation unit of the memory subsystem has become unmapped, programming the allocation unit by a processing device with a data pattern based on a voltage change direction of a threshold voltage distribution of the allocation unit; Receiving data to be written to the unmapped allocation unit; And Performing a write operation by using a read voltage based on the data pattern to program the received data at the unmapped allocation unit.

2. The method according to claim 1, wherein the performing of the write operation comprises: Performing a pre-read operation of the unmapped allocation unit by applying the read voltage to the unmapped allocation unit to retrieve a stored value; Comparing the stored value with a value of the received data; And Determining whether to write the value of the received data at the allocation unit based on the comparison of the stored value with the value of the received data.

3. The method according to claim 1, wherein the allocation unit comprises a plurality of memory cells, and wherein the programming of the allocation unit with the data pattern corresponds to programming the plurality of memory cells to be in a high voltage state, and wherein the read voltage is lower than a voltage level of the high voltage state.

4. The method according to claim 1, wherein the allocation unit comprises a plurality of memory cells, and wherein the programming of the allocation unit with the data pattern corresponds to programming the plurality of memory cells to be in a low voltage state, and wherein the read voltage is higher than a voltage level of the low voltage state.

5. The method according to claim 1, wherein the allocation unit is unmapped based on removing the allocation unit from a logical address space of a host system.

6. The method according to claim 5, further comprising: Receiving an indication that the allocation unit will change from unmapped to mapped based on the allocation unit being added to the logical address space of the host system, and wherein the data is received for writing to the allocation unit in view of the allocation unit being added to the logical address space.

7. A non-transitory computer-readable medium including instructions that, when executed by a processing device, cause the processing device to perform operations including the following: Receiving an indication that an allocation unit of the memory subsystem has become unmapped; In response to receiving the indication that the allocation unit of the memory subsystem has become unmapped, programming the allocation unit with a data pattern based on a voltage change direction of a threshold voltage distribution of the allocation unit; Receiving data to be written to the unmapped allocation unit; And Performing a write operation by using a read voltage based on the data pattern to program the received data at the unmapped allocation unit.

8. The non-transitory computer-readable medium according to claim 7, wherein for performing the write operation, the operation further comprises: Performing a pre-read operation on the de-mapped allocation unit by applying the read voltage to the de-mapped allocation unit to retrieve the stored value; Comparing the stored value with the value of the received data; And Determining whether to write the value of the received data at the allocation unit based on the comparison of the stored value with the value of the received data.

9. The non-transitory computer-readable medium according to claim 7, wherein the allocation unit comprises a plurality of memory cells, and wherein programming the allocation unit with the data pattern corresponds to programming the plurality of memory cells to be in a high voltage state, and wherein the read voltage is lower than the voltage level of the high voltage state.

10. The non-transitory computer-readable medium according to claim 7, wherein the allocation unit comprises a plurality of memory cells, and wherein programming the allocation unit with the data pattern corresponds to programming the plurality of memory cells to be in a low voltage state, and wherein the read voltage is higher than the voltage level of the low voltage state.

11. The non-transitory computer-readable medium according to claim 7, wherein the allocation unit is de-mapped based on removing the allocation unit from the logical address space of the host system.

12. The non-transitory computer-readable medium according to claim 11, wherein the operation further comprises: Receiving an indication that the allocation unit will change from de-mapped to mapped based on the allocation unit being added to the logical address space of the host system, and wherein in view of the allocation unit being added to the logical address space, receiving the data to be written to the allocation unit.

13. A memory system, comprising: A memory component; And A processing device operatively coupled to the memory component to perform the following operations: Receiving an indication to remove a group of memory cells of the memory subsystem from the logical address space for accessing the memory subsystem; In response to receiving the indication, removing the group of memory cells of the memory subsystem from the logical address space; And Programming the group of memory cells removed from the logical address space with a voltage state, wherein the voltage state is based on the voltage change direction of the threshold voltage distribution of the group of memory cells.

14. The memory system according to claim 13, wherein the processing device further performs the following operations: Receiving an indication to return the group of memory cells to the logical address space; Receiving data to be written to the group of memory cells that has been returned to the logical address space; and Performing a write operation by using a read voltage based on the voltage state to program the received data at the group of memory cells.

15. The memory system according to claim 14, wherein for performing the write operation, the processing device will perform the following operations: Performing a pre-read operation on the memory cell group by applying the read voltage to the memory cell group to retrieve the stored value; Comparing the stored value with the value of the received data; And Determining whether to write the value of the received data at the memory cell group based on the comparison of the stored value with the value of the received data.

16. The memory system according to claim 14, wherein the voltage state corresponds to a high voltage state, and wherein the read voltage is lower than the voltage level of the high voltage state.

17. The memory system according to claim 14, wherein the voltage state corresponds to a low voltage state, and wherein the read voltage is higher than the voltage level of the low voltage state.

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