Plasma processing apparatus and plasma processing method

Abstract

The present invention provides a plasma processing apparatus and a plasma processing method for improving processing performance using three electric power pulse signals, comprising: a generation source RF generation section that generates a generation source RF pulse signal of at least three power levels; first and second bias RF generation sections that generate first and second bias RF pulse signals of at least two power levels at a frequency lower than that of the generation source RF pulse signal; a synchronization signal generation section that generates a synchronization signal for synchronizing the generation source RF generation section and the first and second bias RF generation sections; a first matching circuit that is connected to the generation source RF generation section and an antenna, and causes the generation source RF pulse signal to be supplied from the generation source RF generation section to the antenna via the first matching circuit; and a second matching circuit that is connected to the first and second bias RF generation sections and a substrate support section, and causes the first and second bias RF pulse signals to be supplied from the first and second bias RF generation sections to the substrate support section via the second matching circuit.

Description

Technical Field

[0001] This invention relates to plasma processing apparatus and plasma processing method. Background Technology

[0002] For example, Patent Document 1 proposes an ICP (Inductively Coupled Plasma) device having two high-frequency power supplies, supplying high-frequency electrical power at two frequencies to an antenna at the top of the chamber and a lower electrode (base). One of the two high-frequency power supplies supplies high-frequency electrical power for biasing at a frequency of, for example, 13 MHz, to the lower electrode. An antenna is positioned above the chamber, and the other high-frequency power supply supplies high-frequency electrical power for plasma excitation at, for example, 27 MHz, to the midpoint or vicinity of the line forming the outer coil of the antenna.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-67503 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] This invention provides a technique for improving processing performance by using three high-frequency (RF) electrical power pulses.

[0008] Technical means for solving problems

[0009] According to one aspect of the present invention, a plasma processing apparatus is provided, comprising: a processing chamber; a substrate support disposed within the processing chamber; an antenna disposed on the upper part of the processing chamber; a generation source RF generation unit configured to generate generation source RF pulse signals having at least three power levels, wherein each power level of the generation source RF pulse signals is 0 or higher; a first bias RF generation unit configured to generate a first bias RF pulse signal, wherein the frequency of the first bias RF pulse signal is lower than the frequency of the generation source RF pulse signal, and the first bias RF pulse signal has at least two power levels, each power level being 0 or higher; and a second bias RF generation unit configured to generate a second bias RF pulse signal, wherein the second bias RF pulse signal has at least two power levels, each power level being 0 or higher. The system comprises: a level of 0 or higher; a synchronization signal generation unit configured to generate a synchronization signal for synchronizing the generation source RF generation unit, the first bias RF generation unit, and the second bias RF generation unit; a first matching circuit connected to the generation source RF generation unit and the antenna, which enables the generation source RF pulse signal to be supplied from the generation source RF generation unit to the antenna via the first matching circuit; and a second matching circuit connected to the first bias RF generation unit, the second bias RF generation unit, and the substrate support unit, which enables the first bias RF pulse signal to be supplied from the first bias RF generation unit to the substrate support unit via the second matching circuit, and enables the second bias RF pulse signal to be supplied from the second bias RF generation unit to the substrate support unit via the second matching circuit.

[0010] Invention Effects

[0011] In one aspect, three high-frequency electrical power pulse signals can be used to improve processing performance. Attached Figure Description

[0012] Figure 1 This is a cross-sectional schematic diagram illustrating an example of a plasma processing system according to an embodiment.

[0013] Figure 2 This is a diagram illustrating an example of a plasma processing apparatus according to an embodiment.

[0014] Figure 3 This is a diagram illustrating an example of a matching circuit for two biased RF pulse signals in an embodiment.

[0015] Figure 4 This is a diagram representing an example of free radicals, ions, electron temperature, ion energy, and byproducts.

[0016] Figure 5This is a diagram showing the pulse pattern of two high-frequency electrical power pulses of the implementation method.

[0017] Figure 6 This is a diagram showing the pulse patterns of the three frequencies of high-frequency electrical power pulses in the implementation method.

[0018] Figure 7 This is a diagram showing the pulse patterns of the three frequencies of high-frequency electrical power pulses in the implementation method.

[0019] Figure 8 This is a diagram showing the pulse patterns of the three frequencies of high-frequency electrical power pulses in the implementation method.

[0020] Figure 9 This is a diagram illustrating an example of a plasma processing apparatus as a variation of the embodiment.

[0021] Figure 10 This is a diagram showing the pulse patterns of the DC pulse and the high-frequency power pulse in Variation Example 1.

[0022] Figure 11 This is a diagram showing the pulse patterns of the DC pulse and the high-frequency power pulse in Variation Example 2.

[0023] Figure 12 This is a diagram showing the pulse patterns of the DC pulse and the high-frequency power pulse in Modified Example 3.

[0024] Explanation of reference numerals in the attached figures

[0025] 1. Plasma processing device

[0026] 2 Control Department

[0027] 10 chambers

[0028] 10s plasma processing space

[0029] 11. Substrate support

[0030] 12 Ring-shaped components

[0031] 13 Gas Inlet Section

[0032] 14 antennas

[0033] 20 Gas Supply Department

[0034] 21 Computer

[0035] 21a Processing Department

[0036] 21b Storage Section

[0037] 21c communication interface

[0038] 31 RF Power Supply Department

[0039] 31a Source RF Generation Unit

[0040] 31b First bias RF generation unit

[0041] 31c Second Bias RF Generation Unit

[0042] 31d Synchronization Signal Generation Unit

[0043] 32a DC pulse generation unit

[0044] 34b1 First Regulation Circuit

[0045] 34b2 First Separation Circuit

[0046] 34C1 Second Adjustment Circuit

[0047] 34C2 Second Separator Circuit

[0048] 33 First Matching Circuit

[0049] 34 Second Matching Circuit

[0050] 37 Power supply line Detailed Implementation

[0051] Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings. In the drawings, the same reference numerals are used to label the same components, and sometimes repeated descriptions are omitted.

[0052] [Plasma Processing System]

[0053] First, refer to Figure 1 and Figure 2 The plasma processing system of the embodiment will be described. Figure 1 This is a cross-sectional schematic diagram illustrating an example of a plasma processing system according to an embodiment. Figure 2 This is a diagram illustrating an example of a plasma processing apparatus 1 according to an embodiment.

[0054] In this embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing apparatus 1 is configured to generate plasma from the processing gas within the chamber 10 by supplying three high-frequency electrical power pulses (three RF pulse signals) into the chamber 10. Furthermore, the plasma processing apparatus 1 processes the substrate by exposing the generated plasma to the substrate.

[0055] The plasma processing apparatus 1 includes a chamber (plasma processing chamber) 10, a substrate support 11, and a plasma generation unit. The chamber 10 defines a plasma processing space 10s. Furthermore, the chamber 10 has a gas inlet 10a for supplying at least one processing gas to the plasma processing space 10s, and a gas outlet 10b for discharging gas from the plasma processing space. The gas inlet 10a is connected to at least one gas supply unit 20.

[0056] Gas outlet 10b is, for example, an exhaust port located at the bottom of chamber 10, connected to exhaust system 40. Exhaust system 40 can be connected to gas outlet. Exhaust system 40 may also include pressure valve and vacuum pump. Vacuum pump may include turbomolecular pump, roughing pump, or a combination thereof.

[0057] The substrate support 11 is disposed within the plasma processing space 10s and supports the substrate W. The plasma generation unit is configured to generate plasma from at least one processing gas supplied to the plasma processing space 10s.

[0058] The control unit 2 processes computer-executable commands that cause the plasma processing apparatus 1 to perform the various steps described herein. The control unit 2 can be configured to control the various elements of the plasma processing apparatus 1 to perform the various steps described herein. In embodiments, such as... Figure 1 As shown, part or all of the control unit 2 is included in the plasma processing apparatus 1. The control unit 2 may include, for example, a computer 21. The computer 21 may include, for example, a processing unit (CPU: Central Processing Unit) 21a, a storage unit 21b, and a communication interface 21c. The processing unit 21a may be configured to perform various control actions based on the program stored in the storage unit 21b. The storage unit 21b may also include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 21c may also communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network).

[0059] The following will Figure 2Taking an inductively coupled plasma processing apparatus as an example, the structure of plasma processing apparatus 1 will be further described. Plasma processing apparatus 1 includes a chamber 10. Chamber 10 includes a dielectric window 10c and a sidewall 10d. The dielectric window 10c and sidewall 10d define a plasma processing space 10s within chamber 10. Furthermore, plasma processing apparatus 1 includes a substrate support 11, a gas inlet 13, a gas supply 20, an electrical power supply, and an antenna 14.

[0060] The substrate support 11 is disposed in the plasma processing space 10s within the chamber 10. The antenna 14 is disposed on the upper part or above the chamber 10 (dielectric window 10c).

[0061] The substrate support portion 11 includes a main body and an annular member (edge ​​ring) 12. The main body has a central region (substrate support surface) 11a for supporting a substrate (wafer) W and an annular region (edge ​​ring support surface) 11b for supporting the annular member 12. The annular region 11b of the main body surrounds the central region 11a of the main body. The substrate W is disposed on the central region 11a of the main body, and the annular member 12 is disposed on the annular region 11b of the main body in such a way that it surrounds the substrate W on the central region 11a of the main body. In an embodiment, the main body includes an electrostatic chuck 111 and a conductive member 112. The electrostatic chuck 111 is disposed on the conductive member 112. The conductive member 112 functions as an RF electrode, and the upper surface of the electrostatic chuck 111 functions as the substrate support surface (central region 11a). Furthermore, although not shown in the figure, in an embodiment, the substrate support portion 11 may also be configured as a temperature control module capable of adjusting at least one of the electrostatic chuck 111 and the substrate W to a target temperature. The temperature control module may include a heater, a flow path, or a combination thereof. A temperature-regulating fluid, such as a refrigerant or heat transfer gas, can flow through the flow path. Furthermore, the chamber 10, the substrate support 11, and the annular component 12 are arranged such that axis Z is the central axis and aligned with axis Z.

[0062] The gas inlet 13 is configured to supply at least one processing gas from the gas supply unit 20 to the plasma processing space 10s. In this embodiment, the gas inlet 13 is disposed above the substrate support 11 and installed in the central opening formed in the dielectric window 10c.

[0063] The gas supply unit 20 may also include at least one gas source 23 and at least one flow controller 22. In an embodiment, the gas supply unit 20 is configured to supply one or more processing gases from their respective gas sources 23 to the gas inlet unit 13 via their respective flow controllers 22. Each flow controller 22 may also include, for example, a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may also include one or more flow modulation devices for modulating or pulsedizing the flow rate of one or more processing gases.

[0064] The power supply unit includes an RF power supply unit 31 coupled to the chamber 10. The RF power supply unit 31 is configured to supply three RF signals (RF power) to the conductive member 112 or the antenna 14 of the substrate support 11. Thus, plasma is formed from at least one processing gas supplied to the plasma processing space 10s. Alternatively, the plasma generation unit may be configured to include a gas supply unit 20 supplying at least one processing gas to the plasma processing space 10s and an RF power supply unit 31, capable of generating plasma from the processing gas.

[0065] Antenna 14 includes one or more coils. In one embodiment, antenna 14 may also include an outer coil and an inner coil arranged coaxially. In this case, the RF power supply unit 3 may be connected to both the outer coil and the inner coil, or to either the outer coil or the inner coil. In the former case, the same RF generating unit may be connected to both the outer coil and the inner coil, or different RF generating units may be connected to the outer coil and the inner coil respectively.

[0066] In one embodiment, the RF power supply unit 31 includes a source RF generation unit 31a, a first bias RF generation unit 31b, and a second bias RF generation unit 31c. The source RF generation unit 31a is coupled to the antenna 14, and the first bias RF generation unit 31b and the second bias RF generation unit 31c are coupled to the conductive member 112. The source RF generation unit 31a is configured to be connected to the antenna 14 via a first matching circuit 33 and is capable of generating a source RF pulse signal (hereinafter also referred to as HF power) for plasma generation. In one embodiment, the source RF pulse signal has a frequency in the range of 10MHz to 100MHz. In another embodiment, the source RF pulse signal has a frequency in the range of 20MHz to 60MHz. In yet another embodiment, the source RF pulse signal has a frequency of 100MHz or higher. The generated source RF pulse signal is supplied to the antenna 14. The source RF pulse signal has at least three power levels, each of which is 0 or higher. Therefore, the generated RF pulse signal can have high / medium / low (high / medium / low) power levels, which are greater than 0. Furthermore, the generated RF pulse signal can also have high / low power levels and zero power level (off).

[0067] Furthermore, the first bias RF generation unit 31b is configured to be connected to the conductive member 112 of the substrate support unit 11 via the second matching circuit 34 and the power supply line 37, and is capable of generating a first bias RF pulse signal (hereinafter also referred to as LF1 power). The generated first bias RF pulse signal is supplied to the conductive member 112 of the substrate support unit 11. In one embodiment, the first bias RF pulse signal has a frequency different from the frequency of the generating source RF pulse signal. In another embodiment, the first bias RF pulse signal has a frequency lower than the frequency of the generating source RF pulse signal. In yet another embodiment, the first bias RF pulse signal has the same frequency as the generating source RF pulse signal. In yet another embodiment, the first bias RF pulse signal has a frequency in the range of 1MHz to 40MHz. In yet another embodiment, the first bias RF pulse signal has a frequency in the range of 1.2MHz to 15MHz. The first bias RF pulse signal has at least two power levels, each of which is greater than or equal to 0. Therefore, the first bias RF pulse signal can have high / low power levels, which are greater than 0. In addition, the first bias RF pulse signal can also have a power level greater than 0 and a zero power level, i.e., an on / off signal.

[0068] Furthermore, the second bias RF generation unit 31c is configured to be connected to the conductive member 112 of the substrate support 11 via the second matching circuit 34 and the power supply line 37, and is capable of generating a second bias RF pulse signal (hereinafter also referred to as LF2 power). The generated second bias RF pulse signal is supplied to the conductive member 112 of the substrate support 11. In one embodiment, the second bias RF pulse signal has a frequency lower than that of the first bias RF pulse signal. In one embodiment, the second bias RF pulse signal has a frequency in the range of 100 kHz to 5 MHz. In one embodiment, the second bias RF pulse signal has a frequency in the range of 200 kHz to 4 MHz. In one embodiment, the second bias RF pulse signal has a frequency in the range of 400 kHz to 2 MHz. The first bias RF pulse signal has at least two power levels, each of which is greater than or equal to 0. Therefore, the second bias RF pulse signal can have high / low power levels, which are greater than 0. In addition, the second bias RF pulse signal can also have a power level greater than 0 and a zero power level, i.e., an on / off signal.

[0069] In this way, the source RF pulse signal, the first bias RF pulse signal, and the second bias RF pulse signal are pulsed. The first bias RF pulse signal and the second bias RF pulse signal are pulsed between an on and off state, or between two or more different on states (high / low). The source RF pulse signal is pulsed between two or more different on states (high / low) and an off state, or between three or more different on states (high / medium / low).

[0070] The first matching circuit 33 is connected to the RF generation unit 31a and the antenna 14. The first matching circuit 33 enables the RF pulse signal from the RF generation unit 31a to be supplied to the antenna 14 via the first matching circuit 33.

[0071] The second matching circuit 34 is connected to the first bias RF generation unit 31b, the second bias RF generation unit 31c, and the substrate support unit 11 (conductive member 112). The second matching circuit 34 enables the first bias RF pulse signal to be supplied from the first bias RF generation unit 31b to the substrate support unit 11 via the second matching circuit 34. Furthermore, the second matching circuit 34 enables the second bias RF pulse signal to be supplied from the second bias RF generation unit 31c to the substrate support unit 11 via the second matching circuit 34.

[0072] The RF power supply unit 31 further includes a synchronization signal generation unit 31d. The synchronization signal generation unit 31d is configured to generate a synchronization signal 31s for synchronizing the generation source RF generation unit 31a, the first bias RF generation unit 31b, the second bias RF generation unit 31c, the first matching circuit 33, and the second matching circuit 34. The synchronization signal generation unit 31d is disposed in any one of the generation source RF generation unit 31a, the first bias RF generation unit 31b, and the second bias RF generation unit 31c. Furthermore, the synchronization signal generation unit 31d is configured to supply the synchronization signal 31s to the other two RF generation units, the first matching circuit 33, and the second matching circuit 34. In one embodiment, the synchronization signal generation unit 31d is configured to be disposed in the generation source RF generation unit 31a and is capable of generating the synchronization signal 31s to the first bias RF generation unit 31b, the second bias RF generation unit 31c, the first matching circuit 33, and the second matching circuit 34. In addition, the synchronization signal generation unit 31d can also be configured independently. In this case, the synchronization signal 31s is supplied to the generation source RF generation unit 31a, the first bias RF generation unit 31b, the second bias RF generation unit 31c, the first matching circuit 33, and the second matching circuit 34.

[0073] Control unit 2 outputs control signals instructing the supply of pulse signals to the source RF generation unit 31a, the first bias RF generation unit 31b, and the second bias RF generation unit 31c, respectively. Thus, the source RF pulse signal, the first bias RF pulse signal, and the second bias RF pulse signal are supplied at predetermined times, generating plasma from the processing gas within chamber 10. Then, the generated plasma is exposed to the substrate for substrate processing. This improves processing efficiency and enables high-precision substrate processing. The on / off states or power levels of the source RF pulse signal, the first bias RF pulse signal, and the second bias RF pulse signal of control unit 2 will be explained later.

[0074] [An example of the internal structure of the second matching circuit]

[0075] Below, refer to Figure 3 An example of the structure of the second matching circuit 34 will be described. Figure 3 This is a diagram illustrating an example of the internal structure of the second matching circuit 34 in the implementation method.

[0076] The first bias RF generator 31b and the second bias RF generator 31c are connected to the substrate support 11 (conductive member 112) via the second matching circuit 34 and the power supply line 37. In the following description, the first bias RF pulse signal supplied from the first bias RF generator 31b will be denoted as LF1 power. Furthermore, in the following description, the second bias RF pulse signal supplied from the second bias RF generator 31c will be denoted as LF2 power.

[0077] When the first bias RF pulse signal (LF1 power) supplied from the first bias RF generation unit 31b is coupled to the opposite side (the side of the second bias RF generation unit 31c) via the power supply line 36 in the second matching circuit 34, the supply efficiency of the LF1 power supplied to the chamber 10 decreases. Similarly, when the second bias RF pulse signal (LF2 power) supplied from the second bias RF generation unit 31c is supplied to the opposite side (the side of the first bias RF generation unit 31b) via the power supply line 36, the supply efficiency of the LF2 power supplied to the chamber 10 decreases. As a result, due to the reduced supply of bias power to the chamber 10, the control of ion energy becomes difficult, and the processing performance deteriorates.

[0078] Therefore, the second matching circuit 34 of this embodiment includes a first adjustment circuit 34b1, a first separation circuit 34b2, a second adjustment circuit 34c1, and a second separation circuit 34c2. The first adjustment circuit 34b1 and the first separation circuit 34b2 are connected between the first bias RF generation unit 31b and the power supply line 37. The second adjustment circuit 34c1 and the second separation circuit 34c2 are connected between the second bias RF generation unit 31c and the power supply line 37. With this configuration, the first bias RF pulse signal (LF1 power) generated in the first bias RF generation unit 31b is suppressed from coupling to the second bias RF generation unit 31c while being supplied to the substrate support unit 11 (conductive member 112). Furthermore, the second bias RF pulse signal (LF2 power) generated in the second bias RF generation unit 31c is suppressed from coupling to the first bias RF generation unit 31b while being supplied to the substrate support unit 11 (conductive member 112).

[0079] The first adjustment circuit 34b1 has a variable element configured to match the impedance of the load side (substrate support 11 side) of the first bias RF generation unit 31b with the output impedance of the first bias RF generation unit 31b. In one embodiment, the variable element of the first adjustment circuit 34b1 is a variable capacitor.

[0080] The second separation circuit 34c2 is connected between the second bias RF generation unit 31c and the substrate support unit 11 to prevent the coupling of the LF1 electrical power, i.e. the first bias RF pulse signal, from the first bias RF generation unit 31b.

[0081] The second adjustment circuit 34c1 has a variable element configured to match the impedance of the load side (substrate support 11 side) of the second bias RF generation unit 31c with the output impedance of the second bias RF generation unit 31c. In one embodiment, the variable element of the second adjustment circuit 34c1 is a variable inductor.

[0082] The first separation circuit 34b2 is connected between the first bias RF generation unit 31b and the substrate support unit 11 to prevent the coupling of the LF2 electrical power, i.e. the second bias RF pulse signal, from the second bias RF generation unit 31c.

[0083] The second separation circuit 34c2 is an RF choke circuit containing inductor L2. The first separation circuit 34b2 is a resonant circuit containing capacitor C1 and inductor L1. The first separation circuit 34b2 is composed of capacitor C1 and inductor L1. The second separation circuit 34c2 is composed of inductor L2.

[0084] The impedance of the first separation circuit 34b2 is 0 or close to 0 from the perspective of the first bias RF pulse signal, and high from the perspective of the second bias RF pulse signal. The circuit constants of C1 and L1 are set such that the side of the first bias RF generation unit 31b is considered a wall. Therefore, the impedance of the first separation circuit 34b2 from the perspective of the second bias RF pulse signal is denoted as Z. LF2 Let the load impedance of the plasma be denoted as Z. chamber At that time, Z LF2 >>Z chamber .

[0085] Furthermore, the impedance of the second separation circuit 34c2 is 0 or close to 0 from the perspective of the second bias RF pulse signal, and high from the perspective of the first bias RF pulse signal. The circuit constant of L2 is set such that the side of the second bias RF generation unit 31c is considered a wall. Therefore, the impedance in the second separation circuit 34c2 from the perspective of the first bias RF pulse signal is denoted as Z. LF1 At that time, Z LF1 >>Z chamber Established.

[0086] In this way, by setting the circuit constants of the first separation circuit 34b2 as described above, the impedance Z in the first separation circuit 34b2 is... LF2 Much greater than the load impedance Z of the plasma chamber Therefore, the first separation circuit 34b2 prevents the coupling of the second bias RF pulse signal from the second bias RF generation unit 31c. Figure 3 (LF2 power → ×). As a result, LF2 power is supplied to chamber 10 via power supply line 37, thereby suppressing the reduction in the supply efficiency of LF2 power.

[0087] Similarly, by setting the circuit constants of the second separation circuit 34c2 as described above, the impedance Z in the second separation circuit 34c2 is... LF1 Much greater than the load impedance Z of the plasma chamber Therefore, the second separation circuit 34c2 prevents the coupling of the first bias RF pulse signal from the first bias RF generation unit 31b. Figure 3 (LF1 power → ×). As a result, LF1 power is supplied to chamber 10 via power supply line 37, thereby suppressing the reduction in the supply efficiency of LF1 power.

[0088] With this configuration, two bias electrical power pulse signals (LF1 electrical power and LF2 electrical power) with different frequencies can be efficiently supplied to the substrate support portion 11.

[0089] [Pulse signal]

[0090] For example, when etching deep holes with high aspect ratios, using pulse signals of HF, LF1, and LF2 power can make the ion incident angle perpendicular or improve the mask selectivity.

[0091] Figure 4 This is a diagram representing an example of free radicals, ions, electron temperature, ion energy, and byproducts. Figure 4 The horizontal axis represents the elapsed time (one cycle) after the RF power supply is stopped (turned off). Figure 4 The vertical axis represents the radical (Radical), ion (Ions), electron temperature (Te), and ion energy (ε) during the turn-off time. l The state of by-products at various times.

[0092] Accordingly, the change in radicals (radicals) from the point where the RF power is turned off is gradual, while the changes in ions (ion power) and plasma temperature (Te) occur earlier than those of radicals. Considering the decay of radicals and ions, energy changes, etc., in such a plasma, the pulse signals for controlling the HF power and LF power (e.g., LF1 power and LF2 power) are analyzed. As an example of the pulse signal for supplying LF power after turning off the HF power, considering the initial time when the plasma temperature (Te) is high, the LF power is turned off, and then turned on after the plasma temperature (Te) decreases. Therefore, although ions may remain, using LF power at the time when the plasma temperature (Te) is low allows for efficient ion attraction to the substrate.

[0093] As another example of the pulse signal for the LF power supplied after the HF power is turned off, ε, representing ion energy, is used as a plasma parameter. l The LF2 electrical power is controlled while the plasma electron temperature Te remains essentially unchanged. Therefore, the ion energy ε can be controlled. l This allows for more vertical control of the ion incident angle.

[0094] In this way, by precisely controlling the timing of turning the HF and LF electric power on and off based on variations in plasma parameters such as free radicals, ions, plasma electron temperature, ion energy, and byproducts, the processing performance can be improved. (See below for reference.) Figures 5-8 The timing of supplying the high-frequency electrical power pulse signal is explained. Furthermore, the timing of supplying the high-frequency electrical power pulse signal is controlled by the control unit 2.

[0095] (Pulse signals at two frequencies)

[0096] Figure 5 This is a diagram showing the pulse patterns of two high-frequency electrical power pulses at different frequencies in the implementation method. First, regarding... Figure 5 The timing of the supply of pulse signals for the two high-frequency electrical powers shown, namely HF power (Source Power) and LF1 power (Bias Power), is explained. Figure 5 The horizontal axis represents the time of one cycle, and the vertical axis represents the on and off states of HF power and LF1 power. The period (1) to (4) is taken as one cycle, and the control of each pulse signal of HF power and LF1 power is repeated.

[0097] In the control of high-frequency electrical power pulses at two frequencies, the on-state of HF electrical power and the on-state of LF1 electrical power are not allowed to overlap in time. During the period when HF electrical power is on, LF1 electrical power is off, and during the period when HF electrical power is off, LF1 electrical power is on. The generator RF generation unit 31a is configured to generate a generator RF pulse signal (HF electrical power). In this embodiment, the generator RF pulse signal has two power levels (on / off). For example, the generator RF pulse signal may also have a frequency of 27MHz.

[0098] The first bias RF generation unit 31b is configured to generate a first bias RF pulse signal (LF1 power). In this embodiment, the first bias RF pulse signal has two power levels (on / off). The frequency of the first bias RF pulse signal is lower than the frequency of the source RF pulse signal. For example, the first bias RF pulse signal has a frequency of 13MHz.

[0099] exist Figure 5 During the period (1), the HF power is turned on and the LF1 power is turned off. That is, the time T from time t0 to time t1 is... s By supplying HF electrical power, plasma containing free radicals and ions is generated.

[0100] After time T s When the HF power is controlled to be off at time t1, such as Figure 4 In one example shown, the free radicals, ions, and plasma temperature decay with their respective time constants. Based on the decay state of these plasma parameters, the timing of turning on the LF1 power is controlled during periods (2) and (3) when the HF power is controlled to be off. During period (2), the behavior of the ions is primarily controlled by controlling the timing of the LF1 power supply. During period (3), the exhaust of byproducts is controlled.

[0101] For example, when the plasma temperature is high and the LF1 power is turned on, more byproducts are generated, which can hinder etching. Therefore, it is sometimes preferable to avoid turning on the LF1 power when the plasma temperature is high. That is, from the moment t1 when the HF power is turned off until a predetermined delay time T is elapsed. delay At time t2, the LF1 power is controlled to be on, thereby suppressing the amount of by-products during etching and promoting etching.

[0102] During the delay time T delayIn this process, both the HF and LF1 electrical powers are temporarily switched off. Therefore, the generation of free radicals and ions is temporarily halted earlier than the time t2 when the LF1 electrical power is supplied. As a result, it is possible to control the supply of LF1 electrical power at the time T... b The ion beam (ion quantity) that reaches the bottom of the etched recess can promote etching.

[0103] Additionally, by setting a delay time T delay After the plasma temperature decreases, the LF1 electrical power can be controlled to be switched on. This increases the ion energy ε. l Furthermore, the increased Vpp (peak-to-peak voltage) of the LF1 power allows for more precise control of the ion incident angle towards the etched recess. However, when the delay time T is increased... delay When it is too long, due to Figure 4 The decay and disappearance of ions are shown, therefore the time delay T is... delay Set to an appropriate value beforehand.

[0104] At time t3, the LF1 power is controlled to be off. During period (3), the exhaust period T from time t3 to time t4 is... off The HF and LF1 electrical power are controlled to be off to discharge byproducts. During exhaust, T off The time that byproducts are not pre-set to adhere to the substrate W.

[0105] During the exhaust period T off At time t4, the HF power is switched on again, returning from period (4) to period (1). Thus, the switching on and off states of the HF power and the LF1 power are controlled separately for time T in a way that their on states do not overlap in time. s Time T b Delay time T delay Time T off In particular, the first bias RF generation unit 31b is configured to stagger the timing of the change in the power level of the first bias RF pulse signal relative to the timing of the change in the power level of the generation source RF pulse signal. Therefore, at a delay time T, the power is supplied to LF1 earlier than the timing of the power supply to LF1. delay The supply of power to HF and LF1 is stopped. As a result, it is possible to control the time T during which LF1 power is switched on. b The ion beam is directed to the bottom of the etched recess. However, the timing of the supply of HF and LF1 power is not limited to this. For example, a delay time T may not be set. delay .

[0106] (Pulse signals at 3 frequencies)

[0107] Figures 6-8 This is a diagram showing the pulse patterns of the three frequencies of high-frequency electrical power pulses in the implementation method. First, regarding... Figures 6-8 The timing of supplying the pulse signals of the three high-frequency electrical power pulses shown, namely HF electrical power (Source Power), LF1 electrical power (Bias1 Power), and LF2 electrical power (Bias2 Power), is explained. Figures 6-8 The horizontal axis represents the time of one cycle, and the vertical axis represents the on and off states of HF power, LF1 power and LF2 power. The period (1) to (4) is taken as one cycle, and the control of each pulse signal of HF power, LF1 power and LF2 power is repeated.

[0108] In the control of high-frequency power pulses at three frequencies, the on-states of LF1 and LF2 power are designed to not overlap in time. During the period when LF1 is on, LF2 is off, and vice versa. The on-states of HF power and LF1, as well as the on-states of HF power and LF2, may or may not overlap in time.

[0109] The RF generation unit 31a is configured to generate a source RF pulse signal (HF electrical power). In this embodiment, the source RF pulse signal has four power levels (high / medium / low / off). These power levels can be arbitrarily set and changed depending on the object being processed. For example, the source RF pulse signal has a frequency of 27MHz.

[0110] The first bias RF generation unit 31b is configured to generate a first bias RF pulse signal (LF1 electrical power). In this embodiment, the first bias RF pulse signal has two power levels (on / off). That is, the first bias RF pulse signal has two or more power levels, including a zero power level. The frequency of the first bias RF pulse signal is lower than the frequency of the source RF pulse signal. For example, the first bias RF pulse signal has a frequency of 13MHz.

[0111] The second bias RF generation unit 31c is configured to generate a second bias RF pulse signal (LF2 electrical power). In this embodiment, the second bias RF pulse signal has two power levels (on / off). That is, the second bias RF pulse signal has two or more power levels, including a zero power level. The frequency of the second bias RF pulse signal is lower than the frequency of the first bias RF pulse signal. For example, the second bias RF pulse signal has a frequency of 1.2 MHz.

[0112] exist Figures 6-8 In this context, the source power (HF power) represents the source RF pulse signal, the first bias power (LF1 power) represents the first bias RF pulse signal, and the second bias power (LF2 power) represents the state of the second bias RF pulse signal.

[0113] exist Figure 6 During period (1), the HF power has a high power level, while the LF1 and LF2 power are off. That is, from time t0 to time t... 11 Time T s By supplying HF electrical power, a plasma containing free radicals and ions is generated. Thus, Figure 6 As shown in (a), the etch target film 100 is etched via mask 101, and free radicals R are mainly attached to the inner wall of the hole HL formed in the etch target film 100.

[0114] After time T s The time after t 11 When the HF power switches to the off state, such as Figure 4 As shown in one example, the free radicals, ions, and plasma temperature decay with their respective time constants. Depending on the decay state of these plasma parameters, the timing of turning on the LF1 and LF2 electric powers is controlled during the periods when the power level of the HF electric power is reduced or turned off (2), (3) and during the period when by-products are discharged (4).

[0115] In this embodiment, the time t from when the HF power is reduced from a high power level to a medium power level (or turned off) is... 11 until the delay time T was staggered delay1 The moment t 12 LF1 power is switched to the ON state. Therefore, as... Figure 6 As shown in (b), the ion beam that reaches the bottom of the etched recess can be controlled. In addition, the amount of by-products during etching can be suppressed.

[0116] Additionally, by setting a delay time T delay1Turning on the LF1 power supply when the plasma temperature decreases can increase the ion energy ε. l This allows for more perpendicular control of the ion incident angle. However, as... Figure 4 As shown, when the delay time T delay1 The ions disappear if the delay is too long, therefore the time T is increased. delay1 Set to an appropriate value beforehand.

[0117] During period (2), the HF power is at a medium power level, the LF1 power is on, and the LF2 power is maintained in the off state. At time t 13 During this process, the HF power level transitions to a low power level (or is off), and the LF1 power level transitions to an off state. Then, from time t... 13 The delay time T was staggered (delayed). delay2 The moment t 14 At time t, the LF2 power supply switches to the ON state. 13 During this period (3), the HF power is maintained at a low power level (or off state), and the LF1 power is maintained at the off state. During this period (3), the HF power is at a low power level (or off state), the LF2 power is on state, and the LF1 power is off state.

[0118] In this embodiment, during period (3), LF2 power at a lower frequency than the LF1 power supplied during period (2) is supplied. The Vpp of LF2 power is greater than the Vpp of LF1 power. Therefore, during period (3), the bias voltage Vpp is greater than that during period (2), and the ion energy ε is increased. l Larger diameter allows for more precise control of the ion incident angle. This, in turn, enables control over the time T during which electrical power is supplied to LF2. b2 The ion beam is directed to the bottom of the etched recess. Thus, as... Figure 6 As shown in (c), byproducts such as B remaining at the bottom corner of the hole HL are etched, which can promote etching. However, as Figure 4 As shown, when the delay time T delay2 The ions disappear if the delay is too long, therefore the time T is increased. delay2 Set to an appropriate value beforehand.

[0119] In this way, in the etching of deep holes with high aspect ratios, using pulsed signals of HF, LF1, and LF2 power can improve the mask selectivity and make the ion incident angle perpendicular. This allows for a perpendicular etched shape or promotes etching. However, etching deep holes with high aspect ratios is just one example of substrate processing, and the types of processing are not limited to this.

[0120] During period (4), the exhaust of byproducts is controlled. That is, during period (4), the HF power, LF1 power, and LF2 power are controlled to be off. Thus, as Figure 6 As shown in (d), the byproduct B attached to the hole HL is vented. This facilitates etching in the next cycle. Period (4) is preset to the time during which the byproduct B does not reattach to the substrate W.

[0121] exist Figure 6 In the example, the power level of HF is controlled at four levels, and the power levels of LF1 and LF2 are controlled at two levels: on and off. However, this is not a limitation. For example, the power level of HF can also be controlled at three or more levels.

[0122] Figure 7 Another example of a pulse pattern representing high-frequency electrical power pulses at three frequencies. In this example, the period (1) to (4) is taken as one cycle, and the control of each pulse signal of HF electrical power, LF1 electrical power and LF2 electrical power is repeated.

[0123] During period (1), in time T from time t0 to time t1 s1 HF electric power has a high power level. As a result, a plasma containing free radicals and ions is generated.

[0124] During the time T when the HF electric power has a high power level s1 Time T within b1 The LF1 electrical power is switched to the ON state. This attracts the generated ions to the substrate W, promoting etching.

[0125] At time t1, the LF1 power supply switches to the off state, and then the HF power supply switches to the medium power level. That is, at time T... s2 By supplying a lower HF electrical power, the generation of free radicals and ions decreases. In the next period (3), the HF electrical power switches to an off state. Alternatively, in period (3), the HF electrical power has a lower power level than in period (2). In this case, the HF electrical power has a medium power level in period (2) and a low power level in period (3). Figure 4 In one example shown, the free radicals, ions, and plasma temperature decay with their respective time constants. Depending on the decay state of these plasma parameters, the timing of turning the LF1 and LF2 electric powers on and off is controlled accordingly, based on the power level of the HF electric power.

[0126] For example, when the plasma temperature is high, turning on either LF1 or LF2 power leads to the generation of more byproducts, which can hinder etching. Therefore, it is advisable to avoid turning on LF2 power when the plasma temperature is high. That is, after a predetermined delay time T has elapsed from time t1... delay At time t2, after the initial time, the plasma temperature decreases. At this point, the LF2 power switch is switched on. That is, the time t1 when the LF1 power switch is switched off is offset (delayed) by a delay time T. delay Then, the LF2 power is switched to the on state. This suppresses the amount of byproducts during etching and promotes etching. Furthermore, in this embodiment, the power level of the HF power during period (2) is lower than the power level of the HF power during period (1). However, the HF power can also be switched off during period (2).

[0127] In this embodiment, during the delay time T delay When LF1 power is switched off, the power level of HF power decreases. Therefore, a delay time T earlier than the time t2 when LF2 power is supplied is possible. delay This reduces the generation of free radicals and ions. As a result, it is possible to control the time T during which electrical power is supplied to LF2. b2 The ion beam is directed to the bottom of the recess formed on the etched film.

[0128] Furthermore, during period (1), the LF2 power is off, and after the plasma temperature decreases, the LF2 power switches to on, thereby enabling more vertical control of the ion incident angle. However, as Figure 4 As shown, when the delay time T delay The ions disappear if the delay is too long, therefore the time T is increased. delay Set to an appropriate value beforehand.

[0129] Based on the above control, the on / off states of LF1 and LF2 power are switched on at different time intervals, thereby primarily controlling ion behavior. The LF1 power at time T... b1 The LF2 electric power has a power level greater than 0 at time T. b1 It has a zero power level. The electric power of LF2 at time T b2 The LF1 electric power has a power level greater than 0 in time T. b2 The power level is zero. That is, the times when the power of LF1 and the power of LF2 have a power level greater than 0 do not overlap.

[0130] The LF2 power has a higher mask selectivity compared to the LF1 power, enabling vertical etching. During period (1), when the HF power level is higher than during period (2), a large number of free radicals and ions are generated, and the aforementioned effect is difficult to achieve even when LF2 power is supplied during this period (1). On the other hand, during period (2), when the HF power level is lower than during period (1), the generation of free radicals and ions decreases, and the aforementioned effect is difficult to achieve even when LF2 power is supplied during this period (2). Therefore, by supplying LF2 power during period (2), the ion energy can be increased, resulting in a vertical ion incident angle. Thus, during period (2), the mask selectivity is higher than during period (1), enabling vertical etching.

[0131] Furthermore, LF1 and LF2 can generate pulse signals with two power levels, one on and one off. However, it is also possible to generate pulse signals with more than two power levels by having LF1 and LF2 have on, off, and intermediate power levels. LF1 and LF2 have two different on states.

[0132] At time t3, the HF power is switched off. During period (3), the exhaust of byproducts is controlled. That is, during the exhaust period T from time t3 to time t4... off The HF, LF1, and LF2 electrical powers are off, thus allowing byproducts to be discharged. During exhaust, T... off The time that byproducts do not adhere to the substrate W is preset.

[0133] During the exhaust period T off At time t4, the HF power level changes to a high power level, and at time t5 it returns from period (4) to period (1). In this way, the power levels of HF power, LF1 power, and LF2 power are controlled respectively.

[0134] exist Figure 6 and Figure 7 In the control of the pulse signal shown, the timing of the change in the power level of the second bias RF pulse signal is staggered relative to the timing of the change in the power level of the source RF pulse signal and / or the power level of the first bias RF pulse signal. However, it is not limited to this, and a delay time may not be set.

[0135] Figure 8 Another example of a pulse pattern representing high-frequency electrical power pulses at three frequencies. In this example, the control of each pulse signal of HF electrical power, LF1 electrical power and LF2 electrical power is repeatedly performed, with the period (1) to (4) being taken as one cycle.

[0136] For this example and Figure 7 The differences in the patterns of the pulse signals will be explained. Figure 7 In the example, the HF power level has three levels, including a 0 power level (off state). Conversely, the HF power level can also have four levels, as in this example. Furthermore, the HF power level can include a 0 power level or not. For example, as in this example, during the period of byproduct discharge (3), the HF power can be kept on by decreasing its power level instead of being off.

[0137] In addition, Figure 7 In this example, the LF1 power has two levels: on and off. Conversely, as in this case, the LF1 power can also have a time-dependent duration T. b1-1 Time T b1-2 The system has two on-state levels and three power levels (0 power level). Furthermore, in this example, the on-state with the highest power level of LF1 (high power level) and the on-state with the highest power level of LF2 do not overlap in time.

[0138] [Modifications of plasma processing devices]

[0139] Reference Figure 9 A modified example of plasma processing device 1 will be described. Figure 9 This is a diagram illustrating an example of a modified embodiment of the plasma processing apparatus 1. In the modified plasma processing apparatus 1, Figure 2 Apart from the structure of the plasma processing apparatus 1 shown, the only difference is that the power supply section includes a DC power supply section 32.

[0140] The DC power supply unit 32 includes a DC pulse generating unit 32a coupled to the substrate support unit 11. The DC pulse generating unit 32a is configured to be connected to the conductive member 112 of the substrate support unit 11 via a second matching circuit 34, and is capable of generating a bias DC pulse signal (voltage). The generated bias DC pulse signal is applied to the conductive member 112 of the substrate support unit 11. The DC pulse generating unit 32a may be provided in addition to the RF power supply unit 31, or it may be provided in place of the second bias RF generating unit 31c. Other configurations of the modified plasma processing apparatus 1 are as follows... Figure 2 The plasma processing device 1 shown is the same, so its description is omitted.

[0141] Below, refer to Figures 10-12 An example of the pulse mode of DC pulse and high-frequency power pulse in Modification Examples 1 to 3 will be described. Figures 10-12This is a diagram showing the pulse patterns of DC pulses and high-frequency power pulses in variations 1 to 3.

[0142] Figure 10 Modification 1 illustrates the pulse pattern of HF power, LF1 power, and DC pulse voltage (DC pulse signal) when a DC pulse generation unit 32a is provided instead of the second bias RF generation unit 31c. In Modification 1, the control of each pulse signal of HF power, LF1 power, and DC pulse voltage is repeatedly performed during one cycle, with the period (1) to the period (3) and the exhaust period (not shown) after the period (3).

[0143] From time t0 to time t 21 During period (1), the HF power has a high power level, the LF1 power has a high power level, and the DC pulse voltage is off. At time t 21 During this process, the HF power level and the LF1 power level both transition to a low power level, while the DC pulse voltage remains off. From time t... 21 up to time t 22 During period (2), the HF power is at a low power level, the LF1 power is at a low power level, and the DC pulse voltage is off. At time t 22 During this process, the HF power supply transitions to the off state, the LF1 power supply transitions to the off state, and the DC pulse voltage maintains the off state. From time t... 22 After a delay of time T delay Afterwards, the DC pulse voltage transitions to the ON state. From time t... 22 After a delay of time T delay After that, until time t 23 During period (3), the HF power and LF1 power are in the off state, and the DC pulse voltage is in the on state. The DC pulse generation unit 32a generates a pulse sequence in the on state of the DC pulse voltage.

[0144] As described above, in Modification 1, the power of LF1 has a zero power level during the on-time of the DC pulse voltage during period (3). The DC pulse generation unit 32a is configured to generate a DC pulse signal during the DC on-time and to stop generating the DC pulse during the DC off-time, which is different from the DC on-time.

[0145] Figure 11Modification 2 illustrates the pulse patterns of HF power, LF1 power, LF2 power, and DC pulse voltage when a DC pulse generation unit 32a is provided in addition to the second bias RF generation unit 31c. In Modification 2, the control of each pulse signal of HF power, LF1 power, LF2 power, and DC pulse voltage is repeatedly performed by taking the period (1) to (4) and the exhaust period (not shown) after period (4) as one cycle.

[0146] From time t0 to time t 24 During period (1), the HF power and LF1 power are in the ON state, while the LF2 power and DC pulse voltage are in the OFF state. At time t 24 During this process, the HF power remains on, the LF1 power switches to the off state, the LF2 power remains off, and the DC pulse voltage switches to the on state. From time t... 24 up to time t 25 During period (2), the HF power is on, the LF1 and LF2 power are off, and the DC pulse voltage is on. The DC pulse generation unit 32a generates a pulse sequence when the DC pulse voltage is on. At time t 25 During this process, the HF power remains on, the LF1 power remains off, the LF2 power switches to the on state, and the DC pulse voltage switches to the off state. From time t... 25 up to time t 26 During period (3), the HF power is on, the LF1 power is off, the LF2 power is on, and the DC pulse voltage is off. At time t 26 During this process, the HF power supply transitions to the off state, the LF1 power supply remains off, the LF2 power supply remains on, and the DC pulse voltage remains off. From time t... 26 up to time t 27 During the period (4), the HF power is off, the LF1 power is off, the LF2 power is on, and the DC pulse voltage is off.

[0147] As described above, in Modification 2, the LF2 power has a zero power level during the on-time of the DC pulse voltage during period (2). The DC pulse generation unit 32a is configured to generate a DC pulse signal during the DC on-time and to stop generating the DC pulse during the DC off-time, which is different from the DC on-time.

[0148] Figure 12Modification 3 does not represent another example of the pulse pattern of HF power, LF1 power, LF2 power and DC pulse voltage when a DC pulse generation unit 32a is provided in addition to the second bias RF generation unit 31c. In Modification 3, the control of each pulse signal of HF power, LF1 power, LF2 power and DC pulse voltage is repeatedly performed by taking the period (1) to the period (3) and the exhaust period after the period (3) as one cycle.

[0149] From time t0 to time t 28 During period (1), the HF power has a high power level, the LF1 power has a low power level, the LF2 power is off, and the DC pulse voltage is on. The transition of the DC pulse voltage to the power level relative to the transition of the LF1 power to the high power level is delayed before transitioning to the on state. The DC pulse generation unit 32a generates a pulse sequence during the on state of the DC pulse voltage. At time t 28 During this process, the HF power level and the LF1 power level both transition to a low power level, while the LF2 power level remains off, and the DC pulse voltage remains on. From time t... 28 up to time t 29 During period (2), the HF power is at a low power level, the LF1 power is at a low power level, the LF2 power is off, and the DC pulse voltage is on. At time t 29 During this process, the HF power supply transitions to the off state, the LF1 power supply transitions to the off state, the LF2 power supply remains off, and the DC pulse voltage transitions to the off state. From time t... 29 After a delay of time T delay Afterwards, the LF2 power supply switches to the ON state. From time t... 29 After a delay of time T delay After that, until time t 30 During the period (3), the HF power and LF1 power are in the off state, the LF2 power is in the on state, and the DC pulse voltage is in the off state.

[0150] As described above, in Modification 3, the power of LF2 is at zero during the on-time of the DC pulse voltage in periods (1) and (2). The DC pulse generation unit 32a is configured to generate a DC pulse signal during the DC on-time and to stop generating DC pulses during the DC off-time, which is different from the DC on-time.

[0151] As mentioned above, the on-state of the DC pulse voltage and the on-state of the LF2 power supply do not overlap in time. Furthermore, the on-state of the DC pulse voltage and the on-state of the LF1 power supply may or may not overlap in time.

[0152] As explained above, the plasma processing apparatus and plasma processing method according to this embodiment can use three high-frequency electrical power pulse signals to improve processing performance.

[0153] It should be understood that the plasma processing apparatus and plasma processing method disclosed herein are illustrative in all respects and not limiting. The embodiments can be modified and improved in various ways without departing from the scope and spirit of the appended claims. The contents described in the foregoing embodiments can also be configured in other ways without contradiction, and can also be combined without contradiction.

[0154] For example, in the above embodiment, an inductively coupled plasma device was described as an example, but it is not limited to this and can be applied to other plasma devices. For example, instead of an inductively coupled plasma device, a capacitively-coupled plasma (CCP) device can be used. In this case, the capacitively-coupled plasma device includes an upper electrode and a lower electrode. The lower electrode is disposed within the substrate support, and the upper electrode is disposed above the substrate support. Furthermore, the first matching circuit 33 is coupled to the upper electrode, and the second matching circuit 34 is coupled to the lower electrode. Therefore, the first matching circuit 33 is coupled to the antenna 14 of the inductively coupled plasma device or the upper electrode of the capacitively-coupled plasma device. That is, the first matching circuit 33 is coupled to the chamber 10.

Claims

1. A plasma processing device, characterized in that, have: Plasma processing chamber; The substrate support portion is disposed within the plasma processing chamber; An antenna is disposed at the upper part of the plasma processing chamber; The RF generation unit is configured to generate RF pulse signals with at least three power levels, wherein each power level of the RF pulse signals is 0 or higher. The first bias RF generation unit is configured to generate a first bias RF pulse signal, wherein the frequency of the first bias RF pulse signal is lower than the frequency of the generation source RF pulse signal, and the first bias RF pulse signal has at least two power levels, each of which is 0 or higher. The second bias RF generation unit is configured to generate a second bias RF pulse signal, wherein the second bias RF pulse signal has at least two power levels, each of which is 0 or higher; The synchronization signal generation unit is configured to generate a synchronization signal for synchronizing the generation source RF generation unit, the first bias RF generation unit, and the second bias RF generation unit with each other; A first matching circuit, connected to the RF generation unit and the antenna, enables the RF pulse signal from the RF generation unit to be supplied to the antenna via the first matching circuit; and The second matching circuit, connected to the first bias RF generation unit, the second bias RF generation unit, and the substrate support unit, enables the first bias RF pulse signal to be supplied from the first bias RF generation unit to the substrate support unit via the second matching circuit, and enables the second bias RF pulse signal to be supplied from the second bias RF generation unit to the substrate support unit via the second matching circuit. The second matching circuit has: A first separation circuit, connected between the first bias RF generation unit and the substrate support unit, prevents coupling of the second bias RF pulse signal from the second bias RF generation unit; and The second separation circuit is connected between the second bias RF generation unit and the substrate support unit to prevent coupling of the first bias RF pulse signal from the first bias RF generation unit. The first separation circuit is a resonant circuit that includes a capacitor and an inductor. The second separation circuit is an RF choke circuit containing an inductor.

2. The plasma processing apparatus as described in claim 1, characterized in that: The frequency of the second bias RF pulse signal is different from the frequency of the first bias RF pulse signal.

3. The plasma processing apparatus as described in claim 1 or 2, characterized in that: The frequency of the second bias RF pulse signal is lower than the frequency of the first bias RF pulse signal.

4. The plasma processing apparatus as described in claim 1 or 2, characterized in that: The synchronization signal generation unit is configured in any one of the generation source RF generation unit, the first bias RF generation unit, and the second bias RF generation unit.

5. The plasma processing apparatus as described in claim 1 or 2, characterized in that: The first bias RF generation unit is configured to stagger the timing of the change in the power level of the first bias RF pulse signal relative to the timing of the change in the power level of the generated source RF pulse signal.

6. The plasma processing apparatus as described in claim 1 or 2, characterized in that: The second bias RF generation unit is configured to make the timing of the change in the power level of the second bias RF pulse signal staggered relative to the timing of the change in the power level of the generation source RF pulse signal and / or the timing of the change in the power level of the first bias RF pulse signal.

7. The plasma processing apparatus as described in claim 1 or 2, characterized in that: The second bias RF pulse signal has two power levels, including a zero power level.

8. The plasma processing apparatus as described in claim 7, characterized in that: The first bias RF pulse signal has a power level greater than 0 in the first time interval. The second bias RF pulse signal has a zero power level during the first time.

9. The plasma processing apparatus as described in claim 1 or 2, characterized in that: It has a DC pulse generating unit configured to be electrically connected to the substrate support unit, and is capable of generating a bias DC pulse signal.

10. The plasma processing apparatus as described in claim 9, characterized in that: The second bias RF pulse signal has a zero power level during the DC on-time. The DC pulse generation unit is configured to generate a bias DC pulse signal during the DC turn-on time and to stop generating DC pulses during a DC turn-off time that is different from the DC turn-on time.

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