Load switch with transistors connected back to back

Abstract

The present application discloses a device, a method and a controller. The device comprises: a first drain / source region and a second drain / source region located above a substrate; and a first gate region adjacent to the first drain / source region, a second gate region adjacent to the second drain / source region, and a third gate region located between the first gate region and the second gate region, wherein the first drain / source region, the second drain / source region, the first gate region, the second gate region and the third gate region form two transistors connected back to back.

Description

Technical Field

[0001] The present invention relates to a load switch, and in some specific embodiments, to a load switch having a pair of back-to-back connected transistors. Background Art

[0002] With the development of semiconductor technology, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been widely used in integrated circuits. MOSFET is a voltage-controlled device. When a control voltage is applied to the gate of the MOSFET and the control voltage is greater than the threshold of the MOSFET, a conductive channel is established between the drain and source of the MOSFET. After the conductive channel is established, current flows between the drain and source of the MOSFET. On the other hand, when the control voltage applied to the gate is less than the threshold of the MOSFET, the MOSFET is turned off accordingly.

[0003] MOSFET can be divided into two categories, namely n-channel MOSFET and p-channel MOSFET. According to the different structures, MOSFET can be divided into three subcategories: planar MOSFET, lateral double-diffused MOS (LDMOS) devices and vertical double-diffused MOSFET. Compared with the other two MOSFETs, the asymmetric structure of LDMOS devices provides a short channel between the drain and source of LDMOS, so LDMOS devices can provide a larger current per unit area. In order to further improve the performance of LDMOS devices, reduced surface electric field (RESURface Field, RESURF) diffusion can be set in the drift region to increase the breakdown voltage of LDMOS devices at a given on-resistance (specific-on-resistance, Rsp).

[0004] The load switch is configured to connect the load to the power supply or disconnect the load from the power supply. The load switch can be controlled by an external signal. In operation, when the load switch is closed, the load switch is able to prevent current from flowing in both directions. On the other hand, when the load switch is turned on, a conductive path is established between the load and the power supply. Current flows from the power supply to the load through the conductive path. The load switch can be implemented as an isolation switch with two transistors connected back to back. For high voltage applications (e.g., 24V), each transistor can be implemented as an LDMOS device. The LDMOS devices connected back to back are able to achieve bidirectional current blocking.

[0005] The disadvantage of the existing high voltage load switch is that the back-to-back connection of the LDMOS device actually quadruples the on-resistance of the load switch because the device area and on-resistance of the LDMOS device are both doubled. With the further development of the semiconductor industry, the load switch can be implemented on an integrated circuit. It is expected to reduce the occupied space of the load switch to improve the efficiency and cost of the integrated circuit. Summary of the invention

[0006] The present disclosure provides a load switch having a pair of back-to-back connected transistors. In some preferred embodiments of the present disclosure, the above-mentioned problems and other problems are generally solved or circumvented, and technical advantages are achieved.

[0007] According to one embodiment of the present disclosure, a device is provided, including: a first drain / source region and a second drain / source region located above a substrate; and a first gate region adjacent to the first drain / source region, a second gate region adjacent to the second drain / source region, and a third gate region located between the first gate region and the second gate region, wherein the first drain / source region, the second drain / source region, the first gate region, the second gate region and the third gate region form two transistors connected back to back.

[0008] According to another embodiment of the present disclosure, a method is provided, comprising: in an off state of a load switch, the load switch comprises two back-to-back connected transistors, connecting a first gate region and a second gate region of the two back-to-back connected transistors to a first voltage potential lower than a turn-on threshold of the two back-to-back connected transistors, and connecting a third gate region to a first source of the two back-to-back connected transistors; and in an on state of the load switch, connecting the first gate region and the second gate region of the two back-to-back connected transistors to a second voltage potential higher than a turn-on threshold of the two back-to-back connected transistors, and connecting the third gate region to a third voltage potential higher than the turn-on threshold of the two back-to-back connected transistors.

[0009] According to another embodiment of the present disclosure, a controller is provided, comprising: a first gate driver configured to apply a first voltage potential to a first gate region of the load switch in an off state of the load switch, and to apply a second voltage potential to the first gate region of the load switch in an on state of the load switch, wherein the first voltage potential is lower than a turn-on threshold of the first switch of the load switch, and the second voltage potential is higher than the turn-on threshold of the first switch of the load switch; a second gate driver configured to apply the first voltage potential to the second gate region of the load switch in the off state of the load switch, and to apply the second voltage potential to the second gate region of the load switch in the on state of the load switch; and a third gate driver configured to connect the third gate region of the load switch to the first source of the load switch in the off state of the load switch, and to apply a third voltage potential to the third gate region of the load switch in the on state of the load switch, wherein the third voltage potential is higher than the turn-on threshold of the first switch of the load switch formed by two transistors connected back to back.

[0010] According to one embodiment of the present disclosure, another device is provided, including: a first drain / source region and a second drain / source region located above a substrate; and a first gate region adjacent to the first drain / source region, and a second gate region adjacent to the second drain / source region, wherein the first drain / source region, the second drain / source region, the first gate region and the second gate region form two transistors connected back to back.

[0011] According to another embodiment of the present disclosure, another method is provided, characterized in that it includes: growing an epitaxial layer of a first conductive type above a substrate of a first conductive type; forming a drift layer of a second conductive type above the epitaxial layer; forming a first body region and a second body region of the first conductive type in the drift layer; performing ion implantation of the second conductive type to form a first source region in the first body region and a second source region in the second body region; and forming a first gate region adjacent to the first source region and a second gate region adjacent to the second source region, wherein the first source region and the second source region are respectively located on opposite sides of the first gate region and the second gate region.

[0012] According to another embodiment of the present disclosure, a load switch is provided, comprising: a first transistor; and a second transistor connected back-to-back to the first transistor, wherein: a source of the first transistor and a source of the second transistor are formed above a substrate; a gate of the first transistor is adjacent to the source of the second transistor; and a gate of the second transistor is adjacent to the source of the first transistor, wherein the gate of the first transistor and the gate of the second transistor are separated from each other.

[0013] The above description broadly summarizes the features and technical advantages of the present disclosure so that the following detailed description of the present disclosure can be better understood. Additional features and advantages of the present disclosure will be described below, and these additional features and advantages also constitute the subject matter protected by the claims of the present disclosure. It should be understood by those skilled in the art that, based on the concepts and specific embodiments of the present disclosure, it is easy to modify and design other structures or processes that have the same purpose as the present disclosure. It should also be recognized by those skilled in the art that these equivalent structures do not deviate from the spirit and scope of the present disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more fully understand the present disclosure and its advantages, the following description is now provided for reference in conjunction with the accompanying drawings, in which:

[0015] Figure 1 A schematic diagram of a common drain transistor according to an embodiment of the present disclosure is shown;

[0016] Figure 2 shows a simplified cross-sectional view of a load switch formed by a common drain LDMOS transistor according to an embodiment of the present disclosure;

[0017] Figure 3 The embodiment according to the present disclosure is shown Figure 2 A simplified top view of a load switch is shown;

[0018] Figure 4 shows a simplified cross-sectional view of another load switch formed by a common drain LDMOS transistor according to an embodiment of the present disclosure;

[0019] Figure 5 shows a simplified cross-sectional view of another load switch formed by two transistors according to an embodiment of the present disclosure;

[0020] Figure 6 shows a simplified cross-sectional view of another load switch formed by a common drain LDMOS transistor according to various embodiments of the present disclosure;

[0021] Figure 7shows a simplified cross-sectional view of another load switch formed by a common drain LDMOS transistor according to an embodiment of the present disclosure;

[0022] Figure 8 The formation according to the embodiment of the present disclosure is shown Figure 1 A flowchart of a method for sharing a drain transistor as shown;

[0023] Fig. 9 The method for driving the Figure 1 A controller for the load switch shown;

[0024] Fig.10 A schematic diagram of a load switch with a split gate structure according to an embodiment of the present disclosure is shown;

[0025] Fig.11 The embodiment according to the present disclosure is shown Fig.10 A simplified cross-sectional view of a first embodiment of a load switch is shown;

[0026] Fig.12 The embodiment according to the present disclosure is shown Fig.10 A simplified cross-sectional view of a second embodiment of a load switch is shown;

[0027] Fig.13 The embodiment according to the present disclosure is shown Fig.10 A simplified cross-sectional view of a third embodiment of a load switch is shown;

[0028] Fig.14 The method for controlling the Fig.10 A flow chart of a load switch method shown;

[0029] Fig.15 The method for driving the Fig.10 A controller for the load switch shown;

[0030] Fig.16 A schematic diagram of another load switch with a split gate structure according to an embodiment of the present disclosure is shown;

[0031] Fig.17 The embodiment according to the present disclosure is shown Fig.16 A simplified cross-sectional view of a first embodiment of a load switch is shown;

[0032] Fig.18 The embodiment according to the present disclosure is shown Fig.16 A simplified cross-sectional view of a second embodiment of a load switch is shown;

[0033] Fig.19 The embodiment according to the present disclosure is shown Fig.16A simplified cross-sectional view of a third embodiment of a load switch is shown;

[0034] Fig. 20 The method for controlling the Fig.16 A flow chart of a load switch method shown; and

[0035] Fig.21 The method for driving the Fig.16 The load switch controller is shown.

[0036] In the different drawings, corresponding numerals and symbols are generally used to indicate corresponding parts unless otherwise indicated. These drawings are for the purpose of clearly illustrating the relevant aspects of the various embodiments and are not necessarily and necessarily drawn to scale. DETAILED DESCRIPTION

[0037] The implementation and application of the preferred embodiments of the present disclosure will be discussed in detail below. However, it should be understood that the present disclosure provides many applicable inventive concepts that can be embodied in a variety of specific contexts. The specific embodiments discussed are merely illustrations of some specific ways to implement and apply the present disclosure and do not limit the scope of the present disclosure.

[0038] The present disclosure will describe some preferred embodiments in a specific context, namely, a load switch comprising a pair of lateral double-diffused metal oxide semiconductor (LDMOS) devices connected back to back. However, the embodiments of the present disclosure can also be applied to various metal oxide semiconductor field effect transistors (MOSFETs).

[0039] Figure 1 A schematic diagram of a shared-drain transistor according to an embodiment of the present disclosure is shown. The load switch can be implemented as two LDMOS devices connected back to back, and the two LDMOS devices share a drain. In the full description, "load switch" may be alternatively referred to as "shared-drain transistor".

[0040] like Figure 1 As shown, the common drain transistor 100 includes two N-type transistors connected back to back. The first transistor includes a first drain D1, a first gate G1 and a first source S1. The second transistor includes a second drain D2, a second gate G2 and a second source S2. The drains of the two N-type transistors are directly connected to each other, as shown in FIG. Figure 1 shown. Figure 1The back-to-back connected N-type transistors shown can be used as a load switch. A load switch is capable of bidirectional current blocking. Therefore, a load switch can also be called an isolation switch.

[0041] In operation, the source of the second transistor can be connected to a high voltage potential, such as a bias voltage. The source of the first transistor can be connected to a low voltage potential. In this configuration, the second switch is turned on when the second gate is driven by a voltage higher than the high voltage potential. A charge pump can be used to provide a gate drive voltage higher than the high voltage potential.

[0042] In some embodiments, Figure 1 Each transistor shown may be implemented as a lateral double diffused metal oxide semiconductor (LDMOS). The common drain transistor 100 may have only four terminals, namely a first gate terminal, a first source terminal, a second gate terminal, and a second source terminal. Figure 1 As shown, the drains of the two back-to-back connected N-type transistors are connected to each other. In other words, the first transistor and the second transistor share a drain. Figure 1 As shown in FIG. 1 , the common drain is floating. Therefore, the common drain transistor 100 does not have a drain terminal. By removing unnecessary drain regions (e.g., drain diffusion regions, drain contacts, drain metal regions, etc.), the layout of the common drain transistor 100 can be improved. By removing unnecessary drain regions, Figure 1 The two transistors shown are placed as close together as possible while ensuring that the two gates (G1 and G2) are separated by the minimum spacing specified by the design rules. Figure 2-3 A detailed structure of the common drain transistor 100 is described.

[0043] Figure 2 A simplified cross-sectional view of a load switch formed by a common drain LDMOS transistor according to an embodiment of the present disclosure is shown. The common drain LDMOS transistor 200 includes a substrate 102, a first structure layer 104, a drift layer 106 formed above the first structure layer 104, a first body region 112, and a second body region 122 formed in the drift layer 106. The LDMOS transistor 200 also includes a first drain / source region 114 formed in the first body region 112, a second drain / source region 124 formed in the second body region 122, a first gate dielectric layer 133, a high voltage oxide region 132, a second gate dielectric layer 135, a first source contact 116, a first gate region 134, a second gate region 136, and a second source contact 126.

[0044] In some embodiments, the substrate 102, the first structure layer 104, the first body region 112, and the second body region 122 have a first conductivity type, and the drift layer 106, the first drain / source region 114, and the second drain / source region 124 have a second conductivity type. In some embodiments, the first conductivity type is P-type, the second conductivity type is N-type, and the common drain LDMOS transistor 200 is formed by two n-type transistors. Alternatively, the first conductivity type is N-type, the second conductivity type is P-type, and the common drain LDMOS transistor 200 is formed by two p-type transistors.

[0045] The substrate 102 may be formed of a suitable semiconductor material, such as silicon, silicon germanium, silicon carbide, etc. According to different applications and design requirements, the substrate 102 may be N-type or P-type. In some embodiments, the substrate 102 is a P-type substrate, and a suitable P-type dopant (such as boron, etc.) is doped into the substrate 102. Alternatively, the substrate 102 is an N-type substrate, and a suitable N-type dopant (such as phosphorus, etc.) is doped into the substrate 102.

[0046] The first structure layer 104 may be implemented as a P-type epitaxial layer. In the full description, the first structure layer 104 may be alternatively referred to as the P-type epitaxial layer 104. The P-type epitaxial layer 104 is grown from the substrate 102. The epitaxial growth of the P-type epitaxial layer 104 may be achieved by using any suitable semiconductor manufacturing process, such as chemical vapor deposition (CVD). In some embodiments, the doping concentration of the P-type epitaxial layer 104 is about 10 14 / cm 3 to about 10 16 / cm 3 within the range.

[0047] The drift layer 106 is an N-type layer formed on the first structure layer 104. In some embodiments, the drift layer 106 may be doped with an N-type dopant such as phosphorus to reach about 10 15 / cm 3 to about 10 17 / cm 3 It should be noted that other N-type dopants, such as arsenic, antimony, etc., may be used instead. It should also be noted that the drift layer 106 may also be referred to as an extended drift region.

[0048] The first body region 112 and the second body region 122 are P-type body regions. The P-type body region may be formed by implanting a P-type doping material such as boron. Alternatively, the P-type body region may be formed by a diffusion process. In some embodiments, a P-type material such as boron may be implanted to achieve about 10 16 / cm 3 to about 1018 / cm 3 The first body region 112 may alternatively be referred to as a first channel region. The second body region 122 may alternatively be referred to as a second channel region.

[0049] The first drain / source region 114 is a first N+ region formed in the first body region 112. The first drain / source region 114 may alternatively be referred to as a first N+ region. According to one embodiment, the first N+ region 114 is used as a first source region of the common drain LDMOS transistor 200. The first source region may be implanted with a concentration of about 10 19 / cm 3 to about 10 20 / cm 3 In addition, a first source contact 116 is formed on the first N+ region 114 .

[0050] It should be noted that a P+ region (not shown, but shown in FIG. 1 ) is formed on one side of the first body region 112 adjacent to the first N+ region 114. Figure 3 P+ region (e.g., Figure 3 The P+ region 115 shown in FIG. 1 can be implanted with a concentration of about 10 19 / cm 3 to about 10 20 / cm 3 The P+ region may contact the P-type body region. In order to eliminate the body effect, the P+ region is directly connected to the first source region (the first N+ region 114) through the first source contact 116.

[0051] The second drain / source region 124 is a second N+ region 124 formed in the second body region 122. The second drain / source region 124 may alternatively be referred to as a second N+ region 124. According to one embodiment, the second N+ region 124 is used as a second source region of the common drain LDMOS transistor 200. The second source region may be implanted with a concentration of about 10 19 / cm 3 to about 10 20 / cm 3 In addition, a second source contact 126 is formed on the second N+ region 124 .

[0052] It should be noted that a P+ region (not shown, but in the drawings) is formed on one side of the second body region 122 adjacent to the second N+ region 124. Figure 3 P+ region (e.g., Figure 3 The P+ region 125 shown in FIG. 1 can be implanted with a concentration of about 10 19 / cm 3 to about 10 20 / cm 3 The P+ region may contact the P-type body region. To eliminate the body effect, the P+ region is directly connected to the second source region (the second N+ region 124) through the second source contact 126.

[0053] The first gate dielectric layer 133, the high voltage oxidation region 132 and the second gate dielectric layer 135 are formed on the drift layer 106. Figure 2 As shown, the first gate dielectric layer 133 is partially located on the first gate dielectric layer 133 and partially located on the drift layer 106. Similarly, the second gate dielectric layer 135 is partially located on the second body region 122 and partially located on the drift layer 106. The high voltage oxidation region 132 is formed between the first gate dielectric layer 133 and the second gate dielectric layer 135. Figure 2 As shown, the high-voltage oxidation region 132 is a trapezoid. Within the scope and spirit of the present disclosure, the high-voltage oxidation region may also include other shapes, such as but not limited to square, rectangle, etc.

[0054] like Figure 2 As shown, the thickness of the high voltage oxidation region 132 is much greater than the thickness of the first gate dielectric layer 133 and the second gate dielectric layer 135. In some embodiments, the thickness of the first gate dielectric layer 133 and the second gate dielectric layer 135 is between about 100 angstroms and about 200 angstroms. The thickness of the high voltage oxidation region 132 is about 5000 angstroms. In some embodiments, the first gate dielectric layer 133, the high voltage oxidation region 132 and the second gate dielectric layer 135 can be formed of a suitable oxide material, such as silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide, etc.

[0055] The first gate region 134 is formed on the first gate dielectric layer 133 and the high voltage oxidation region 132. The second gate region 136 is formed on the second gate dielectric layer 135 and the high voltage oxidation region 132. The first gate region 134 and the second gate region 136 may be formed of polysilicon, polysilicon germanium, nickel silicide or other metal or metal alloy materials.

[0056] like Figure 2 As shown, the first gate region 134 extends upward onto the high voltage oxidation region 132. The first gate region 134 covers the first sidewall and the first edge portion of the high voltage oxidation region 132. The combination of the first gate region 134 and the high voltage oxidation region 132 serves as a first field plate. The first field plate helps maintain the breakdown voltage of the first transistor in the common drain LDMOS transistor 200. Similarly, the second gate region 136 extends upward onto the high voltage oxidation region 132. The second gate region 136 covers the second sidewall and the second edge portion of the high voltage oxidation region 132. The combination of the second gate region 136 and the high voltage oxidation region 132 serves as a second field plate. The second field plate helps maintain the breakdown voltage of the second transistor in the common drain LDMOS transistor 200.

[0057] The first gate region 134 and the second gate region 136 can be formed by the following steps: depositing a polysilicon layer with a thickness of about 4000 angstroms above the gate dielectric layer and the high-voltage oxidation region, depositing a photoresist layer on the polysilicon layer, developing the photoresist layer to define the first gate region 134 and the second gate region 136, and etching the polysilicon layer to form gates 134 and 136.

[0058] like Figure 2 As shown, the first drain / source region 114 and the second drain / source region 124 are symmetrically arranged relative to the center line 101 passing through the high voltage oxidation region 132 . The first gate region 134 and the second gate region 136 are symmetrically arranged relative to the center line 101 passing through the high voltage oxidation region 132 .

[0059] In a conventional common drain LDMOS transistor, two LDMOS transistors are arranged symmetrically with respect to a common drain. Each LDMOS transistor has an independent high voltage oxidation region, and the two high voltage oxidation regions are separated by a drain contact. According to the design rules of a 24V LDMOS device, the size of a single LDMOS transistor is about 2.16um, and the size of two LDMOS transistors is about 4.32um. It should be noted that the sizes selected for use in the preceding examples are for demonstration purposes only and are not intended to limit the various embodiments of the present invention to any particular size. Those skilled in the art will appreciate that the size of the LDMOS may vary in many ways depending on the different manufacturing processes.

[0060] like Figure 2 As shown, the present disclosure uses a single high voltage oxide region 132 to replace the two high voltage oxide regions in the conventional common drain LDMOS transistor. In addition, the drain region and the drain contact have been removed. Since the two high voltage oxide regions are merged into one high voltage oxide region and the drain region and the drain contact are removed, the two LDMOS transistors are close to each other.

[0061] like Figure 2 As shown, D represents the size of the common drain LDMOS transistor 200. Specifically, D is the distance between the first source contact 116 and the second source contact 126. According to the design rules of the 24V LDMOS device, D is about 3.15 μm. Figure 2 The size of the common drain LDMOS transistor 200 is much smaller than that of a conventional common drain LDMOS transistor (4.32 um).

[0062] For a common drain LDMOS transistor formed by a 24V LDMOS device, Figure 2The area of ​​the common drain LDMOS transistor shown is about 1.46 times the area of ​​a single transistor. Its on-resistance is equal to the area of ​​the semiconductor device multiplied by the on-resistance of the semiconductor device. The effective on-resistance is obtained through a normalization process. Based on the normalization process, the effective on-resistance of a single 24V LDMOS device is equal to 1. According to the same normalization process, Figure 2 The common drain LDMOS transistor shown has an effective on-resistance of 2.92. In a conventional device, the effective on-resistance is 4. Therefore, Figure 2 The common drain LDMOS transistor shown has a 27% improvement in on-resistance relative to conventional devices.

[0063] In operation, when the first gate voltage and the second gate voltage are applied to the first gate region 134 and the second gate region 136, respectively, and the gate voltage is greater than the threshold of the corresponding transistor. A first inversion layer is formed in the first body region 112, and the first inversion layer couples the first N+ region 114 to the drift layer 106. A second inversion layer is formed in the second body region 122, and the second inversion layer couples the second N+ region 124 to the drift layer 106. Due to the first inversion layer and the second inversion layer, a conductive channel is established between the first source region and the second source region. Current flows between the first source region and the second source region of the common drain LDMOS transistor. On the other hand, when the gate voltage is lower than the threshold of the transistor, the common drain LDMOS transistor is correspondingly turned off.

[0064] Figure 3 The embodiment according to the present disclosure is shown Figure 2 A simplified top view of a load switch is shown. Two U-shaped N+ regions are arranged adjacent to each other. On the left, the end portion of the first U-shaped N+ region and the end portion of the second U-shaped N+ region form Figure 2 The first source region 114 is shown. The first source region 114 is formed in the first body region 112. Similarly, the end portion of the U-shaped first N+ region and the end portion of the U-shaped second N+ region form Figure 2 The second source region 124 is shown. The second source region 124 is formed in the second body region 122.

[0065] The first P+ region 115 (ie, the first body contact region) is located between the two N+ regions of the first source region 114. The first P+ region 115 may contact Figure 2 A plurality of first source contacts 116 are formed on the first P+ region 115 and on the adjacent N+ region. At least one source contact 116 couples the first P+ region 115 to the adjacent N+ region.

[0066] It should be noted that, although there is only one P+ region 115 on the left side, the semiconductor device may include a plurality of P+ regions 115. More specifically, the N+ region and the plurality of P+ regions may be formed in an alternating manner.

[0067] The second P+ region 125 (ie, the second body contact region) is located between the two N+ regions of the second source region 124. The second P+ region 125 may contact Figure 2 A second p-type body region is shown. A plurality of second source contacts 126 are formed on the second P+ region 125 and on the adjacent N+ region. At least one source contact 126 couples the second P+ region 125 to the adjacent N+ region.

[0068] It should be noted that, although there is only one P+ region 125 on the left side, the semiconductor device may include a plurality of P+ regions 125. More specifically, the N+ region and the plurality of P+ regions may be formed in an alternating manner.

[0069] The high voltage oxidation region 132 is located between the first body region 112 and the second body region 122. The active region 120 of the common drain LDMOS transistor is orthogonal to the high voltage oxidation region 132. Figure 3 As shown. The first gate region 134 is disposed adjacent to the first source region 114. A plurality of first gate contacts 137 are formed above the first gate region 134. The second gate region 136 is disposed adjacent to the second source region 124. A plurality of second gate contacts 139 are formed above the second gate region 136. Figure 3 As shown, the first gate region 134 and the second gate region 136 are separated from each other.

[0070] Figure 4 A simplified cross-sectional view of another load switch formed from common-drain LDMOS transistors according to an embodiment of the present disclosure is shown. Figure 4 The common drain LDMOS transistor 400 is shown with Figure 2 The common drain LDMOS transistor 200 is similar to the common drain LDMOS transistor 400, except that the common drain LDMOS transistor 400 does not include a high voltage oxide region. Figure 4 As shown, the first gate region 134 and the second gate region 136 are formed on the first gate dielectric layer 133 and the second gate dielectric layer 135, respectively. The first gate dielectric layer 133 and the second gate dielectric layer 135 are made of the same material. The first gate dielectric layer 133 and the second gate dielectric layer 135 are collectively referred to as gate dielectric layers. Figure 4 As shown, the first gate region 134 covers a first edge portion of the gate dielectric layer. The second gate region 136 covers a second edge portion of the gate dielectric layer. The first gate region 134 and the second gate region 136 are separated from each other. Figure 4 The common drain LDMOS transistor 400 shown may be suitable for medium voltage applications, such as 12V applications.

[0071] Figure 5 FIG. 2 shows a simplified cross-sectional view of another load switch formed by two transistors according to an embodiment of the present disclosure. Figure 5 The load switch 500 shown is similar to Figure 2 The principle is the same as shown, except that Figure 5 The load switch shown is suitable for low voltage applications (eg, 5V applications).

[0072] exist Figure 5 In the embodiment of the present invention, an epitaxial layer 104 is formed on a substrate 102. A well 107 is formed on the epitaxial layer 104. A first drain / source region 114 and a second drain / source region 124 are formed in the well 107. In some embodiments, the substrate 102, the epitaxial layer 104, and the well 107 have a first conductivity type. The first drain / source region 114 and the second drain / source region 124 have a second conductivity type. In some embodiments, the first conductivity type is a P type. The second conductivity type is an N type.

[0073] It should be noted that when the first drain / source region 114 and the second drain / source region 124 are implemented as source regions, the load switch is formed by two transistors with a common drain. On the other hand, when the first drain / source region 114 and the second drain / source region 124 are implemented as drain regions, the load switch is formed by two transistors with a common source.

[0074] Figure 6 A simplified cross-sectional view of another load switch formed by common-drain LDMOS transistors according to various embodiments of the present disclosure is shown. Figure 6 The common drain LDMOS transistor 600 is shown with Figure 2 The common drain LDMOS transistor 200 shown in FIG. 1 is similar to the common drain LDMOS transistor 200 shown in FIG. 1 , except that the high voltage oxide region is replaced by a shallow trench isolation (STI) region. It is well known in the art that LDMOS devices use shallow trench isolation regions to increase the breakdown voltage and will not be described in detail herein. Figure 6 As shown, the shallow trench isolation region is an inverted trapezoid. The first gate region 134 extends from the edge of the first drain / source region 114 and covers the first edge region of the shallow trench isolation region. The second gate region 136 extends from the edge of the second drain / source region 124 and covers the second edge region of the shallow trench isolation region. Figure 6 The illustrated common drain LDMOS transistor 600 may be suitable for medium voltage applications, such as 24V applications.

[0075] Figure 7 A simplified cross-sectional view of another load switch formed from common-drain LDMOS transistors according to an embodiment of the present disclosure is shown. Figure 7 The common drain LDMOS transistor 700 is shown with Figure 2The common drain LDMOS transistor 200 shown is similar, except that the high voltage oxide region is replaced by a local oxidation of silicon (LOCOS) structure. The upper portion of the LOCOS structure is located above the drift layer 106, and the lower portion thereof extends into the drift layer 106. Figure 7 As shown, the first gate region 134 is formed along the edge of the first drain / source region 114. The gate 134 covers the first sidewall and the first edge portion of the LOCOS structure. The second gate region 136 is formed along the edge of the second drain / source region 124. The second gate region 136 covers the second sidewall and the second edge portion of the LOCOS structure.

[0076] It is well known in the art that the LDMOS device adopts a LOCOS structure for increasing the breakdown voltage. Therefore, the detailed working principle of the LDMOS device is not described here. Figure 7 The illustrated common drain LDMOS transistor 700 may be suitable for medium voltage applications, such as 24V applications.

[0077] Figure 8 The formation according to the embodiment of the present disclosure is shown Figure 1 A flow chart of a method for sharing drain transistors is shown. Figure 8 The flowchart shown is only an example and should not unduly limit the scope of the claims. Many variations, substitutions, and modifications will be apparent to those skilled in the art. For example, Figure 8 The various steps shown may be added, removed, substituted, rearranged and repeated.

[0078] Return to reference Figure 1 The common drain transistor includes two N-type transistors connected back to back. The first transistor includes a first drain, a first gate and a first source. The second transistor includes a second drain, a second gate and a second source. The drains of the two N-type transistors are directly connected to each other, such as Figure 1 shown. Figure 1 The back-to-back connected N-type transistors shown can be used as load switches. The load switch is capable of bidirectional current blocking. The common drain transistor can be made by the following steps.

[0079] In step 802, an epitaxial layer having a first conductivity type is grown on a substrate having a first conductivity type. In some embodiments, the first conductivity type is a P-type. In other words, a P-type epitaxial layer is grown on a P-type substrate.

[0080] In step 804, a drift layer having a second conductivity type is formed on the epitaxial layer. In some embodiments, the second conductivity type is N-type. In other words, an N-type drift layer is formed on the P-type epitaxial layer.

[0081] In step 806 , a first body region and a second body region having a first conductivity type are formed in the drift layer.

[0082] In step 808, ion implantation of the second conductivity type is performed to form a first source region in the first body region and a second source region in the second body region.

[0083] In step 810, a first gate is formed adjacent to the first source region, and a second gate is formed adjacent to the second source region. The first source region and the second source region are located at opposite sides of the first gate and the second gate, respectively.

[0084] Return to reference Figure 2 The method also includes forming a high voltage oxidation region above the drift layer, forming a gate of the first transistor along an edge of the source of the first transistor, wherein the gate of the first transistor covers a first sidewall and a first edge portion of the high voltage oxidation region, and forming a gate of the second transistor along an edge of the source of the second transistor, wherein the gate of the second transistor covers a second sidewall and a second edge portion of the high voltage oxidation region.

[0085] Return to reference Figure 4 The method also includes forming a gate dielectric layer extending from an edge of the first source to an edge of the second source, forming a gate of the first transistor covering a first edge portion of the gate dielectric layer, and forming a gate of the second transistor covering a second edge portion of the gate dielectric layer.

[0086] Return to reference Figure 6 The method also includes forming a shallow trench isolation region in the drift layer, forming a gate of a first transistor extending from an edge of the first source region and covering a first edge region of the shallow trench isolation region, and forming a gate of a second transistor extending from an edge of the second source region and covering a second edge region of the shallow trench isolation region.

[0087] Return to reference Figure 7 The method further includes forming a local oxide of silicon (LOCOS) structure having a lower portion in the drift layer and an upper portion above the drift layer, forming a gate of the first transistor along an edge of a source of the first transistor, wherein the gate of the first transistor covers a first sidewall and a first edge portion of the LOCOS structure, and forming a gate of the second transistor along an edge of a source of the second transistor, wherein the gate of the second transistor covers a second sidewall and a second edge portion of the LOCOS structure.

[0088] Fig. 9 The method for driving the Figure 1The controller 900 includes a first gate driver and a second gate driver. The first gate driver is configured to generate a first gate drive signal applied to a first gate G1 of a first transistor. The second gate driver is configured to generate a second gate drive signal applied to a second gate G2 of a second transistor.

[0089] In operation, the first gate driver is configured to apply a first voltage potential to a first gate of the load switch in an off state of the load switch, and to apply a second voltage potential to the first gate of the load switch in an on state of the load switch. The second gate driver is configured to apply a first voltage potential to a second gate of the load switch in an off state of the load switch, and to apply a second voltage potential to the second gate of the load switch in an on state of the load switch. The first voltage potential is lower than a turn-on threshold of a first transistor and a second transistor in the load switch. The second voltage potential is higher than a turn-on threshold of the first transistor and the second transistor in the load switch.

[0090] It should be noted that the controller with two gate drivers is only used as an example and should not unduly limit the scope of the claims. A person skilled in the art will know various changes, substitutions and modifications. For example, a single gate driver can be used to drive the first transistor and the second transistor.

[0091] Fig.10 FIG. 1 is a schematic diagram of a load switch with a split-gate structure according to an embodiment of the present disclosure. Figure 1 The load switch 100 shown is similar, except that each transistor has a split gate structure. Fig.10 As shown, the first transistor has two gates, namely, the first gate G1a and the third gate G1b. Similarly, the second transistor has two gates, namely, the second gate G2a and the fourth gate G2b.

[0092] In operation, when the load switch 1000 is in the off state, the first gate G1a and the second gate G2a are connected to a first voltage potential below the conduction threshold of the two transistors. In some embodiments, the first voltage potential is a ground voltage potential. The third gate G1b is connected to the first source S1. The fourth gate G2b is connected to the second source S2. In some embodiments, the third gate G1b and the fourth gate G2b act as field plates to provide high voltage blocking capability.

[0093] When the load switch 1000 is in the on state, the first gate G1a and the second gate G2a are connected to a second voltage potential higher than the on threshold of the two transistors. The third gate G1b and the fourth gate G2b are connected to a third voltage potential higher than the on threshold of the two transistors. In some embodiments, the third gate G1b and the fourth gate G2b are used as additional gates to minimize the on resistance of the load switch 1000.

[0094] In some embodiments, the third voltage potential is equal to the second voltage potential. Alternatively, the third voltage potential is higher than the second voltage potential. Applying a higher gate drive voltage to the third gate G1b and the fourth gate G2b helps to further reduce the on-resistance of the load switch 1000.

[0095] In addition, in order to further improve the performance (e.g., power loss) of the load switch 1000, the gate drive signal can be applied to the four gates in sequence. Specifically, when the load switch 1000 is in the on state, before the third gate G1b and the fourth gate G2b are connected to the third voltage potential, the first gate G1a and the second gate G2a are connected to the second voltage potential. When the load switch 1000 is in the off state, before the first gate G1a and the second gate G2a are connected to the first voltage potential, the third gate G1b is connected to the first source S1, and the fourth gate G2b is connected to the second source S2.

[0096] Fig.11 The embodiment according to the present disclosure is shown Fig.10 A simplified cross-sectional view of a first embodiment of a load switch is shown. Fig.11 The simplified cross-section shown is similar to Figure 2 The simplified cross-sectional view shown is similar, except that the load switch includes four gates, namely a first gate G1a, a second gate G2a, a third gate G1b and a fourth gate G2b.

[0097] like Fig.11 As shown, a high voltage oxidation region 132 is formed above the substrate 102. A first gate dielectric layer 133 is formed between the high voltage oxidation region 132 and the first drain / source region 114. A second gate dielectric layer 135 is formed between the high voltage oxidation region 132 and the second drain / source region 124. In some embodiments, the first drain / source region 114 serves as a first source S1. The second drain / source region 124 serves as a second source S2. Throughout the description, the first drain / source region 114 and the first source S1 may be used interchangeably. Similarly, the second drain / source region 124 and the second source S2 may be used interchangeably.

[0098] The first gate G1a is connected to the first gate region 134. In the entire description, the first gate G1a and the first gate region 134 may be used interchangeably. Fig.11As shown, the first gate region 134 is formed on the first gate dielectric layer 133 and the first sidewall of the high voltage oxidation region 132. The second gate G2a is connected to the second gate region 136. In the full description, the second gate G2a and the second gate region 136 can be used interchangeably. Fig.11 As shown, the second gate region 136 is formed on the second gate dielectric layer 135 and the second sidewall of the high voltage oxidation region 132. The third gate G1b is connected to the third gate region 164. In the full description, the third gate G1b and the third gate region 164 can be used interchangeably. Fig.11 As shown, the third gate region 164 is formed on the top of the high voltage oxidation region 132. The fourth gate G2b is connected to the fourth gate region 166. In the full description, the fourth gate G2b and the fourth gate region 166 can be used interchangeably. Fig.11 As shown, the fourth gate region 166 is formed on the top of the high voltage oxidation region 132. Fig.11 As shown, the third gate region 164 and the fourth gate region 166 are separated from each other.

[0099] like Fig.11 As shown, the first source 114 and the second source 124 are arranged in a symmetrical manner with respect to a dielectric region (e.g., high voltage oxide region 132) formed between the first source and the second source. In addition, the first gate region 134 and the second gate region 136 are arranged in a symmetrical manner with respect to the dielectric region. In addition, the third gate region 164 and the fourth gate region 166 are arranged with respect to a center line (not shown, but in FIG. 1 ) passing through the high voltage oxide region 132. Figure 2 ) are arranged in a symmetrical manner.

[0100] Fig.12 The embodiment according to the present disclosure is shown Fig.10 A simplified cross-sectional view of a second embodiment of a load switch is shown. Fig.12 The simplified cross-section shown is similar to Fig.11 The simplified cross-sectional view shown is similar except that the third gate region 164 and the fourth gate region 166 are formed over the shallow trench isolation region 132 .

[0101] like Fig.12As shown, the first gate dielectric layer 133 is formed between the shallow trench isolation region 132 and the first drain / source region 114. The second gate dielectric layer 135 is formed between the shallow trench isolation region 132 and the second drain / source region 124. The third gate region 164 and the fourth gate region 166 are formed between the first gate region 134 and the second gate region 136. The shallow trench isolation region 132 is formed on the substrate 102. The first gate region 134 is located on the first gate dielectric layer 133. In particular, the first gate region 134 extends from the edge of the first drain / source region 114 and covers the first edge region of the shallow trench isolation region 132. The second gate region 136 is located above the second gate dielectric layer 135. In particular, the second gate region 136 extends from the edge of the second drain / source region 124 and covers the second edge region of the shallow trench isolation region 132. The third gate region 164 and the fourth gate region 166 are formed on the top of the shallow trench isolation region 132. As shown Fig.12 As shown, the third gate region 164 and the fourth gate region 166 are separated from each other.

[0102] Fig.13 The embodiment according to the present disclosure is shown Fig.10 A simplified cross-sectional view of a third embodiment of a load switch is shown. Fig.13 The simplified cross-section shown is similar to Fig.11 The simplified cross-sectional view shown is similar except that the third gate region 164 and the fourth gate region 166 are formed on top of the LOCOS structure.

[0103] like Fig.13 As shown, the third gate region 164 and the fourth gate region 166 are formed between the first gate region 134 and the second gate region 136. The LOCOS structure 132 is formed over the substrate 102. The lower portion of the LOCOS structure 132 is located below the top surface of the drain / source region (e.g., 114), and the upper portion of the LOCOS structure 132 is located above the top surface of the drain / source region (e.g., 114).

[0104] A first gate dielectric layer 133 is formed between the LOCOS structure 132 and the first drain / source region 114. A second gate dielectric layer 135 is formed between the LOCOS structure 132 and the second drain / source region 124. A first gate region 134 is formed over the first gate dielectric layer 133 and the first sidewall of the LOCOS structure 132. A second gate region 136 is formed over the second gate dielectric layer 135 and the second sidewall of the LOCOS structure 132. A third gate region 164 and a fourth gate region 166 are formed on top of the LOCOS structure 132. Fig.13 As shown, the third gate region 164 and the fourth gate region 166 are separated from each other.

[0105] Fig.14 The method for controlling the Fig.10A flow chart of a load switch method is shown. Fig.14 The flowchart shown is only an example and should not unduly limit the scope of the claims. Many variations, substitutions, and modifications will be apparent to those skilled in the art. For example, Fig.14 The various steps shown may be added, removed, substituted, rearranged and repeated.

[0106] Return to reference Fig.10 The common drain transistor includes two N-type transistors connected back to back. The first transistor includes a first drain D1, a first gate G1a, a third gate G1b and a first source S1. The second transistor includes a second drain D2, a second gate G2a, a fourth gate G2b and a second source S2. The drains of the two N-type transistors are directly connected to each other, such as Fig.10 shown. Fig.10 The back-to-back connected N-type transistors shown can be used as a load switch. The load switch can achieve bidirectional current blocking. In addition, the load switch can achieve low-resistance conduction in another state (when the load switch is turned on).

[0107] In step 1402, in the off state of the load switch, the first gate and the second gate of the two back-to-back connected transistors are connected to a first voltage potential lower than the turn-on threshold of the two back-to-back connected transistors, the third gate is connected to the first source of the two back-to-back connected transistors, and the fourth gate is connected to the second source of the two back-to-back connected transistors.

[0108] In step 1404, when the load switch is in the on state, the first gate and the second gate of the two back-to-back connected transistors are connected to a second voltage potential higher than the on-threshold of the two back-to-back connected transistors, and the third gate and the fourth gate are connected to a third voltage potential higher than the on-threshold of the two back-to-back connected transistors.

[0109] Fig.15 The method for driving the Fig.10 Controller 1500 of the load switch shown. Controller 1500 includes a first gate driver, a second gate driver, a third gate driver, and a fourth gate driver. The first gate driver is configured to generate a first gate drive signal applied to the first gate G1a of the first transistor. The second gate driver is configured to generate a second gate drive signal applied to the second gate G2a of the second transistor. The third gate driver is configured to generate a third gate drive signal applied to the third gate G1b of the first transistor. The fourth gate driver is configured to generate a fourth gate drive signal applied to the fourth gate G2b of the second transistor.

[0110] In operation, the first gate driver is configured to apply a first voltage potential to the first gate of the load switch in the off state of the load switch, and to apply a second voltage potential to the first gate of the load switch in the on state of the load switch. The first voltage potential is lower than the on threshold of the first switch (i.e., the first transistor) of the load switch. The second voltage potential is higher than the on threshold of the first switch of the load switch.

[0111] In operation, the second gate driver is configured to apply a first voltage potential to the second gate of the load switch in the off state of the load switch, and to apply a second voltage potential to the second gate of the load switch in the on state of the load switch. The first voltage potential is lower than the turn-on threshold of the second switch (i.e., the second transistor) of the load switch. The second voltage potential is higher than the turn-on threshold of the second switch of the load switch.

[0112] In operation, the third gate driver is configured to connect the third gate of the load switch to the first source of the load switch in the off state of the load switch, and to apply a third voltage potential to the third gate of the load switch in the on state of the load switch. The third voltage potential is higher than the turn-on threshold of the first switch of the load switch.

[0113] In operation, the fourth gate driver is configured to connect the fourth gate of the load switch to the second source of the load switch in the off state of the load switch, and to apply a third voltage potential to the fourth gate of the load switch in the on state of the load switch. The third voltage potential is higher than a turn-on threshold of the second switch of the load switch.

[0114] Fig.16 FIG. 1 is a schematic diagram of another load switch having a split gate structure according to an embodiment of the present disclosure. Fig.10 The load switch 1000 shown in FIG. 1 is similar, except that the third gate and the fourth gate are combined into a single gate. Fig.16 As shown, the load switch 1600 has three gates, namely, a first gate G1, a second gate G2 and a third gate G3.

[0115] In operation, when the load switch 1600 is in the off state, the first gate G1 and the second gate G2 are connected to a first voltage potential lower than the turn-on threshold of the two transistors. The third gate G3 is connected to one of the two sources of the load switch 1600. The third gate G3 acts as a field plate to provide high voltage blocking capability. In some embodiments, when the voltage potential coupled to S1 is lower than the voltage potential coupled to S2, the third gate G3 is connected to S1. On the other hand, when the voltage potential coupled to S1 is higher than the voltage potential coupled to S2, the third gate G3 is connected to S2.

[0116] In operation, when the load switch 1600 is in the on state, the first gate G1 and the second gate G2 are connected to a second voltage potential higher than the on threshold of the two transistors. The third gate G3 is connected to a third voltage potential higher than the on threshold of the two transistors. The third gate G3 is used as an additional gate to minimize the on resistance of the load switch 1600.

[0117] In some embodiments, the third voltage potential is equal to the second voltage potential. Alternatively, the third voltage potential is higher than the second voltage potential. Applying a higher gate drive voltage to the third gate G3 helps to further reduce the on-resistance of the load switch 1600.

[0118] In addition, in order to further improve the performance (e.g., power loss) of the load switch 1600, the gate drive signal can be applied to the three gates in sequence. In particular, when the load switch 1600 is in the on state, the first gate G1 and the second gate G2 are connected to the second voltage potential before the third gate G3 is connected to the third voltage potential. When the load switch 1600 is in the off state, the third gate G3 is connected to the source before the first gate G1 and the second gate G2 are connected to the first voltage potential.

[0119] Fig.17 The embodiment according to the present disclosure is shown Fig.16 A simplified cross-sectional view of a first embodiment of a load switch is shown. Fig.17 The simplified cross-section shown is similar to Fig.11 The simplified cross-section shown is similar except that the third and fourth gates have been merged into a single gate.

[0120] like Fig.17 As shown, a high voltage oxidation region 132 is formed on the substrate 102. A first gate dielectric layer 133 is formed between the high voltage oxidation region 132 and the first drain / source region 114. A second gate dielectric layer 135 is formed between the high voltage oxidation region 132 and the second drain / source region 124.

[0121] The first gate region 134 is formed on the first gate dielectric layer 133 and the first sidewall of the high voltage oxidation region 132. The second gate region 136 is formed on the second gate dielectric layer 135 and the second sidewall of the high voltage oxidation region 132. The third gate region 168 is formed on the top of the high voltage oxidation region 132. The third gate region 168 is located at the center of the top surface of the high voltage oxidation region 132.

[0122] Fig.18 The embodiment according to the present disclosure is shown Fig.16 A simplified cross-sectional view of a second embodiment of a load switch is shown. Fig.18 The simplified cross-section shown is similar to Fig.12The simplified cross-section shown is similar except that the third and fourth gates have been merged into a single gate.

[0123] like Fig.18 As shown, the first gate dielectric layer 133 is formed between the shallow trench isolation region 132 and the first drain / source region 114. The second gate dielectric layer 135 is formed between the shallow trench isolation region 132 and the second drain / source region 124. The third gate region 168 is formed between the first gate region 134 and the second gate region 136. The shallow trench isolation region 132 is formed above the substrate 102. The first gate region 134 is located above the first gate dielectric layer 133. In particular, the first gate region 134 extends from the edge of the first drain / source region 114 and covers the first edge region of the shallow trench isolation region 132. The second gate region 136 is located above the second gate dielectric layer 135. In particular, the second gate region 136 extends from the edge of the second drain / source region 124 and covers the second edge region of the shallow trench isolation region 132. The third gate region 168 is located at the center of the top surface of the shallow trench isolation region 132.

[0124] Fig.19 The embodiment according to the present disclosure is shown Fig.16 A simplified cross-sectional view of a third embodiment of a load switch is shown. Fig.19 The simplified cross-section shown is similar to Fig.13 The simplified cross-section shown is similar except that the third and fourth gates have been merged into a single gate.

[0125] like Fig.19 As shown, the third gate region 168 is formed between the first gate region 134 and the second gate region 136. The LOCOS structure 132 is formed over the substrate 102. The lower portion of the LOCOS structure 132 is located below the top surface of the drain / source region (e.g., 114), and the upper portion of the LOCOS structure 132 is located above the top surface of the drain / source region (e.g., 114).

[0126] A first gate dielectric layer 133 is formed between the LOCOS structure 132 and the first drain / source region 114. A second gate dielectric layer 135 is formed between the LOCOS structure 132 and the second drain / source region 124. A first gate region 134 is formed on the first gate dielectric layer 133 and the first sidewall of the LOCOS structure 132. A second gate region 136 is formed on the second gate dielectric layer 135 and the second sidewall of the LOCOS structure 132. A third gate region 168 is formed on top of the LOCOS structure 132. Fig.19 As shown, the third gate region 168 is located at the center of the top surface of the LOCOS structure 132 .

[0127] Fig. 20 The method for controlling the Fig.16A flow chart of a load switch method is shown. Fig. 20 The flowchart shown is only an example and should not unduly limit the scope of the claims. Many variations, substitutions, and modifications will be apparent to those skilled in the art. For example, Fig. 20 The various steps shown may be added, removed, substituted, rearranged and repeated.

[0128] Return to reference Fig.16 , the common drain transistor includes two N-type transistors connected back to back. The first transistor includes a first drain D1, a first gate region G1, and a first source S1. The second transistor includes a second drain D2, a second gate region G2, and a second source S2. In addition, the first transistor and the second transistor share a third gate region G3. The drains of the two N-type transistors are directly connected to each other, such as Fig.16 shown. Fig.16 The back-to-back connected N-type transistors shown can be used as a load switch. The load switch can achieve bidirectional current blocking. In addition, the load switch can achieve low-resistance conduction in another state (when the load switch is turned on).

[0129] In step 2002, in the off state of the load switch, the first gate region and the second gate region of the two back-to-back connected transistors are connected to a first voltage potential lower than the turn-on threshold of the two back-to-back connected transistors, and the third gate region is connected to one of the two sources of the two back-to-back connected transistors.

[0130] In step 2004, when the load switch is in the on state, the first gate region and the second gate region of the two back-to-back connected transistors are connected to a second voltage potential higher than the on-threshold of the two back-to-back connected transistors, and the third gate region is connected to a third voltage potential higher than the on-threshold of the two back-to-back connected transistors.

[0131] Fig.21 The method for driving the Fig.16 Controller 2100 of the load switch shown. Controller 2100 includes a first gate driver, a second gate driver, and a third gate driver. The first gate driver is configured to generate a first gate drive signal applied to a first gate G1 of the first transistor. The second gate driver is configured to generate a second gate drive signal applied to a second gate G2 of the second transistor. The third gate driver is configured to generate a third gate drive signal applied to a third gate G3 shared by the first transistor and the second transistor.

[0132] In operation, the first gate driver is configured to apply a first voltage potential to the first gate of the load switch in an off state of the load switch, and to apply a second voltage potential to the first gate of the load switch in an on state of the load switch. The first voltage potential is lower than a turn-on threshold of the first switch of the load switch. The second voltage potential is higher than a turn-on threshold of the first switch of the load switch.

[0133] In operation, the second gate driver is configured to apply a first voltage potential to the second gate of the load switch in the off state of the load switch, and to apply a second voltage potential to the second gate of the load switch in the on state of the load switch. The first voltage potential is lower than the turn-on threshold of the second switch of the load switch. The second voltage potential is higher than the turn-on threshold of the second switch of the load switch.

[0134] In operation, the third gate driver is configured to connect the third gate of the load switch to one of the two sources of the load switch in the off state of the load switch, and to apply a third voltage potential to the third gate of the load switch in the on state of the load switch. The third voltage potential is higher than a turn-on threshold of a first switch in the load switch of the two transistors connected back-to-back.

[0135] Although the embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0136] In addition, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, devices, methods and steps described in the specification. As can be easily understood by those skilled in the art from this disclosure, processes, machines, manufactures, material compositions, devices, methods or steps having substantially the same functions or achieving substantially the same results as the corresponding embodiments described herein can be adopted according to the present disclosure, and these processes, machines, manufactures, material compositions, devices, methods or steps may be currently existing or developed in the future. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, devices, methods or steps within their scope.

Claims

1. A device, characterized in that include: A first drain / source region and a second drain / source region located above the substrate; a first gate region adjacent to the first drain / source region, a second gate region adjacent to the second drain / source region, and a third gate region located between the first gate region and the second gate region; as well as a high voltage oxidation region located above the substrate; or a shallow trench isolation (STI) region located above the substrate; or a local oxide of silicon (LOCOS) structure, a lower portion of which is located below a top surface of the first drain / source region and an upper portion of which is located above the top surface of the first drain / source region, The first drain / source region, the second drain / source region, the first gate region, the second gate region and the third gate region form two transistors connected back to back, The first gate region and the second gate region are located above the same high voltage oxidation region or the shallow trench isolation region or the local silicon oxide structure.

2. The device according to claim 1, characterized in that Also includes: a fourth gate region located between the first gate region and the second gate region; a first gate dielectric layer formed between the high voltage oxidation region and the first drain / source region; and A second gate dielectric layer is formed between the high voltage oxidation region and the second drain / source region, wherein: The first gate region is formed on the first gate dielectric layer and the first sidewall of the high voltage oxidation region, The second gate region is formed on the second gate dielectric layer and the second sidewall of the high voltage oxidation region, and The third gate region and the fourth gate region are formed on the top of the high voltage oxidation region, and the third gate region and the fourth gate region are separated from each other.

3. The device according to claim 1, characterized in that Also includes: a fourth gate region located between the first gate region and the second gate region, wherein: The first gate region extends from the edge of the first drain / source region and covers the first edge region of the shallow trench isolation region, The second gate region extends from an edge of the second drain / source region and covers a second edge region of the shallow trench isolation region, and The third gate region and the fourth gate region are formed on top of the shallow trench isolation region, and the third gate region and the fourth gate region are separated from each other.

4. The device according to claim 1, characterized in that Also includes: a fourth gate region located between the first gate region and the second gate region; a first gate dielectric layer formed between the local silicon oxide structure and the first drain / source region; as well as A second gate dielectric layer is formed between the local silicon oxide structure and the second drain / source region, wherein: The first gate region is formed on the first gate dielectric layer and the first sidewall of the local silicon oxide structure, The second gate region is formed on the second gate dielectric layer and the second sidewall of the local silicon oxide structure, and The third gate region and the fourth gate region are formed on the top of the local silicon oxide structure, and the third gate region and the fourth gate region are separated from each other.

5. The device according to claim 1, characterized in that Also includes: a first gate dielectric layer formed between the high voltage oxidation region and the first drain / source region; and A second gate dielectric layer is formed between the high voltage oxidation region and the second drain / source region, wherein: The first gate region is formed on the first gate dielectric layer and the first sidewall of the high voltage oxidation region, The second gate region is formed on the second gate dielectric layer and the second sidewall of the high voltage oxidation region, and The third gate region is located at the center of the top surface of the high voltage oxidation region.

6. The device according to claim 1, characterized in that in: The first gate region extends from the edge of the first drain / source region and covers the first edge region of the shallow trench isolation region, The second gate region extends from an edge of the second drain / source region and covers a second edge region of the shallow trench isolation region, and The third gate region is located at the center of the top surface of the shallow trench isolation region.

7. The device according to claim 1, characterized in that Also includes: a first gate dielectric layer formed between the local silicon oxide structure and the first drain / source region; as well as A second gate dielectric layer is formed between the local silicon oxide structure and the second drain / source region, wherein: The first gate region is formed on the first gate dielectric layer and the first sidewall of the local silicon oxide structure, The second gate region is formed on the second gate dielectric layer and the second sidewall of the local silicon oxide structure, and The third gate region is located at the center of the top surface of the local silicon oxide structure.

8. The device according to claim 1, characterized in that The first drain / source region serves as a first source of the two back-to-back connected transistors; and The second drain / source region serves as a second source of the two back-to-back connected transistors.

9. A method, characterized in that include: In an off state of the load switch, the load switch comprises two transistors connected back to back, connecting first gate regions and second gate regions of the two transistors connected back to back to a first voltage potential lower than a turn-on threshold of the two transistors connected back to back, and connecting the third gate region to first sources of the two transistors connected back to back; as well as In the on-state of the load switch, the first gate region and the second gate region of the two back-to-back connected transistors are connected to a second voltage potential higher than a turn-on threshold of the two back-to-back connected transistors, and the third gate region is connected to a third voltage potential higher than a turn-on threshold of the two back-to-back connected transistors, Among the two transistors connected back to back, the first gate region and the second gate region are located above the same high-voltage oxidation region.

10. The method according to claim 9, characterized in that Also includes: In the off state of the load switch, connecting the fourth gate region to the second sources of the two back-to-back connected transistors; as well as In the on-state of the load switch, the fourth gate region is connected to the third voltage potential, wherein the two back-to-back connected transistors include: A first source electrode and a second source electrode are disposed on the substrate; the first gate region adjacent to the first source; the second gate region adjacent to the second source; the high voltage oxidation region located above the substrate; a first gate dielectric layer formed between the high voltage oxidation region and the first source; and A second gate dielectric layer is formed between the high voltage oxidation region and the second source, wherein: The first gate region is formed on the first gate dielectric layer and the first sidewall of the high voltage oxidation region, The second gate region is formed on the second gate dielectric layer and the second sidewall of the high voltage oxidation region, and The third gate region and the fourth gate region are formed on the top of the high voltage oxidation region, and the third gate region and the fourth gate region are separated from each other.

11. The method according to claim 9, characterized in that Also includes: In the off state of the load switch, connecting the fourth gate region to the second sources of the two back-to-back connected transistors; as well as In the on-state of the load switch, the fourth gate region is connected to the third voltage potential, wherein the two back-to-back connected transistors include: A first source electrode and a second source electrode are disposed on the substrate; a first gate region adjacent to the first source; a second gate region adjacent to the second source; A shallow trench isolation region located above the substrate; wherein: The first gate region extends from an edge of the first source and covers a first edge region of the shallow trench isolation region. The second gate region extends from an edge of the second source and covers a second edge region of the shallow trench isolation region, and The third gate region and the fourth gate region are formed on top of the shallow trench isolation region, and the third gate region and the fourth gate region are separated from each other.

12. The method according to claim 9, characterized in that Also includes: In the off state of the load switch, connecting the fourth gate region to the second sources of the two back-to-back connected transistors; as well as In the on-state of the load switch, the fourth gate region is connected to the third voltage potential, wherein the two back-to-back connected transistors include: A first source electrode and a second source electrode are disposed on the substrate; a first gate region adjacent to the first source; a second gate region adjacent to the second source; a local oxide of silicon (LOCOS) structure, a lower portion of which is located below a top surface of the first source and an upper portion of which is located above the top surface of the first source; a first gate dielectric layer formed between the local silicon oxide structure and the first source; and A second gate dielectric layer is formed between the local silicon oxide structure and the second source, wherein: The first gate region is formed on the first gate dielectric layer and the first sidewall of the local silicon oxide structure, The second gate region is formed on the second gate dielectric layer and the second sidewall of the local silicon oxide structure, and The third gate region and the fourth gate region are formed on the top of the local silicon oxide structure, and the third gate region and the fourth gate region are separated from each other.

13. The method according to claim 9, characterized in that A voltage coupled to the first source of the two back-to-back connected transistors is lower than a voltage coupled to the second source of the two back-to-back connected transistors.

14. The method according to claim 9, characterized in that The third gate region is formed above the dielectric region, and the dielectric region is located between the first source and the second source of the two back-to-back connected transistors; The first source and the second source are symmetrically arranged with respect to the dielectric region; and The third gate region is located at the center of the top surface of the dielectric region.

15. The method according to claim 9, characterized in that In the on-state of the load switch, the first gate region and the second gate region of the two back-to-back connected transistors are connected to the second voltage potential higher than the on-threshold of the two back-to-back connected transistors before the third gate region is connected to the third voltage potential higher than the on-threshold of the two back-to-back connected transistors.

16. The method according to claim 9, characterized in that In the off state of the load switch, the third gate region is connected to the first source of the two back-to-back connected transistors before the first gate region and the second gate region of the two back-to-back connected transistors are connected to the first voltage potential lower than the turn-on threshold of the two back-to-back connected transistors.

17. A controller, characterized in that: include: a first gate driver configured to apply a first voltage potential to a first gate region of the load switch in an off state of the load switch, and to apply a second voltage potential to the first gate region of the load switch in an on state of the load switch, wherein the first voltage potential is lower than a turn-on threshold of the first switch of the load switch, and the second voltage potential is higher than a turn-on threshold of the first switch of the load switch; a second gate driver configured to apply the first voltage potential to a second gate region of the load switch in the off state of the load switch, and to apply the second voltage potential to the second gate region of the load switch in the on state of the load switch; and a third gate driver configured to connect a third gate region of the load switch to the first source of the load switch in the off state of the load switch, and to apply a third voltage potential to the third gate region of the load switch in the on state of the load switch, wherein the third voltage potential is higher than a turn-on threshold of the first switch of the load switch, Wherein, in the load switch, the first gate region and the second gate region are located above the same dielectric region.

18. The controller according to claim 17, characterized in that Also includes: A fourth gate driver is configured to connect the fourth gate region of the load switch to the second source of the load switch in the off state of the load switch, and to apply the third voltage potential to the fourth gate region of the load switch in the on state of the load switch.

19. The controller according to claim 18, characterized in that The load switch comprises two transistors connected back to back; The first source and the second source are symmetrically arranged with respect to the dielectric region, and the dielectric region is formed between the first source and the second source; and The first gate region and the second gate region are symmetrically arranged relative to the dielectric region.

20. The controller according to claim 19, characterized in that The first gate region is formed above a first sidewall of the dielectric region; The second gate region is formed on a second sidewall of the dielectric region; and The third gate region and the fourth gate region are formed on the dielectric region, and the third gate region and the fourth gate region are separated from each other.

21. A device, characterized in that include: A first drain / source region and a second drain / source region located above the substrate; a first gate region adjacent to the first drain / source region, and a second gate region adjacent to the second drain / source region; as well as a high voltage oxidation region located above the substrate, The first drain / source region, the second drain / source region, the first gate region and the second gate region form two transistors connected back to back, The first gate region and the second gate region are located above the same high voltage oxidation region.

22. The device according to claim 21, characterized in that Also includes: The first drain / source region serves as a first source of the two back-to-back connected transistors; as well as The second drain / source region serves as a second source of the two back-to-back connected transistors.

23. The device according to claim 21, characterized in that Also includes: An epitaxial layer of a first conductivity type, located above the substrate of the first conductivity type; A drift layer of a second conductivity type, located above the epitaxial layer; A first body region of a first conductivity type is formed in the drift layer, and the first drain / source region is formed in the first body region and has a second conductivity type; A second body region of a first conductivity type is formed in the drift layer, and the second drain / source region is formed in the second body region and has a second conductivity type; a first gate dielectric layer formed between the high voltage oxidation region and the first drain / source region; and A second gate dielectric layer is formed between the high voltage oxidation region and the second drain / source region.

24. The device according to claim 23, characterized in that The first conductivity type is P type; and The second conductivity type is N type.

25. The device according to claim 23, characterized in that Also includes: a first body contact region formed in the first body region; as well as a second body contact region formed in the second body region, wherein: The first body contact region is coupled to the first drain / source region through a first source contact; and The second body contact region is coupled to the second drain / source region through a second source contact.

26. The device according to claim 23, characterized in that The first drain / source region and the second drain / source region are arranged symmetrically with respect to a center line passing through the high voltage oxidation region; and The first gate and the second gate are arranged symmetrically with respect to the center line passing through the high voltage oxidation region.

27. The device according to claim 21, characterized in that Also includes: An epitaxial layer of a first conductivity type, located above the substrate of the first conductivity type; A drift layer of a second conductivity type, located above the epitaxial layer; A first body region of a first conductivity type is formed in the drift layer, and the first drain / source region is formed in the first body region and has a second conductivity type; A second body region of a first conductivity type is formed in the drift layer, and the second drain / source region is formed in the second body region and has a second conductivity type; a first gate dielectric layer formed below the first gate region; and A second gate dielectric layer is formed below the second gate region.

28. The device according to claim 21, characterized in that Also includes: An epitaxial layer of a first conductivity type, located above the substrate of the first conductivity type; A well region of a second conductivity type, located above the epitaxial layer, wherein the first drain / source region and the second drain / source region are formed in the well region and have the second conductivity type; a first gate dielectric layer formed below the first gate region; and A second gate dielectric layer is formed below the second gate region.

29. A method, characterized in that include: growing an epitaxial layer of a first conductivity type over a substrate of the first conductivity type; forming a drift layer of a second conductivity type above the epitaxial layer; forming a first body region and a second body region of a first conductivity type in the drift layer; Performing ion implantation of a second conductivity type to form a first source region in the first body region and a second source region in the second body region; forming a first gate region adjacent to the first source region and a second gate region adjacent to the second source region, wherein the first source region and the second source region are located at opposite sides of the first gate region and the second gate region, respectively; and forming a high voltage oxidation region above the drift layer, wherein the first gate region and the second gate region are located above the same high voltage oxidation region; or forming a shallow trench isolation (STI) region in the drift layer, wherein the first gate region and the second gate region are located above the same shallow trench isolation region; or A local oxide of silicon (LOCOS) structure is formed, a lower portion of which is located in the drift layer and an upper portion of which is located above the drift layer, and the first gate region and the second gate region are located above the same local oxide of silicon structure.

30. The method according to claim 29, characterized in that Also includes: forming the first gate region along the edge of the first source region, the first gate region covering the first side wall and the first edge portion of the high voltage oxidation region; as well as The second gate region is formed along the edge of the second source region, and the second gate region covers the second side wall and the second edge portion of the high voltage oxidation region.

31. The method according to claim 30, characterized in that The first source region, the first gate region, the second source region, and the second gate region form a common drain transistor; and An active region of the common drain transistor is orthogonal to the high voltage oxide region.

32. The method according to claim 29, characterized in that Also includes: forming a gate dielectric layer from an edge of the first source region to an edge of the second source region; forming a first gate region covering a first edge portion of the gate dielectric layer; as well as A second gate region is formed covering a second edge portion of the gate dielectric layer.

33. The method according to claim 29, characterized in that Also includes: forming a first gate region extending from an edge of the first source region and covering a first edge region of the shallow trench isolation region; A second gate region is formed extending from an edge of the second source region and covering a second edge region of the shallow trench isolation region.

34. The method according to claim 29, characterized in that Also includes: forming a first gate region along an edge of the first source region, wherein the first gate region covers a first sidewall and a first edge portion of the local silicon oxide structure; as well as A second gate region is formed along an edge of the second source region, wherein the second gate region covers a second sidewall and a second edge portion of the local silicon oxide structure.

35. The method according to claim 29, characterized in that Also includes: Forming multiple source regions; as well as A plurality of body contact regions are formed, wherein the plurality of source regions and the plurality of body contact regions are alternately arranged.

36. The method according to claim 35, characterized in that Also includes: A plurality of contacts are formed over the plurality of source regions and the plurality of body contact regions, wherein at least one of the contacts couples a source region and an adjacent body contact region.

37. A load switch, characterized in that: include: a first transistor; as well as a second transistor connected back-to-back with the first transistor, wherein: A source of the first transistor and a source of the second transistor are formed above a substrate; The gate of the first transistor is adjacent to the source of the second transistor; and The gate of the second transistor is adjacent to the source of the first transistor, wherein the gate of the first transistor and the gate of the second transistor are separated from each other, A high voltage oxidation region or a shallow trench isolation region or a local silicon oxide structure is arranged between the source of the first transistor and the source of the second transistor, and the gate of the first transistor and the gate of the second transistor are located above the same high voltage oxidation region or the shallow trench isolation region or the local silicon oxide structure.

38. The load switch according to claim 37, characterized in that: Also includes: an epitaxial layer located above the substrate; a drift layer located above the epitaxial layer; as well as A first body region and a second body region located in the drift layer, wherein: The gate of the first transistor covers a first sidewall and a first edge portion of the high voltage oxidation region; and The gate of the second transistor covers the second side wall and the second edge portion of the high voltage oxidation region.

39. The load switch according to claim 37, characterized in that: Also includes: an epitaxial layer located above the substrate; a drift layer located above the epitaxial layer; as well as and a first body region and a second body region located in the drift layer; wherein: The gate of the first transistor extends from an edge of the source of the first transistor and covers a first edge region of the shallow trench isolation region; The gate of the second transistor extends from an edge of the source of the second transistor and covers a second edge region of the shallow trench isolation region.

40. The load switch according to claim 37, characterized in that: Also includes: an epitaxial layer located above the substrate; a drift layer located above the epitaxial layer; as well as and a first body region and a second body region located in the drift layer; wherein: The gate of the first transistor is along an edge of the source of the first transistor, wherein the gate of the first transistor covers a first sidewall and a first edge portion of the local silicon oxide structure; and The gate of the second transistor is along an edge of the source of the second transistor, wherein the gate of the second transistor covers a second sidewall and a second edge portion of the local silicon oxide structure.

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