Access command delay using delay locked loop (DLL) circuitry

Abstract

This application relates to access command delay using delay-locked loop (DLL) circuitry. A memory device can have a memory array and a delay-locked loop (DLL) circuit that adjusts signals associated with access operations of the memory array. The memory device can also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the DLL circuit. This can cause the access command to be delayed a first duration when output from the delay circuitry. The delay of the access command can align a data signal with the access command so that the access command and a system clock can cause a proper data of the data signal to be latched.

Description

Technical Field

[0001] This disclosure relates to memory, and more particularly to access command latency using a Delayed Locked Loop (DLL) circuit system. Background Technology

[0002] This section aims to introduce the reader to various aspects of the technology that may be related to the aspects described below and / or claimed in this disclosure. It is believed that this discussion will help provide the reader with background information to facilitate a better understanding of the aspects of this disclosure. Therefore, it should be understood that these statements should be read in this context and not as an endorsement of prior art.

[0003] Generally, a computing system includes a processing circuitry, such as one or more processors or other suitable components; and a memory device, such as a chip or integrated circuit. One or more memory devices may be used on memory modules, such as dual in-line memory modules (DIMMs), to store data accessible to the processing circuitry. For example, based on user input to the computing system, the processing circuitry may request a memory module to retrieve data corresponding to the user input from its memory device. In some examples, the retrieved data may contain firmware, or instructions executable by the processing circuitry to perform an operation, and / or may contain data that will be used as input to said operation. Additionally, in some cases, data output from said operation may be stored in memory, for example, so that the data can be retrieved from said memory later.

[0004] Some memory devices include memory cells that can be accessed by turning on transistors that couple the memory cells (e.g., capacitors) to word lines or bit lines. In contrast, threshold-type memory devices include those accessed by providing a voltage across the memory cells, where data values ​​are stored based on a threshold voltage of the memory cells. For example, the data value may be based on whether it exceeds the threshold voltage of the memory cell, and the memory cell conducts current in response to the voltage provided across the memory cell. The stored data value may be changed, for example, by applying a voltage sufficient to change the threshold voltage of the memory cell. An example of a threshold-type memory cell may be a crosspoint memory cell.

[0005] In the case of threshold-type memories, word lines and bit lines are used to transmit selection signals to the corresponding memory cells. The selection signals may include signals characterized by voltage levels used to store data in or retrieve data from a memory cell. Word lines and bit lines may be coupled to the selection signal source via drivers. Memory cells may be organized into one or more layers of memory cells, such as layers defined between overlapping word lines and bit lines. These layers may be referred to as stacks (e.g., memory stacks). Various combinations of word lines, bit lines, and / or decoders may be referenced for specific memory operations using addresses (e.g., memory addresses). An address may indicate which memory cell will be selected using a combination of signals from the word lines, bit lines, and / or decoders, and a specific value of the address may be based on a range of addresses for the memory device.

[0006] The controller accesses memory cells to obtain the stored voltage, which can be interpreted as data. Access operations may include read and write operations. When accessing memory, different clock domains may be used, such as a clock domain (e.g., a global or system timing domain) and a data strobe or data clock (DQS) domain. Sometimes signals are exchanged between different clock domains, and sometimes the exchanged signals are re-tied between different clock domains. For example, data being input to a memory cell may be timed to the DQS domain. A write command requesting data to be written to a memory cell may be timed to the clock domain, and therefore timed and / or latched using the clock domain. However, timing based on the clock domain may result in a timing difference relative to the DQS domain. Summary of the Invention

[0007] One aspect of this disclosure provides an apparatus comprising: a plurality of access lines arranged in a grid; a plurality of memory cells located at intersections of the access lines in the grid; a driver configured to transmit a corresponding signal to a memory cell among the plurality of memory cells in response to an access command; and a delay-locked loop (DLL) circuit configured to delay the access command for a first duration in response to a result from a phase detection operation.

[0008] Another aspect of this disclosure provides a method comprising: receiving a reference clock signal and a data reference signal at a phase detector; determining a phase difference between transitions of the reference clock signal and the data reference signal; transmitting a control signal from the phase detector to a delay line based at least in part on the phase difference; and delaying an access command using the delay line in response to the control signal.

[0009] Another aspect of this disclosure provides a memory device comprising: a memory array; a delay-locked loop (DLL) circuit configured to adjust one or more signals associated with an access operation of the memory array; and a controller configured to: detect a phase difference between a data reference signal and a clock reference signal using the DLL circuit; adjust a delay circuit system of the DLL circuit at least in part based on the phase difference; delay an access command at least in part by transmitting an access command via the delay circuit system, wherein the access command is delayed for a first duration at an output from the delay circuit system; and operate a latch after transmitting the access command via the delay circuit system to capture the value of a data signal on an edge of a clock reference signal configured to align with an edge of the access command. Attached Figure Description

[0010] A better understanding of the various aspects of this disclosure can be achieved by reading the following detailed description and referring to the figures, in which:

[0011] Figure 1 This is a simplified block diagram illustrating certain features of a memory device according to embodiments of the present disclosure;

[0012] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 2 An orthogonal view of a portion of the memory array diagram;

[0013] Figure 3 This is a timing diagram illustrating a comparison of the timing of a system clock (CLK) signal, a first possible timing of a data clock (DQS) signal, a second possible timing of a data clock (DQS) signal, and the timing of an access command expected to be aligned with the rising edge of the CLK signal and having a specific amount of overlap with the DQS signal, according to embodiments of the present disclosure; and

[0014] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 1 A block diagram of a delay-locked loop (DLL) circuitry system for a memory device, the DLL circuitry system being configured to delay access commands (e.g., write commands) by an amount substantially similar to a reference clock (CLKref) signal when generating timing signals associated with one or more data (DQ) pins. Detailed Implementation

[0015] One or more specific embodiments will be described below. To provide a concise description of these embodiments, not all features of the actual implementation are described in the specification. It should be understood that, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints that can vary from one implementation to another. Furthermore, it should be understood that such development attempts can be complex and time-consuming, but remain customary practices for design, fabrication, and manufacturing by those skilled in the art who benefit from this disclosure.

[0016] Memory typically comprises an array of memory cells, each of which is coupled between at least two access lines. For example, a memory cell may be coupled to access lines such as bit lines and word lines. Each access line may be coupled to a large number of memory cells. To select a memory cell, one or more drivers may provide selection signals (e.g., voltage and / or current) on the access lines to access the memory cell's storage capacity. By applying voltage and / or current to the corresponding access line, the memory cell can be accessed to write data to and / or read data from the memory cell. Access commands (e.g., read commands, write commands) can be used to generate the selection signals, for example, by indicating which memory cells to read and / or write.

[0017] When reading from or writing data to a memory cell, the data can cross time domains (e.g., between the storage time domain and the device time domain). In practice, the memory cell can operate according to a data strobe or data clock signal (DQS signal), and the device can operate according to a system clock signal (e.g., a clock signal). When writing to and / or reading data from a memory cell, the data can be timed according to the time domain it is entering, as a way of converting the timing of the data to the desired time domain. For example, when writing data to a memory cell, it may be necessary to align the phase of the data to be stored and the corresponding write command with the phase of the data leaving the memory cell.

[0018] Alignment of timing transitions between time domains allows for latching access command information for further use and / or transmission. In practice, when these signals are substantially aligned, the clock arriving at the clock input can overlap with the corresponding data arriving at the data input, where the data arriving at the data input can be latched by the data clock arriving at the data clock input. The arrival time of each signal at each of the clock and data clock inputs can be determined and used to determine the amount of timing offset to improve alignment. However, these inputs can be arranged relatively spaced apart on the integrated circuit. In practice, upon receiving information about the timing difference associated with the current access command, the control system may not be able to adjust the timing difference between the data clock and the clock used to adjust the current access command (e.g., the adjustment may be delayed by one or more timing cycles). Although it may not be possible to perform timing difference adjustment at the clock pad and / or in response to signals received at the clock pad, a delay-locked loop (DLL) can be used to compensate for the timing difference.

[0019] Specifically, the DLL circuitry is operable to align timing signals with data transmitted throughout the device. To improve timing alignment of transmitted commands between the storage time domain and the device time domain, the DLL circuitry can also be used to transmit access command signals (e.g., read command signals, write command signals) such that the access commands experience the same process delay as the signals in the storage time domain and / or device time domain, thereby allowing for easier alignment with the other in the time domain. In practice, the DLL can align internal signals to the device time domain before they are transmitted into the device from external circuitry (e.g., circuitry outside the core of the device, signals from memory). Access command signals are transmitted via the DLL circuitry (e.g., similar DLL circuitry transmitted in parallel with another DLL circuitry, identical DLL circuitry, at least partially shared DLL circuitry), with the access command signals used for the same clock latch for timing data, where both are modified with the same or substantially similar delays (e.g., delays from changes in voltage and / or temperature). It should be noted that this disclosure refers to three-dimensional cross-point memories and / or threshold memories in discussing systems and methods, as these types of memories, for example, can experience the specific timing differences described herein. However, different types of memory can benefit from implementations of systems and methods used to perform timing alignment operations between the signal and the DQS clock signal.

[0020] Remember the above introduction, Figure 1 This is a block diagram of a portion of memory device 90. Memory device 90 may also be referred to as an electronic memory device. Figure 1 This is an illustrative representation of the various components and features of the memory device 90. Thus, it should be understood that the components and features of the memory device 90 are shown to illustrate their functional interrelationships, not their actual physical locations within the memory device 90. Figure 1 In an illustrative example, memory device 90 includes a three-dimensional (3D) memory array 92. The 3D memory array 92 includes memory cells 94 programmable to store different states. In some instances, each memory cell 94 is programmable to store two states (e.g., voltages having voltage levels indicating or interpretable as a certain value), represented as logic 0 and logic 1. In some instances, memory cells 94 may be configured to store more than two logic states. Although Figure 1 Some of the elements contained are marked with numerical indicators, while other corresponding elements are not marked, but they are the same or will be understood as similar, in order to increase the visibility and clarity of the depicted features.

[0021] 3D memory array 92 may comprise two or more two-dimensional (2D) memory stacks 98 formed by stacking one another (e.g., stack 98B disposed on stack 98A). Compared to 2D arrays, this can increase the number of memory cells that can be placed or created on a single die or substrate (e.g., increasing the density of memory cells 94), thereby reducing manufacturing costs or improving the performance of the memory device, or both. Memory array 92 may comprise two levels of memory cells 94 and can therefore be considered a 3D memory array; however, the number of levels is not limited to two. Each level may be aligned or positioned such that memory cells 94 can be aligned (specifically, overlapped, or substantially aligned) with each other across each level, thereby forming memory cell stack 100. In some cases, memory cell stack 100 may comprise multiple memory cells 94 stacked one another and simultaneously sharing access lines for both, as described below. In some cases, memory cells 94 may be multi-level memory cells configured to store more than one data bit using multi-level memory technology.

[0022] In some instances, each row of memory cells 94 is connected to word lines 102, and each column of memory cells 94 is connected to bit lines 104, generally forming a grid. The term access line can refer to word lines 102, bit lines 104, or a combination thereof. Word lines 102 and bit lines 104 can be perpendicular (or nearly perpendicular) to each other, creating an array of memory cells 94. Figure 1As shown, two memory cells 94 in memory cell stack 100 may share a common conductive line, such as bit line 104. That is, bit line 104 may be coupled to the bottom electrode of the upper memory cell 94 and the top electrode of the lower memory cell 94. Other configurations are possible; for example, a third stack may share word line 102 with the lower stack. Generally, a memory cell 94 may be located at the intersection of two conductive lines, such as word line 102 and bit line 104. This intersection may be referred to as the address of the memory cell. The target memory cell 94 may be the memory cell 94 located at the intersection of the activated word line 102 and bit line 104, that is, word line 102 and bit line 104 may be activated to read or write memory cell 94 at their intersection. Other memory cells 94 coupled (e.g., connected) to the same word line 102 or bit line 104 may be referred to as non-target memory cells 94.

[0023] Electrodes may be coupled to memory cell 94 and word line 102 or bit line 104. The term electrode can refer to an electrical conductor and, in some cases, can serve as an electrical contact to memory cell 94. Electrodes may comprise traces, wires, conductive lines, conductive materials, etc., providing a conductive path between elements or components of memory device 90. In some instances, memory cell 94 may comprise a chalcogenide material positioned between a first electrode and a second electrode. One side of the first electrode may be coupled to word line 102, and the other side of the first electrode may be coupled to the chalcogenide material. Additionally, one side of the second electrode may be coupled to bit line 104, and the other side of the second electrode may be coupled to the chalcogenide material. The first and second electrodes may be the same material (e.g., carbon) or different materials.

[0024] Operations such as reading and writing can be performed on memory cell 94 by activating or selecting word line 102 and bit line 104. In some instances, bit line 104 may also be referred to as a digital line. References to access lines, word lines, and bit lines or the like may be interchanged without affecting understanding or operation. Activating or selecting word line 102 or bit line 104 may involve applying a voltage to the respective line. Word line 102 and bit line 104 may be made of conductive materials such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductive doped semiconductors or other conductive materials, alloys, compounds, etc.

[0025] Access to memory cells 94 can be controlled via row decoder 106 and column decoder 108. For example, row decoder 106 may receive a row address from memory controller 110 and activate the appropriate word line 102 based on the received row address. Similarly, column decoder 108 may receive a column address from memory controller 110 and activate the appropriate bit line 104. For example, memory array 92 may include a plurality of word lines 102 labeled WL_1 to WL_M and a plurality of bit lines 104 labeled BL_1 to BL_N, where M and N depend on the array size. Thus, by activating word lines 102 and bit lines 104 (e.g., WL_2 and BL_3), memory cells 94 at their intersection can be accessed. As discussed in more detail below, access to memory cells 94 can be controlled via row decoder 106 and column decoder 108, which may comprise one or more doped materials extending in a direction away from the surface of the substrate coupled to memory array 92.

[0026] After access, memory cell 94 can be read or sensed by sensing component 112 to determine the stored state of memory cell 94. For example, a voltage can be applied to memory cell 94 (using corresponding word lines 102 and bit lines 104), and the presence of the resulting current can depend on the applied voltage and threshold voltage of memory cell 94. In some cases, more than one voltage can be applied. Furthermore, if the applied voltage does not cause current flow, other voltages can be applied until sensing component 112 detects current. By evaluating the voltage that generates current flow, the stored logic state of memory cell 94 can be determined. In some cases, the magnitude of the voltage can be ramped up until current flow is detected. In other cases, predetermined voltages can be applied sequentially until current is detected. Similarly, current can be applied to memory cell 94, and the magnitude of the voltage used to create the current can depend on the resistance or threshold voltage of memory cell 94. In some instances, memory cell 94 can be programmed by providing electrical pulses to the cell, which may contain memory storage elements. Pulses can be provided via word line 102, bit line 104, or a combination thereof.

[0027] Sensing component 112 may include various transistors or amplifiers to detect and amplify differences in signals. The detected logic state of memory cell 94 may then be output via input / output 114 through column decoder 108. In some cases, sensing component 112 may be part of column decoder 108 or row decoder 106. Alternatively, sensing component 112 may be connected to or coupled to column decoder 108 or row decoder 106. The sensing component may be associated with either column decoder or row decoder.

[0028] Memory cell 94 can be set or written by activating the associated word line 102 and bit line 104, and at least one logic value can be stored in memory cell 94. Column decoder 108 or row decoder 106 can accept data to be written to memory cell 94, such as input / output 114. In the case of memory cells containing chalcogenide materials, memory cell 94 can be written to store a logic state in memory cell 94 as part of an access operation by applying a first voltage to memory cell 94 based on coupling a first conductive line of the decoder (e.g., row decoder 106 or column decoder 108) to an access line (e.g., word line 102 or bit line 104).

[0029] In some cases, memory device 90 may be in an idle phase; the idle phase may be, for example, a configuration with low power consumption. In some instances, memory device 90 may be in an active phase; the active phase may be, for example, a configuration in which the memory device is immediately ready to execute a received command. In some instances, memory device may be in a pulse phase; the pulse phase may be, for example, a configuration in which a command is executed during this period, such as when a target memory cell is accessed and biased to program logic state into or read logic state from a memory cell.

[0030] Based on the phases of the memory device 90 (e.g., idle phase, active phase, or pulse phase, and others), the memory controller 110 can control the operation and voltage of the memory cells 94 (e.g., read, write, rewrite, refresh, discharge, shield, float) via various components such as row decoder 106, column decoder 108, and sensing component 112. In some cases, one or more of the row decoder 106, column decoder 108, and sensing component 112 may be co-located with the memory controller 110.

[0031] The memory controller 110 can generate row and column address signals to activate the desired word line 102 and bit line 104. The memory controller 110 can also generate and control various other voltages or currents used during operation of the memory device 90. For example, the memory controller 110 can bias access lines with shield voltages (e.g., ground voltage) adjacent to the target access line and / or access lines in the same group as the addressed access lines. The memory controller 110 can also float other access lines unrelated to the addressed access lines.

[0032] Memory controller 110 may be configured to select memory cell 94 by applying a first voltage to a first conductive line of a decoder (e.g., row decoder 106 or column decoder 108). In some cases, memory controller 110 may be configured to couple the first conductive line of the decoder to an access line (e.g., word line 102 or bit line 104) associated with the memory cell 94 based on the selection of memory cell 94. Memory controller 110 may be configured to apply the first voltage to memory cell 94 at least in part based on coupling the first conductive line of the decoder to the access line.

[0033] In some instances, the memory controller 110 may be configured to apply a second voltage to a second conductive line of the decoder as part of an access operation. Applying a first voltage to the memory cell 94 may be based on applying a second voltage to the second conductive line. For example, the memory controller 110 may select the memory cell 94 based on the intersection of the first and second voltages. In some cases, the signal applied to the memory cell 94 as part of the access operation may have positive or negative polarity.

[0034] In some instances, the memory controller 110 may receive a command including instructions to perform an access operation on the memory cell 94, and identify the address of the memory cell 94 based on the received command. In some cases, applying a second voltage to a second conductive line may be based on the identified address. If the access operation is a read operation, the memory controller 110 may be configured to output a logical state stored in the memory cell 94 based on applying a first voltage to the memory cell 94. If the access operation is a write operation, the memory controller 110 may store a logical state in the memory cell 94 based on applying a first voltage to the memory cell 94.

[0035] In some instances, the memory controller 110 may modify the state of the memory device 90 based on receiving the command. For example, the memory controller 110 may implement a transition from an idle phase to an active phase based on receiving an access command. For example, the memory controller 110 may implement a transition from an active phase to a pulse phase based on receiving an access command. For example, the memory controller 110 may implement a transition from a pulse phase back to an active phase based on the completion of a pulse phase command. For example, the memory controller 110 may implement a transition from an active phase back to an idle phase based on an access counter or a time counter meeting a corresponding threshold, as will be described in detail below. For example, if the access counter and the time counter are below the corresponding threshold, the memory controller 110 may keep the memory device 90 in the active phase.

[0036] Figure 2This illustration shows a perspective view of an exemplary 3D memory array supporting a single transistor driver according to embodiments of the present disclosure. Memory array 92 may be used as a reference. Figure 1 An example of a portion of the described memory array 92. The memory array 92 may include a first array or stack 98A of memory cells positioned above a substrate 122, and a second array or stack 98B of memory cells positioned on top of the first array or stack 98A. The memory array 92 may also include word lines 102A and 102B, and bit line 104A, which may be as described in reference... Figure 1 Examples of the described word line 102 and bit line 104. The memory cells of the first stack 98A and the second stack 98B may each have one or more memory cells (e.g., memory cell 94A and memory cell 94B, respectively). Although Figure 2 Some of the elements contained are marked with numerical indicators, while other corresponding elements are not marked, but they are the same or will be understood as similar, in order to increase the visibility and clarity of the depicted features.

[0037] The memory cell 94 of the first stack 98A may include a first electrode 124A, a memory cell 94A (e.g., containing a chalcogenide material), and a second electrode 126A. Furthermore, the memory cell of the second stack 98B may include a first electrode 124B, a memory cell 94B (e.g., containing a chalcogenide material), and a second electrode 126B. In some embodiments, the memory cells of the first stack 98A and the second stack 98B may have a common conductive line, such that corresponding memory cells in each stack 98A and 98B can share a bit line 104 or a word line 102, as referenced. Figure 1 As described herein. For example, the first electrode 124B of the second stack 98B and the second electrode 126A of the first stack 98A may be coupled to bit line 104A, such that bit line 104A is shared by vertically adjacent memory cells 94. According to the teachings herein, if the memory array 92 contains more than one stack, the decoder may be located above or below each stack. For example, the decoder may be located above the first stack 98A and above the second stack 98B. In some cases, the memory cell 94 may be an instance of a phase-change memory cell or a self-selecting memory cell.

[0038] In some cases, the architecture of memory array 92 can be referred to as a cross-point architecture, where memory cells are formed at the topological cross-points between word lines and bit lines, such as... Figure 2As shown in the diagram, this crosspoint architecture can provide relatively high-density data storage at a lower manufacturing cost compared to some other memory architectures. For example, the crosspoint architecture can have memory cells with a smaller area compared to other architectures, thus allowing for increased memory cell density. For example, compared to other architectures with a memory cell area of ​​6F² (e.g., those with three-terminal selectors), this architecture can have a memory cell area of ​​4F², where F is the minimum feature size. For example, DRAM can use transistors as three-terminal devices as selectors for each memory cell and can have a larger memory cell area compared to the crosspoint architecture.

[0039] Although Figure 2 The example shows two memory stacks, but other configurations are possible. In some instances, a single memory stack of memory cells can be constructed above substrate 122, which may be referred to as a two-dimensional memory. In some instances, three or four memory stacks of memory cells can be configured in a similar manner in a three-dimensional cross-point architecture.

[0040] In some instances, one or more memory cells 94 in the memory stack may contain memory cells 94 comprising chalcogenide materials. Memory cells 94 may, for example, contain chalcogenide glasses, such as alloys of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In one instance, a chalcogenide material primarily containing selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some instances, the SAG alloy may contain silicon (Si) or indium (In), or combinations thereof, and these chalcogenide materials may be referred to as SiSAG alloys or InSAG alloys, or combinations thereof. In some instances, the chalcogenide glass may contain additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0041] In some instances, a memory cell 94 containing a chalcogenide material can be programmed to a certain logic state by applying a first voltage. By way of example and without being bound by any particular theory, when a particular memory cell 94 is programmed, the elements within the cell separate, resulting in ion migration. Depending on the polarity of the voltage applied to the memory cell, the ions may migrate toward a specific electrode. For example, in memory cell 94, ions may migrate toward the negative electrode. The memory cell 94 can then be read by applying a voltage across the cell to be sensed. The threshold voltage experienced during the read operation can be based on the distribution of ions in the memory cell 94 and the polarity of the read pulse.

[0042] In some cases, a first voltage may be applied to a first conductive line of the decoder as part of an access operation of memory cell 94. After the first voltage is applied, the first conductive line may be coupled to an access line associated with memory cell 94 (e.g., word line 102A, word line 102B, or bit line 104A). In some instances, a shielding voltage may be applied to a second conductive line of the decoder, and the second conductive line may be coupled to an access line adjacent to the addressed access line or to an access line grouped together with the addressed access line. In some instances, a floating voltage may be applied to an access line that is neither adjacent to the addressed access line nor grouped together with the addressed access line (e.g., other access lines in the same stack as the addressed access line). Figure 2 (Not shown in the image).

[0043] Recalling the foregoing, the memory controller 110 may use a clock signal when selecting a memory cell 94 to be accessed. As described above, two or more clock domains may exist within the memory device, such as a clock domain used by a computing device communicatively coupled to the memory controller 110, and a clock domain used by the memory controller 110, sensing component 112, memory array 92, etc. (e.g., components of the memory device 90). These clock domains may be misaligned relative to each other, causing access commands received from the computing device to be timed at inappropriate times, and achieving timing alignment based on signals received at the comparison input / output circuitry system can be challenging due to the relatively large proximity between the inputs described in the 3D memory array 92. To at least improve this operation, access commands may be issued via a delay-locked loop (DLL) circuitry system to align the timing of the access commands with the timing of the memory device 90. When these timings are aligned, the access command can be timed for the appropriate portion of data for reading from or writing to the memory device 90, without relying on the determination of timing misalignment between the timing of the access command and the timing of the data to be timed (e.g., the timing of the data clock (DQS) signal) to retime the access command.

[0044] To be precise, Figure 3An example timing diagram is shown, according to an embodiment of the present disclosure, comparing the timing of a system clock (CLK) signal 140 (e.g., timing of X) with two data strobe or data clock (DQS) signals 142, where DQS signal 142A represents a first timing alignment (e.g., timing of -1.27*X), and where DQS signal 142B represents a second timing alignment (e.g., timing of +1.27*X). In a given memory device 90, there may be timing variations of a threshold amount for the DQS signal permitted by the memory device 90, such as threshold amounts defined by design specifications and / or by the user. In this example, the timing variation of the threshold amount of the DQS signal 142 is the timing of the CLK signal 140 + / - 0.27 (e.g., + / - 0.27tck). The timing variation of the threshold amount is used to define how early the DQS signal 142 can be timed relative to the CLK signal 140 while still conforming to the operating standards for the memory device 90. It should be noted that any timing variation of a suitable threshold amount can be used for memory device 90, such as + / -0.50tclk, + / -0.04tclk, etc.

[0045] Given the variability of the DQS signal 142, in situations where there is no specific information about the timing of the DQS signal 142 at the time of timing (or the time used for timing), access commands such as write command signal 144 may be relatively difficult to align with the transition of the DQS signal 142. The timing of the DQS signal 142 can be obtained based on the signal received at the input pad (e.g., the input pad of input / output 114); however, the amount of time used to transmit the timing to the computing device generating the access command may cause the obtained timing to be outdated. For example, the input pad receiving the CLK signal 140 may be positioned relatively far from the input pad receiving the DQS signal 142, and therefore may be difficult to use for retiming the write command signal 144.

[0046] Another aspect to consider when considering timing alignment for operation with memory array 92 is how the timing of write command signal 144 will be aligned with the timing of DQS signal 142 to latch the data for write command signal 144. Write command signal 144 can be created from the falling edge of CLK signal 140. To latch write command signal 144 at the midpoint of command emission, a 0.5tclk set-time and a 0.5tclk hold-time can be used for DQS signal 142 to latch the value of write command signal 144. However, since DQS signal 142 can vary by + / - 0.27tclk relative to CLK signal 140 according to the specification, a set-time and hold-time of 0.23tclk may be required. A 0.23tclk set-time and hold-time can be achieved under ideal internal timing. However, due to silicon variations and temperature changes, a certain tolerance succumbs to variable material properties. Therefore, a 0.23tclk set-time and hold-time may be difficult to obtain. However, the desired 0.23tclk setting and hold time can be maintained by sending the write command signal 144 via the DLL circuitry. It should be noted that the 0.23tclk setting and hold time are referred to herein as specified instances; however, these values ​​can be adjusted for different devices, and any suitable values ​​can be used.

[0047] Figure 4 A block diagram of an analog DLL circuitry system according to an embodiment of the present disclosure is shown. The analog DLL circuitry system receives a write command signal 144 (or another access command) and delays the write command signal 144 by the same or substantially similar amount as the clock transmitted via the DLL circuitry system. The write command signal 144 may be timed by a clock received at a clock input pad 154 (e.g., a CLK pad) and received by a command decoder block 152. Input buffer circuitry systems such as an input buffer 156 and a router and buffer circuitry system 158 may be included to match the delay or to better align the write command signal 144 with a reference clock (CLKref) signal 160 (e.g., a clock reference signal). Typically, the write command signal 144 is transmitted in parallel with the CLKref signal 160 such that both experience similar amounts of degradation and delay before being output from the DLL circuitry system and / or before being latched via a latch 148 (e.g., latch circuitry). In practice, when aligned, the falling edge of the CLKref signal 160 may be aligned with the first rising edge of the write command signal 144. Furthermore, when aligned, the duration of the DQS signal 142 received at the data clock (DQS) pad 146 (between the corresponding rising edge and the subsequent falling edge) can be aligned with the 0.5tclk period of the write command signal 144 (e.g., the midpoint of the total duration for transmitting the write command signal 144), such as... Figure 3The general outline is shown in the figure. Alignment in this manner can reduce the probability that the DQS signal 142 causes the data of the access command (e.g., write command signal 144) to be latched too early or too late, thereby generally improving the quality of memory operations before the access command reaches the latch 148.

[0048] The DLL circuitry receives the CLKref signal 160 and aligns it to the phase of the data reference (DQref) signal 162 detected by the phase detector circuitry 164. To do this, the phase detector circuitry 164 detects the phase difference and / or timing difference between the CLKref signal 160 and the DQref signal 162. The phase detector circuitry 164 can use any suitable technique to detect the phase of the data signal being transmitted at the data pin (DQ pin) to / from the memory array 92. For example, the phase detector circuitry 164 can manage count indications to determine the duration between the rising edges of the DQref signal 162 corresponding to the phase of the DQref signal 162.

[0049] The delay line circuitry 166 can receive a control signal 168 from the phase detector circuitry 164. In response to (and based on) the control signal 168, the delay line circuitry 166 can delay the write command signal 144 and the CLKref signal 160 by the same amount, respectively, to correct or reduce phase difference and / or timing difference. Once delayed, the CLKref signal 160 and the write command signal 144 (now characterized by a phase shift or delay relative to the original timing of the signals, respectively) can be transmitted to the DLL clock tree 170 (e.g., DLL clock tree 170A, DLL clock tree 170B). The DLL clock tree 170A can distribute the CLKref signal 160 to one or more data drivers 172 (DQ drivers), and thus one or more data (DQ) pins 174 and input buffers 180. Thus, the DLL clock tree 170A may contain multiple transmit paths with the same or similar circuitry (e.g., logic gates, latch circuitry, etc.) to transmit signals in parallel from the delay line circuitry 166 to each of the data drivers 172.

[0050] The DLL clock tree 170B (e.g., an analog DLL clock tree) may include circuitry that matches one of the transmit paths of the DLL clock tree 170A, thereby causing the write command signal 144 transmitted via the delay line circuitry 166 to arrive at the analog data driver 176 at the same time as the CLKref signal 160 arrives at the one or more data drivers 172. The analog data driver 176 and the analog input buffer 178 may include components for matching the delay applied to the CLKref signal 160 when transmitted to the input buffer 180. For example, the analog data driver 176, the analog input buffer 178, and / or the DLL clock tree 170B may include sequentially coupled delay circuitry, inverter circuitry, flip-flops, etc., to adjust the transmit delay of the write command signal 144 by an appropriate amount to match the delay of the CLKref signal 160. In fact, the DLL clock tree 170B includes a logic circuit system configured to delay the write command signal 144 (e.g., an access command) which has already been delayed for a first duration for a second duration, the second duration corresponding to the delay applied by the DLL clock tree 170A to the CLKref signal 160 output from the delay line circuit system 166.

[0051] By aligning the write command signal 144 to the CLKref signal 160 and by subjecting both signals to the same delay (generally similar delays, within each other's threshold delay amounts), the transitions of the two signals can be aligned, thereby allowing the latching of the appropriate data value. Signal alignment enables... Figure 4 Write command signal 144 and Figure 4 The CLKref signal is aligned at 160 degrees, similar to... Figure 4 CLK signal 140 and Figure 4 The desired alignment is indicated between the write command signal 144 and the CLKref signal 160. When the timing of the write command signal 144 matches or is substantially similar to the timing of the CLKref signal 160, the desired setup and hold time can be achieved when the DQS signal 142 operates within its operating range.

[0052] It should be noted that the DLL circuitry may include a delay line circuitry 166 coupled to the DLL CLK tree 170A, data driver 172, DQ pin 174, input buffer 180, router and buffer circuitry 182, and phase detector circuitry 164. Signals from the phase detector circuitry 164 can control the delay line circuitry 166. An analog DLL circuitry included for delaying the write command signal 144 may include a delay line circuitry 166 coupled to the analog DLL CLK tree 170B, analog data driver 176, and analog input buffer 178. The delay applied to the signal via the respective components can be considered as the delay duration. The delay associated with the input buffer (tIB), the delay associated with the router and buffer circuitry 182 (tR&B), the delay associated with the DLL clock tree 170A (tTree), and the delay associated with the DQ pin 174 (tDQ) may each be fixed for a given voltage and / or temperature combination. Therefore, the adjustment of the difference between the transmission path of the CLKref signal 160 (e.g., through the DLL circuitry) and the transmission path of the write command signal 144 (e.g., through the analog DLL circuitry, an additional delay circuitry, or a delay circuitry branch) can be made via a delay (tDL) associated with the delay line circuitry 166. In this way, the change applied to the delay line circuitry 166 can compensate for the phase and / or frequency difference between the CLKref signal 160 and the write command signal 144. It should also be noted that input buffer circuitry systems such as input buffer 180, analog input buffer 178, and input buffer 184 may be included to improve the quality of the transmitted signal, for example, by resetting using a voltage for transmitting a specific data value (e.g., a logic high voltage, a logic low voltage). Sometimes, input buffer circuitry systems (e.g., input buffer 180, analog input buffer 178, input buffer 184) may be included to align the delays between the transmission paths, and thus unequal delay amounts may be introduced. For example, input buffer 180 may introduce more or less delay to CLKref signal 160 than to DQS signal 142 transmitted via input buffer 184.

[0053] In some cases, control locking can be used within the DLL circuitry. Control locking prevents the transmission of an access command (e.g., write command signal 144) via the delay line circuitry 166 when the DLL circuitry is unlocked and / or the CLKref signal 160 is still being adjusted and locked to its target phase (e.g., the phase of the DQref signal 162). When the CLKref signal 160 is locked to the target phase (e.g., when the phase detector 164 detects zero phase difference between the CLKref signal 160 and the DQref signal 162, or a phase difference less than or equal to a threshold amount), a control signal 168 from the phase detector circuitry 164 can be permitted to be transmitted to both portions of the delay line circuitry 166, and thus can be permitted to delay (e.g., adjust) the write command signal 144.

[0054] It should be noted that the “rising” and “falling” edges of the reference signals are specifically referred to herein. For ease of description, these references are made consistently relative to each other. However, it should be understood that the opposite may apply depending on the specific logic circuitry system used within the memory device 10. In practice, in actual embodiments, a rising edge may correspond to a falling edge of this disclosure.

[0055] The systems and methods described herein can be applied to both read and write commands (as described herein). To align a read command with the center of the DQS signal 142, a similar transmission via a DLL circuitry can occur, but a different latching circuitry than latch 148 can be used. Latch 148 can time the data for a write command to memory array 92. A latch used with a read command can time the data from memory array 92 that is associated with or incorporated into the read command. However, these operations can similarly benefit from alignment performed via the DLL circuitry.

[0056] The technical effects of this disclosure include systems and methods that enable memory systems to align access commands with a reference clock used to time data signals arriving at or from the memory array. Delay-locked loop (DLL) circuitry can be used to align access commands, such as write commands, with the reference clock by subjecting the access command to a circuitry used to emulate or replicate the delay applied to the reference clock as it is transmitted via a delay line, clock tree, and finally arrives at the input buffer for use. Other systems of the computing device can benefit from using DLL circuitry to delay signals to the same amount as the reference clock signal. When access commands are aligned with the reference clock signal, computing device operation is improved because the data associated with the access command can be latched at the appropriate time without further concern about timing delays between signals (e.g., latching at 0.5 tclk).

[0057] While this disclosure allows for various modifications and alternatives, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed. In fact, this disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of this disclosure as defined by the appended claims.

[0058] Referring to the techniques proposed and claimed herein, and applied to tangible objects and specific instances having practical properties, these tangible objects and specific instances demonstrate improvements to the technical field of the invention in an illustrative manner and are therefore not abstract, intangible, or purely theoretical.

Claims

1. An apparatus for memory operations, comprising: Multiple access lines are arranged in a grid; Multiple memory cells located at the intersections of the access lines in the grid; A driver configured to send corresponding signals to memory cells among the plurality of memory cells in response to an access command; as well as A command delay circuit is configured to delay the access command for a first duration based on the phase difference between the transition of a reference clock signal and a data signal from the data DQ pin.

2. The apparatus of claim 1, wherein the command delay circuit is configured to transmit a control signal to at least one additional delay line, wherein the additional delay line delays the access command for a first duration in response to the control signal, and wherein the control signal is generated based on the phase difference.

3. The apparatus of claim 1, wherein the plurality of access lines include bit lines and word lines, wherein the grid includes the plurality of memory cells disposed in the same plane as additional memory cells in one or more other parallel planes, and wherein a subset of the plurality of memory cells shares access lines among the plurality of access lines.

4. The apparatus of claim 1, further comprising a phase detector configured to perform a phase detection operation to generate the phase difference.

5. The apparatus of claim 1, further comprising a command decoder circuit configured to generate the access command in response to a change in the system clock received from the routing and buffer circuitry.

6. The apparatus of claim 1, wherein the access command includes a write command.

7. The apparatus of claim 1, wherein the access command includes a read command.

8. The apparatus of claim 1, comprising a first delay-locked loop (DLL) clock tree, wherein the first DLL clock tree includes a logic circuitry configured to delay the access command, which has already been delayed for a first duration, for a second duration.

9. The apparatus of claim 8, wherein the second duration is equal to the delay applied to the reference clock signal when a subset of components of the delay line circuit configured to delay the access command is emitted via the exclusion of the command delay circuit.

10. The apparatus of claim 9, wherein the second duration is equal to the delay associated with the operation of the second delay-locked loop DLL clock tree, the data DQ driver, the data DQ pin, and the input buffer.

11. The apparatus of claim 9, further comprising command decoder circuitry, wherein the second duration and the first duration are selected to cause a data signal arriving at the data DQ pin to be in phase with a system clock arriving at the clock CLK pad, wherein the CLK pad transmits the system clock to routing and buffer circuitry, wherein the routing and buffer circuitry is configured to delay the system clock while transmitting the system clock to the command decoder circuitry configured to transmit the access command in response to the system clock.

12. A method for memory operations, comprising: The phase detector receives a reference clock signal and a data signal from the data DQ pin. and Access commands are delayed based on the phase difference between the transitions of the reference clock signal and the data signal.

13. The method of claim 12, wherein delaying the access command includes transmitting the access command via a delay line, the delay line including a circuitry that adjusts in response to receiving a control signal on the delay line.

14. The method of claim 12, further comprising: Addressing one or more memory cells located in a memory array including crosspoint memory; as well as The access command is sent to the latch circuit to cause a write operation, wherein the write operation latches data for storage in the one or more memory cells.

15. The method of claim 12, further comprising: Determine the total delay associated with the transmission of the reference clock signal via the delay-locked loop DLL clock tree, data DQ driver, data DQ pin, input buffer, and routing and buffering circuitry; as well as The amount of latency applied to the access command is adjusted at least in part based on the total latency.

16. The method of claim 15, further comprising: The access command is transmitted from the delay line via the first data DQ driver; as well as At least in part, the first data transmission to the second data DQ driver is adjusted by transmitting the reference clock signal from the delay line via the second data DQ driver, wherein the access command transmitted via the first data DQ driver is not configured to be adjusted to any data transmission of the first data DQ driver.

17. The method of claim 12, wherein delaying the access command includes using an additional delay line arranged in parallel with the delay line to delay the clock reference signal by the same amount as the access command is delayed.

18. A memory device comprising: Memory array; Command delay circuitry configured to adjust one or more signals associated with access operations of the memory array; as well as The controller is configured to delay access commands based on the phase difference between the transition of the reference clock signal and the data signal from the data DQ pin.

19. The memory device of claim 18, wherein the controller is configured to operate a latch to emit data to the memory array in response to an access command including a write command.

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