Determining the Critical Timing Path in Superconducting Circuit Design

Abstract

A system and method are provided for determining critical timing paths in a superconducting circuit design including a Josephson junction. An example method includes providing timing information about a plurality of source terminals of at least one logic gate coupled to a first terminal of the at least one logic gate. The method further includes using a processor to determine, based on a first phase assigned to the at least one logic gate and in view of the timing information, whether the first terminal is reachable by a single-throughput quantum SFQ pulse within a predetermined time range.

Description

Background Technology

[0001] Semiconductor-based integrated circuits used in electronic devices such as digital processors include digital circuits based on complementary metal-oxide-semiconductor (CMOS) technology. However, CMOS technology is reaching its limits in terms of device size. Furthermore, the power consumption of CMOS-based digital circuits at high clock speeds is increasingly becoming a limiting factor for high-performance digital circuits and systems. For example, servers in data centers consume increasingly large amounts of power. Even when CMOS circuits are inactive, power consumption is partly a result of power loss due to energy dissipation. This is because, even when such circuits are inactive and do not consume any dynamic power, they still consume power to maintain the state of the CMOS transistors.

[0002] Another approach to using processors and related components based on CMOS technology is to use components and devices based on superconducting logic. Circuits based on superconducting logic can also be used to process quantum information such as qubits. Many superconducting logic circuits include Josephson junctions, which can be controlled using high-speed clocks or microwave signals. Such circuits can include active transmission elements, which can complicate the creation of accurate timing designs. Summary of the Invention

[0003] In one aspect, this disclosure relates to a processor-implemented method for determining critical timing paths in a superconducting circuit design, wherein the superconducting circuit design includes at least one logic gate, the at least one logic gate including at least one Josephson junction, and wherein the at least one logic gate has an assigned first phase associated with a clock signal used for clocking the at least one logic gate. The method may include: providing timing information about a plurality of source terminals of the at least one logic gate coupled to a first terminal of the at least one logic gate. The method may further include: using the processor, based on the first phase assigned to the at least one logic gate, and in view of the timing information, determining whether the first terminal is reachable by a single-through-quantum (SFQ) pulse within a predetermined time range of arrival.

[0004] In another aspect, this disclosure relates to a processor-implemented method for determining critical timing paths in a superconducting circuit design, wherein the superconducting circuit design includes a plurality of logic gates, and wherein each of the plurality of logic gates includes at least one Josephson junction. The method may include providing timing information about a plurality of source terminals associated with the plurality of logic gates. The method may further include receiving a selection of a first terminal from a plurality of terminal blocks associated with a target logic gate, the target logic gate being selected from the plurality of logic gates. The method may further include receiving an assignment of a phase to the target logic gate. The method may further include, for each of a plurality of terminal blocks: using a processor, determining whether each of the plurality of terminal blocks is reachable by a corresponding single-through-quantum (SFQ) pulse within a predetermined arrival time range; and if the first terminal block is not reachable within the predetermined arrival time range, inserting a Josephson transmission line (JTL) between the source terminal associated with the target logic gate and the first terminal block determined to be unreachable within the predetermined arrival time range; and removing the first terminal block from the plurality of terminal blocks as associated with a critical timing path after determining that the first terminal block is reachable within the predetermined arrival time range following the insertion of the JTL.

[0005] In another aspect, this disclosure relates to a system configured to determine a critical timing path in a superconducting circuit design, wherein the superconducting circuit design includes at least one logic gate, the at least one logic gate including at least one Josephson junction, and wherein the at least one logic gate has an assigned first phase associated with a clock signal used to time the at least one logic gate. The system may include a first subsystem configured to provide timing information regarding a plurality of source terminals of the at least one logic gate coupled to a first terminal of the at least one logic gate. The system may also include a second subsystem comprising a processor configured to: based on the first phase assigned to the at least one logic gate, and in view of the timing information, determine whether the first terminal is reachable by a single-through-quantum (SFQ) pulse within a predetermined time range of arrival.

[0006] In another aspect, this disclosure relates to a processor-implemented method for determining timing paths and harmonic topologies in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path, the first timing path including a first set of timing pins, and wherein a first subset of the first set of timing pins is associated with a first timing constraint group including a first timing endpoint and a second timing endpoint. The method may include using a processor to process the first timing constraint group to assign a first legal start time to the first timing endpoint and a second legal start time to the second timing endpoint. The method may further include inserting a first shadow element on the timing path, the first shadow element representing a component of a first physical connection, wherein the first shadow element precedes the first timing endpoint or follows the second timing endpoint. The method may further include resolving any changes to the first legal start time or the second legal start time caused by the insertion of the first shadow element on the timing path.

[0007] In another aspect, this disclosure relates to a processor-implemented method for determining timing paths and harmonic topologies in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path, the first timing path including a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, and wherein each of the first and second circuit components includes a Josephson junction, and wherein the first circuit component is assigned a first phase and the second circuit component is assigned a second phase. The method may include using a processor to determine a first legal start time for the first timing endpoint on the timing path, and to determine a second legal start time for the second timing endpoint on the timing path. The method may further include inserting a first shadow element on the timing path, the first shadow element representing a component of a first physical connection, wherein the first shadow element precedes the first circuit component on the timing path. The method may further include inserting a second shadow element on the timing path, the second shadow element representing a component of a second physical connection, wherein the second shadow element follows the second circuit component on the timing path. The method may further include resolving any changes to the first and second legal start times caused by the insertion of the first and second shadow elements on the timing path.

[0008] In another aspect, this disclosure relates to a system configured to determine timing paths and harmonic topologies in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path, the first timing path including a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, and wherein each circuit element in the first and second circuit components includes a Josephson junction, and wherein the first circuit component is assigned a first phase and the second circuit component is assigned a second phase. The system may include a processor and a memory including instructions. The instructions may be configured to: (1) determine a first legal start time of the first timing endpoint on the timing path and determine a second legal start time of the second timing endpoint on the timing path, (2) insert a first shadow element on the timing path, the first shadow element representing a component of a first physical connection, wherein the first shadow element precedes the first circuit component on the timing path, (3) insert a second shadow element on the timing path, the second shadow element representing a component of a second physical connection, wherein the second shadow element follows the second circuit component on the timing path, and (4) resolve any changes to the first and second legal start times caused by the insertion of the first and second shadow elements on the timing path.

[0009] This summary is provided to introduce, in a simplified form, a series of concepts further described in the following detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Attached Figure Description

[0010] This disclosure is illustrated by way of example and is not limited to the accompanying drawings, wherein the same reference numerals indicate similar elements. The elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale.

[0011] Figure 1 It is a block diagram based on an example system environment;

[0012] Figure 2 It is a block diagram based on an example object model;

[0013] Figure 3 A diagram illustrating a timing component and its relationship to an object model, based on an example;

[0014] Figure 4 The illustration shows a computing platform that can be used to implement [something related to computing]. Figure 1 The functions associated with the system environment;

[0015] Figure 5 A schematic diagram of an example logic circuit being timed, based on an example example;

[0016] Figure 6 This is a flowchart 600 based on an example method for determining the validity of timing paths in a superconducting circuit design;

[0017] Figure 7 The flowchart 700 is based on another example of a method used to determine the critical timing path and to solve for the critical timing path in a superconducting circuit design.

[0018] Figure 8 A diagram showing an example of a timing constraint group (TCG) is provided, which includes timing pins as part of the constraint group.

[0019] Figure 9 This illustrates, according to an example, the inclusion of [something] as part of a superconducting circuit design. Figure 8 A diagram of the shadow component corresponding to the TCG before or after the Timing Constraint Group (TCG);

[0020] Figure 10 It shows the direction Figure 8 A diagram illustrating the addition of active transmission elements to a TCG;

[0021] Figure 11 It is a diagram showing the timing information and phase assignments populated for other timing constraint groups, as well as additional JTLs (as needed);

[0022] Figure 12 This is to show an example based on... Figure 8 A diagram illustrating the timing changes of the head of a TCG.

[0023] Figure 13 This is shown based on an example. Figure 8 A diagram illustrating the timing variations of the remaining components of the TCG, which are the result of the solution steps;

[0024] Figure 14 This is a diagram illustrating the timing changes of other TCGs based on an example.

[0025] Figure 15 This is a flowchart based on an example method for determining timing paths and harmonic topologies in superconducting circuit design; and

[0026] Figure 16 This is a flowchart of an example method used to determine timing paths and harmonic topologies in superconducting circuit design. Detailed Implementation

[0027] The examples described in this disclosure relate to systems and methods for determining critical timing paths for superconducting circuit design. Certain other examples relate to systems and methods for determining timing paths and harmonic topologies in superconducting circuit design. Superconducting circuits can use Josephson junctions to achieve the functionality associated with the circuit. An exemplary Josephson junction may comprise two superconductors coupled via regions that impede current. These regions can be the superconductor itself, a metallic region, or a physical narrowing of a thin insulating barrier. For example, a superconductor-insulator-superconductor (SIS) type Josephson junction can be implemented as part of a superconducting circuit. As an example, a superconductor is a material that can transmit direct current (DC) without an electric field. Superconductors have a critical temperature (Tc) below which their resistance is zero. One such superconductor, niobium, has a critical temperature (Tc) of 9.3 Kelvin. Below Tc, niobium is superconducting; however, above Tc, it behaves as a resistive ordinary metal. Therefore, in an SIS type Josephson junction, the superconductor can be a niobium superconductor, and the insulator can be an Al₂O₃ barrier. In SIS-type junctions, superconducting electrons are described by quantum mechanical wave functions. The phase difference of the superconducting electron wave function between two superconductors, which varies with time, corresponds to the potential difference between the two superconductors.

[0028] Depending on the requirements, various superconducting circuits, including transmission lines, can be formed by coupling multiple Josephson junctions with inductors or other components. Microwave pulses can travel through these transmission lines under the control of at least one clock. Microwave pulses can be positive or negative, or a combination thereof. Microwave pulses can have frequencies up to 10 GHz or higher. Clocks can also have frequencies up to 10 GHz or higher.

[0029] In one example, the circuit's logic can be referred to as wave pipelined logic, and digital data can be encoded using a pair of positive and negative SFQ pulses. As an example, a logic 1 (one) bit can be encoded as a pair of SFQ pulses generated in the positive and negative phases of a sinusoidal clock. A logic 0 (zero) bit can be encoded by the absence of a positive / negative pulse pair during the clock cycle. A positive SFQ pulse can arrive during the positive portion of the clock, while a negative pulse can arrive during the negative portion. A positive SFQ pulse can arrive before the positive portion of the clock, but it will not propagate before the positive clock arrives. Similarly, a negative SFQ pulse can arrive before the negative portion of the clock, but it will not propagate before the negative pulse arrives.

[0030] Some examples also involve timing designs for superconducting circuits based on phase-mode logic (PML). These superconducting circuits can also utilize devices based on PML. In PML-based devices, a logic "1" can be encoded as a phase high, and a logic "0" can be encoded as a phase low. The transition between phase high and phase low can be triggered by a single-flux quantum (SFQ) pulse event. In phase-mode logic-based superconducting circuits, digital values ​​can be encoded as Josephson junction (JJ) phases. A high phase can indicate a logic "1," and a low phase can indicate a logic "0." Unlike wave pipelined logic encoding, these values ​​remain constant across clock cycles because no negative pulse is needed to reset the JJ phase. As an example, if a phase-mode logic superconducting circuit is powered using an AC clock with four phases, the output of the phase-mode logic circuit can remain constant across all four phases of the AC clock. In one example, the four-phase clock can be derived from two AC clock sources. The four phases of the clock can provide directionality for single-flux quantum (SFQ) pulses. Therefore, as an example, for a four-phase clock, a positive pulse can cross the leading edge of the clock from one phase to the next and arrive at the output after a one-cycle delay, while a negative pulse can follow the break of half a cycle. Other types of timing arrangements can also be used, including timing using more than four phases.

[0031] The building blocks of superconducting circuits can include various types of logic gates. Example logic gates include AND gates, OR gates, A-NAND-B (AanB) gates, and AND-OR gates. An A-NAND-B gate can have two inputs and one output (Q). Input pulse A can propagate to output Q unless input pulse B occurs first. An AND-OR gate can have two inputs and two outputs (Q1 and Q2). The first input pulse, either input pulse A or input pulse B, goes to output Q1, and the second input pulse goes to output Q2. The logical behavior of these gates can be based on the reciprocal data encoding mentioned earlier or on the phase-mode logic-based data encoding mentioned earlier.

[0032] Figure 1This is a block diagram of an example system environment 100. System environment 100 illustrates example blocks for performing methods and systems related to timing determination and phase assignment of superconducting circuits. System environment 100 may include a user interface (UI) block 110, a design block 120, a timing and phase block (TPB) 130, an object model 150, a component type system 160, and a timing library 170. UI block 110 may include code for enabling the user interface, which allows designers or other users to interact with the system. For example, UI block 110 may include code and data structures that allow users to perform actions such as determining critical paths in superconducting circuits, assigning phases, and modifying timing-related designs of superconducting circuits. Design block 120 may include at least one object that can specify design definitions related to various parameters associated with the timing-related design. For example, design block 120 may be an object specifying frequencies associated with the timing design. As another example, design block 120 may specify which timing library should be used with a superconducting circuit or a set of superconducting circuits associated with an integrated circuit.

[0033] Continue to refer to Figure 1 The TPB 130 may include a timing engine 132, timing results 134, a circuit analyzer 136, and delay determination 138. The timing engine 132 may calculate pulse propagation and timing constraints based on timing data. In this example, the output of the timing engine 132 may be a set of minimum hold times and maximum setup times for each arc between timing pins (also referred to as timing terminals) in each direction. This information may be stored as part of the timing results 134. The circuit analyzer 136 may determine the topology of the circuit being timed and store this topology for processing by the delay determination 138. The delay determination 138 may process the topology, including gates in the timing path, to determine the delays between timing pins. The delays thus determined may be stored in a lookup table or another data structure. The timing engine 132 may look up the individual delays between pins from the lookup table or another data structure and sum the results. Additionally, as described later, the timing engine 132 may provide additional information, including data related to critical timing paths, topology, paths with slack, and the number of Josephson transmission line (JTL) elements added. In this example, the timing engine 132 can be implemented as a set of callable methods that allow timing-related calculations and the generation of outputs for circuit design. High-level aspects of the timing engine 132 may include the features shown in Table 1 below:

[0034]

[0035] Table 1

[0036] Still referencing Figure 1Object model 150 may include data structures and code used to support timing-related definitions for abstracting entities (e.g., logic gates or circuits) that require timing design. Table 2 below lists examples of data structures and their illustrations.

[0037]

[0038] Table 2

[0039] Continue to refer to Figure 1 The Component Type System (CTS) 160 can be used to store data related to associated timing libraries (e.g., timing library 170). In this example, adding or changing data associated with a timing library will require a one-time reinitialization of CTS 160. Timing library 170 may include information about frequency, AC amplitude, and other parameters related to the type of logic gates associated with the design. For example, the logic gates may correspond to wave pipelined logic gates or phase-mode logic gates. In this example, the timing library may include JSON and Verilog definitions for the logic gates. These definitions may include clock-consistent rise / fall tables and signal types (return-to-zero / non-return-to-zero, etc.). In one example, these definitions may be Verilog attributes for the gates. Although... Figure 1 This diagram shows some of the blocks included as part of system environment 100, but there may be more or fewer blocks. As an example, system environment 100 may include a reporting block that can be used to generate reports about timing design. As another example, system environment 100 may include additional timing libraries that can include similar information that can be used to support superconducting circuits built to operate at different temperatures or using different manufacturing processes. Other timing libraries may be used solely for testing purposes.

[0040] Figure 2 A block diagram of an object model 200 based on an example is shown. Object model 200 is... Figure 1 An example of object model 150. Object model 200 may include timing diagram 220. In this example of the object model, a timing diagram (e.g., timing diagram 220) is shown, but timing components are not shown. Timing components and their relationship to the object model are discussed below. Figure 3 Described. In one example, timing diagram 220 can be implemented as the data structure shown in Table 3.

[0041]

[0042] Table 3

[0043] Continue to refer to Figure 2The TimingConstraintGroup 210 may include a set of connected timing constraints (e.g., timing constraint 212, timing constraint 214, and timing constraint 216). Example information contained in the data structure corresponding to the timing constraints may include: BeginTimingPin, EndTimingPin, Hold, and Setup. Therefore, in this example, the data structure may include information about the timing pin at the beginning of the timing constraint (e.g., a terminal associated with a logic gate) and the timing pin at the end of the timing constraint. The data structure may also include information about hold and setup times. Table 4 shows an example of the information included in the data structure used to implement the TimingConstraintGroup 210.

[0044]

[0045] Table 4

[0046] Still referencing Figure 2 Timing constraint group 210 may include a set of information related to timing constraints, including timing constraint 212, timing constraint 214, and timing constraint 216. Each of these timing constraints may be implemented using a data structure, and each may point to a data structure associated with a timing pin to indicate that the timing constraint is associated with that specific timing pin or that group of timing pins. Table 5 below shows an example set of information included in a data structure timing constraint.

[0047]

[0048] Table 5

[0049] Each timing pin (or timing terminal) can also have a corresponding data structure, which can include information about items such as ExtraJTL and information about what pin (or terminal) type it is. For example, each pin can be a source pin or a sink pin for a gate. Figure 2 The object model 200 shown includes timing pins: timing pins 221, 222, 223, 224, 225, 226, 227, 228, and 229, each of which can have a corresponding data structure derived from the TimingPinBase data structure. In one example, the TimingPinBase data structure may include the information shown in Table 6 below.

[0050]

[0051] Table 6

[0052] Continue to refer to Figure 2 Table 7 shows the information contained in the data structure corresponding to the source pin. In this example table, arc refers to the timing relationship between the input time and the output time of each pin.

[0053]

[0054] Table 7

[0055] As shown above, Table 8 is an example of the information contained in the data structure corresponding to the sink pin.

[0056]

[0057] Table 8

[0058] Figure 3 A block diagram of another timing object model 300 according to another example is shown. Object model 300 is Figure 1 An example of object model 150. In this example, timing diagrams and timing components are shown. In this example, [the text abruptly ends here, likely due to an incomplete sentence or a formatting error]. Figure 2 Similar data structures are used to model pins and timing constraints associated with an object model that corresponds to a circuit design including active transmission elements such as JTL. Therefore, the Timing Graph 310 can be implemented in a similar manner and with similar information as described above with respect to Table 3. Similarly, the Timing Constraint Group 320 can be implemented with information similar to that described above with respect to Table 4. In this example, the Timing Constraint Group 320 can point to a Timing Constraint Pair 330. In one example, the information included in the data structure corresponding to the Timing Constraint Pair 330 is shown in Table 9 below.

[0059]

[0060] Table 9

[0061] Continue to refer to Figure 3 Object model 300 may include timing components, including timing components 340, 350, 360, and 370, which can represent components to be timed and can be used to find relevant timing constraint groups for physically connected components in different timing graphs during the reconciliation process. These graphs are constructed using the timing components of all physically connected components on the timing path. The mapping of each graph may contain all timing components owned by that graph. Except for the header, all components on the timing path are owned by their timing graph. The header belongs to its predecessor timing graph. Figure 3The object model 300 shown includes timing pins: timing pins 342, 344, 346, 348, 362, 366 and 368, where each timing pin can have a corresponding data structure derived from TimingPinBase, as described above with respect to Table 6.

[0062] Figure 4 The computing platform 400 is shown, which can be used to implement [unclear - possibly related to computing platforms]. Figure 1 The system environment 100 is associated with the following functions. The computing platform 400 may include processor(s) 402, I / O components(s) 404, memory 406, presentation components(s) 408, sensors(s) 410, database(s) 412, networking interfaces(s) 414, and I / O ports(s) 416, which may be interconnected via bus 420. The processor(s) 402 may execute instructions or code stored in memory 406. These instructions may correspond to various algorithms described in this disclosure. Therefore, these algorithms can be implemented using a programming language and compiled into an executable file that can then be executed. The I / O components(s) 404 may include components such as a keyboard, mouse, voice recognition processor, or touchscreen. Memory 406 may be any combination of non-volatile storage devices or volatile storage devices (e.g., flash memory, DRAM, SRAM, or other types of memory). The presentation components(s) 408 may be any type of display such as LCD, LED, or other types of displays, or other types of output components including audio or haptic output components. (Multiple) sensors 410 may include audio sensors, optical sensors, or other types of sensors.

[0063] Continue to refer to Figure 4 Multiple databases 412 can be used to store timing libraries and other timing-related information. Additionally, multiple databases 412 can also store data used to generate reports related to the timing libraries. Multiple networking interfaces 414 may include communication interfaces such as Ethernet, cellular radio, Bluetooth radio, UWB radio, or other types of wireless or wired communication interfaces. Multiple I / O ports 416 can allow the computing platform 400 to communicate with the bus 420 or multiple other I / O components 404. Although... Figure 4 The computing platform 400 is shown as comprising a certain number of components arranged and coupled in a certain way, but it may also include fewer or additional components arranged and coupled differently. Furthermore, the functionality associated with the computing platform 400 may be distributed or composite, depending on the need. Moreover, it may not be necessary to implement all aspects of the computing platform 400 to implement the various methods described herein.

[0064] Figure 5A schematic diagram of an example logic circuit 500 being timed according to an example is shown. The example logic circuit 500 may include an AND gate 510 and several JTLs. The AND gate 510 may include two input terminals: ai and bi, and an output terminal: ao. JTLs 512 and 514 may be coupled to the input terminal ai, as shown below. Figure 5 As shown in the diagram. JTL 516 and JTL 518 can be coupled to input terminal bi, as shown in the diagram. Figure 5 As shown in the figure. JTL 520 can be coupled to output JTL 516. Although not shown in this figure, JTL 520 can be used to couple logic circuit 500 to (multiple) other logic circuits. JTL 524 can be coupled to output terminal ao, as shown in the figure. Figure 5 As shown in the diagram. Additional JTLs can be coupled as needed; for example, JTL 526 and JTL 528 can be coupled to JTL 524. JTL 526 and JTL 528 can be used to couple logic circuit 500 to (multiple) other logic circuits. (See diagram for reference.) Figure 5 As shown, each JTL and logic gate included in logic circuit 500 can have an initial phase assignment. This example circuit is assumed to operate with a four-phase clock, such that the phase assignments include 0 degrees, 90 degrees, 180 degrees, and 270 degrees. Logic circuits driven by clocks including fewer or more phases can also be designed. A single-through-quantum pulse can reach the input terminals of AND gate 510 via JTLs coupled to their respective input terminals. After being processed by AND gate 510, the SFQ pulse representing the logical AND value can be output via the output terminal. To ensure the correct operation of logic circuit 500, instructions corresponding to the algorithm stored in memory 406, when executed by processor(s) 402, can help the designer design the timing and phase assignment aspects of logic circuit 510. Example algorithms are shown in Table 10 below.

[0065]

[0066] Table 10

[0067] The steps shown in Table 10 can be performed for each logic gate included in the design (e.g., logic gate 510 of logic circuit 500). The steps shown in Table 10 relate to any gate G containing C bank pins. The first step may include finding the bank pin with the maximum rise time (MRT) for any arriving SFQ pulse from a set of C bank pins. In one example, the MRT can be determined by the processor performing a lookup in a table where the MRT value is stored. In step 2 of Table 10, the phase associated with the gate can be changed to P+ as needed. As an example, while the assignment of phase 0 may apply to one bank pin of the gate, it may not apply to another bank pin. In this case, the phase assigned to the gate can be increased by 90 degrees (assuming the logic circuit being designed is timed by a four-phase AC clock, where the next phase assignment is 90 degrees). If the phase assigned to the gate changes (e.g., increased by 90 degrees), the phases assigned to downstream gates and JTLs are invalidated.

[0068] Referring again to Table 10, in step 3, the target time for the selected phase assignment of T can be assigned to the logic gate. In step 4, for each bank pin, starting from a path where no JTL is inserted, the algorithm can determine whether the bank pin is reachable before time T. If the bank pin is not reachable, an additional JTL can be inserted. Therefore, if logic gate 510 is initially assigned a 90-degree phase and if the input terminal ai of logic gate 510 (one of the bank pins of the gate) is not reachable within time T (i.e., MRT is greater than T), an additional JTL can be inserted. As an example, an additional buffer (e.g., JTL 514) can be inserted into the path leading to one of the bank pins. The delay associated with the sequence of buffers to which JTLs have been added can be looked up in a lookup table. If MRT is still greater than T, the bank pin is still not reachable before time T. For a logic gate, starting with the phase of the source pin, a phase can be assigned to each buffer (e.g., each JTL). For example, if assigning a 0-degree phase to a logic gate does not work, it can be assigned a 90-degree phase.

[0069] Continuing with the algorithm description in Table 10, the CreateComponentGraph method can be used to create a component graph for the logic circuit being designed. As an example, a component graph can be created for logic circuit 500. Next, the algorithm may include calling the RunLengthChecker method, which can create different reports based on the JTL added for timing. Next, the algorithm may include calling the WithinReach method to determine if a sink pin is reachable before a target time T. If the sink pin is reachable, it can be removed from C gates. If C is empty and all sink pins associated with logic gate G have been processed, then in step 5, the critical path is identified as the last sink pin that has been removed from C. If C is not empty, then (in this example) as part of step 6, the algorithm returns to step 2. After determining the critical path, the logic gates and JTLs require phase assignment. An example algorithm for phase assignment is described in Table 11.

[0070]

[0071] Table 11

[0072] As shown in Table 11, unless already determined, the first step requires identifying the critical path for the gate being processed. Next, in step 2, phase assignments can be made to various JTLs and gates based on this critical path. As an example, as described earlier with respect to Table 10, phase assignments can be changed during critical path determination. Using these phase assignments, in step 3, a method called ArePinRelativePhasesValid is invoked to determine whether the phase assignments are valid. This method can consider the logic of the superconducting circuit, including whether the logic is wave pipeline logic or phase-mode logic.

[0073] Referring again to Table 11, the next step involves adding an additional JTL with the assigned phase to disable the constraint on the critical pin. This can change the initial phase assignment of the gate if a phase change is required or desired. Failures here include failure to route or failure to add another required JTL to meet the timing. Another failure may be related to timing exceeding the legal arrival time range (e.g., due to adding a JTL to cover a distance). The next step involves adding an additional JTL with the assigned phase to disable the non-critical pin. As an example, regarding logic circuit 500, if the sink pin corresponding to input ai is determined to be a critical path, this step involves adding an additional JTL as needed to ensure that the timing of the sink pin corresponding to input bi of AND gate 510 is correct.

[0074] Figure 6This is a flowchart 600 based on an example method for determining the validity of timing paths in a superconducting circuit design. In this example, the various steps listed as part of flowchart 600 can be... Figure 1 The timing engine 132 executes this step. Step 610 may include providing timing information regarding a plurality of source terminals of the at least one logic gate coupled to a first terminal of the at least one logic gate. In one example, this information may be provided via... Figure 1 The timing library 170 is provided.

[0075] Step 620 may include: determining, based on a first phase assigned to at least one logic gate and in light of timing information, whether a first terminal is reachable by a single-through-quantum (SFQ) pulse within a predetermined arrival time range. In this example, when the code / algorithm associated with timing engine 132 (e.g., in...) Figure 4 The code or algorithm stored in memory 406 is processed by a processor (e.g., Figure 4 When the (multiple) processors 402) execute, this step can be performed by the timing engine 132. When the timing engine 132 is loaded into memory (e.g., Figure 4 When the timing engine 132 is in the memory 406), it can access the timing library 170. As an example, the timing engine 132 can perform step 4 of the steps shown in Table 10 to determine whether the first terminal is reachable by a single-through-quantum (SFQ) pulse within a predetermined arrival time range, based on the first phase assigned to at least one logic gate and in view of the timing information. Although Figure 6 A specific number of steps are shown to be performed in a particular order, but method 600 may include more or fewer steps performed in a different order.

[0076] Figure 7 This is flowchart 700, based on another example of a method for determining critical timing paths and for solving critical timing paths in superconducting circuit design. In this example, the various steps described as part of flowchart 700 can be... Figure 1 The timing engine 132 executes this step. Step 710 may include providing timing information about multiple source terminals associated with multiple logic gates. In one example, this information may be provided via... Figure 1 The timing library 170 associated with system 100 is provided to timing engine 132.

[0077] Step 720 may include: receiving a selection of a first terminal from a plurality of terminal blocks associated with a target logic gate, the target logic gate being selected from the plurality of logic gates. In this example, when the code / algorithm associated with timing engine 132 (e.g., Figure 4The code or algorithm stored in memory 406 is processed by a processor (e.g., Figure 4 When the (multiple) processors 402) are executing, this step can be performed by the timing engine 132. In this example, the timing engine 132 can perform step 1 as shown in Table 10. Therefore, as an example, the timing engine 132 can find the bank pin with the minimum maximum rise time (MRT) in a set of C bank pins. In one example, the timing engine 132 can do this by looking up a lookup table (which can be stored in...) Figure 4 The memory (406) is searched to find the junction pin.

[0078] Step 730 may include receiving a phase assignment to the target logic gate. In this example, when the code / algorithm related to the timing engine 132 (e.g., in...) Figure 4 The code or algorithm stored in memory 406 is processed by a processor (e.g., Figure 4 When executed by the (multiple) processors 402, this step can be performed by the timing engine 132. In this example, the timing engine 132 can perform step 1 as shown in Table 10. Therefore, as an example, the timing engine 132 can assign an initial phase to the target logic gate. As an example, with respect to logic circuit 500, logic gate 510 is initially assigned a phase of 180 degrees. This phase assignment can vary based on topological changes in the design of logic circuit 500.

[0079] Step 740 may include, for each of a plurality of junction terminals: (1) determining whether each of the plurality of junction terminals is reachable by a corresponding single-through-quantum (SFQ) pulse within a predetermined arrival time range, and (2) if the first junction terminal is not reachable within the predetermined arrival time range, inserting a Josephson transmission line (JTL) between the source terminal associated with the target logic gate and the first junction terminal determined to be unreachable within the predetermined arrival time range, and removing the first junction terminal from the plurality of junction terminals as associated with a critical timing path after determining that the first junction terminal is reachable within the predetermined arrival time range following the insertion of the JTL. In this example, when the code / algorithm associated with timing engine 132 (e.g., Figure 4 The code or algorithm stored in memory 406 is processed by a processor (e.g., Figure 4 When the (multiple) processors 402) execute, this step can be performed by the timing engine 132. In this example, the timing engine 132 can perform step 4 as shown in Table 10. Although Figure 7 The method illustrates a specific number of steps performed in a particular order, but may include more or fewer steps performed in a different order.

[0080] To decompose timing pins into sets of operations that can be processed asynchronously, timing constraint groups can be formed from sets of connected timing constraints. A design can have multiple timing constraint groups. Each design can have one large timing constraint group and several smaller timing constraint groups. As mentioned earlier... Figure 2 As explained in Tables 4 and 5, timing constraint group 210 may include a collection of information related to timing constraints, including timing constraint 212, timing constraint 214, and timing constraint 216. Each item in this information may be implemented using a data structure, and each item may point to a data structure associated with a timing pin to indicate that the timing constraint is related to that specific timing pin or that group of timing pins. A timing diagram may point to a diagram of timing pins within the timing constraint group.

[0081] Timing graphs can be constructed using the timing components of all physically connected components along a timing path. Each graph has a mapping containing all the timing components it possesses. All components along a timing path, except the header, are owned by their respective timing graphs. The header is owned by its predecessor's timing graph. Table 12 provides examples of algorithms for solving and harmonic constraint groups.

[0082]

[0083] Table 12

[0084] Step 1 involves identifying the critical path and assigning phases to a set of timing endpoints associated with all constraint groups being analyzed (e.g., timing constraint groups that may be part of a timing path). In this example, timing endpoints are pins that define individual timing “runs” that can be independently timed and validated based on their timing and phase constraints. They are defined by the circuit designer and are explicit components in the circuit design. Different types of timing endpoints can be specified depending on whether the logic associated with the circuit is implemented using phase-mode logic or wave pipelined logic. For wave pipelined logic circuits or phase-mode logic circuits, the presence or absence of arcs in the library data will indicate whether a timing pin is a start or end timing endpoint. In this example, the set of timing endpoints includes timing endpoints associated with timing pins that are part of the same timing constraint group. For example, timing pins associated with logic circuit 500 may be part of the same timing constraint group. This set of timing endpoints may also include timing endpoints associated with timing constraint groups within a specific number of hops. In one example, these groups may include groups of two hops backward and one hop forward, or two hops forward and one hop backward. To analyze these timing pins, "shadow" elements can be created to represent the physically connected elements on the timing path.

[0085] Referring again to Table 12, step 2 may include reconciliation for all timing components. The winner of the reconciliation step is the value in the timing constraint group that "owns" the pin used for timing. For all timing components and tails in the path, it is their timing constraint group. For the head, it is the timing constraint group of the timing component when it is the tail. Therefore, in summary, this step may include: using the timing path of the gate to set the values ​​of other timing paths physically connected to that gate, reconciling differences in arrival time and signal propagation elements (e.g., JTL insertion).

[0086] Referring again to Table 12, step 3 includes determining if there have been any changes to the timing and phase assignments. If there have been changes, the algorithm returns to step 3. If there have been no changes, the process includes solving the timing constraint group to ensure that the timing information and phase assignments for additional components (e.g., additional JTLs) within the timing constraint group are accurate. Therefore, using the algorithm described in Table 12, iterative progress can be made towards a convergent solution where the iterations result in the timing and phase assignments being fixed and no longer requiring modification. Regarding as Figures 8-13 A sample circuit is provided to illustrate the application of the algorithm described in Table 12.

[0087] Figure 8 The diagram illustrates a circuit representing an example timing constraint group (TCG) 800, which includes timing pins as part of a constraint group that can be processed using the solving and harmonic algorithms described with respect to Table 12. The TCG 800 may include buffers 812, 814, and 816, which can be coupled to, for example... Figure 8 The input and output terminals of gate 810 are shown. From a timing analysis perspective, the TCG 800 includes three timing endpoints. The first two timing endpoints correspond to the inputs of buffers 812 and 814, and the third timing endpoint corresponds to the output of buffer 816. Timing constraint group data structures can be used to represent the relevant details of the TCG 800 timing analysis. Solving and harmonic algorithms can handle the timing design in light of timing constraints imposed by other circuits in the design. In one example, components within the depth of the three timing endpoints (referred to as shadow components) can be included as part of the analysis. Additionally, real components within the depth of the three timing endpoints can also be included as part of the analysis. This is because timing changes not only as a result of changes to shadow components but also as a result of changes to real components.

[0088] Figure 9A diagram 900 is shown including shadow components corresponding to TCGs preceding or following Timing Constraint Group (TCG) 800 as part of the superconducting circuit design. These shadow components are part of other timing constraint groups and are not timed, except that they need to be considered to solve and reconcile TCG 800. In this example, two backward timing endpoints and one forward timing endpoint are included as part of the analysis. In this example, TCG 910 may include buffers 918, 920, and 922, which, as... Figure 9 The TCG 910 is coupled and arranged as shown. It may also include logic gates 912, 914, and 916, as shown... Figure 9 The TCG 930 is coupled and arranged as shown. It may include buffers 934 and 936 and gate 932, which can be coupled and arranged as shown. Figure 9 The figures shown are coupled and arranged. Figure 9 The initial phase assignments for buffers 812 and 814 associated with the two timing endpoints are also shown. In this example, the phase assignments for both buffers 812 and 814 are 0. The first valid start time for the 0-degree phase assignments of these two timing endpoints is determined to be 13 picoseconds (ps), as shown. Figure 9 As marked in the text. In this example, the legal start time is determined based on timing constraints, which are identified based on hardware analysis of the implemented buffers and gates.

[0089] Figure 10 This is diagram 1000 illustrating the addition of an active transmission element to the TCG 800. Figure 10 In this example, the TCG 800 undergoes an initial solution step using critical path and phase assignment (this step corresponds to step 1 of the algorithm in Table 12). In this example, this step involves performing steps 1-4 as shown in Table 11 for the timing pin associated with gate 810 of the TCG 800. The result of performing these steps is the addition of active transfer elements (e.g., JTL 1012, 1014, and 1016) between buffer 812 and one input of gate 810. Additionally, JTL 1018 and 1020 are added between buffer 814 and the other input of gate 810. The phase assignment of gate 810 is also changed from 0 degrees to 90 degrees. Similarly, the phase assignment of buffer 816 is changed from 0 degrees to 90 degrees. Furthermore, the first valid start time for the 90-degree phase of buffer 816 is calculated to be 57 picoseconds (ps). In this example, changes to the timing / phase information of the TCG 800 and the insertion of additional JTLs require changes to the timing information of other timing constraint groups affected by these changes.

[0090] Figure 11This is diagram 1100 illustrating timing information and phase assignment, as well as additional JTLs (as needed) used to fill in other timing constraint groups. Therefore, in this example, TCG 910 is shown as including additional JTLs 1110, 1112, and 1114 added between gate 912 and buffer 918. Additionally, gate 912 has been assigned a valid start time of 60 ps and a phase of 180 degrees. Buffer 918 has been assigned a valid start time of 97 ps and a phase of 270 degrees. Gate 916 has been assigned a valid start time of 108 ps and a phase of 0 degrees. Furthermore, TCG 910 includes additional JTLs 1116, 1118, and 1120, which have been added between gate 914 and the input of buffer 814 of TCG 800. Gate 914 has been assigned a valid start time of 90 ps. Additional JTL pins 1122, 1124, 1126, and 1128 have been added between the output of buffer 922 and one of the bank pins of gate 914. Buffer 920 has been assigned a valid start time of 88 ps and a phase of 270 degrees, and buffer 922 has been assigned a valid start time of 51 ps and a phase of 90 degrees.

[0091] Continue to refer to Figure 11 The TCG 930 is shown with additional JTLs 1132 and 1134. Gate 932 has been assigned a legal start time of 89 ps and a phase of 270 degrees. Buffer 934 has been assigned a legal start time of 60 ps and a phase of 90 degrees. Buffer 936 has been assigned a legal start time of 75 ps and a phase of 180 degrees. For the TCG 930, timing and phase assignments can be determined in a similar manner to those for the TCG 800.

[0092] Figure 12 This is a diagram 1200 illustrating the timing changes in the header of an example TCG 800. Thus, in this example, the legal start time of buffer 812 has been changed from 13 ps to 18 ps, and the legal start time of buffer 814 has been changed from 13 ps to 16 ps. These timing changes can be determined as part of a harmonic reconciliation step (e.g., step 3 of the algorithm in Table 12). Next, the timing and phase information associated with the remaining components—gate 810 and buffer 816 in the TCG 800—is cleared. The TCG 800 then undergoes another solving step.

[0093] Figure 13This is diagram 1300 illustrating the timing changes of the remaining components of an example TCG 800 as a result of the solution steps. In this example, the legal start time of gate 810 changes from 54 ps to 56 ps, and the legal start time of buffer 816 changes from 57 ps to 58 ps. Although the solution steps do not change the phase assignments of gate 810 and buffer 816, they can be changed if needed. Next, the timing and phase assignments associated with shadow components in other TCGs are updated.

[0094] Figure 14 This is a diagram 1400 illustrating timing changes for other TCGs (e.g., TCG 910 and TCG 930) according to an example. In this example, the step is performed as part of the algorithm described in Table 12 to update the timing and phase assignment of the shadow components. In this example, the legal start time of gate 912 is changed from 60 ps to 61 ps; the legal start time of gate 914 is changed from 90 ps to 91 ps; and the legal start time of gate 916 is changed from 108 ps to 109 ps. The legal start time of buffer 918 remains unchanged (97 ps); the legal start time of buffer 920 is changed from 88 ps to 89 ps; and the legal start time of buffer 922 is changed from 51 ps to 52 ps. For TCG 930, the legal start time of gate 932 is changed from 89 ps to 90 ps. The valid start time of buffer 934 is changed from 60 ps to 61 ps, and the valid start time of buffer 936 is changed from 75 ps to 76 ps. The steps involving the reconciliation process can be repeated until there are no conflicts related to timing and phase assignment. For example, except for the valid start time associated with buffer 918 being changed from 97 ps to 98 ps, subsequent reconciliation steps can keep all timings the same. Therefore, in this example, Figures 8-14 The algorithm shown in Table 12 is applied to find a convergent solution, where the iteration of the algorithm results in the timing and phase assignments being fixed and no longer needing to be changed.

[0095] Figure 15This is a flowchart 1500 of an example method for determining timing paths and harmonic topologies in a superconducting circuit design. In this example, the superconducting circuit design may include a first timing path comprising a first set of timing pins, and a first subset of the first set of timing pins may be associated with a first timing constraint group comprising a first timing endpoint and a second timing endpoint. Step 1510 may include processing the first timing constraint group to assign a first valid start time to the first timing endpoint and a second valid start time to the second timing endpoint. In this example, when the code / algorithm related to timing engine 132 (e.g., Figure 4 The code or algorithm stored in memory 406 is processed by a processor (e.g., Figure 4 When the processor(s) 402(s) are executed, this step can be performed by the timing engine 132. In this example, the timing engine 132 can perform step 1 of the algorithm described in Table 12. As an example, this step may include using the previously described critical timing path algorithm to determine the (multiple) valid start times for each timing endpoint in the timing endpoints.

[0096] Step 1520 may include: inserting a first shadow element on the timing path, the first shadow element representing a component of a first physical connection, wherein the first shadow element precedes a first timing endpoint or follows a second timing endpoint. In this example, when the code / algorithm related to timing engine 132 (e.g., Figure 4 The code or algorithm stored in memory 406 is processed by a processor (e.g., Figure 4 When the (multiple) processors 402 in the process are executed, this step can be performed by the timing engine 132. In this example, the timing engine 132 can be executed with respect to... Figure 9 This step is performed in a similar manner to that described above. Therefore, given the timing constraints imposed by other circuitry in the design, the timing engine 132 can handle the timing design. In one example, as part of this analysis, components within the depth of the three timing endpoints (referred to as shadow elements or shadow components) can be included. The legal start times of these endpoints and the phase assignments of the gates or buffers that are part of the shadow elements can be obtained in a manner similar to that described above.

[0097] Step 1530 may include: resolving any changes to the first or second valid start time caused by the insertion of a first shadow element on the timing path. In this example, when the code / algorithm related to timing engine 132 (e.g., Figure 4 The code or algorithm stored in memory 406 is processed by a processor (e.g., Figure 4When the (multiple) processors 402) in the process are executed, this step can be performed by the timing engine 132. In this example, the timing engine 132 can execute steps 2 and 3 as described in Table 12. As an example, in Figure 8 With the help of example timing constraint group 800, regarding Figures 10-14 These steps are described. Although Figure 15 The method illustrates a specific number of steps performed in a particular order, but may include more or fewer steps performed in a different order.

[0098] Figure 16 This is a flowchart 1600 of an example method for determining a timing path and harmonizing a topology in a superconducting circuit design. In this example, the superconducting circuit design may include a first timing path, which includes a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, wherein each of the first and second circuit components includes a Josephson junction. The first circuit component is assigned a first phase and the second circuit component is assigned a second phase. Step 1610 may include: using a processor, determining a first valid start time for the first timing endpoint on the timing path, and determining a second valid start time for the second timing endpoint on the timing path. In this example, when the code / algorithm associated with timing engine 132 (e.g., ...) is... Figure 4 The code or algorithm stored in memory 406 is processed by a processor (e.g., Figure 4 When the processor(s) 402(s) are executed, this step can be performed by the timing engine 132. In this example, the timing engine 132 can perform step 1 of the algorithm described in Table 12. As an example, this step may include using the critical timing path algorithm described above to determine the (multiple) valid start times for each timing endpoint in the timing endpoints.

[0099] Step 1620 may include: inserting a first shadow element on the timing path, the first shadow element representing a component of a first physical connection, wherein the first shadow element precedes a first circuit component on the timing path. In this example, when the code / algorithm related to timing engine 132 (e.g., Figure 4 The code or algorithm stored in memory 406 is processed by a processor (e.g., Figure 4 When the (multiple) processors 402 in the process are executed, this step can be performed by the timing engine 132. In this example, the timing engine 132 can be executed with respect to... Figure 9The step is performed in a similar manner to the description. Therefore, given the timing constraints imposed by other circuits in the design, timing engine 132 can process the timing design. In one example, as part of this analysis, components within the depth of the three timing endpoints (referred to as shadow elements or shadow components) may be included. As part of step 1620, the first shadow element may be part of a group of timing constraints preceding the first circuit component on the timing path. Therefore, in this example, the first shadow element may be... Figure 9 Gate 914. The legal start times of these endpoints, which are included as part of the shadow element, and the phase assignment of the gate or buffer can be obtained in a manner similar to that described above.

[0100] Step 1630 may include: inserting a second shadow element on the timing path, the second shadow element representing a component of a second physical connection, wherein the second shadow element follows a second circuit component on the timing path. In this example, when the code / algorithm related to timing engine 132 (e.g., Figure 4 The code or algorithm stored in memory 406 is processed by a processor (e.g., Figure 4 When the (multiple) processors 402 in the process are executed, this step can be performed by the timing engine 132. In this example, the timing engine 132 can be executed with respect to... Figure 9 The described method is similar in how this step is performed. Therefore, given the timing constraints imposed by other circuits in the design, timing engine 132 can process the timing design. In one example, as part of this analysis, components within the depth of the three timing endpoints (referred to as shadow elements or shadow components) may be included. As part of step 1630, a second shadow element may be part of a group of timing constraints following the second circuit component on the timing path. Therefore, in this example, the second shadow element may be... Figure 9 Gate 934. The legal start times of these endpoints, which are included as part of the shadow element, and the phase assignment of the gate or buffer can be obtained in a manner similar to that described above.

[0101] Step 1640 may include resolving any changes to the first and second valid start times caused by the insertion of the first and second shadow elements on the timing path. In this example, when the code / algorithm related to the timing engine 132 (e.g., Figure 4 The code or algorithm stored in memory 406 is processed by a processor (e.g., Figure 4 When the (multiple) processors 402) in the process are executed, this step can be performed by the timing engine 132. In this example, the timing engine 132 can execute steps 2 and 3 as described in Table 12. As an example, in Figure 8With the help of example timing constraint group 800, regarding Figures 10-14 These steps are described. Although Figure 16 The method illustrates a specific number of steps performed in a particular order, but may include more or fewer steps performed in a different order.

[0102] In summary, this disclosure relates to a processor-implemented method for determining critical timing paths in a superconducting circuit design, wherein the superconducting circuit design includes at least one logic gate, the at least one logic gate including at least one Josephson junction, and wherein the at least one logic gate has an assigned first phase associated with a clock signal used to time the at least one logic gate. The method may include providing timing information about a plurality of source terminals of the at least one logic gate coupled to a first terminal of the at least one logic gate. The method may further include, using the processor, determining, based on the first phase assigned to the at least one logic gate and in view of the timing information, whether the first terminal is reachable by a single-through-quantum (SFQ) pulse within a predetermined time range of arrival.

[0103] The method may further include inserting a Josephson transmission line (JTL) element between at least one of the plurality of source terminals and the first terminal if the first terminal is unreachable by a single-through-quantum (SFQ) pulse within a predetermined arrival time range. The method may further include determining whether the first terminal is reachable by an SFQ pulse within the predetermined arrival time range after the insertion of the JTL element. The method may further include removing the first terminal from the plurality of terminal terminals associated with at least one logic gate, as associated with a critical timing path, upon determining that the first terminal is reachable by an SFQ pulse within the predetermined arrival time range after the insertion of the JTL element.

[0104] The method may further include: selecting a first terminal from a plurality of terminal blocks associated with at least one logic gate based on a predetermined behavior. Selecting the first terminal block based on the predetermined behavior may include: selecting a terminal block having the minimum of the maximum rise time values ​​of the corresponding SFQ pulses associated with the plurality of terminal blocks as the first terminal block.

[0105] The method may include, prior to the determination step, assigning a second phase to at least one logic gate by adding a phase offset to the first phase. Timing information may be provided via a timing library, which includes at least timing constraints and permitted signal types, wherein the permitted signal types are selected from a group comprising either wave pipeline logic types of signals or phase mode logic types of signals.

[0106] In another aspect, this disclosure relates to a processor-implemented method for determining critical timing paths in a superconducting circuit design, wherein the superconducting circuit design includes a plurality of logic gates, and wherein each of the plurality of logic gates includes at least one Josephson junction. The method may include providing timing information regarding a plurality of source terminals associated with the plurality of logic gates. The method may further include receiving a selection of a first terminal from a plurality of terminal blocks associated with a target logic gate, the target logic gate being selected from the plurality of logic gates. The method may further include receiving an assignment of a phase to the target logic gate. The method may further include, for each of a plurality of terminal blocks: using a processor, determining whether each of the plurality of terminal blocks is reachable by a corresponding single-through-quantum (SFQ) pulse within a predetermined arrival time range; and if the first terminal block is not reachable within the predetermined arrival time range, inserting a Josephson transmission line (JTL) between the source terminal associated with the target logic gate and the first terminal block determined to be not reachable within the predetermined arrival time range; and removing the first terminal block from the plurality of terminal blocks as associated with a critical timing path after determining that the first terminal block is reachable within the predetermined arrival time range following the insertion of the JTL.

[0107] The method may further include selecting a first terminal from a plurality of terminal blocks associated with the target logic gate based on a predetermined behavior. Selecting the first terminal block based on the predetermined behavior may include selecting a first terminal block having the minimum of the maximum rise time values ​​of the corresponding SFQ pulses associated with the plurality of terminal blocks as the first terminal block.

[0108] The method may further include: assigning a second phase to a target logic gate by adding a phase offset to the first phase prior to the determination step. Timing information may be provided via a timing library, which includes at least timing constraints and permitted signal types, wherein the permitted signal types are selected from a group including wave pipeline logic types or phase mode logic types of signals.

[0109] In another aspect, this disclosure relates to a system configured to determine a critical timing path in a superconducting circuit design, wherein the superconducting circuit design includes at least one logic gate, the logic gate including at least one Josephson junction, and wherein the at least one logic gate has an assigned first phase associated with a clock signal used to time the at least one logic gate. The system may include a first subsystem configured to provide timing information regarding a plurality of source terminals of the at least one logic gate coupled to a first terminal of the at least one logic gate. The system may also include a second subsystem comprising a processor configured to: based on the first phase assigned to the at least one logic gate, and in view of the timing information, determine whether the first terminal is reachable by a single-through-quantum (SFQ) pulse within a predetermined time range of arrival.

[0110] The system can also be configured to allow the insertion of a Josephson transmission line (JTL) element between at least one of the multiple source terminals and the first terminal if the first terminal is unreachable by an SFQ pulse within a predetermined arrival time range. The system can also be configured to determine, after inserting the JTL element, whether the first terminal is reachable by an SFQ pulse within the predetermined arrival time range. The system can also be configured to remove the first terminal from among the multiple terminals associated with at least one logic gate, as associated with a critical timing path, upon determining that the first terminal is reachable by an SFQ pulse within the predetermined arrival time range after JTL element insertion. The system can also be configured to select the terminal having the minimum maximum rise time value of the corresponding SFQ pulses associated with the multiple terminals as the first terminal.

[0111] The system can also be configured to assign a second phase to at least one logic gate by adding a phase offset to the first phase. The system may also include a timing library, which includes at least timing constraints and permitted signal types, wherein the permitted signal types are selected from a group comprising wave pipeline logic types or phase mode logic types of signals.

[0112] In another aspect, this disclosure relates to a processor-implemented method for determining timing paths and harmonic topologies in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path, the first timing path including a first set of timing pins, and wherein a first subset of the first set of timing pins is associated with a first timing constraint group including a first timing endpoint and a second timing endpoint. The method may include using a processor to process the first timing constraint group to assign a first legal start time to the first timing endpoint and a second legal start time to the second timing endpoint. The method may further include inserting a first shadow element on the timing path, the first shadow element representing a component of a first physical connection, wherein the first shadow element precedes the first timing endpoint or follows the second timing endpoint. The method may further include resolving any changes to the first legal start time or the second legal start time caused by the insertion of the first shadow element on the timing path.

[0113] In this method, processing a first timing constraint group to assign a first legitimate start time to a first timing endpoint may include: determining whether the first timing endpoint is reachable by a single-flux quantum (SFQ) pulse within a first arrival time range, and wherein processing the first timing constraint group to assign a second legitimate start time to a second timing endpoint includes: determining whether the second timing endpoint is reachable by an SFQ pulse within a second arrival time range. The method may further include: if the second timing endpoint is not reachable by an SFQ pulse within the second arrival time range, inserting a Josephson transmission line (JTL) element between the first and second timing endpoints.

[0114] The timing path may include a second timing constraint group and a third timing constraint group, wherein the second timing constraint group includes a third timing endpoint and a fourth timing endpoint, and the third timing constraint group includes a fifth timing endpoint and a sixth timing endpoint, and wherein the method further includes: processing the second timing constraint group to assign a third valid start time to the third timing endpoint and a fourth valid start time to the fourth timing endpoint, and processing the third timing constraint group to assign a fifth valid start time to the fifth timing endpoint and a sixth valid start time to the sixth timing endpoint.

[0115] The method may further include: inserting a second shadow element on the timing path, the second shadow element representing a second physical connection component, wherein the second shadow element precedes the first timing endpoint or follows the second timing endpoint. Resolving any changes to the first or second legal start time may include: modifying the first legal start time to generate a first modified legal start time or modifying the second legal start time to generate a second modified legal start time.

[0116] The method may also include addressing any changes to the first or second modified legal start time caused by the insertion of a second shadow element on the timing path. Timing information about the timing path can be provided via a timing library that includes at least timing constraints and permitted signal types, wherein permitted signal types are selected from a group including wave pipeline logic types or phase mode logic types of signals.

[0117] In another aspect, this disclosure relates to a processor-implemented method for determining timing paths and harmonic topologies in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path, the first timing path including a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, and wherein each of the first and second circuit components includes a Josephson junction, and wherein the first circuit component is assigned a first phase and the second circuit component is assigned a second phase. The method may include: using the processor, determining a first legal start time for the first timing endpoint on the timing path and determining a second legal start time for the second timing endpoint on the timing path. The method may further include inserting a first shadow element on the timing path, the first shadow element representing a component of a first physical connection, wherein the first shadow element precedes the first circuit component on the timing path. The method may further include inserting a second shadow element on the timing path, the second shadow element representing a component of a second physical connection, wherein the second shadow element follows the second circuit component on the timing path. The method may further include resolving any changes to the first and second legal start times caused by the insertion of the first and second shadow elements on the timing path.

[0118] Determining a first legitimate start time for a first timing endpoint may include: determining whether the first timing endpoint is reachable by a single-flux quantum (SFQ) pulse within a first arrival time range; and wherein determining a second legitimate start time for a second timing endpoint includes: determining whether the second timing endpoint is reachable by an SFQ pulse within a second arrival time range. The method may further include: if the second timing endpoint is not reachable by an SFQ pulse within the second arrival time range, inserting a Josephson transmission line (JTL) element between the first and second circuit components and assigning phase to the JTL. Resolving any changes to the first or second legitimate start time may include: modifying the first legitimate start time to generate a first modified legitimate start time or modifying the second legitimate start time to generate a second modified legitimate start time.

[0119] The method may also include addressing any changes to the first or second modified legal start time caused by the insertion of a second shadow element on the timing path. Timing information about the timing path can be provided via a timing library that includes at least timing constraints and permitted signal types, wherein permitted signal types are selected from a group including signals of wave pipeline logic type or signals of phase mode logic type.

[0120] In another aspect, this disclosure relates to a system configured to determine timing paths and harmonic topologies in a superconducting circuit design, wherein the superconducting circuit design includes a first timing path, the first timing path including a first timing endpoint associated with a first circuit component and a second timing endpoint associated with a second circuit component, and wherein each of the first and second circuit components includes a Josephson junction, and wherein the first circuit component is assigned a first phase and the second circuit component is assigned a second phase. The system may include a processor and a memory including instructions. The instructions may be configured to: (1) determine a first legal start time of the first timing endpoint on the timing path and determine a second legal start time of the second timing endpoint on the timing path, (2) insert a first shadow element on the timing path, the first shadow element representing a component of a first physical connection, wherein the first shadow element precedes the first circuit component on the timing path, (3) insert a second shadow component on the timing path, the second shadow component representing a component of a second physical connection, wherein the second shadow element follows the second circuit component on the timing path, and (4) resolve any changes to the first and second legal start times caused by the insertion of the first and second shadow elements on the timing path.

[0121] A first shadow element may be coupled to a first circuit assembly via a first active transmission element, and a second circuit assembly may be coupled to a second shadow element via a second active transmission element. The first active transmission element may include a first Josephson transmission line (JTL), and the second active transmission element may include a second JTL.

[0122] A first active transmission element may be assigned a third phase, and a second active transmission element may be assigned a fourth phase. Each of the first, second, third, and fourth phases can be selected from a group consisting of 0-degree phases, 90-degree phases, 180-degree phases, and 270-degree phases. The system may also include a timing library containing timing information about timing paths, wherein the timing information includes at least timing constraints and permitted signal types, wherein the permitted signal types are selected from a group including wave pipeline logic types of signals or phase mode logic types of signals.

[0123] It should be understood that the methods, modules, and components described herein are merely exemplary. Alternatively or additionally, the functionality described herein may be implemented at least in part by one or more hardware logic components. For example, but not limited to, illustrative types of hardware logic components that may be used include Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SOCs), Complex Programmable Logic Devices (CPLDs), etc. In an abstract but still explicit sense, any arrangement of components that achieves the same functionality is effectively “associated” to achieve the desired functionality. Therefore, any two components combined to implement a particular function in this document can be considered “associated” with each other to achieve the desired functionality, regardless of the architecture or intermediate components. Similarly, any two such associated components can also be considered “operably connected” or “coupled” with each other to achieve the desired functionality.

[0124] The functionality associated with the examples described in this disclosure may also include instructions stored in non-transient media. As used herein, the term "non-transient media" refers to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Exemplary non-transient media include non-volatile media and / or volatile media. Non-volatile media include, for example, hard disks, solid-state drives, magnetic disks or magnetic tapes, optical disks or magnetic tapes, flash memory, EPROM, NVRAM, PRAM, or other such media, or network versions of such media. Volatile media include, for example, dynamic memory, such as DRAM, SRAM, cache, or other such media. Non-transient media differs from transport media but can be used in conjunction with transport media. Transport media are used to transfer data and / or instructions to a machine (e.g., Figure 4 The processor (402) in the machine or the processor (or processor) in the machine transmits data and / or instructions. Example transmission media include coaxial cable, fiber optic cable, copper wire, and wireless media such as radio waves.

[0125] Furthermore, those skilled in the art will recognize that the boundaries between the functionalities of the above-described operations are merely illustrative. The functionality of multiple operations can be combined into a single operation, and / or the functionality of a single operation can be distributed across additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments.

[0126] While specific examples are provided in this disclosure, various modifications and alterations may be made without departing from the scope of this disclosure as set forth in the following claims. Therefore, the specification and drawings are to be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the invention. Any benefits, advantages, or solutions to problems described herein with reference to specific examples should not be construed as key, essential, or fundamental features or elements of any or all claims.

[0127] Furthermore, the term "a" or "an" as used herein is defined as one or more. Moreover, even if the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an," the use of introductory phrases such as "at least one" and "one or more" in a claim should not be construed as implying that another claim element introduced by the indefinite article "a" or "an" limits any particular claim containing such an introduced claim element to an invention containing only one such element. The same applies to the use of definite articles.

[0128] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the time or other priority of such elements.

Claims

1. A method for determining a critical timing path in a superconducting circuit design, the method being implemented by a processor, wherein the superconducting circuit design includes at least one logic gate, the at least one logic gate including at least one Josephson junction, and wherein the at least one logic gate has an assigned first phase associated with a clock signal for timing the at least one logic gate, the method comprising: Timing information is provided for a plurality of source terminals of the at least one logic gate, wherein the plurality of source terminals of the at least one logic gate are coupled to a first terminal of the at least one logic gate; as well as Using the processor, based on the first phase assigned to the at least one logic gate, and taking into account the timing information, it is determined whether the first terminal is reachable by a single-throughput quantum SFQ pulse within a predetermined arrival time range. The method further includes inserting a Josephson transmission line (JTL) element between at least one of the plurality of source terminals and the first terminal if the first terminal is unreachable by the SFQ pulse within the predetermined arrival time range.

2. The method of claim 1, further comprising: Determine whether the first terminal block is reachable by the SFQ pulse within the predetermined arrival time range after the insertion of the JTL element.

3. The method of claim 2, further comprising: When it is determined that the first terminal is reachable by the SFQ pulse within the predetermined arrival time range after the insertion of the JTL element, the first terminal is removed from the plurality of terminal blocks associated with the at least one logic gate as associated with the critical timing path.

4. The method according to claim 1, further comprising: Based on a predetermined behavior, the first terminal is selected from a plurality of terminal blocks associated with the at least one logic gate.

5. The method of claim 4, wherein selecting the first terminal based on the predetermined behavior comprises: The terminal that has the minimum value among the maximum rise time values ​​of the corresponding SFQ pulses associated with the plurality of terminal terminals is selected as the first terminal terminal.

6. The method according to claim 1, further comprising: Prior to the determination step, a second phase is assigned to the at least one logic gate by adding a phase offset to the first phase.

7. The method of claim 1, wherein the timing information is provided via a timing library, the timing library including at least timing constraints and permitted signal types, wherein the permitted signal types are selected from a group including wave pipeline logic types of signals or phase mode logic types of signals.

8. A method for determining critical timing paths in a superconducting circuit design, the method being implemented by a processor, wherein the superconducting circuit design includes a plurality of logic gates, and wherein each of the plurality of logic gates includes at least one Josephson junction, the method comprising: Provide timing information about multiple source terminals associated with the plurality of logic gates; Receive selection of a first terminal from a plurality of terminal blocks associated with a target logic gate, wherein the target logic gate is selected from the plurality of logic gates; Receive the phase assignment for the target logic gate; as well as For each of the plurality of terminal blocks: Using the processor, it is determined whether each of the plurality of sink terminals is reachable by a corresponding single-throughput quantum SFQ pulse within a predetermined arrival time range, and If the first terminal is unreachable within the predetermined arrival time range, a Josephson transmission line (JTL) is inserted between the source terminal associated with the target logic gate and the first terminal that is determined to be unreachable within the predetermined arrival time range. After the insertion of the JTL, when it is determined that the first terminal is reachable within the predetermined arrival time range, the first terminal is removed from the plurality of terminal terminals as associated with the critical timing path.

9. The method according to claim 8, further comprising: Based on a predetermined behavior, the first terminal is selected from the plurality of terminal blocks associated with the target logic gate.

10. The method of claim 9, wherein selecting the first terminal based on the predetermined behavior comprises: The terminal that has the minimum value among the maximum rise time values ​​of the corresponding SFQ pulses associated with the plurality of terminal terminals is selected as the first terminal terminal.

11. The method of claim 8, wherein the target logic gate has an assigned first phase, the method further comprising: Before the step of determining whether each of the plurality of sink terminals is reachable by the corresponding single-through-quantum SFQ pulse within a predetermined arrival time range, a second phase is assigned to the target logic gate by adding a phase offset to the first phase.

12. The method of claim 8, wherein the timing information is provided via a timing library, the timing library including at least timing constraints and permitted signal types, wherein the permitted signal types are selected from a group including wave pipeline logic types of signals or phase mode logic types of signals.

13. A system configured to determine a critical timing path in a superconducting circuit design, wherein the superconducting circuit design includes at least one logic gate, the at least one logic gate including at least one Josephson junction, and wherein the at least one logic gate has an assigned first phase associated with a clock signal for timing the at least one logic gate, the system comprising: A first subsystem is configured to provide timing information about a plurality of source terminals of the at least one logic gate, the plurality of source terminals of the at least one logic gate being coupled to a first terminal of the at least one logic gate; as well as The second subsystem, including a processor, is configured to: determine, based on the first phase assigned to the at least one logic gate and in view of the timing information, whether the first terminal is reachable by a single-throughput quantum SFQ pulse within a predetermined arrival time range; The system is further configured to allow the insertion of a Josephson transmission line (JTL) element between at least one of the plurality of source terminals and the first terminal if the first terminal is unreachable by the SFQ within the predetermined arrival time range.

14. The system of claim 13, wherein the system is further configured to: determine whether the first terminal is reachable by the SFQ pulse within the predetermined arrival time range after the insertion of the JTL element.

15. The system of claim 14, wherein the system is further configured to: remove the first terminal from among a plurality of terminals associated with the at least one logic gate as associated with the critical timing path when it is determined that the first terminal is reachable by the SFQ pulse within the predetermined arrival time range after the insertion of the JTL element.

16. The system of claim 15, wherein the system is further configured to: select a terminal having the minimum of the maximum rise time values ​​of the corresponding SFQ pulses associated with the plurality of terminal terminals as the first terminal terminal.

17. The system of claim 13, wherein the system is further configured to: assign a second phase to the at least one logic gate by adding a phase offset to the first phase.

18. The system of claim 13 further includes a timing library, the timing library including at least timing constraints and permitted signal types, wherein the permitted signal types are selected from the group consisting of wave pipeline logic types of signals or phase mode logic types of signals.

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