Memory management unit, processing unit, system, and memory access methods

Abstract

This invention provides a memory management unit, a processing unit, a system, and a memory access method. The memory access method is applied to a memory management unit and a processing unit connected to an external bus. The memory management system includes the memory management unit and the processing unit. The memory management unit acquires a memory access request from an external device, obtains a virtual memory address included in the memory access request, and sends the virtual memory address to the processing unit via the external bus. The processing unit converts the virtual memory address into a physical memory address. The memory management unit further acquires the physical memory address from the processing unit via the external bus and performs memory access based on the physical memory address. This invention reduces the implementation cost of memory access by external devices.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory management unit, a processing unit, a system, and a memory access method. Background Technology

[0002] Generally, for various computer architectures, processing units such as the CPU need to access instructions and data in memory to perform calculations and execute programs in memory. In addition, external devices such as graphics cards and network cards also need to access memory, thus achieving close cooperation between processing units, external devices, and memory.

[0003] To improve the efficiency and flexibility of memory access for external devices, external devices send virtual memory addresses to memory management units such as the Input / output Memory Management Unit (IOMMU) or the System Memory Management Unit (SMMU), which translate the virtual memory addresses into physical memory addresses for memory access based on the physical memory addresses.

[0004] However, the configuration cost of existing memory management units is relatively high. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a memory management unit, a processing unit, a system, and a memory access method to at least partially solve the above-mentioned problems.

[0006] According to a first aspect of the present invention, a memory management unit is provided, which is connected to a processing unit via an external bus. The memory management unit includes: a first acquisition module, which acquires a memory access request from an external device and obtains a virtual memory address included in the memory access request; a sending module, which sends the virtual memory address to the processing unit via the external bus to convert the virtual memory address into a physical memory address; a second acquisition module, which acquires the physical memory address from the processing unit via the external bus; and an access module, which performs memory access based on the physical memory address.

[0007] In other examples, the sending module is specifically used to: send an interrupt request to the processing unit via the external bus, the interrupt request instructing the processing unit to begin acquiring the virtual memory address, thus being compatible with the processing mechanism of the processing unit and the external bus transmission mechanism.

[0008] In other examples, the memory management unit is configured with a first interface for connecting to the external device via the external bus. The first acquisition module is specifically used to: acquire the memory access request sent by the external device via the external bus through the first interface, which is compatible with the external bus transmission mechanism and realizes reliable and efficient data transmission using the first interface.

[0009] In other examples, the memory management unit is configured with a second interface connected to the processing unit via the external bus. The first acquisition module is specifically used to: acquire the memory access request of the external device through the first interface to obtain the virtual memory address. The memory management unit further includes a forwarding module to forward the virtual memory address from the first interface to the second interface. The sending module is specifically used to: send the virtual memory address to the processing unit via the second interface and the external bus. Reliable, orderly and efficient data transmission is achieved using the first interface and the second interface.

[0010] In other examples, the memory management unit is configured with a third interface connected to the memory via the external bus. The second acquisition module is further configured to: acquire the physical memory address from the processing unit through the second interface. The forwarding module is further configured to: forward the physical memory address to the third interface. The access module is specifically configured to: access the physical memory address in the memory through the third interface. Reliable and efficient data transmission is achieved using the third interface, and the internal processing logic of the memory management unit is simplified.

[0011] In other examples, the memory management unit is configured with a cache that stores the correspondence between the virtual memory address and the physical memory address. The second acquisition module is specifically used to send the virtual memory address to the processing unit when the correspondence is not found in the cache. Therefore, while ensuring reliable address translation results, it saves CPU computing resources and communication resources between the memory management unit and the CPU.

[0012] In other examples, the second acquisition module is further configured to: when the corresponding relationship is found in the cache, prevent the sending module from sending the virtual memory address to the processing unit, and acquire the physical memory address from the cache. Therefore, while ensuring reliable address translation results, CPU computing resources are saved, as are communication resources between the memory management unit and the CPU.

[0013] According to a second aspect of the present invention, a processing unit is provided, which is connected to a memory management unit via an external bus, comprising: a third acquisition module for acquiring a virtual memory address of the memory management unit via the external bus; a conversion module for converting the virtual memory address into a physical memory address; and a sending module for sending the physical memory address to the memory management unit via the external bus.

[0014] In other examples, the processing unit is connected to memory via the external bus, and the memory stores an address translation program. The third acquisition module is specifically used to: respond to an interrupt request sent by the memory management unit via the external bus, execute the address translation program in the memory, and acquire the virtual memory address. Therefore, it is compatible with the CPU's processing mechanism and improves the configuration flexibility of the address translation program.

[0015] In other examples, the translation module is specifically used to: translate the virtual memory address into a physical memory address by executing the address translation program in the memory.

[0016] In other examples, the sending module is specifically used to: in response to the acquisition of the physical memory address, send the physical memory address to the memory management unit via the external bus. This saves the operation of writing back to memory, directly sending the physical memory address to the memory management unit, improving overall address translation efficiency, and thus improving memory access efficiency.

[0017] According to a third aspect of the present invention, a memory management system is provided, comprising: a memory management unit according to the first aspect and a processing unit according to the second aspect.

[0018] According to a fourth aspect of the present invention, a system-on-a-chip is provided, comprising: a memory management system according to the third aspect.

[0019] According to a fifth aspect of the present invention, a memory access method is provided, applied to a memory management unit and a processing unit connected by an external bus. The method includes: using the memory management unit to obtain a memory access request from an external device, obtaining a virtual memory address included in the memory access request, and sending the virtual memory address to the processing unit via the external bus; using the processing unit to convert the virtual memory address into a physical memory address; using the memory management unit to obtain the physical memory address from the processing unit via the external bus, and performing memory access based on the physical memory address.

[0020] In the embodiment of this invention, the memory management unit sends a virtual memory address to the processing unit via an external bus. The processing unit translates the virtual memory address into a physical memory address, and the memory management unit obtains the physical memory address for memory access from the processing unit. Since the translation from virtual memory address to physical memory address is performed within the processing unit, the implementation complexity of the memory management unit is reduced, freeing up its computing resources. Furthermore, the processing unit can run corresponding functions implemented by software programs stored in storage media such as memory, which facilitates flexible processing of software programs. Moreover, using the processing unit to run software programs does not increase the configuration cost of the processing unit. In summary, the overall implementation cost of memory access by external devices is significantly reduced. Furthermore, the communication and interaction between internal processing units is imperceptible to external devices and memory, providing excellent compatibility with the configuration of external devices and memory. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0022] Figure 1 A schematic architecture diagram for memory access of an example external device.

[0023] Figure 2A This is a schematic architecture diagram of a memory management system according to an embodiment of the present invention.

[0024] Figure 2B This is a schematic block diagram of a memory management unit according to another embodiment of the present invention.

[0025] Figure 3 This is a schematic block diagram of a processing unit according to another embodiment of the present invention.

[0026] Figure 4A This is a schematic block diagram of a memory access method according to another embodiment of the present invention.

[0027] Figure 4B This is a schematic interactive diagram of a memory access method according to another embodiment of the present invention.

[0028] Figure 5 This is a flowchart of the steps of a memory access method according to another embodiment of the present invention. Detailed Implementation

[0029] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this specification as detailed in the appended claims.

[0030] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “the,” and “the” as used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0031] It should be understood that although the terms first, second, third, etc., may be used in this specification to describe various modules, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. Depending on the context, the word "if" as used herein can be interpreted as "when," "when," or "in response to a determination."

[0032] Figure 1 A schematic architecture diagram for memory access of an example external device. Figure 1 The architecture includes a Central Processing Unit (CPU) 110, memory 120, external devices 130, and an IOMMU 140, any two of which can communicate via an external bus 150. It should be understood that the external bus is a concept corresponding to the CPU's internal bus, but is not limited to this naming convention and can be called the system bus, etc. External buses include, but are not limited to, I2C bus, ISA (Industry Standard Architecture) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus, AGP (Accelerated Graphics Port) bus, etc. The external bus 150 is not limited to one type of bus and can be implemented using different types of buses. For example, different communication methods among the aforementioned components can be arranged with multiple bus interfaces and communicate using the corresponding buses.

[0033] Furthermore, the CPU 110 shown exemplarily includes a memory management unit (MMU) 111; however, it should be understood that the MMU 111 can be configured externally to the CPU and connected to an external bus 150. The memory 120 can be implemented using dynamic random access memory (DRAM) or static random access memory (SRAM) as the storage medium. The IOMMU 140 shown in the figure is also exemplary. Generally, for different CPU architectures, the memory management unit of the external device 130 itself can be of different types; for example, in another example, it could be an SMMU.

[0034] In addition, external devices may include dedicated devices such as graphics cards and network cards, or driver devices, or devices that work with memory to improve data processing efficiency. In one example, an external device needs to access data or instructions in memory 120. If memory 120 is accessed through physical memory addresses, a faster access speed can be obtained for a single piece of data. However, the way physical memory addresses are calculated makes the requirements for the partitioning of storage areas in memory 120 relatively rigid, resulting in poor flexibility in memory access.

[0035] In another example, Figure 1 This architecture is applied in virtual machine scenarios, where virtual machines implement the runtime environment requirements of specific software by virtualizing specific hardware environments, or provide protection for real hardware. In this case, if external device 130 uses physical memory addresses for memory access, it increases the configuration cost of external device 130 and also reduces flexibility.

[0036] Memory management units such as IOMMU 140 can flexibly configure the correspondence between virtual memory addresses and physical memory addresses by performing the translation between virtual memory addresses and physical memory addresses. This enables flexible access configuration between various external devices 130 and various memory modules 120 without changing the addressing logic of memory 120 and the access logic of external devices 130, thereby improving the memory access efficiency of external devices.

[0037] It should be understood that the number of external devices 130 can be one or more, and multiple external devices can use one or more memory management units 140 to perform functions such as address translation. Preferably, one external device corresponds to one memory management unit, or one memory management unit performs address translation based on the address translation correspondences corresponding to each external device.

[0038] Typically, the access process of external device 130 to memory 120 requires high access speed. In order not to affect the access speed, memory management unit 140 also needs to have high computing speed. On the one hand, memory management units such as IOMMU will use specific hardware configurations to ensure the speed of this address translation to match the access speed. On the other hand, this also makes the configuration cost of memory management unit 140 high.

[0039] Figure 2A This is a schematic architecture diagram of a memory management system according to an embodiment of the present invention. Figure 2A The memory management system includes a processing unit 2100 and a memory management unit 2400 that communicate via an external bus 2500.

[0040] In one example, the memory management system, including the processing unit 2100 and the memory management unit 2400, communicates with the memory 2200 and external devices 2300 via an external bus 2500, which can be used for devices such as memory 2200 and external devices 2300. Figure 1 The external bus 150 is the communication bus.

[0041] The processing unit 2100 can be any device with processing capabilities, such as a CPU, a graphics processing unit (GPU), an embedded controller, or a microprocessor.

[0042] In addition, memory 2200 can be used for things like Figure 1 The memory 120 is a storage device. External devices 2300 can include, for example... Figure 1 The external device 130 is not described in detail in this embodiment.

[0043] Furthermore, another embodiment of the present invention provides a System on Chip (SoC) that integrates a memory management system, including a processing unit 2100 and a memory management unit 2400, as well as an external bus 2500. Additionally, the SoC may also integrate at least one of a memory 2200 and an external device 2300.

[0044] Figure 2B This is a schematic block diagram of a memory management unit according to another embodiment of the present invention.

[0045] The memory management unit in Figure 2 can be a memory management unit 2400, connected to a processing unit 2100 such as a CPU via an external bus 2500. This memory management unit includes:

[0046] The first acquisition module 210 acquires the memory access request from the external device and obtains the virtual memory address included in the memory access request.

[0047] Specifically, the memory access request indicates an external device's request to access memory. The memory can be directly or indirectly connected to the external bus 2500. The external device receives the response result of the access request from the memory management unit 2400, and the response result indicates the physical memory address corresponding to the virtual memory address. The first acquisition module 210 may also have the ability to parse using the bus communication protocol in order to obtain the virtual memory address from the memory access request.

[0048] Furthermore, the virtual memory address mentioned in this text can also be called a logical memory address, which corresponds to the actual physical memory address. The physical memory address is the actual memory address where data or instructions can be found. The way logical memory addresses are divided and marked is flexible, and this embodiment does not limit it.

[0049] When connected via external bus 2500, the external device can encapsulate the virtual memory address using the protocol of external bus 2500 to obtain a memory access request. Correspondingly, the first acquisition module 210 decapsulates the memory access request to obtain the virtual memory address. The response result can use the same encapsulation protocol as the memory access request.

[0050] The sending module 220 sends the virtual memory address to the processing unit via an external bus to convert the virtual memory address into a physical memory address.

[0051] Specifically, the sending module 220 can communicate directly with the processing unit 2100 via the external bus 2500, or via an interface based on the external bus 2500, to send virtual memory addresses. The processing unit 2100 can directly convert virtual memory addresses to physical memory addresses, or indirectly, in conjunction with a software program for address conversion, convert virtual memory addresses to physical memory addresses.

[0052] The second acquisition module 230 acquires the physical memory address from the processing unit via an external bus.

[0053] Specifically, the second acquisition module 230 can communicate directly with the processing unit 2100 via the external bus 2500, or it can communicate with the processing unit 2100 via an interface based on the external bus 2500, to obtain the physical memory address.

[0054] In addition, the physical memory address can be obtained from the processing unit, and the physical memory address generated by the processing unit 2100 can be actively monitored, or the physical memory address sent by the processing unit 2100 can be received.

[0055] Access module 240 performs memory access based on the physical memory address.

[0056] Specifically, the access module 240 can directly use the physical memory address to access memory and then delete the physical memory address; alternatively, it can perform memory access based on the physical memory address while caching it. The cached physical memory address can be directly determined or locked later based on the resolved virtual memory address, without needing to obtain the physical memory address from the processing. After performing the memory access, the above-mentioned response result can be obtained.

[0057] It should be understood that the above modules can be implemented using software or hardware configuration. In one example, the modules are implemented using hardware configuration; for example, each module can be configured as a hardware circuit to perform its respective function. In another example, the modules can be implemented using software configuration; for example, the function of each module can be configured as such as firmware; or it can be configured as a software program, which performs the corresponding function by running the software program on a certain hardware configuration.

[0058] In the embodiment of this invention, the memory management unit sends a virtual memory address to the processing unit via an external bus. The processing unit translates (or addresses) the virtual memory address into a physical memory address. The memory management unit then obtains the physical memory address for memory access from the processing unit. Since the virtual memory address to physical memory address translation is performed within the processing unit, the implementation complexity of the memory management unit is reduced, freeing up its computing resources. The processing unit can run corresponding functions implemented by software programs stored in storage media such as memory, which facilitates flexible processing of software programs. Furthermore, using a processing unit to run software programs does not increase the configuration cost of the processing unit. In summary, the overall implementation cost of external devices accessing memory is significantly reduced.

[0059] Figure 3 This is a schematic block diagram of a processing unit according to another embodiment of the present invention.

[0060] Figure 3 The processing unit can be a processing unit 2100, which is connected to the memory management unit via an external bus. This processing unit includes:

[0061] The third acquisition module 310 acquires the virtual memory address of the memory management unit via an external bus.

[0062] The conversion module 320 converts virtual memory addresses to physical memory addresses.

[0063] The sending module 330 sends the physical memory address to the memory management unit via the external bus.

[0064] It should be understood that the above modules can be implemented using software or hardware configuration. In one example, the modules are implemented using hardware configuration; for example, each module can be configured as a hardware circuit to perform its respective function. In another example, the modules can be implemented using software configuration; for example, the function of each module can be configured as such as firmware; or it can be configured as a software program, which performs the corresponding function by running the software program on a certain hardware configuration.

[0065] In the embodiment of this invention, the memory management unit sends a virtual memory address to the processing unit via an external bus. The processing unit translates the virtual memory address into a physical memory address, and the memory management unit obtains the physical memory address for memory access from the processing unit. Since the translation from virtual memory address to physical memory address is performed within the processing unit, the implementation complexity of the memory management unit is reduced, freeing up its computing resources. Furthermore, the processing unit can run corresponding functions implemented by software programs stored in storage media such as memory, which facilitates flexible processing of software programs. Moreover, using the processing unit to run software programs does not increase the configuration cost of the processing unit. In summary, the overall implementation cost of external devices accessing memory is significantly reduced.

[0066] Figure 4A and Figure 4B These are schematic block diagrams and schematic interaction diagrams of a memory access method according to another embodiment of the present invention.

[0067] Figure 4A The architecture applied to the memory access methods and Figure 2A The architecture is similar, and the following will combine... Figure 4A The architecture is described and explained in detail. Figure 4B The memory access methods, but it should be understood that, Figure 4B The memory access method can also be applied to other architectures, and this embodiment does not limit it.

[0068] In this embodiment, the processing unit 2100 is implemented as a CPU. The CPU executes programs in memory 2200 by accessing instructions and data in memory 2200. For example, memory 2200 may have applications installed (via an operating system). These applications are compiled into various machine language instructions. The CPU reads the instructions, performs corresponding data operations, and stores the results of the data operations back to memory 2200. It should be understood that specific addressing logic is required for the CPU 2100 to read instructions and data or write data to memory 2200. In one example, the CPU 2100 may use physical memory address-based addressing. For example, the CPU 2100 directly determines the physical address of the data or instruction to be read and reads the data or instruction corresponding to the physical memory address in memory 2200. Alternatively, the CPU 2100 may write the data operation result to the physical memory address in memory 2200. In another example, CPU 2100 can use virtual memory address-based addressing. For example, CPU 2100 can directly determine the virtual memory address of the data or instruction to be read, and convert the virtual memory address into a physical memory address through the CPU's own MMU, and read the data or instruction corresponding to the physical memory address in memory 2200. Alternatively, CPU 2100 can write the data operation result at the physical memory address of memory 2200.

[0069] S4100: External device 2300 can send a memory access request to memory management unit 2400, and the memory access request may include a virtual memory address. In addition, memory management unit 2400 can obtain the physical memory address corresponding to the virtual memory address and access memory 2200 based on the physical memory address.

[0070] Unlike conventional memory management unit configurations, the memory management unit in this embodiment of the invention is equivalent to an input / output gateway (IO gateway). The internal processing logic of the memory management unit (e.g., address translation logic) is invisible to the external device 2300 and can be highly compatible with conventional memory access configurations. Specifically, the memory access requests sent by the external device 2300 to the memory management unit 2400, as well as the access logic of the memory management unit 2400 to the memory 2200, can be compatible with conventional access schemes.

[0071] S4200: The memory management unit 2400 parses the virtual memory address from the memory access request and sends the virtual memory address to the CPU 2100. Specifically, the memory management unit 2400 sends the virtual memory address to the cache of the CPU 2100.

[0072] S4300: CPU 2100 translates virtual memory addresses to physical memory addresses. In one example, address translation instructions that translate virtual memory addresses to physical memory addresses can be executed in the cache. The CPU can fetch the address translation instructions, obtain the virtual memory address from the cache, execute the address translation instructions on the virtual memory address, and obtain the physical memory address. Alternatively, address translation instructions or address translation-related instructions can also be fetched from memory 2200, i.e., memory 2200 is configured with address translation instructions, or, as... Figure 4A As shown, memory 2200 stores multiple instructions from an address translation program (2210) used for address translation.

[0073] In another example, the CPU's own MMU can be used to translate virtual memory addresses to obtain physical memory addresses.

[0074] In another example, CPU 2100 can obtain a virtual memory address from memory management unit 2400. For example, CPU 2100 can send a virtual memory address acquisition request to memory storage unit 2400 at cycles consistent with memory access frequency. Alternatively, CPU 2100 can also detect the acquisition of a virtual memory address in memory management unit 2400 and return the virtual memory address to CPU 2100. For example, CPU 2100 can be connected to a first interface 291 (also referred to as an external device interface) in memory management unit 2400 for acquiring virtual memory addresses via external bus 2500. When the first interface 291 acquires a virtual memory address, it returns the virtual memory address to CPU 2100 via external bus 2500. It should be understood that the returned virtual memory address can be returned to a register or cache of CPU 2100, which can be used by CPU 2100's own MMU for address translation, thereby achieving address translation compatible with conventional CPU configurations. It should be understood that the address translation mapping of external devices may differ from that of the CPU itself, and the MMU may perform corresponding address translations based on different address translation mappings.

[0075] As an example of the CPU 2100 obtaining a virtual memory address, the memory management unit 2400 can send an interrupt request to the CPU 2100, and the CPU 2100 responds to the interrupt to obtain the virtual memory address. Specifically, the memory management unit 2400 can respond to the first interface 291 resolving the virtual memory address and generate the aforementioned interrupt request. Alternatively, the CPU 2100 can obtain the virtual memory address through the second interface 292 (also referred to as the CPU interface) in the memory management unit 2400. The memory management unit 2400 can write the virtual address to the second interface 292. As another example of interrupt request generation, it can also respond to the second interface 292 receiving a virtual memory address and generate an interrupt request. Specifically, the memory management unit 2400 can directly store the virtual memory address parsed from the memory access request into the second interface 292, or it can receive the memory access request from the external device using the first interface 291, obtain the virtual memory address, and forward the virtual memory address to the second interface 292. Thus, the memory management unit 2400 implements the memory access request parsing logic. Since the memory access request is closely related to the type of external device, configuring the parsing logic within the memory management unit rather than in external components such as the CPU improves the configuration flexibility of the external device. Furthermore, the first interface 291 and the second interface 292 are independent interfaces, corresponding to different communication interaction objects and implementing different functions, avoiding the configuration difficulties caused by using a unified interface.

[0076] S4400: CPU 2100 sends the physical memory address to memory management unit 2400 via the external bus. Specifically, unlike CPU 2100 executing regular instructions in memory 2200, after the CPU 2100 uses the address translation program in memory 2200, it does not store the obtained physical memory address back to memory 2200, but instead returns the physical memory address to memory management unit 2400. In other words, if the physical memory address is returned to memory 2200, memory 2200 still needs to indirectly or directly return the physical memory address to memory management unit 2400. Therefore, the solution in this example saves the communication overhead between memory and CPU, as well as the communication overhead between memory 2200 and memory management unit 2400. CPU 2100 can also return the physical memory address to memory management unit 2400 through second interface 292 to improve the communication efficiency between CPU and memory management unit. In addition, second interface 292 can be configured with a first register and a second register, corresponding to the virtual memory address to be sent and the received physical memory address, respectively. The first register can maintain a first queue for managing virtual memory addresses, and the second register can maintain a second queue for managing physical memory addresses. After the first interface 291 resolves the virtual memory address, it adds the virtual memory address to the first queue. The first register then retrieves the current virtual memory address from the first queue in order and places it in the second interface 292 to send to the CPU. Similarly, the second register retrieves the arrived physical memory address from the second interface 292 and places it in the second queue. The second register also retrieves the current physical memory address from the second queue in order and writes it to cache 294 or the third interface 293, which will be described below.

[0077] S4500: The memory management unit 2400 accesses memory 2200 based on the physical memory address. Specifically, the memory access based on the physical memory address described above can be implemented through the third interface 293 (also referred to as the memory interface). In another implementation of memory access, the physical memory address can be associated with and stored in the memory management unit 2400 along with the virtual memory address. For example, the mapping relationship between the virtual memory address and the physical memory address can be stored in the cache 294 of the memory management unit 2400. After the memory management unit 2400 obtains the physical memory address, it can perform two operations: storing the physical memory address and operating based on the physical memory address. The order of these two operations is not limited in this example; that is, these two operations can be performed simultaneously or sequentially. Then, after the memory management unit 2400 subsequently (e.g., within a certain time period) obtains the virtual memory address again, it can directly obtain the physical memory address based on the associated storage, without needing to obtain the physical memory address from the CPU 2100 again, thus saving communication overhead between the CPU and the memory management unit.

[0078] Specifically, after obtaining the physical memory address through the second interface 292, the physical memory address can be written from the second interface 292 to the third interface 293, and memory access can be performed through the third interface 293. The physical memory address is then written from the second interface 292 (e.g., the second register corresponding to the second interface) to the cache 294 of the memory management unit 2400, thereby improving the parallel processing of the two operations. Alternatively, the physical memory address can be written from the second interface 292 (e.g., the second register) to the third interface 293 and then written to the cache 294. This serial processing, while maintaining the priority of memory access, saves computational resources when they are limited.

[0079] It should be understood that the first interface 291, the second interface 292, and the third interface 293 can all be connected to the external bus 2500. In one example, the memory management unit 2400 can be connected to the external bus through an interface multiplexing unit (not shown). The interface multiplexing unit can use time-division multiplexing to manage the communication channels of the first interface 291, the second interface 292, and the third interface 293. For example, the interface multiplexing unit can be configured with three queues corresponding to the three interfaces respectively. When one interface occupies the external bus 2500, the data transmitted by the other interfaces is buffered in the corresponding queue, and the data is switched between the three queues in a manner such as polling, and data is retrieved from the corresponding queues in turn and sent to the external bus 2500.

[0080] The above combination Figure 4A and Figure 4BThis paper describes in detail various exemplary implementations of the memory management system. The following section will combine... Figure 5 Describe the corresponding memory access method, wherein the implementation of each step or sub-step can refer to the specific exemplary implementation described above.

[0081] Figure 5 This is a flowchart of the steps of a memory access method according to another embodiment of the present invention.

[0082] Figure 5 A memory access method, applied to a memory management unit and a processing unit connected to an external bus, the method comprising:

[0083] S510: Using the memory management unit, it obtains memory access requests from external devices and gets the virtual memory address included in the memory access request.

[0084] S520: Using the memory management unit, virtual memory addresses are sent to the processing unit via the external bus.

[0085] S530: Uses the processing unit to translate virtual memory addresses into physical memory addresses.

[0086] S540: Uses the memory management unit to obtain the physical memory address from the processing unit via the external bus.

[0087] S550: Utilizes the memory management unit to access memory based on physical memory addresses.

[0088] In the embodiment of this invention, the memory management unit sends the virtual memory address to the processing unit via an external bus. The processing unit translates the virtual memory address into a physical memory address, and the memory management unit obtains the physical memory address for memory access from the processing unit. Since the translation from virtual memory address to physical memory address is performed within the processing unit, the implementation complexity of the memory management unit is reduced, freeing up its computing resources. Furthermore, the processing unit has strong computing power and flexible software configuration of its processing logic, without increasing the configuration cost of the processing unit. Therefore, the implementation cost of external devices accessing memory is reduced.

[0089] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of the present invention can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present invention.

[0090] The methods described above according to embodiments of the present invention can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored on a remote recording medium or a non-transitory machine-readable medium and subsequently stored on a local recording medium, downloaded via a network. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processing unit, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processing unit, microprocessor unit controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processing unit, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0091] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the embodiments of the present invention.

[0092] The above embodiments are only used to illustrate the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present invention, and the patent protection scope of the embodiments of the present invention should be defined by the claims.

Claims

1. A memory management unit connected with a processing unit through an external bus, comprising: a first obtaining module, configured to obtain a memory access request of an external device, and to obtain a virtual memory address included in the memory access request; a sending module, configured to send the virtual memory address to the processing unit through the external bus, the processing unit performing address translation on the virtual memory address through a register or a cache, to obtain a physical memory address, the register or the cache being used for address translation by a memory management unit of the processing unit, an address translation correspondence of the external device being different from an address translation correspondence of the processing unit itself, the address translation correspondence being a correspondence between the virtual memory address and the physical memory address; a second obtaining module, configured to obtain the physical memory address from the processing unit through the external bus; an accessing module, configured to perform memory access according to the physical memory address.

2. The memory management unit of claim 1, wherein, The sending module is specifically configured to send an interrupt request to the processing unit through the external bus, the interrupt request indicating that the processing unit starts to obtain the virtual memory address.

3. The memory management unit of claim 1, wherein, The memory management unit is configured with a first interface connected with the external device through the external bus, The first obtaining module is specifically configured to obtain the memory access request of the external device sent through the external bus through the first interface.

4. The memory management unit of claim 3, wherein, The memory management unit is configured with a second interface connected with the processing unit through the external bus, The first obtaining module is specifically configured to obtain the memory access request of the external device to obtain the virtual memory address through the first interface, The memory management unit further comprises a forwarding module, configured to forward the virtual memory address from the first interface to the second interface, The sending module is specifically configured to send the virtual memory address to the processing unit through the second interface through the external bus.

5. The memory management unit of claim 4, wherein, The memory management unit is configured with a third interface connected with a memory through the external bus, The second obtaining module is further configured to obtain the physical memory address from the processing unit through the second interface, The forwarding module is further configured to forward the physical memory address to the third interface, The accessing module is specifically configured to access the physical memory address in the memory through the third interface.

6. The memory management unit of claim 1, wherein, The memory management unit is configured with a cache; The second obtaining module is specifically configured to send the virtual memory address to the processing unit when the correspondence is not found in the cache.

7. The memory management unit of claim 6, wherein, The second obtaining module is further configured to prohibit the sending module from sending the virtual memory address to the processing unit and to obtain the physical memory address from the cache when the correspondence is found in the cache.

8. A processing unit connected with a memory management unit through an external bus, comprising: a third obtaining module, configured to obtain a virtual memory address of the memory management unit through the external bus, The conversion module converts the virtual memory address into a physical memory address through a register or a cache for address conversion of a memory management unit of the processing unit, and the address conversion correspondence of the external device is different from the address conversion correspondence of the processing unit itself, and the address conversion correspondence is a correspondence between the virtual memory address and the physical memory address. The sending module sends the physical memory address to the memory management unit through the external bus.

9. The memory management unit of claim 8, wherein, The processing unit and the memory are connected via the external bus, and the address conversion program is stored in the memory, The third obtaining module is specifically configured to: in response to an interrupt request sent by the memory management unit via the external bus, execute the address conversion program in the memory, and obtain the virtual memory address.

10. The memory management unit of claim 8, wherein, The sending module is specifically configured to: in response to the obtaining of the physical memory address, send the physical memory address to the memory management unit through the external bus.

11. A memory management system, comprising: The memory management unit according to any one of claims 1-7 and the processing unit according to any one of claims 8-10.

12. A system on chip, comprising: The memory management system, the memory and the external device according to claim 11, Wherein the memory management unit, the processing unit, the memory and the external device in the memory management system are connected through an external bus.

13. A memory access method applied to a memory management unit and a processing unit connected through an external bus, the method comprising: Using the memory management unit, obtaining a memory access request of an external device, obtaining a virtual memory address included in the memory access request, and sending the virtual memory address to the processing unit via the external bus; Using the register or cache of the processing unit to perform address conversion on the virtual memory address to obtain a physical memory address, the register or cache being used for address conversion of a memory management unit of the processing unit, and the address conversion correspondence of the external device being different from the address conversion correspondence of the processing unit itself, and the address conversion correspondence being a correspondence between the virtual memory address and the physical memory address; Using the memory management unit, obtaining the physical memory address from the processing unit via the external bus, and performing memory access according to the physical memory address.

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