Display substrate, display panel, and display device

Abstract

A display substrate, a display panel and a display device are provided. The display substrate comprises: a substrate substrate; a plurality of sub-pixels, the plurality of sub-pixels are arranged in an array along a row direction and a column direction on the substrate substrate and are located in the display area, each sub-pixel comprises a light-emitting device, the light-emitting device comprises a first electrode; a plurality of signal lines arranged on the substrate substrate, at least a portion of each signal line is located in the display area, the plurality of signal lines at least comprise a first signal line and a second signal line; a signal line lead arranged on the substrate substrate, the signal line lead is located in the non-display area; and a signal line switching structure arranged on the substrate substrate, the signal line switching structure is used to connect the signal line lead with the second signal line, wherein the signal line switching structure and the first signal line are located in the same layer, and the signal line switching structure and the first signal line are arranged at intervals; the orthographic projection of the first electrode on the substrate substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate substrate, and the orthographic projection of the first electrode on the substrate substrate at least partially overlaps with the orthographic projection of the signal line switching structure on the substrate substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a display substrate, a display panel, and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display devices are a type of display device that uses light-emitting OLEDs to display images and other information. OLED display devices have characteristics such as low power consumption, high brightness, and high response speed. With the development of OLED technology, the requirements for display effects are becoming higher and higher, and performance parameters such as color deviation need to be continuously improved. There are many factors that affect the color deviation of products. From the perspective of substrate design, the flatness of the planarization layer or pixel electrode has a great influence on the color deviation.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore, the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In one aspect, a display substrate is provided, the display substrate comprising a display area and a non-display area, wherein the display substrate comprises:

[0005] substrate substrate;

[0006] A plurality of sub-pixels located in the display area, the plurality of sub-pixels are arranged in an array on the base substrate along a row direction and a column direction, each sub-pixel includes a light emitting device, and the light emitting device includes a first electrode;

[0007] A plurality of signal lines disposed on the substrate, the plurality of signal lines at least comprising a first signal line and a second signal line, the first signal line being used to transmit a voltage signal, and the second signal line being used to transmit a scan signal;

[0008] A signal line lead is provided on the base substrate, the signal line lead is located in the non-display area; and

[0009] A signal line transfer structure is provided on the base substrate, and the signal line transfer structure is used to connect the signal line lead and the second signal line.

[0010] Wherein, the signal line transfer structure and the first signal line are located in the same layer, and the signal line transfer structure and the first signal line are spaced apart;

[0011] And among them, the positive projection of the first electrode of at least one of the sub-pixels on the substrate overlaps at least partially with the positive projection of the first signal line on the substrate, and the positive projection of the first electrode of at least one of the sub-pixels on the substrate overlaps at least partially with the positive projection of the signal line transfer structure on the substrate.

[0012] According to some exemplary embodiments, the plurality of sub-pixels includes at least one row of edge sub-pixels located at an edge position of the display area close to the non-display area; and the positive projection of the first electrode of each edge sub-pixel in the at least one row of edge sub-pixels on the substrate overlaps at least partially with the positive projection of the first signal line on the substrate, and the positive projection of the first electrode of each edge sub-pixel in the at least one row of edge sub-pixels on the substrate overlaps at least partially with the positive projection of the signal line transfer structure on the substrate.

[0013] According to some exemplary embodiments, the at least one row of edge sub-pixels includes at least one column of edge sub-pixels, and the arrangement direction of the at least one column of edge sub-pixels is substantially the same as the extension direction of the first signal line.

[0014] According to some exemplary embodiments, the signal line transfer structure is substantially the same as the extension direction of the first signal line, and the arrangement direction of the plurality of signal line transfer structures is substantially the same as the extension direction of the first signal line.

[0015] According to some exemplary embodiments, the positive projection of the signal line transfer structure overlapping with an edge sub-pixel in the at least one row of edge sub-pixels on the substrate penetrates the positive projection of the first electrode of the edge sub-pixel on the substrate.

[0016] According to some exemplary embodiments, the display substrate further includes a pixel defining layer on a side of the first electrode away from the substrate, the pixel defining layer includes an opening, the first electrode of the at least one sub-pixel is at least partially exposed by the opening, and the size of the signal line transfer structure extending in the column direction is greater than the size of the opening of the pixel defining layer corresponding to the at least one sub-pixel extending in the column direction.

[0017] According to some exemplary embodiments, the size of the pixel driving circuit corresponding to the at least one sub-pixel extending in the column direction is a, and the size of the signal line transfer structure extending in the column direction is between.

[0018] According to some exemplary embodiments, in a direction perpendicular to the first signal line, the signal line transfer structure is located on a side of the first signal line closer to the non-display area.

[0019] According to some exemplary embodiments, the first electrode of each edge sub-pixel in the at least one row of edge sub-pixels includes a first edge portion close to the non-display area, and an orthographic projection of the first edge portion on the base substrate at least partially overlaps with an orthographic projection of the signal line transfer structure on the base substrate.

[0020] According to some exemplary embodiments, the first electrode of each edge sub-pixel in the at least one row of edge sub-pixels includes a second edge portion away from the non-display area, and the orthographic projection of the second edge portion on the base substrate at least partially overlaps with the orthographic projection of the first signal line on the base substrate.

[0021] According to some exemplary embodiments, a thickness of the signal line transfer structure in a direction perpendicular to the substrate is substantially equal to a thickness of the first signal line in a direction perpendicular to the substrate.

[0022] According to some exemplary embodiments, the first electrode includes a main body, the orthographic projection of the main body on the base substrate has a regular shape; and the orthographic projection of the first signal line on the base substrate and the orthographic projection of the signal line switching structure on the base substrate are respectively located on both sides of the center of the orthographic projection of the main body of the first electrode on the base substrate.

[0023] According to some exemplary embodiments, the display substrate further includes a planarization layer, wherein the planarization layer is located between the signal line switching structure and a layer where the first signal line is located and a layer where the first electrode is located.

[0024] According to some exemplary embodiments, each sub-pixel further includes a pixel driving circuit, the pixel driving circuit includes a storage capacitor and at least one thin film transistor, each of the thin film transistors includes a semiconductor layer, a gate, a source electrode and a drain electrode, and the storage capacitor includes a first capacitor electrode and a second capacitor electrode;

[0025] And wherein, the display substrate further comprises:

[0026] A first conductive layer is disposed on a side of the semiconductor layer away from the substrate, wherein the gate and the first capacitor electrode are located in the first conductive layer;

[0027] A second conductive layer disposed on a side of the first conductive layer away from the base substrate, wherein the second capacitor electrode is located on the second conductive layer; and

[0028] A third conductive layer is arranged on a side of the second conductive layer away from the base substrate, and the source and the drain are located in the third conductive layer.

[0029] According to some exemplary embodiments, the signal line transfer structure and the first signal line are located in one selected from the first conductive layer, the second conductive layer, and the third conductive layer.

[0030] According to some exemplary embodiments, the display substrate further includes: a connection conductive portion disposed between the third conductive layer and the layer where the first electrode is located, and the connection conductive portion is configured to electrically connect one of the source electrode and the drain electrode to the first electrode.

[0031] According to some exemplary embodiments, the signal line transfer structure and the first signal line are located in the layer where the connection conductive portion is located.

[0032] According to some exemplary embodiments, at least one of the signal line lead and the second signal line is in a different layer from the signal line transfer structure.

[0033] According to some exemplary embodiments, the signal line lead and the second signal line are in the same layer, and both the signal line lead and the second signal line are in a different layer from the signal line transfer structure; the display substrate further includes an insulating layer between the layer where the signal line lead and the second signal line are located and the layer where the signal line transfer structure is located, and the insulating layer includes a first via and a second via; a part of the signal line transfer structure is connected to the second signal line through a first conductive plug formed in the first via, and another part of the signal line transfer structure is connected to the signal line lead through a second conductive plug formed in the second via; or,

[0034] The signal line lead and the second signal line are in different layers, and the signal line lead and the signal line transfer structure are in the same layer; the display substrate further includes an insulating layer between the layer where the signal line lead and the signal line transfer structure are located and the layer where the second signal line is located, and the insulating layer includes a first via; a part of the signal line transfer structure is connected to the second signal line through a first conductive plug formed in the first via, and another part of the signal line transfer structure is directly connected to the signal line lead; or,

[0035] The signal line lead and the second signal line are in different layers, and the second signal line and the signal line transfer structure are in the same layer; the display substrate further includes an insulating layer between the layer where the second signal line and the signal line transfer structure are located and the layer where the signal line lead is located, and the insulating layer includes a second via; a part of the signal line transfer structure is directly connected to the second signal line, and another part of the signal line transfer structure is connected to the signal line lead through a second conductive plug formed in the second via.

[0036] According to some exemplary embodiments, the display substrate further includes a gate driving circuit disposed on the substrate substrate and located in the non-display area. The signal line lead includes a signal output line of the gate driving circuit. The signal output line is configured to output a gate scanning signal, and the second signal line includes a scanning signal line for transmitting the gate scanning signal.

[0037] According to some exemplary embodiments, the display substrate further includes an initial voltage signal line disposed on the substrate substrate and located in the non-display area. The signal output line is electrically connected to the signal line transfer structure through a plurality of third vias, and the plurality of third vias are arranged along a direction parallel to the extending direction of the initial voltage signal line.

[0038] According to some exemplary embodiments, the scanning signal line is electrically connected to the signal line transfer structure through a plurality of fourth vias, and the plurality of fourth vias are arranged along a direction perpendicular to the extending direction of the initial voltage signal line.

[0039] According to some exemplary embodiments, the signal line transfer structure includes a widened portion. The positive projections of the plurality of third vias and the plurality of fourth vias on the substrate substrate all fall within the positive projection of the widened portion on the substrate substrate; and the positive projection of the first edge portion of the first electrode on the substrate substrate at least partially overlaps with the positive projection of the widened portion of the signal line transfer structure on the substrate substrate.

[0040] According to some exemplary embodiments, the first signal line includes a driving voltage line for transmitting a driving voltage, and the positive projection of the second edge portion of the first electrode on the substrate substrate at least partially overlaps with the positive projection of the driving voltage line on the substrate substrate.

[0041] According to some exemplary embodiments, the first signal line further includes a data line for transmitting a data signal, and the positive projection of the second edge portion of the first electrode on the substrate substrate also at least partially overlaps with the positive projection of the data line on the substrate substrate.

[0042] According to some exemplary embodiments, the scanning signal line is located in the first conductive layer, the signal output line is located in the second conductive layer, and the signal line transfer structure is located in the third conductive layer.

[0043] According to some exemplary embodiments, the display substrate further includes a reset control signal line disposed on the substrate substrate. The reset control signal line is electrically connected to the signal line transfer structure through a plurality of fifth vias, and the plurality of fifth vias are arranged along a direction perpendicular to the extending direction of the initial voltage signal line.

[0044] According to some exemplary embodiments, the signal output line includes a first signal output line sub-segment, a second signal output line sub-segment and a third signal output line sub-segment connected in sequence, the orthographic projection of the first signal output line sub-segment on the substrate substrate falls within the orthographic projection of the signal line switching structure on the substrate substrate, the orthographic projection of the second signal output line sub-segment on the substrate substrate at least partially overlaps with the orthographic projection of the initial voltage signal line on the substrate substrate, and the third signal output line sub-segment is located on a side of the initial voltage signal line away from the signal line switching structure; and in a direction parallel to the extension direction of the initial voltage signal line, the size of the second signal output line sub-segment is smaller than the size of the first signal output line sub-segment, and the size of the first signal output line sub-segment is smaller than the size of the third signal output line sub-segment.

[0045] According to some exemplary embodiments, the second capacitor electrode includes a second capacitor electrode main body portion and a second capacitor electrode connecting portion, and the second capacitor electrode connecting portion is located between two adjacent second capacitor electrode main bodies; a projection of the second signal output line sub-segment in a direction perpendicular to an extension direction of the initial voltage signal line at least partially overlaps with a projection of the second capacitor electrode connecting portion in a direction perpendicular to the extension direction of the initial voltage signal line.

[0046] According to some exemplary embodiments, the display substrate also includes another initial voltage signal line arranged on the base substrate and located in the non-display area, the other initial voltage signal line and the first electrode are located in the same layer; and the other initial voltage signal line and the initial voltage signal line are electrically connected.

[0047] According to some exemplary embodiments, the display substrate also includes an initialization voltage line arranged on the base substrate, the initial voltage signal line is electrically connected to the initialization voltage line through a plurality of sixth vias, and the plurality of sixth vias are arranged in a direction parallel to an extension direction of the initial voltage signal line.

[0048] According to some exemplary embodiments, the light emitting device includes an organic light emitting diode, and the first electrode is an anode of the organic light emitting diode.

[0049] According to some exemplary embodiments, the at least one row of edge sub-pixels includes a plurality of red sub-pixels and a plurality of blue sub-pixels alternately arranged along the column direction.

[0050] In another aspect, a display panel is provided, comprising the display substrate as described above.

[0051] In yet another aspect, a display device is provided, comprising the display substrate or the display panel as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The features and advantages of the present disclosure will become more apparent by describing exemplary embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0053] Figure 1 is a partial plan view of an organic light-emitting diode display substrate in the related art;

[0054] Figure 2 is along Figure 1 a cross-sectional view taken along line AA' in

[0055] Figure 3 is a schematic diagram schematically showing the flatness of anodes of different sub-pixels of a display substrate in the related art;

[0056] Figure 4 is a plan view of a display substrate according to some embodiments of the present disclosure;

[0057] Figure 5 is a partial enlarged view of part I of a display substrate according to some embodiments of the present disclosure in Figure 4 ;

[0058] Figure 6 is a cross-sectional view taken along line BB' of a display substrate according to some embodiments of the present disclosure in Figure 5 ;

[0059] Figure 7A is a schematic diagram of a signal line transfer structure of a display substrate according to some exemplary embodiments of the present disclosure;

[0060] Figure 7B is along Figure 7A a cross-sectional view taken along line CC' in

[0061] Figure 8A is a schematic diagram of a signal line transfer structure of a display substrate according to some exemplary embodiments of the present disclosure;

[0062] Figure 8B is along Figure 8A a cross-sectional view taken along line CC' in

[0063] Figure 9A is a schematic diagram of a signal line transfer structure of a display substrate according to some exemplary embodiments of the present disclosure;

[0064] Figure 9B is along Figure 9A a cross-sectional view taken along line CC' in

[0065] Figure 10 is a partial enlarged view of part I of a display substrate according to some embodiments of the present disclosure in Figure 4 ;

[0066] Figure 11 is a cross-sectional view of a display substrate taken along line DD' according to some embodiments of the present disclosure; Figure 10 in;

[0067] Figure 12 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure;

[0068] Figure 13 is a plan view showing an exemplary implementation of sub-pixels in a display area AA of a display substrate according to some exemplary embodiments of the present disclosure;

[0069] Figures 14 to 17 is a view showing Figure 13 some film layers of an exemplary implementation of sub-pixels in;

[0070] Figure 18 is a circuit diagram schematically showing a first scan driving circuit according to some exemplary embodiments of the present disclosure;

[0071] Figure 19 is Figure 18 a timing diagram of the scan driving circuit described above;

[0072] Figure 20 is a circuit diagram schematically showing a second scan driving circuit according to some exemplary embodiments of the present disclosure;

[0073] Figure 21 is Figure 20 a timing diagram of the scan driving circuit described above;

[0074] Figure 22 is an enlarged view of a signal line transfer structure of a display substrate according to some exemplary embodiments of the present disclosure;

[0075] Figure 23 is a plan view of a display substrate according to some exemplary embodiments of the present disclosure, showing film layer structures such as a signal line transfer structure and an anode layer;

[0076] Figure 24 is a timing diagram of a light emission control signal, a scan signal, and a reset control signal for driving multiple adjacent rows of pixels of a display substrate according to some exemplary embodiments of the present disclosure;

[0077] Figure 25 is a schematic cross-sectional view of a display panel taken along line HH' according to some exemplary embodiments of the present disclosure; Figure 23 in;

[0078] Figure 26 is a display panel according to some other exemplary embodiments of the present disclosure alongFigure 23 Schematic cross-sectional view taken along line HH' in

[0079] Figure 27 A display panel according to some exemplary embodiments of the present disclosure along Figure 23 Schematic cross-sectional view taken along line II' in

[0080] Figure 28 A display panel according to some exemplary embodiments of the present disclosure along Figure 23 Schematic cross-sectional view taken along line JJ' in; and

[0081] Figure 29 Schematic diagram of a display device according to some exemplary embodiments of the present disclosure. Detailed implementation manners

[0082] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0083] It should be noted that in the drawings, for clarity and / or for the purpose of description, the sizes and relative sizes of elements may be enlarged. Thus, the sizes and relative sizes of the respective elements are not necessarily limited to the sizes and relative sizes shown in the figures. In the description and the drawings, the same or similar reference numerals indicate the same or similar components.

[0084] When an element is described as being "on", "connected to", or "coupled to" another element, the element can be directly on, directly connected to, or directly coupled to the other element, or there can be intervening elements. However, when an element is described as being "directly on", "directly connected to", or "directly coupled to" another element, there are no intervening elements. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" can refer to physical connection, electrical connection, communication connection, and / or fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any combination and all combinations of one or more of the listed related items.

[0085] It should be noted that although terms such as "first", "second", etc. may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below can be referred to as the second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0086] For ease of description, spatial relationship terms such as "above", "below", "left", "right", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatial relationship terms are intended to cover other different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is inverted, an element described as being "below" or "beneath" another element or feature will be oriented "above" or "on top of" the other element or feature.

[0087] In this text, terms such as "substantially", "about", "approximately", "roughly", and other similar terms are used as approximate terms rather than terms of degree, and they are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art. Considering factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein includes the stated value and represents that the particular value determined by a person of ordinary skill in the art is within an acceptable deviation range. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0088] It should be noted that in this text, the expression "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern and then patterning the film layer by using the same mask through a single patterning process. Depending on the different specific patterns, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures, and / or parts located in "the same layer" are composed of the same material and are formed through the same patterning process. Generally, multiple elements, components, structures, and / or parts located in "the same layer" have substantially the same thickness.

[0089] Those skilled in the art should understand that in this text, unless otherwise specified, the expressions "height" or "thickness" refer to the dimension along the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light-emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0090] Embodiments of the present disclosure provide at least one display substrate. The display substrate includes a display area and a non-display area. Wherein, the display substrate includes: a substrate; a plurality of sub-pixels arranged in an array along a row direction and a column direction on the substrate and located in the display area, and each sub-pixel includes a light-emitting device, and the light-emitting device includes a first electrode; a plurality of signal lines arranged on the substrate, the plurality of signal lines at least include a first signal line for transmitting a voltage signal and a second signal line for transmitting a scan signal; a signal line lead arranged on the substrate, and the signal line lead is located in the non-display area; and a signal line transfer structure arranged on the substrate, and the signal line transfer structure is used to connect the signal line lead and the second signal line. Wherein, the signal line transfer structure and the first signal line are on the same layer, and the signal line transfer structure and the first signal line are arranged at intervals; and wherein, a positive projection of the first electrode on the substrate and a positive projection of the first signal line on the substrate at least partially overlap, and a positive projection of the first electrode on the substrate and a positive projection of the signal line transfer structure on the substrate at least partially overlap. In this way, the flatness of the first electrode can be improved, and the inclination of the first electrode can be avoided, so as to improve the color shift phenomenon of the display substrate.

[0091] Figure 1 is a partial plan view of an organic light-emitting diode (hereinafter referred to as OLED) display substrate in the related art. Figure 2 is along Figure 1 a cross-sectional view taken along line AA' in. It should be noted that, in order to clearly show the relative positional relationship between the signal line, the planarization layer and the anode, Figure 1 and Figure 2 some other film layer structures included in the OLED display substrate are omitted in.

[0092] Referring to Figure 1 and Figure 2 , the OLED display substrate may include a substrate 02 and a plurality of sub-pixels arranged on the substrate 02. For example, Figure 1 SP1, SP2 and SP3 shown in. For example, Figure 1 SP1, SP2 and SP3 in may represent the areas for display of each sub-pixel. For example, the part corresponding to the opening of the pixel defining layer.

[0093] It should be understood that the OLED display substrate may further include: an OLED light-emitting device 01 and a pixel driving circuit electrically connected to the OLED light-emitting device 01. The pixel driving circuit may be electrically connected to a driving IC located outside the OLED display substrate through a signal line 03. The OLED display substrate may include: a planarization layer 04 for covering the pixel driving circuit and the signal line 03. The OLED light-emitting device 01 may include an anode 011, an organic light-emitting layer 012, and a cathode 013 which are stacked. The pixel driving circuit may include a plurality of thin-film transistors.

[0094] For example, the signal line 03 may be on the same layer as the source and drain electrodes of the thin-film transistor and formed of the same material as the source and drain electrodes.

[0095] Such as Figure 1 and Figure 2 As shown, in the direction perpendicular to the substrate 02, at least a part 031 of the signal line 03 is located below the anode 011. Since the signal line 03 has a certain thickness, and the thickness of the signal line 03 is usually large, for example, usually more than 3000 angstroms, and the thickness of the planarization layer 04 covering the signal line 03 and the thickness of the anode 011 are not sufficient to fill the height difference caused by the signal line 03, the planarization layer 04 cannot completely planarize the signal line 03. As a result, at the position corresponding to a part 031 of the signal line 03, the planarization layer 04 will have a bulge, making the flatness of the anode 011 formed on the planarization layer 04 insufficient, such as "tilting".

[0096] Figure 3 is a schematic diagram schematically showing the flatness of the anodes of different sub-pixels in a display substrate in the related art. It should be noted that, in order to clearly show the unevenness of the anode, Figure 3 its degree of tilt is exaggerated, and it should be understood that, Figure 3 it is not drawn according to the actual ratio.

[0097] Referring to Figure 3 , schematically shows the anodes of 3 sub-pixels. For the convenience of description, the anodes of the 3 sub-pixels are respectively referred to as 013A, 013B, and 013C. Under the influence of the signal line 03 below it, the right side of the leftmost anode 013A is higher than the left side, resulting in a tilt towards Figure 3 the upper right in Figure 3The tilt in the upper left. The anode 013C located on the rightmost side does not tilt because there is no signal line 03 below it. Since the directions and degrees of tilting of the anodes of sub-pixels of different colors are inconsistent, the intensities of the light emitted by the three types of sub-pixels towards the left and right sides do not match. In this case, when observing the screen of the display substrate at a large viewing angle, a color shift phenomenon will occur. For example, when observing from one side, the displayed screen appears red, and when observing from the other side, the displayed screen appears cyan.

[0098] Figure 4 It is a schematic plan view of a display substrate according to some embodiments of the present disclosure. For example, the display substrate may be an array substrate for an OLED display panel.

[0099] Referring to Figure 4 , the display substrate may include a display area AA and a non-display area NA. For example, the display area AA and the non-display area NA may include multiple boundaries, such as Figure 4 AAS1, AAS2, AAS3, and AAS4 shown in Figure 4 . The display substrate may further include a driving circuit located in the non-display area NA. For example, the driving circuit may be located on at least one side of the display area AA. In the

[0100] It should be noted that although Figure 4 shows that the driving circuit is located on the left and right sides of the display area AA, however, the embodiments of the present disclosure are not limited thereto, and the driving circuit may be located at any suitable position in the non-display area NA.

[0101] For example, the driving circuit may adopt the GOA technology, i.e., Gate Driver on Array. In the GOA technology, the gate driving circuit is directly disposed on the array substrate to replace an external driving chip. Each GOA unit serves as a stage of shift register, and each stage of shift register is connected to a gate line. By sequentially outputting the turn-on voltage through each stage of shift register in turn, the line-by-line scanning of pixels is realized. In some embodiments, each stage of shift register may also be connected to multiple gate lines. In this way, the development trend of high resolution and narrow border of the display substrate can be adapted.

[0102] Referring to Figure 4 , on the display substrate, a left GOA circuit DA1, a plurality of pixels P in the display area AA, and a right GOA circuit DA2 are provided. The left GOA circuit DA1 and the right GOA circuit DA2 are respectively electrically connected to the display IC through signal lines, and the supply of the GOA signal is controlled by the display IC. The display IC is, for example, disposed on the lower side (the direction of human eye viewing) of the display substrate. The left GOA circuit DA1 and the right GOA circuit DA2 are also respectively electrically connected to each pixel through signal lines (such as gate lines GL) to supply driving signals to each pixel.

[0103] Figure 5 FIG. is a partial enlarged view of a portion I in Figure 4 of a display substrate according to some embodiments of the present disclosure, Figure 6 FIG. is a cross-sectional view of a display substrate according to some embodiments of the present disclosure taken along Figure 5 the line BB'. It should be noted that, in order to clearly show the relative positional relationship between the signal line, the planarization layer, and the anode, Figure 5 and Figure 6 some other film layer structures included in the display substrate are omitted in

[0104] It should also be noted that in the figure, the shape of the orthographic projection of the sub-pixel on the substrate is exemplarily shown as a rounded rectangle. However, the embodiments of the present disclosure are not limited thereto. For example, the shape of the orthographic projection of the sub-pixel on the substrate may be other shapes such as a rectangle, a hexagon, a pentagon, a square, a circle, etc. Moreover, the arrangement manner of the 3 sub-pixels in a pixel unit is not limited to the manner shown in Figure 5 .

[0105] With reference to Figure 4 , Figure 5 and Figure 6, the display substrate may include a substrate 1, and a plurality of pixel units P disposed on the substrate 1 and located in the display area AA. Each pixel unit P may include a plurality of sub-pixels. For example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For ease of understanding, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be respectively described as a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, the embodiments of the present disclosure are not limited thereto.

[0106] The plurality of sub-pixels are arranged in an array along the row direction X and the column direction Y on the substrate 1. It should be noted that although in the illustrated embodiment, the row direction X and the column direction Y are perpendicular to each other, the embodiments of the present disclosure are not limited thereto.

[0107] It should be understood that each sub-pixel includes a pixel driving circuit and a light-emitting device. For example, the light-emitting device may be an OLED light-emitting device, including an anode, an organic light-emitting layer, and a cathode arranged in a stacked manner. The pixel driving circuit may include a plurality of thin-film transistors.

[0108] With reference to Figure 5 and Figure 6 , the display substrate may include a first signal line 31 disposed on the substrate 1, a planarization layer 4 disposed on the substrate 1 and covering the first signal line 31, and an anode 5 disposed on the side of the planarization layer 4 away from the substrate 1.

[0109] The first signal line 31 is used to supply required signals to the sub-pixels located in the display area AA. Hereinafter, the signal lines will be described in more detail.

[0110] With reference to Figure 5 , the display substrate may further include a dummy pixel column and a signal line transfer structure 7 disposed between the dummy pixel column and the GOA circuit. The dummy pixel column includes a plurality of dummy sub-pixels (i.e., dummy pixels) DP. The dummy pixel column is located at an edge position of the display area AA close to the GOA circuit. The plurality of dummy sub-pixels DP are arranged along the column direction Y.

[0111] It should be noted that the signal line transfer structure will be described in more detail hereinafter with reference to the accompanying drawings.

[0112] As Figure 5 shown, the orthographic projection of the anode 5 on the substrate 1 and the orthographic projection of the first signal line 31 on the substrate 1 at least partially overlap. For example, the orthographic projection of the anode 5 on the substrate 1 covers at least a part of the orthographic projection of the first signal line 31 on the substrate 1.

[0113] For the column of sub-pixels closest to the GOA circuit, for example, Figure 5For the leftmost column of sub-pixels, the orthographic projection of the anode 5 of each sub-pixel on the substrate 1 at least partially overlaps with the orthographic projection of a pseudo sub-pixel DP on the substrate 1.

[0114] Specifically, the pseudo sub-pixel DP includes a padding structure 6. The padding structure 6 can be on the same layer as the first signal line 31, that is, the padding structure 6 can be made of the same material as the first signal line 31 and formed through the same lithography process. For example, the padding structure 6 and the first signal line 31 can be on the same layer as the source and drain electrodes of the thin film transistor. In this way, the thickness of the padding structure 6 and the first signal line 31 can be made substantially equal.

[0115] For Figure 5 the leftmost column of sub-pixels, the orthographic projection of the anode 5 of each sub-pixel on the substrate 1 at least partially overlaps with the orthographic projection of the padding structure 6 of the pseudo sub-pixel DP on the substrate 1.

[0116] In this article, for convenience of description, the sub-pixels located at the edge position of the display area close to the non-display area can be referred to as edge sub-pixels. For example, Figure 5 the leftmost column of sub-pixels includes multiple edge sub-pixels. In some embodiments, the boundary between the display area and the non-display area can be divided by the column of sub-pixels used for display when lit. For example, the boundary between the display area and the non-display area on the left border can be located to the left of the leftmost column of edge sub-pixels close to the non-display area, and the leftmost column of edge sub-pixels close to the non-display area is located in the display area. For example, the multiple sub-pixels include at least one row of edge sub-pixels located at the edge position of the display area close to the non-display area. For example, the at least one row of edge sub-pixels can include a column of edge sub-pixels, and / or, can include a row of edge sub-pixels. For another example, the at least one row of edge sub-pixels can include two columns of edge sub-pixels located on opposite sides, and / or, two rows of edge sub-pixels located on opposite sides. For example, in some embodiments, the display area can be generally rectangular in shape. In this case, the at least one row of edge sub-pixels can include two columns of sub-pixels that are basically located on opposite sides of the rectangle and closest to the non-display area. With reference to Figure 4 and Figure 5 , the at least one row of edge sub-pixels can include some edge sub-pixels arranged close to the boundaries AAS1 and AAS3, or rather, the at least one row of edge sub-pixels is located on the side where the GOA circuit is located. In Figure 4 and Figure 5 's example, the GOA circuits are located on the left and right sides. Correspondingly, the at least one row of edge sub-pixels includes edge sub-pixels located at the left edge and the right edge of the display area AA, that is, the at least one row of edge sub-pixels can include the leftmost column of sub-pixels and the rightmost column of sub-pixels.

[0117] That is, a first signal line 31 is disposed below one side of the anode 5 of each edge sub-pixel, and a padding structure 6 is disposed below the other side. Moreover, the first signal line 31 and the padding structure 6 have the same thickness. In this way, the flatness of the anode 5 can be improved, the inclination of the anode 5 can be avoided, and thus the color shift phenomenon of the display substrate can be improved.

[0118] The inventors have found through research that since the signal lines are concentrated at the edge of the display area, the inclination of the anode of the sub-pixel located at the edge of the display area is more obvious. In the embodiments of the present disclosure, by padding the anode of the sub-pixel located at the edge of the display area with the structure in the pseudo sub-pixel located at the edge of the display area, the inclination of the anode at the edge can be better improved, and thus the color shift phenomenon of the display substrate can be effectively improved.

[0119] Next, the signal line transfer structure included in the display substrate according to some exemplary embodiments of the present disclosure will be described in detail with reference to the drawings.

[0120] Figure 7A 、 Figure 8A and Figure 9A are respectively schematic diagrams of the signal line transfer structure of the display substrate according to some exemplary embodiments of the present disclosure. Referring to Figure 7A 、 Figure 8A and Figure 9A , the display substrate may include: at least a second signal line 32 located in the display area AA, a signal line lead 8 located in the non-display area NA, and at least a signal line transfer structure 7 located in the non-display area NA. One end of the second signal line 32 (e.g., the end far from the signal line lead) is connected to the pixel driving circuit of each sub-pixel. One end of the signal line lead 8 (e.g., the end far from the second signal line 32) is connected to the GOA circuit. One end of the signal line transfer structure 7 is connected to the other end of the second signal line 32, and the other end of the signal line transfer structure 7 is connected to the other end of the signal line lead 8.

[0121] In the embodiments of the present disclosure, the second signal line 32 and the signal line lead 8 are two independent parts. Here, the second signal line 32 and the signal line lead 8 being two independent parts means that the second signal line 32 and the signal line lead 8 are isolated from each other, that is to say, the orthographic projections of the second signal line 32 and the signal line lead 8 on the substrate 1 do not contact each other.

[0122] In this way, even if a large amount of static electricity is accumulated on the signal line lead 8 in the non-display area NA, since the second signal line 32 and the signal line lead 8 are set as two independent parts in the embodiment of the present disclosure, before the second signal line 32 and the signal line lead 8 are connected through the above-mentioned signal line transfer structure 7, the large amount of static electricity accumulated on the signal line lead 8 in the non-display area NA will not be transferred to the second signal line 32 in the display area AA, thereby reducing the probability of electronic devices in the display area AA that are electrically connected to the above-mentioned second signal line 32 (such as the transistors T2 and T3 in the pixel driving circuit mentioned later) being damaged due to electrostatic shock, thereby improving the yield of the product.

[0123] In some exemplary embodiments, at least one of the second signal line 32 and the signal line lead 8 is located at a different layer from the signal line transfer structure 7 .

[0124] For example, the second signal line 32 and the signal line lead 8 can be located in the same layer, that is, the two are made of the same material and are formed by one composition process. Optionally, the second signal line 32 and the signal line lead 8 can be located in different layers, that is, the two need to be formed separately by two composition processes. The embodiments of the present disclosure are not limited to this, and the setting method can be selected according to the type of display substrate and the type of signal line, as long as the signal line switching structure 7, the second signal line 32 and the signal line lead 8 are not in the same layer and are not directly connected together, that is, the signal line switching structure 7, the second signal line 32 and the signal line lead 8 are distributed in at least two layers.

[0125] Figure 7B is along Figure 7A A cross-sectional view taken along line CC' in FIG. Figure 7A and Figure 7B The second signal line 32 and the signal line lead 8 are located in the same layer, and they are located in a different layer from the signal line transfer structure 7. An insulating layer 101 is provided between the layer where the second signal line 32 and the signal line lead 8 are located and the layer where the signal line transfer structure 7 is located. The insulating layer 101 is formed with a first via hole V1 and a second via hole V2.

[0126] For example, the second signal line 32 and the signal line lead 8 can be located in the same layer as the source and drain of the thin film transistor, that is, they can be composed of the material that forms the source and drain. The signal line transfer structure 7 can be located on the side of the layer where the second signal line 32 and the signal line lead 8 are located away from the base substrate 1. The signal line transfer structure 7 can also be composed of, for example, a material that forms the source and drain. Of course, the embodiments of the present disclosure are not limited to this, and the second signal line 32, the signal line lead 8 and the signal line transfer structure 7 can also be composed of other conductive materials. The insulating layer 101 can be composed of an insulating material such as silicon nitride, silicon oxide or silicon oxynitride, and the insulating layer 101 can have a single film layer structure or a stacked structure composed of multiple film layers.

[0127] The first via hole V1 penetrates the insulating layer 101 to expose a portion of the second signal line 32. The second via hole V2 penetrates the insulating layer 101 to expose a portion of the signal line lead 8. A portion of the signal line transfer structure 7 is formed in the first via hole V1 to form a first conductive plug 71, and the signal line transfer structure 7 contacts the second signal line 32 through the first conductive plug 71. Another portion of the signal line transfer structure 7 is formed in the second via hole V2 to form a second conductive plug 72, and the signal line transfer structure 7 contacts the signal line lead 8 through the second conductive plug 72.

[0128] Figure 8B is along Figure 8A A cross-sectional view taken along line CC' in FIG. Figure 8A and Figure 8B The second signal line 32 and the signal line lead 8 are located in different layers, and the signal line transfer structure 7 and the signal line lead 8 can be located in the same layer.

[0129] One end of the signal line transfer structure 7 is directly connected to the signal line lead 8. Optionally, the signal line transfer structure 7 and the signal line lead 8 may be continuously extended, that is, they are an integral structure.

[0130] An insulating layer 101 is provided between the layer where the signal line transfer structure 7 and the signal line lead 8 are located and the second signal line 32. The insulating layer 101 is provided with a first via hole V1.

[0131] The first via hole V1 penetrates the insulating layer 101 to expose a portion of the second signal line 32 . A portion of the signal line transfer structure 7 is formed in the first via hole V1 to form a first conductive plug 71 , through which the signal line transfer structure 7 contacts the second signal line 32 .

[0132] Figure 9B is along Figure 9A A cross-sectional view taken along line CC' in FIG. Figure 9A and Figure 9B, the second signal line 32 and the signal line lead 8 are located on different layers, and the signal line transfer structure 7 can be on the same layer as the second signal line 32.

[0133] One end of the signal line transfer structure 7 is directly connected to the second signal line 32. Optionally, the signal line transfer structure 7 and the second signal line 32 can be continuously extended, that is, they are an integral structure.

[0134] An insulating layer 101 is provided between the layer where the signal line transfer structure 7 and the second signal line 32 are located and the signal line lead 8. A second via V2 is provided in the insulating layer 101.

[0135] The second via V2 penetrates the insulating layer 101 to expose a part of the signal line lead 8. A part of the signal line transfer structure 7 is formed in the second via V2 to form a second conductive plug 72, and the signal line transfer structure 7 contacts the signal line lead 8 through the second conductive plug 72.

[0136] Figure 10 is a partial enlarged view of the display substrate according to some embodiments of the present disclosure at Figure 4 Part I in, Figure 11 is a cross-sectional view of the display substrate taken along the line DD’ according to some embodiments of the present disclosure. It should be noted that, in order to clearly show the relative positional relationship between the signal line, the planarization layer, and the anode, Figure 10 and Figure 10 and Figure 11 Some other film layer structures included in the display substrate are omitted in.

[0137] Next, the differences between this embodiment and the above-mentioned embodiments with reference to Figure 4 and Figure 5 will be mainly described. For the same parts of the two embodiments, reference can be made to the above description and will not be repeated here.

[0138] Referring to Figure 4 , Figure 10 and Figure 11 , in some embodiments of the present disclosure, the above-mentioned dummy pixel columns are omitted. That is, no dummy pixel columns are provided between the GOA circuit and the pixel unit P located in the display area AA. In this way, the width of the non-display area NA can be further reduced, which is beneficial to realizing a narrow-border display panel and display device.

[0139] Combined with reference to Figure 10 and Figure 11 , the display substrate may include a first signal line 31 provided on the substrate 1, a planarization layer 4 provided on the substrate 1 and covering the first signal line 31, and an anode 5 provided on the side of the planarization layer 4 away from the substrate 1.

[0140] The display substrate may further include a signal line transfer structure 7 disposed at an edge of the display area AA close to the GOA circuit. Figure 10 As shown, a plurality of signal line switching structures 7 may be provided, and the plurality of signal line switching structures 7 are arranged along the column direction Y.

[0141] like Figure 10 As shown, the edge sub-pixels include at least one column of edge sub-pixels, and the arrangement direction of the at least one column of edge sub-pixels is substantially the same as the extension direction of the first signal line 31. The signal line switching structure 7 is substantially the same as the extension direction of the first signal line 31, and the arrangement direction of the plurality of signal line switching structures 7 is substantially the same as the extension direction of the first signal line 31.

[0142] like Figure 10 As shown, the orthographic projection of the anode 5 on the substrate 1 at least partially overlaps with the orthographic projection of the first signal line 31 on the substrate 1 , for example, the orthographic projection of the anode 5 on the substrate 1 covers the orthographic projection of the first signal line 31 on the substrate 1 .

[0143] For a column of sub-pixels closest to the GOA circuit, for example, Figure 10 For the leftmost column of sub-pixels, that is, for multiple edge sub-pixels, the orthographic projections of the anodes 5 of the respective edge sub-pixels on the base substrate 1 at least partially overlap with the orthographic projections of the multiple signal line switching structures 7 on the base substrate 1 .

[0144] It should be noted that, for sub-pixels other than the plurality of edge sub-pixels, for example, the plurality of sub-pixels located inside the display area, they are all located between two adjacent first signal lines 31. That is, the orthographic projection of one side portion of the anode 5 of a sub-pixel on the base substrate 1 at least partially overlaps with the orthographic projection of one first signal line 31 on the base substrate 1, and the orthographic projection of the opposite side portion of the anode 5 of the sub-pixel on the base substrate 1 at least partially overlaps with the orthographic projection of another adjacent first signal line 31 on the base substrate 1.

[0145] For example, the at least one row of edge sub-pixels may include a plurality of red sub-pixels and a plurality of blue sub-pixels alternately arranged in the column direction. The orthographic projection of the anode 5 of each green sub-pixel on the substrate 1 does not overlap with the orthographic projection of the signal line switching structure 7 on the substrate 1. For example, as described above, the orthographic projection of the anode 5 of each green sub-pixel on the substrate 1 may at least partially overlap with the orthographic projection of two adjacent first signal lines 31 on the substrate 1.

[0146] Specifically, refer to Figure 11, a first signal line 31 is disposed below one side of the anode 5 of each edge sub-pixel, and a signal line transfer structure 7 is disposed below the other side. More specifically, the anode 5 of each edge sub-pixel includes a first edge portion 51 close to the non-display area NA and a second edge portion 52 far from the non-display area NA (the first edge portion 51 and the second edge portion 52 will be described in more detail below). The orthographic projection of the first edge portion 51 on the substrate 1 at least partially overlaps with the orthographic projection of the signal line transfer structure 7 on the substrate 1, and the orthographic projection of the second edge portion 52 on the substrate 1 at least partially overlaps with the orthographic projection of the first signal line 31 on the substrate 1.

[0147] For example, the first signal line 31 and the signal line transfer structure 7 are located on the same layer, and they can be located on the same layer as the source and drain electrodes of the thin film transistor, that is, they can be formed of the material constituting the source and drain electrodes and are formed by the same patterning process. In this way, the thicknesses of the first signal line 31 and the signal line transfer structure 7 are equal, that is, the thickness of the signal line transfer structure 7 in the direction perpendicular to the substrate 1 is equal to the thickness of the first signal line 31 in the direction perpendicular to the substrate 1.

[0148] Continue to refer to Figure 11 , the planarization layer 4 includes a first surface portion 41 and a second surface portion 42. The orthographic projection of the first surface portion 41 on the substrate 1 at least partially overlaps with the orthographic projection of the signal line transfer structure 7 on the substrate 1, and the orthographic projection of the second surface portion 42 on the substrate 1 at least partially overlaps with the orthographic projection of the first signal line 31 on the substrate 1. The distance between the first surface portion 41 and the substrate 1 in the direction perpendicular to the substrate 1 is substantially equal to the distance between the second surface portion 42 and the substrate 1 in the direction perpendicular to the substrate 1, or the ratio of the two distances is approximately 0.8 to 1.2.

[0149] It should be noted that in Figure 11In the figure, the relative position relationship between the signal line switching structure, the signal line, the planarization layer and the anode is schematically shown. Due to the actual processing technology, the first surface portion 41 and the second surface portion 42 of the planarization layer 4 may have a height error. At this time, the distance between the first surface portion 41 and the substrate substrate 1 in the direction perpendicular to the substrate substrate 1 can be understood as the maximum distance between the first surface portion 41 and the substrate substrate 1 in the direction perpendicular to the substrate substrate 1, and the distance between the second surface portion 42 and the substrate substrate 1 in the direction perpendicular to the substrate substrate 1 can be understood as the maximum distance between the second surface portion 42 and the substrate substrate 1 in the direction perpendicular to the substrate substrate 1; or, the distance between the first surface portion 41 and the substrate substrate 1 in the direction perpendicular to the substrate substrate 1 can be understood as the average distance between the first surface portion 41 and the substrate substrate 1 in the direction perpendicular to the substrate substrate 1, and the distance between the second surface portion 42 and the substrate substrate 1 in the direction perpendicular to the substrate substrate 1 can be understood as the average distance between the second surface portion 42 and the substrate substrate 1 in the direction perpendicular to the substrate substrate 1.

[0150] In this way, the flatness of the anode 5 can be improved, so that the distance between the first edge portion 51 of the anode 5 and the base substrate 1 in a direction perpendicular to the base substrate 1 is substantially equal to the distance between the second edge portion 52 and the base substrate 1 in a direction perpendicular to the base substrate 1. Therefore, the anode 5 can be prevented from tilting, thereby improving the color shift phenomenon of the display substrate.

[0151] Based on the above description, the distance between the first edge portion 51 of the anode 5 and the substrate 1 in the direction perpendicular to the substrate 1 can be understood as the maximum distance between the first edge portion 51 of the anode 5 and the substrate 1 in the direction perpendicular to the substrate 1, and the distance between the second edge portion 52 and the substrate 1 in the direction perpendicular to the substrate 1 can be understood as the maximum distance between the second edge portion 52 and the substrate 1 in the direction perpendicular to the substrate 1. Alternatively, the distance between the first edge portion 51 of the anode 5 and the substrate 1 in the direction perpendicular to the substrate 1 can be understood as the average distance between the first edge portion 51 of the anode 5 and the substrate 1 in the direction perpendicular to the substrate 1, and the distance between the second edge portion 52 and the substrate 1 in the direction perpendicular to the substrate 1 can be understood as the average distance between the second edge portion 52 and the substrate 1 in the direction perpendicular to the substrate 1.

[0152] In addition, in the embodiments of the present disclosure, a signal line transfer structure is used to pad the anode and the dummy pixel column is omitted, which can improve the flatness of the anode and reduce the width of the non-display area, thereby facilitating the realization of a display device with a narrow frame.

[0153] Next, taking a 7T1C pixel driving circuit as an example, the structure of the pixel driving circuit will be described in detail. However, the embodiments of the present disclosure are not limited to the 7T1C pixel driving circuit. Without conflict, other known pixel driving circuit structures can be applied to the embodiments of the present disclosure.

[0154] Figure 12 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure. As Figure 12 shown, the pixel driving circuit may include: a plurality of signal lines 61, 62, 63, 64, 65, 66, and 67, a plurality of thin film transistors T1, T2, T3, T4, T5, T6, and T7, and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (i.e., OLED).

[0155] The plurality of thin film transistors include a driving thin film transistor T1, a switching thin film transistor T2, a compensating thin film transistor T3, an initializing thin film transistor T4, a first light emitting control thin film transistor T5, a second light emitting control thin film transistor T6, and a bypass thin film transistor T7.

[0156] The plurality of signal lines include: a scan signal line 61 for transmitting a scan signal Sn, a reset control signal line 62 for transmitting a reset control signal Sn-1 to the initializing thin film transistor T4, a light emitting control line 63 for transmitting a light emitting control signal En to the first light emitting control thin film transistor T5 and the second light emitting control thin film transistor T6, a data line 64 for transmitting a data signal Dm, a driving voltage line 65 for transmitting a driving voltage ELVDD, an initializing voltage line 66 for transmitting an initializing voltage Vint for initializing the driving thin film transistor T1, and a power supply line 67 for transmitting an ELVSS voltage.

[0157] The gate G1 of the driving thin film transistor T1 is electrically connected to one end Cst1 (hereinafter referred to as the first capacitor electrode) of the storage capacitor Cst. The source S1 of the driving thin film transistor T1 is electrically connected to the driving voltage line 65 via the first light emitting control thin film transistor T5. The drain D1 of the driving thin film transistor T1 is electrically connected to the anode of the OLED via the second light emitting control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 to supply a driving current Id to the OLED.

[0158] The gate G2 of the switching thin-film transistor T2 is electrically connected to the scan signal line 61, the source S2 of the switching thin-film transistor T2 is electrically connected to the data line 64, and the drain D2 of the switching thin-film transistor T2 is electrically connected to the driving voltage line 65 via the first light-emitting control thin-film transistor T5 and is also electrically connected to the source S1 of the driving thin-film transistor T1. The switching thin-film transistor T2 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to perform a switching operation to transmit the data signal Dm transmitted to the data line 64 to the source S1 of the driving thin-film transistor T1.

[0159] The gate G3 of the compensation thin-film transistor T3 is electrically connected to the scan signal line 61, the source S3 of the compensation thin-film transistor T3 is electrically connected to the anode of the OLED via the second light-emitting control thin-film transistor T6 and is also electrically connected to the drain D1 of the driving thin-film transistor T1. And the drain D3 of the compensation thin-film transistor T3 is electrically connected to one end (i.e., the first capacitive electrode) Cst1 of the storage capacitor Cst, the drain D4 of the initialization thin-film transistor T4, and the gate G1 of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to connect the gate G1 and the drain D1 of the driving thin-film transistor T1 to each other, thereby performing diode connection of the driving thin-film transistor T1.

[0160] The gate G4 of the initialization thin-film transistor T4 is electrically connected to the reset control signal line 62, the source S4 of the initialization thin-film transistor T4 is electrically connected to the initialization voltage line 66. And the drain D4 of the initialization thin-film transistor T4 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D3 of the compensation thin-film transistor T3, and the gate G1 of the driving thin-film transistor T1. The initialization thin-film transistor T4 is turned on according to the reset control signal Sn-1 transmitted through the reset control signal line 62 to transmit the initialization voltage Vint to the gate G1 of the driving thin-film transistor T1, thereby performing an initialization operation to initialize the voltage of the gate G1 of the driving thin-film transistor T1.

[0161] The gate G5 of the first light-emitting control thin-film transistor T5 is electrically connected to the light-emitting control line 63, the source S5 of the first light-emitting control thin-film transistor T5 is electrically connected to the driving voltage line 65. And the drain D5 of the first light-emitting control thin-film transistor T5 is electrically connected to the source S1 of the driving thin-film transistor T1 and the drain D2 of the switching thin-film transistor T2.

[0162] The gate G6 of the second light-emitting control thin-film transistor T6 is electrically connected to the light-emitting control line 63, the source S6 of the second light-emitting control thin-film transistor T6 is electrically connected to the drain D1 of the driving thin-film transistor T1 and the source S3 of the compensation thin-film transistor T3. And the drain D6 of the second light-emitting control thin-film transistor T6 is electrically connected to the anode of the OLED. The first light-emitting control thin-film transistor T5 and the second light-emitting control thin-film transistor T6 are concurrently (e.g., simultaneously) turned on according to the light-emitting control signal En transmitted through the light-emitting control line 63 to transmit the driving voltage ELVDD to the OLED, thereby allowing the driving current Id to flow into the OLED.

[0163] The bypass thin-film transistor T7 includes: a gate G7 connected to the reset control signal line 62; a source S7 connected to the drain D6 of the second light-emitting control thin-film transistor T6 and the anode of the OLED; and a drain D7 connected to the initialization voltage line 66. The bypass thin-film transistor T7 transmits the reset control signal Sn-1 from the reset control signal line 62 to the gate G7.

[0164] The other end (hereinafter referred to as the second capacitor electrode) Cst2 of the storage capacitor Cst is electrically connected to the driving voltage line 65, and the cathode of the OLED is electrically connected to the power supply line 67 to receive the common voltage ELVSS. Accordingly, the OLED receives the driving current Id from the driving thin-film transistor T1 to emit light, thereby displaying an image.

[0165] It should be noted that in Figure 12 , each of the thin-film transistors T1, T2, T3, T4, T5, T6, and T7 has a single-gate structure. However, the embodiments of the present disclosure are not limited thereto, and at least some of the thin-film transistors T1, T2, T3, T4, T5, T6, and T7 may have a double-gate structure. In Figure 12 , each of the thin-film transistors T1, T2, T3, T4, T5, T6, and T7 is a p-channel field-effect transistor. However, the embodiments of the present disclosure are not limited thereto, and at least some of the thin-film transistors T1, T2, T3, T4, T5, T6, and T7 may be n-channel field-effect transistors.

[0166] In operation, during the initialization phase, the reset control signal Sn-1 having a low level is supplied through the reset control signal line 62. Subsequently, the initialization thin-film transistor T4 is turned on based on the low level of the reset control signal Sn-1, and the initialization voltage Vint from the initialization voltage line 66 is transmitted to the gate G1 of the driving thin-film transistor T1 through the initialization thin-film transistor T4. Therefore, the driving thin-film transistor T1 is initialized due to the initialization voltage Vint.

[0167] During the data programming phase, a scan signal Sn having a low level is supplied through a scan signal line 61. Subsequently, the switching thin film transistor T2 and the compensation thin film transistor T3 are turned on based on the low level of the scan signal Sn. Accordingly, the driving thin film transistor T1 is placed in a diode-connected state and biased in the forward direction through the turned-on compensation thin film transistor T3.

[0168] Subsequently, a compensation voltage Dm+Vth obtained by subtracting the threshold voltage Vth of the driving thin film transistor T1 from the data signal Dm supplied via the data line 64 (for example, Vth is a negative value) is applied to the gate G1 of the driving thin film transistor T1. Subsequently, the driving voltage ELVDD and the compensation voltage Dm+Vth are applied to the two terminals of the storage capacitor Cst such that charges corresponding to the voltage difference between the corresponding terminals are stored in the storage capacitor Cst.

[0169] During the light emitting phase, a light emission control signal En from a light emission control line 63 changes from a high level to a low level. Subsequently, during the light emitting phase, the first light emission control thin film transistor T5 and the second light emission control thin film transistor T6 are turned on based on the low level of the light emission control signal En.

[0170] Subsequently, a driving current is generated based on the difference between the voltage of the gate G1 of the driving thin film transistor T1 and the driving voltage ELVDD. A driving current Id corresponding to the difference between the driving current and the bypass current is supplied to the OLED through the second light emission control thin film transistor T6.

[0171] During the light emitting phase, based on the current-voltage relationship of the driving thin film transistor T1, the gate-source voltage of the driving thin film transistor T1 is maintained at (Dm+Vth)-ELVDD due to the storage capacitor Cst. The driving current Id is proportional to (Dm-ELVDD) 2 Accordingly, the driving current Id can be unaffected by variations in the threshold voltage Vth of the driving thin film transistor T1.

[0172] Figure 13 is a plan view showing an exemplary embodiment of a sub-pixel in a display area AA of a display substrate according to some exemplary embodiments of the present disclosure. Figures 14 to 17 is a view showing Figure 13 some of the film layers of an exemplary embodiment of the sub-pixel in Figures 14 to 17 For example, a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer are schematically shown, respectively.

[0173] With reference to Figures 12 to 17, the sub-pixels include a scan signal line 61, a reset control signal line 62, a light emission control line 63, and an initialization voltage line 66 arranged along the row direction to respectively apply a scan signal Sn, a reset control signal Sn-1, a light emission control signal En, and an initialization voltage Vint to the sub-pixels. The sub-pixels may include a data line 64 and a driving voltage line 65 that cross the scan signal line 61, the reset control signal line 62, the light emission control line 63, and the initialization voltage line 66 to respectively apply a data signal Dm and a driving voltage ELVDD to the sub-pixels. The sub-pixels may include: a driving thin film transistor T1, a switching thin film transistor T2, a compensating thin film transistor T3, an initialization thin film transistor T4, a first light emission control thin film transistor T5, a second light emission control thin film transistor T6, a bypass thin film transistor T7, a storage capacitor Cst, and an organic light emitting diode OLED.

[0174] The driving thin film transistor T1, the switching thin film transistor T2, the compensating thin film transistor T3, the initialization thin film transistor T4, the first light emission control thin film transistor T5, the second light emission control thin film transistor T6, and the bypass thin film transistor T7 may be formed along the Figure 10 active layer as shown in. The active layer may have a curved or bent shape and may include a driving active layer 20a corresponding to the driving thin film transistor T1, a switching active layer 20b corresponding to the switching thin film transistor T2, a compensating active layer 20c corresponding to the compensating thin film transistor T3, an initialization active layer 20d corresponding to the initialization thin film transistor T4, an operation control active layer 20e corresponding to the first light emission control thin film transistor T5, a light emission control active layer 20f corresponding to the second light emission control thin film transistor T6, and a bypass active layer 20g corresponding to the bypass thin film transistor T7.

[0175] The active layer may include, for example, polysilicon and, for example, includes a channel region, a source region, and a drain region. The channel region may not be doped or may have a doping type different from that of the source region and the drain region, and thus has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region and are doped with impurities and thus have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0176] The driving thin-film transistor T1 includes a driving active layer 20a and a driving gate G1. The driving active layer 20a includes a driving source region 203a, a driving drain region 205a, and a driving channel region 201a connecting the driving source region 203a and the driving drain region 205a. The driving source region 203a and the driving drain region 205a extend in two opposite directions with respect to the driving channel region 201a. The driving source region 203a of the driving thin-film transistor T1 is connected to the switching drain region 205b and the operation control drain region 205e. The driving drain region 205a is connected to the compensation source region 203c and the light emission control source region 203f. The gate G1 of the driving thin-film transistor T1 is connected to the compensation gate G3 of the compensation thin-film transistor T3 through vias VAH1 and VAH2 and a first connection line 68.

[0177] The switching thin-film transistor T2 includes a switching active layer 20b and a switching gate G2. The switching active layer 20b includes a switching channel region 201b, a switching source region 203b, and a switching drain region 205b. The switching thin-film transistor T2 serves as a switching device for selecting a light-emitting target sub-pixel. The switching gate G2 is connected to the scanning signal line 61, the switching source region 203b is connected to the data line 64 through a via VAH4, and the switching drain region 205b is connected to the driving thin-film transistor T1 and the first light emission control thin-film transistor T5.

[0178] The compensation thin-film transistor T3 includes a compensation active layer 20c and a compensation gate G3. The compensation active layer 20c includes a compensation channel region 201c, a compensation source region 203c, and a compensation drain region 205c.

[0179] The initialization thin-film transistor T4 includes an initialization active layer 20d and an initialization gate G4. The initialization active layer 20d includes an initialization channel region 201d, an initialization source region 203d, and an initialization drain region 205d. The initialization source region 203d is connected to the initialization voltage line 66 through a via VAH5.

[0180] The first light emission control thin-film transistor T5 includes an operation control active layer 20e and an operation control gate G5. The operation control active layer 20e includes an operation control channel region 201e, an operation control source region 203e, and an operation control drain region 205e. The operation control source region 203e can be connected to the driving voltage line 65 through a via VAH6.

[0181] The second light emission control thin-film transistor T6 includes a light emission control active layer 20f and a light emission control gate G6, and the light emission control active layer 20f includes a light emission control channel region 201f, a light emission control source region 203f, and a light emission control drain region 205f. The light emission control drain region 205f can be connected to the anode of the OLED through a via VAH7.

[0182] The bypass thin film transistor T7 includes a bypass active layer 20g and a bypass gate G7. The bypass active layer 20g includes a bypass source region 203g, a bypass drain region 205g, and a bypass channel region 201g. The bypass drain region 205g is connected to the initialization source region 203d of the initialization thin film transistor T4. The bypass drain region 205g can be connected to the initialization voltage line 66 through a via VAH8 and a second connection line 69.

[0183] As Figures 12 to 17 shown, some signal lines are schematically shown. For example, scan signal lines 61, reset control signal lines 62, emission control signal lines 63, and initialization voltage lines 66 arranged along the row direction to respectively apply a scan signal Sn, a reset control signal Sn-1, an emission control signal En, and an initialization voltage Vint to the sub-pixels, data lines 64 and drive voltage lines 65 that cross the scan signal lines 61, reset control signal lines 62, emission control signal lines 63, and initialization voltage lines 66 to respectively apply a data signal Dm and a drive voltage ELVDD to the sub-pixels.

[0184] In an exemplary embodiment of the present disclosure, the GOA circuit may include a first scan driving circuit. For example, the first scan driving circuit may be an EM GOA circuit for sending an emission control signal En. As Figure 18 shown, a circuit diagram of the first scan driving circuit according to some exemplary embodiments of the present disclosure is schematically shown. The first scan driving circuit includes a first voltage signal line VGH, a second voltage signal line VGL, a first clock signal line CK, a second clock signal line CB, and a signal output line E0. The first scan driving circuit further includes a plurality of shift register units.

[0185] As Figure 18 shown, at least one of the plurality of shift register units may include a first capacitor C1, an output capacitor C2, an output reset capacitor C3, an output transistor M10, an output reset transistor M9, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8.

[0186] The gate MG10 of the output transistor M10 is coupled to the first plate C2a of the output capacitor C2. The first electrode MS10 of the output transistor M10 is coupled to the second voltage signal line VGL. The second electrode MD10 of the output transistor M10 is coupled to the signal output line E0.

[0187] The gate MG9 of the output reset transistor M9 is coupled to the first plate C3a of the output reset capacitor C3. The first electrode MS9 of the output reset transistor M9 is coupled to the second plate C3b of the output reset capacitor C3. The second electrode MD9 of the output reset transistor M9 is coupled to the signal output line E0.

[0188] The second plate C3b of the output reset capacitor C3 is coupled to the first voltage signal line VGH; the second plate C2b of the output capacitor C2 is coupled to the second clock signal line CB.

[0189] The first electrode MS1 of the first transistor M1 is coupled to the second clock signal line CB. The second electrode MD1 of the first transistor M1 and the first electrode MS2 of the second transistor M2 are respectively coupled to the second plate C1b of the first capacitor C1. The gate MG1 of the first transistor M1 is coupled to the first plate C1a of the first capacitor C1.

[0190] The gate MG2 of the second transistor M2 and the gate MG7 of the seventh transistor M7 are respectively coupled to the first clock signal line CB. The second electrode MD2 of the second transistor M2 is coupled to the second electrode MD3 of the third transistor M3; the first electrode MS2 of the second transistor M2 is coupled to the second plate C1b of the first capacitor.

[0191] The gate MG3 of the third transistor M3 is coupled to the gate MG10 of the output transistor M10. The first electrode MS3 of the third transistor M3 is coupled to the first voltage signal line VGH.

[0192] The gate MG4 of the fourth transistor M4 and the gate MG5 of the fifth transistor M5 are both coupled to the first clock signal line CK. The first electrode MS4 of the fourth transistor M4 and the first electrode MS10 of the output transistor M10 are both coupled to the second voltage signal line VGL. The second electrode MD4 of the fourth transistor M4 is coupled to the second electrode MD6 of the sixth transistor M6.

[0193] The gate MG5 of the fifth transistor M5 is coupled to the first clock signal line CK. The second electrode MD5 of the fifth transistor M5 is coupled to the gate MG6 of the sixth transistor M6; the first electrode MS5 of the fifth transistor M5 is coupled to the input signal terminal E1.

[0194] The first electrode MS1 of the sixth transistor M6 and the gate MG4 of the fourth transistor M4 are both coupled to the first clock signal line CK, and the second electrode MD6 of the sixth transistor M6 is coupled to the second electrode MD4 of the fourth transistor M4; the gate MG6 of the sixth transistor M6 is coupled to the second electrode MD1 of the fifth transistor.

[0195] The gate MG7 of the seventh transistor M7 and the second plate C2b of the output capacitor C2 are both coupled to the second clock signal line CB, the first electrode MS7 of the seventh transistor M7 is coupled to the second electrode MD8 of the eighth transistor M8, and the second electrode MD7 of the seventh transistor M7 is coupled to the gate MG6 of the sixth transistor M6.

[0196] The gate MG8 of the eighth transistor M8 is coupled to the gate MG1 of the first transistor M1, and the first electrode MS8 of the eighth transistor M8 is coupled to the first voltage signal line VGH.

[0197] In Figure 18 In the illustrated embodiment of the shift register unit, all the transistors are p-type transistors, but the embodiments of the present disclosure are not limited thereto.

[0198] In the embodiments of the present disclosure, the first electrode of the transistor may be the source electrode, and the second electrode of the transistor may be the drain electrode; or, the first electrode of the transistor may be the drain electrode, and the second electrode of the transistor may be the source electrode.

[0199] In Figure 18 , the one labeled N1 is the first node, the one labeled N2 is the second node, the one labeled N3 is the third node, and the one labeled N4 is the fourth node.

[0200] In Figure 18 In the illustrated embodiment, the first voltage signal line VGH may provide a high voltage VGH, and the second voltage signal line VGL may provide a low voltage VGL, but it is not limited thereto.

[0201] Figure 19 is Figure 18 The timing diagram of the scanning drive circuit described above. With reference to Figure 18 and Figure 19 , an exemplary description of the working process of the shift register unit as shown in Figure 18 is given.

[0202] During the first time period P1, E1 provides a high level, CK provides a low level, CB provides a high level, M5 and M4 are turned on, the potential of N1 is high, M6 is cut off, the potential of N2 is low, so M7, M3, and M10 are cut off, and M8 and M1 are turned on; at this time, the potential of N3 is high, and CB provides a high level, so M2 is cut off; since the voltage across the capacitor does not change abruptly, the potential of N4 remains at the high level of the previous frame, M9 is cut off, and the potential of the light emission control signal output by E0 remains at the low level of the previous frame.

[0203] During the second time period P2, both E1 and CK provide high levels, CB provides a low level, M5, M6, and M4 are all cut off, the potential of N1 remains high, the potential of N2 remains low, M7, M8, and M1 are all turned on, the potential of N3 changes from high to low, M2 is turned on, the potential of N4 is low, M9 is turned on, and E0 outputs a high level; M3 and M10 are both cut off.

[0204] During the third time period P3, both E1 and CB provide high levels, CK provides a low level, M5 and M4 are both turned on, the potential of N1 is high, the potential of N2 is low, M6 and M7 are both cut off, M8 and M1 are both turned on, the potential of N3 changes from the low level of the previous time period to high, M2 is cut off, the potential of N4 remains low, M9 is turned on, and E0 outputs a high level; M3 and M10 are both cut off.

[0205] During the fourth time period P4, both E1 and CB provide low levels, CK provides a high level, M5 and M4 are both cut off, the potential of N1 is high, M6 is cut off, the potential of N2 remains low, M7, M8, and M1 are all turned on, the voltage of N3 jumps to low, M2 is turned on, the potential of N4 is low, M9 is turned on, and E0 outputs a high level; M3 and M10 are both cut off.

[0206] During the fifth time period P5, both E1 and CK provide low levels, CB provides a high level, M5, M6, and M4 are all turned on, the potentials of N1 and N2 are both low, M7 is cut off, M7 and M1 are both turned on, the voltage of N3 becomes high, M2 is cut off, M3 is turned on, the voltage of N4 becomes high, M9 is cut off, M10 is turned on, and E0 outputs a low level.

[0207] During the sixth time period P6, the E1 and CB signals are low, CK is high, M1 and M3 are cut off, the node N1 remains low, M2 is turned on, the voltage of the N2 node is high, M4 and M5 are turned on, M6 is cut off, the N3 node is high, M7 and M8 are turned on, the N4 node is high, M9 is cut off, M10 is turned on, and the EouM output is low.

[0208] In the seventh time period P7, both E1 and CK provide low levels, CB provides a high level, M5, M6, and M4 are all turned on, the potentials of N1 and N2 are both low levels, M7 is cut off, M8 and M1 are both turned on, the potential of N3 is high level, M2 is cut off, M3 is turned on, the potential of N4 is high level, M9 is cut off, M10 is turned on, and E0 outputs a low level.

[0209] In the eighth time period P8, both E1 and CB provide low levels, CK provides a high level, M5 and M4 are both cut off, the potential of N1 is maintained at a low level, M6 is turned on, the potential of N2 is high level, M7 is turned on, M8 and M1 are both cut off, the potential of N3 is high level, M2 and M3 are both turned on, the voltage of N4 is high level, M9 is cut off, M10 is turned on, and E0 outputs a low level.

[0210] After the sixth time period, M3 remains turned on, M9 remains cut off, M5 periodically charges C2, the potential of N1 remains at a low level, M10 remains turned on, and E0 outputs a low level until the next frame when E1 receives an input signal.

[0211] In an exemplary embodiment of the present disclosure, the GOA circuit may include a second scan driving circuit. For example, the second scan driving circuit may be a GATE GOA circuit for sending a scan signal Sn and / or a reset control signal Sn-1. For example, the GATE GOA circuits may correspond one by one to the pixel rows, that is, one GATE GOA circuit corresponds to one row of pixels. At this time, the signal output by one GATE GOA circuit may be used as the scan signal for one row of pixels corresponding to the GATE GOA circuit of this row, or may be used as the reset control signal for the next row of pixels. In other words, the scan signal for a certain row of pixels comes from the signal output by the GATE GOA circuit corresponding to this row of pixels, and the reset control signal for this row of pixels comes from the signal output by the GATE GOA circuit corresponding to the previous row of pixels. It should be noted that for the EM GOA circuit, a two-row driving or four-row driving method may be adopted, that is, the output signal of one EM GOA circuit can be used to drive two rows or four rows of pixels.

[0212] As Figure 20 shown, it schematically shows the circuit diagram of the second scan driving circuit according to some exemplary embodiments of the present disclosure. The second scan driving circuit includes a first voltage signal line VGH, a second voltage signal line VGL, a third clock signal line GCK, a fourth clock signal line GCB, and a signal output line GO. The second scan driving circuit further includes a plurality of shift register units.

[0213] As Figure 20As shown, at least one of the multiple shift register units may include a first capacitor C1, a second capacitor C2, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8.

[0214] The gate QG1 of the first transistor Q1 is coupled to the clock signal line GCK, the first electrode QS1 is coupled to the input signal terminal GI, and the second electrode QD1 is coupled to the gate QG2 of the second transistor.

[0215] The first electrode QS2 of the second transistor Q2 is coupled to the clock signal line GCK, and the second electrode QD2 is coupled to the sixth node N6.

[0216] The gate QG3 of the third transistor Q3 is coupled to the clock signal terminal GCK, the first electrode QS3 is coupled to the voltage signal line VGL, and the second electrode QD3 is coupled to the sixth node N6.

[0217] The gate QG4 of the fourth transistor Q4 is coupled to the sixth node N6, the first electrode QS4 is coupled to the voltage signal line VGH, and the second electrode QD4 is coupled to the signal output line GO.

[0218] The gate of the fifth transistor Q5 is coupled to the eighth node N8, the first electrode QS5 is coupled to the clock signal terminal QCB, and the second electrode QD5 is coupled to the signal output line GO.

[0219] The gate QG6 of the sixth transistor Q6 is coupled to the sixth node N6, the first electrode QS6 is coupled to the voltage signal line VGH, and the second electrode QD6 is coupled to the seventh node N7.

[0220] The gate QG7 of the seventh transistor Q7 is coupled to the clock signal terminal GCB, the first electrode QS7 is coupled to the seventh node N7, and the second electrode QD7 is coupled to the fifth node N5.

[0221] The gate QG8 of the eighth transistor Q8 is coupled to the voltage signal line VGL, the first electrode QS8 is coupled to the fifth node N5, and the second electrode QD8 is coupled to the eighth node N8.

[0222] One end of the first capacitor C1 is coupled to the eighth node N8, and the other end is coupled to the second electrode QD5 of the fifth transistor Q5. One end of the second capacitor C2 is coupled to the sixth node N6, and the other end is coupled to the first electrode QS4 of the fourth transistor Q4.

[0223] With reference to Figure 20 and Figure 21 the timing diagram of, the working process of the shift register unit as shown in Figure 20 is illustratively described.

[0224] During the time period t1, the second scan driving circuit receives the GSTV low - potential pulse output from the previous stage, and the GCK alternating signal is at a low potential. At this time, transistors Q1, Q2, Q3, Q4, Q5, Q6, and Q8 are turned on, and the signal output line GO outputs a high potential.

[0225] During the time period t2, the potentials of GCK and GCB are reversed. Only transistors Q2, Q5, and Q7 are turned on. At this time, the low - potential GCB signal is output to the signal output line GO through transistor Q5, while transistor Q4 is turned off. Therefore, the voltage signal VGH cannot be output, and at this time, the signal output line GO outputs a low potential.

[0226] During the time period t3, GCK becomes low - potential and GCB becomes high - potential, and the signal output line GO outputs a high potential.

[0227] That is to say, only during the time period t2 does the signal output line GO output a low potential.

[0228] Figure 22 is an enlarged view of the signal line transfer structure of the display substrate according to some exemplary embodiments of the present disclosure. With reference to Figure 13 , Figure 15 , Figure 20 and Figure 22 , the signal line transfer structure 7 is used to transfer the signal output line GO of the second scan driving circuit to the scan signal line 61 and the reset control signal line 62. That is, the signal line transfer structure 7 is used to transfer the gate scan signal and the reset control signal.

[0229] Figure 24 is a timing diagram of the light - emitting control signal, scan signal, and reset control signal for driving multiple adjacent rows of pixels of the display substrate according to some exemplary embodiments of the present disclosure. As described above, the output signal of one EM GOA circuit can be used to drive two or four rows of pixels. Then, Figure 24 the light - emitting control signal En shown in Figure 24 can be used to drive multiple adjacent rows (such as two or four rows) of pixels. For example, it can be used as the light - emitting control signal of the pixel driving circuits of the n - th row and the (n + 1) - th row of pixels, or it can be used as the light - emitting control signal of the pixel driving circuits of the n - th row, (n + 1) - th row, (n + 2) - th row, and (n + 3) - th row of pixels. The scan signal of a certain row of pixels comes from the signal output by the GATE GOA circuit corresponding to that row of pixels, and the reset control signal of that row of pixels comes from the signal output by the GATE GOA circuit corresponding to the previous row of pixels. Then, Figure 24The signal Sn shown in the figure can be used as the scanning signal of the pixel driving circuit for the pixels in the n-th row, and the reset control signal of the pixel driving circuit for the pixels in the (n + 1)-th row; Figure 24 The scanning signal Sn+1 shown in the figure can be used as the scanning signal of the pixel driving circuit for the pixels in the (n + 1)-th row, and the reset control signal of the pixel driving circuit for the pixels in the (n + 2)-th row.

[0230] With reference to Figure 22 , the signal line transfer structure 7 is used to transfer the signal output line GO of the second scanning driving circuit (i.e., the GATE GOA circuit) to the scanning signal line 61 and the reset control signal line 62. The signal output from the signal output line GO can be the Sn signal as shown in Figure 24 . In this way, the Sn signal transmitted by the scanning signal line 61 can be used as the scanning signal of the pixel driving circuit for the pixels in the n-th row, and the Sn signal transmitted by the reset control signal line 62 can be used as the reset control signal of the pixel driving circuit for the pixels in the (n + 1)-th row.

[0231] Figure 23 is a plan view of a display substrate according to some exemplary embodiments of the present disclosure, in which film layer structures such as a signal line transfer structure and an anode layer are shown. Figure 25 is a cross-sectional schematic view of a display panel taken along the line HH' in Figure 23 . Figure 27 is a cross-sectional schematic view of a display panel taken along the line II' in Figure 23 . Figure 28 is a cross-sectional schematic view of a display panel taken along the line JJ' in Figure 23 .

[0232] With reference to Figure 12 , Figures 13 to 17 , Figure 23 , Figure 25 , Figure 27 and Figure 28 , the insulating layer may include at least some of the insulating layers such as the gate insulating layer 30, the first interlayer insulating layer 40, the second interlayer insulating layer 45, and the first planarization layer 50.

[0233] With reference to Figure 23 and Figure 25 , the display substrate may include: an active layer 20 provided on the substrate 1 ( Figure 25(the layer where the light-emitting control source region 203f and the light-emitting control drain region 205f are located), the gate insulating layer 30 provided on the side of the active layer 20 away from the substrate 1, the gate G6 provided on the side of the gate insulating layer 30 away from the substrate 1, the first interlayer insulating layer 40 provided on the side of the gate G6 away from the substrate 1, the initialization voltage line 66 provided on the side of the first interlayer insulating layer 40 away from the substrate 1, the second interlayer insulating layer 45 provided on the side of the initialization voltage line 66 away from the substrate 1, the drain D6 provided on the side of the second interlayer insulating layer 45 away from the substrate 1, the first planarization layer 50 covering the drain D6, and the anode 5 provided on the side of the first planarization layer 50 away from the substrate 1. Among them, the drain D6 can be connected to the light-emitting control drain region 205f through the via hole VAH7, and the anode 5 can be connected to the drain D6 through the via hole VAH9.

[0234] Referring to Figure 15 and Figure 16 , the display substrate may further include a first capacitor electrode Cst1 and a second capacitor electrode Cst2. With reference to Figure 13 , the first capacitor electrode Cst1 and the second capacitor electrode Cst2 face each other and may be spaced apart by the first interlayer insulating layer 40 to form a storage capacitor Cst.

[0235] In the example shown in the figure, conductive elements such as the first capacitor electrode Cst1 and the gate G6 may be located in the same layer, for example, formed by the same lithography process. For convenience of description, the layer where the first capacitor electrode Cst1 and the gate G6 are located may be referred to as the first conductive layer. Conductive elements such as the second capacitor electrode Cst2 and the initialization voltage line 66 may be located in the same layer, for example, formed by the same lithography process. For convenience of description, the layer where the second capacitor electrode Cst2 and the initialization voltage line 66 are located may be referred to as the second conductive layer. The layer where the drain D6 is located may be referred to as the third conductive layer. For example, conductive elements such as the driving voltage line 65 and / or the data line 64 may be located in the third conductive layer.

[0236] It should be understood that the conductive elements of the above-mentioned first scanning driving circuit, second scanning driving circuit and each signal line may be respectively arranged in the first conductive layer, the second conductive layer and the third conductive layer.

[0237] Optionally, a buffer layer 11 may further be provided between the semiconductor layer 20 and the substrate 1.

[0238] Specifically, the scanning signal line 61 and the reset control signal line 62 may be located in the first conductive layer, that is, the layer where the gates of the respective thin film transistors are located, referring to Figure 27 . The signal output line GO of the second scanning driving circuit may be located in the second conductive layer, referring to Figure 28。The signal line transfer structure 7 can be located in the third conductive layer. Refer to Figure 27 and Figure 28 。In Figure 22 ,an initial voltage signal line 660 is also schematically shown. The initial voltage signal line 660 can be located in the third conductive layer.

[0239] For example, the initial voltage signal line 660 can cross the signal output line GO of the second scan driving circuit, that is, there can be partial overlap between their projections on the substrate. For example, the signal output line GO is located in the peripheral area, on the first side in the row direction of the display area, and extends towards the display area. The initial voltage signal line 660 is located in the peripheral area, on the first side in the row direction of the display area, and extends along the contour direction of the boundary on the first side of the display area. For example, the signal output line GO always crosses the initial voltage signal line 660 and extends into the display area or a position closer to the display area relative to the initial voltage signal line 660. The signal output line GO is electrically connected to the signal line transfer structure 7. Exemplarily, Figure 22 shows 2 vias VH3. The signal output line GO of the second scan driving circuit can be electrically connected to the signal line transfer structure 7 through 2 vias VH3. Specifically, refer to Figure 27 ,the signal output line GO is located in the second conductive layer, the signal line transfer structure 7 is located in the third conductive layer, and the signal output line GO and the signal line transfer structure 7 located in different layers are electrically connected through 2 vias VH3. In this way, the electrical connection between the signal output line GO and the signal line transfer structure 7 located in different layers is achieved.

[0240] Exemplarily, the 2 vias VH3 can be arranged in a direction parallel to the extension direction of the initial voltage signal line 660, that is, along the Figure 22 up and down direction (column direction) in

[0241] Furthermore, the first end of the signal line transfer structure 7 is electrically connected to the scan signal line 61 through 2 vias VH1. Refer to Figure 23 and Figure 27 。In this way, the electrical connection between the signal line transfer structure 7 and the scan signal line 61 located in different layers is achieved.

[0242] Exemplarily, the 2 vias VH1 can be arranged in a direction perpendicular to the extension direction of the initial voltage signal line 660, that is, along the Figure 22The arrangement in the left - right direction. It should be understood that the number of vias VH1 is not limited to 2, and more vias VH1 can also be set. By setting multiple vias VH1, the contact area between the signal line transfer structure 7 and the scan signal line 61 can be increased, thereby achieving a good electrical connection between the two.

[0243] Furthermore, the first end of the same signal line transfer structure 7 connecting one GOA unit is electrically connected to the scan signal line 61 through 2 vias VH1, and its second end is electrically connected to the reset control signal line 62 through 2 vias VH2. Refer to Figure 23 and Figure 27 . In this way, the electrical connection between the signal line transfer structure 7 and the reset control signal line 62 located on different layers is achieved.

[0244] Exemplarily, the 2 vias VH1 can be arranged in a direction perpendicular to the extension direction of the initial voltage signal line 660, and the 2 vias VH2 can be arranged in a direction perpendicular to the extension direction of the initial voltage signal line 660, that is, arranged in the Figure 22 left - right direction (row direction) in . It should be understood that the number of vias VH2 is not limited to 2, and more vias VH2 can also be set. By setting multiple vias VH2, the contact area between the signal line transfer structure 7 and the reset control signal line 62 can be increased, thereby achieving a good electrical connection between the two.

[0245] As Figure 22 shown, the first end and the second end of the signal line transfer structure 7 are respectively located on its opposite sides, or rather, on both sides of the signal output line GO (for example, both sides in the column direction). Through the signal line transfer structure 7, the electrical connection between the signal output line GO located on different layers and the scan signal line 61 and the reset control signal line 62 can be achieved, thereby transmitting the gate scan signal and the reset control signal generated by the second scan driving circuit to the pixel driving circuit.

[0246] The signal output line GO may include three segments, which are respectively marked as the first signal output line sub-segment GO1, the second signal output line sub-segment GO2 and the third signal output line sub-segment GO3 for the convenience of description. The orthographic projection of the first signal output line sub-segment GO1 on the substrate substrate at least partially overlaps with the orthographic projection of the signal line adapter structure 7 on the substrate substrate to achieve a via connection. The second signal output line sub-segment GO2 crosses the initial voltage signal line 660, that is, the orthographic projection of the second signal output line sub-segment GO2 on the substrate substrate at least partially overlaps with the orthographic projection of the initial voltage signal line 660 on the substrate substrate. For example, the extension direction of the second signal output line sub-segment GO2 is approximately perpendicular to the extension direction of the initial voltage signal line 660. For example, the area of the overlapping portion of the orthographic projection of a second signal output line sub-segment GO2 on the substrate substrate and the orthographic projection of the initial voltage signal line 660 on the substrate substrate is the line width of the second signal output line sub-segment GO2 multiplied by the line width of the initial voltage signal line 660. Combined with reference Figure 23 , the orthographic projection of the third signal output line sub-segment GO3 on the substrate substrate at least partially overlaps with the orthographic projection of the second electrode QD5 of the fifth transistor Q5 of the second scan driving circuit on the substrate substrate. In a direction parallel to the extension direction of the initial voltage signal line 660 (for example, the column direction), the size of the first signal output line sub-segment GO1 is smaller than the size of the third signal output line sub-segment GO3, and the size of the second signal output line sub-segment GO2 is smaller than the size of each of the first signal output line sub-segment GO1 and the third signal output line sub-segment GO3.

[0247] Continue to refer to Figure 22 The second capacitor electrode Cst2 may include a second capacitor electrode main body Cs21 and a second capacitor electrode connecting part Cs22 for connecting the second capacitor electrode main body Cs21. That is, a second capacitor electrode connecting part Cs22 is provided between every two adjacent second capacitor electrode main bodies Cs21.

[0248] The second signal output line segment GO2 and the second capacitor electrode connection portion Cs22 are substantially aligned with each other in a direction perpendicular to the extension direction of the initial voltage signal line 660. For example, a projection of the second signal output line segment GO2 in a direction perpendicular to the extension direction of the initial voltage signal line 660 and a projection of the second capacitor electrode connection portion Cs22 in a direction perpendicular to the extension direction of the initial voltage signal line 660 at least partially overlap or coincide with each other.

[0249] Reference Figure 23 , which schematically shows an anode 5 of an edge sub-pixel. The anode 5 includes a main body 53 and a connecting portion 54, wherein the main body 53 covers the opening of the sub-pixel, and the connecting portion 54 covers the via VAH9, which is used to connect the anode 5 to other conductive parts (such as the drain D6). For example, the orthographic projection of the main body 53 on the substrate substrate may have a regular shape, such asFigure 23 The rounded rectangle described in . The main body portion 53 may have a center. For example, the center may be the intersection of the two diagonals of the rounded rectangle. As described above, the anode 5 includes a first edge portion 51 and a second edge portion 52, and neither the first edge portion 51 nor the second edge portion 52 overlaps with the center of the main body portion 53. Specifically, the first edge portion 51 and the second edge portion 52 are respectively located on both sides of the center of the main body portion 53 in the row direction, and the first edge portion 51 and the second edge portion 52 are respectively spaced apart from the center of the main body portion 53 in the row direction. For example, the size of each of the first edge portion 51 and the second edge portion 52 in the row direction may be 1 / 10 to 1 / 5 of the size of the main body portion 53 in the row direction.

[0250] The signal line transfer structure 7 corresponding to the connection between the anode 5 of the edge sub-pixel and its corresponding pixel driving circuit (such as a scan signal line or a reset control signal line) at least partially overlaps in the orthographic projection on the substrate 1. The signal line transfer structure 7 is located below the first edge portion 51 of the anode 5, and a driving voltage line 65 and a data line 64 are provided below the second edge portion 52 of the anode 5. In other words, the orthographic projection of the first edge portion 51 on the substrate 1 at least partially overlaps with the orthographic projection of the signal line transfer structure 7 on the substrate 1, and the orthographic projection of the driving voltage line 65 and / or the data line 64 on the substrate 1 at least partially overlaps with the orthographic projection of the second edge portion 52 on the substrate 1. For the anode 5 of the same edge sub-pixel, the overlapping portion of the orthographic projection of the signal line transfer structure 7 corresponding to the connection between the anode 5 of the edge sub-pixel and its corresponding pixel driving circuit (such as a scan signal line or a reset control signal line) on the substrate 1 and the overlapping portion of the driving voltage line 65 and / or the data line 64 with the orthographic projection of the anode 5 of the edge sub-pixel on the substrate 1 are located on both sides of the center line of the anode of the edge sub-pixel, for example, on the left and right sides (in the row direction) of two opposite edges.

[0251] As Figure 23 shown, the orthographic projection of the signal line transfer structure 7 overlapping with the edge sub-pixel on the substrate 1 penetrates the orthographic projection of the anode 5 of the edge sub-pixel on the substrate 1.

[0252] It should be noted that the expression "penetrates" here means that at least a part of the two end portions of the signal line transfer structure 7 in the column direction does not overlap with the anode 5, or in other words, a line along the column direction on the signal line transfer structure 7 passes through the anode 5.

[0253] With reference to Figure 23 and Figure 25, the display substrate further includes a pixel defining layer 56 located on a side of the anode 5 away from the substrate 1, the pixel defining layer 56 includes an opening 5O, and at least a part of the anode 5 is exposed by the opening 5O.

[0254] As Figure 23 shown, the size of the signal line transfer structure 7 extending in the column direction is greater than the size of the opening 5O of the pixel defining layer 56 extending in the column direction.

[0255] The size of the pixel driving circuit corresponding to the sub-pixel in the column direction is a, and the size of the signal line transfer structure 7 in the column direction is between, or, the size of the signal line transfer structure 7 in the column direction is between, or, the size of the signal line transfer structure 7 in the column direction is between.

[0256] It should be noted that the expression "the size of the pixel driving circuit in the column direction" here can be understood as follows: from a signal line extending in the row direction that drives the sub-pixels in the previous row to the same signal line of the sub-pixels in this row, the size in the column direction between the two signal lines that transmit the same signal. For example, "the size of the pixel driving circuit in the column direction" can be the size in the column direction between the reset control line of the sub-pixels in the previous row and the reset control line of the sub-pixels in this row.

[0257] As Figure 23 shown, the size of the signal line transfer structure 7 in the column direction is greater than the pitch in the column direction between the scan signal line 61 and the emission control line 63 in the pixel driving circuit connected by the signal line transfer structure 7.

[0258] As Figure 23 shown, in the direction perpendicular to the drive voltage line 65 and the data line 64 (for example, the row direction), the signal line transfer structure 7 is located on a side of the drive voltage line 65 and the data line 64 closer to the non-display area.

[0259] In the embodiment of the present disclosure, the data line 64, the driving voltage line 65 and the signal line transfer structure 7 are located in the same layer, and they can be located in the same layer as the source and drain of the thin film transistor, that is, they can be composed of the material constituting the source and drain, and formed by the same patterning process. In this way, the thickness of the data line 64, the driving voltage line 65 and the signal line transfer structure 7 are approximately equal, that is, the thickness of the signal line transfer structure 7 in the direction perpendicular to the base substrate 1 is approximately equal to the thickness of each of the data line 64 and the driving voltage line 65 in the direction perpendicular to the base substrate 1. For example, the expression "approximately equal to" can mean in the range of 0.8 to 1.2, that is, the ratio of the thickness of the signal line transfer structure 7 in the direction perpendicular to the base substrate 1 to the thickness of each of the data line 64 and the driving voltage line 65 in the direction perpendicular to the base substrate 1 can be in the range of 0.8 to 1.2.

[0260] Specifically, the signal line transfer structure 7 includes a widened portion 73. Figure 23 As shown, the orthographic projections of the plurality of via holes VH1 and the plurality of via holes VH3 on the base substrate all fall within the orthographic projection of the widening portion 73 on the base substrate. The orthographic projection of the first edge portion 51 on the base substrate 1 at least partially overlaps with the orthographic projection of the widening portion 73 on the base substrate 1. In this way, the widening portion 73 can be used to better pad the anode 5 and better improve the flatness of the anode.

[0261] It should be noted that in Figure 23 In the illustrated embodiment, a plurality of VH1 are arranged in the left-right direction, and a plurality of vias VH3 are arranged in the up-down direction. Thus, the dimensions of the widened portion 73 in both the left-right direction and the up-down direction are widened, thereby facilitating better padding of the anode 5 and achieving reliability of the via connection.

[0262] Continue to refer to Figure 23 , the initial voltage signal line 660 can be electrically connected to the initialization voltage line 66 through the via hole VH4 to transmit the initialization voltage Vint to the pixel driving circuit. For example, the initial voltage signal line 660 can be located in the third conductive layer, and the initialization voltage line 66 can be located in the second conductive layer. For example, the number of via holes VH4 can be 2, and the two via holes VH4 can be arranged in a direction parallel to the extension direction of the initial voltage signal line 660, that is, along Figure 23 It should be understood that the number of via holes VH4 is not limited to 2, and more via holes VH4 may be provided.

[0263] Combined with reference Figure 23 and Figure 28, the second electrode QD5 of the fifth transistor Q5 of the second scan driving circuit can be electrically connected to the signal output line GO through the via VH5. For example, the number of vias VH5 can be 3, and the 3 vias VH5 can be arranged in a direction parallel to the extending direction of the initial voltage signal line 660, that is, along Figure 23 the up-down direction in

[0264] . It should be understood that the number of vias VH5 is not limited to 3, and more vias VH5 can also be provided. Figure 23 and Figure 28 , the display substrate may further include a second initial voltage signal line 661. At this time, the initial voltage signal line 660 can be referred to as the first initial voltage signal line 660. The second initial voltage signal line 661 can be on the same layer as the anode 5. Specifically, with reference to

[0265] , a groove 662 is formed in the first planarization layer 50, and the groove 662 exposes the upper surface of the first initial voltage signal line 660. A part of the second initial voltage signal line 661 located above the first initial voltage signal line 660 is located in the groove 662. In this way, the connection between the first initial voltage signal line 660 and the second initial voltage signal line 661 can be realized. In this way, the second initial voltage signal line 661 can be connected in parallel with the first initial voltage signal line 660 to reduce the resistance on the line for transmitting the initialization voltage.

[0266] Optionally, Figure 26 is a display panel according to some other exemplary embodiments of the present disclosure along Figure 23Schematic cross-sectional view taken along line HH' in [the figure]. In this embodiment, the display substrate may further include a fourth conductive layer located between the third conductive layer and the layer where the anode 5 is located. For example, the display substrate may further include a connecting conductive portion 70 provided on the side of the first planarization layer 50 away from the substrate 1. The connecting conductive portion 70 is located in the fourth conductive layer. The connecting conductive portion 70 is electrically connected to the drain D6 through a via hole VAH10, and the anode 5 is electrically connected to the connecting conductive portion 70 through a via hole VAH11. That is to say, through the connecting conductive portion 70, the anode 5 is electrically connected to the drain D6. In the case where a fourth conductive layer is provided, according to the wiring requirements, some of the above signal lines may be arranged in the fourth conductive layer, or data lines parallel to the above data lines 64 for transmitting data signals Dm and / or driving voltage lines 65 for transmitting a driving voltage ELVDD may be arranged in the fourth conductive layer to reduce the resistance on the lines for transmitting data signals and / or driving voltages.

[0267] Optionally, in Figure 26 , the via hole VAH11 may also be located on the left side of the via hole VAH10. For example, it may be located between the via hole VAH10 and the via hole VAH7, that is, the orthographic projection of the via hole VAH11 on the substrate 1 may be located between the orthographic projection of the via hole VAH10 on the substrate 1 and the orthographic projection of the via hole VAH7 on the substrate 1.

[0268] Optionally, in Figure 25 , Figure 27 and Figure 28 In the embodiment shown, the first planarization layer 50 is shown in the form of a single film layer. However, the embodiments of the present disclosure are not limited thereto. In an alternative embodiment, the first planarization layer 50 may include at least two film layers. For example, two insulating layers may be provided between the third conductive layer and the layer where the anode 5 is located. The two insulating layers may include a passivation layer made of an inorganic material and a planarization layer made of an organic material.

[0269] Optionally, continuing to refer to Figure 26 , the display substrate may further include a second planarization layer 55 provided on the side of the connecting conductive portion 70 away from the substrate 1. The anode 5 of the OLED is provided on the side of the second planarization layer 55 away from the substrate 1. It should be understood that the OLED may further include an organic light-emitting layer and a cathode provided on the side of the anode 5 away from the substrate 1.

[0270] For example, the first conductive layer and the second conductive layer may be conductive layers made of a gate material, such as Mo. For example, the third conductive layer and the fourth conductive layer may be conductive layers made of a source-drain material, such as Ti / Al / Ti.

[0271] For example, the gate material may include a metal material, such as Mo, Al, Cu and other metals and their alloys. The source and drain material may include a metal material, such as Mo, Al, Cu and other metals and their alloys. The semiconductor material constituting the active layer may include, for example, amorphous silicon, polycrystalline silicon, oxide semiconductors, etc., and the oxide semiconductor material may include, for example, IGZO (indium gallium zinc oxide), ZnO (zinc oxide), etc.

[0272] Reference Figure 23 For the convenience of description, the layer where the anode 5 is located is called the fifth conductive layer. The orthographic projection of the third signal output line segment GO3 on the substrate substrate does not overlap with the orthographic projection of the fifth conductive layer on the substrate substrate, so as to avoid the interference of the electrical signal transmitted on the fifth conductive layer on the output signal of the signal output line GO. For example, the third signal output line segment GO3 is located in the peripheral area and does not overlap with the second initial voltage signal line 661 and the anode 5 located in the fifth conductive layer.

[0273] Return to Combined Reference Figure 11 Optionally, the first signal line 31 and the signal line transition structure 7 may be located in the fourth conductive layer, that is, they may be located in the same layer as the connecting conductive portion 70. In this case, the first signal line 31 and the signal line transition structure 7 may also be made of source and drain materials and formed by the same patterning process.

[0274] Optionally, the first signal line 31 and the signal line transition structure 7 may be located in the first conductive layer, that is, they may be located in the same layer as the gate G6. In this case, the first signal line 31 and the signal line transition structure 7 may be made of gate material and formed by the same patterning process.

[0275] Optionally, the first signal line 31 and the signal line transition structure 7 may be located in the second conductive layer, that is, they may be located in the same layer as the first capacitor electrode Cst1. In this case, the first signal line 31 and the signal line transition structure 7 may also be made of gate material and formed by the same patterning process.

[0276] Thus, in the embodiment of the present disclosure, the first signal line 31 and the signal line transfer structure 7 are made of the same material and formed by the same patterning process, which is beneficial for the two to have the same thickness. Figure 11 The first signal line 31 and the signal line transfer structure 7 having the same thickness are respectively located below the anode 5, which is beneficial to improving the flatness of the anode 5 and avoiding the anode 5 from tilting, thereby improving the color shift phenomenon of the display substrate.

[0277] It should be noted that the planarization layer 4 in the above embodiment may include Figure 26The first planarization layer 50 and the second planarization layer 55 are shown in FIG. However, the embodiment of the present disclosure is not limited thereto, and the planarization layer 4 may also have a single film layer structure.

[0278] It should also be noted that Figure 4 As described, on the display substrate according to some embodiments, a left GOA circuit DA1 and a right GOA circuit DA2 are provided. Accordingly, the at least one row of edge sub-pixels may include a column of edge sub-pixels located on the left side of the display area and a column of edge sub-pixels located on the right side of the display area. A plurality of the above-mentioned signal line switching structures 7 are provided between the left GOA circuit DA1 and the column of edge sub-pixels located on the left side of the display area, and the orthographic projections of the first electrodes of the column of edge sub-pixels located on the left side of the display area on the substrate substrate overlap with the orthographic projections of these signal line switching structures 7 on the substrate substrate, respectively. Similarly, a plurality of the above-mentioned signal line switching structures 7 are also provided between the right GOA circuit DA2 and the column of edge sub-pixels located on the right side of the display area, and the orthographic projections of the first electrodes of the column of edge sub-pixels located on the right side of the display area on the substrate substrate overlap with the orthographic projections of these signal line switching structures 7 on the substrate substrate, respectively.

[0279] In the above embodiment, the signal line switching structure 7 is arranged at the edge positions on the left and right sides of the display area AA to realize the function of padding the anode 5. However, the embodiments of the present disclosure are not limited to this. The signal line switching structure 7 can also be arranged at other positions, for example, at the edge positions on the upper and lower sides of the display area AA, or at the edge positions of the corners of the display area AA.

[0280] At least some embodiments of the present disclosure also provide a display panel, wherein the display panel includes the display substrate as described above. For example, the display panel may be an OLED display panel.

[0281] Reference Figure 29 At least some embodiments of the present disclosure further provide a display device. The display device may include the display substrate described above. The display device includes a display area AA and a non-display area NA, and the non-display area NA has a smaller width, thereby realizing a display device with a narrow frame.

[0282] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0283] It should be understood that the display device according to the embodiments of the present disclosure has all the features and advantages of the above-mentioned display substrate. For details, reference may be made to the above description and will not be elaborated herein.

[0284] Although some embodiments of the general technical concept of the present disclosure have been shown and described, those of ordinary skill in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the general technical concept. The scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, the display substrate including a display area and a non-display area, wherein, The display substrate comprises: substrate substrate; A plurality of sub-pixels located in the display area, the plurality of sub-pixels are arranged in an array on the base substrate along a row direction and a column direction, each sub-pixel includes a light emitting device, and the light emitting device includes a first electrode; A plurality of signal lines disposed on the substrate, the plurality of signal lines at least comprising a first signal line and a second signal line, the first signal line being used to transmit a voltage signal, and the second signal line being used to transmit a scan signal; A signal line lead is provided on the base substrate, the signal line lead is located in the non-display area; and A signal line transfer structure is provided on the base substrate, and the signal line transfer structure is used to connect the signal line lead and the second signal line. Wherein, the signal line transfer structure and the first signal line are located in the same layer, and the signal line transfer structure and the first signal line are spaced apart; And wherein, the orthographic projection of the first electrode of at least one of the sub-pixels on the base substrate at least partially overlaps with the orthographic projection of the first signal line on the base substrate, and the orthographic projection of the first electrode of at least one of the sub-pixels on the base substrate at least partially overlaps with the orthographic projection of the signal line switching structure on the base substrate.

2. The display substrate according to claim 1, wherein, The plurality of sub-pixels include at least one row of edge sub-pixels located at an edge position of the display area close to the non-display area; and The orthographic projection of the first electrode of each edge sub-pixel in the at least one row of edge sub-pixels on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate, and the orthographic projection of the first electrode of each edge sub-pixel in the at least one row of edge sub-pixels on the substrate at least partially overlaps with the orthographic projection of the signal line switching structure on the substrate.

3. The display substrate according to claim 2, wherein The at least one row of edge sub-pixels includes at least one column of edge sub-pixels, and an arrangement direction of the at least one column of edge sub-pixels is substantially the same as an extension direction of the first signal line.

4. The display substrate according to claim 2, wherein, The signal line transfer structure and the first signal line extend in substantially the same direction, and the arrangement direction of the plurality of signal line transfer structures is substantially the same as the extension direction of the first signal line.

5. The display substrate according to claim 2, wherein, The orthographic projection of the signal line transfer structure overlapping with an edge sub-pixel in the at least one row of edge sub-pixels on the base substrate passes through the orthographic projection of the first electrode of the edge sub-pixel on the base substrate.

6. The display substrate according to claim 1 further includes a pixel defining layer located on a side of the first electrode away from the base substrate, the pixel defining layer includes an opening, the first electrode of the at least one sub-pixel is at least partially exposed by the opening, and a dimension of the signal line transfer structure extending in a column direction is larger than a dimension of the opening of the pixel defining layer corresponding to the at least one sub-pixel extending in the column direction.

7. The display substrate according to claim 1, wherein, The pixel driving circuit corresponding to the at least one sub-pixel extends in the column direction with a dimension a, and the signal line transfer structure extends in the column direction with a dimension between.

8. The display substrate according to claim 1, wherein, In a direction perpendicular to the first signal line, the signal line switching structure is located on a side of the first signal line closer to the non-display area.

9. The display substrate according to claim 2, wherein, The first electrode of each edge sub-pixel in the at least one row of edge sub-pixels includes a first edge portion close to the non-display area, and an orthographic projection of the first edge portion on the base substrate at least partially overlaps with an orthographic projection of the signal line switching structure on the base substrate.

10. The display substrate according to claim 9, wherein, The first electrode of each edge sub-pixel in the at least one row of edge sub-pixels includes a second edge portion away from the non-display area, and an orthographic projection of the second edge portion on the base substrate at least partially overlaps with an orthographic projection of the first signal line on the base substrate.

11. The display substrate according to any one of claims 1-10, wherein, The thickness of the signal line transfer structure in a direction perpendicular to the base substrate is substantially equal to the thickness of the first signal line in a direction perpendicular to the base substrate.

12. The display substrate according to claim 1, wherein, The first electrode comprises a main body, and the orthographic projection of the main body on the base substrate has a regular shape; as well as The orthographic projection of the first signal line on the base substrate and the orthographic projection of the signal line switching structure on the base substrate are respectively located on two sides of the center of the orthographic projection of the main body of the first electrode on the base substrate.

13. The display substrate according to any one of claims 1-10 and 12, wherein, The display substrate further includes a planarization layer, and the planarization layer is located between the signal line switching structure and the layer where the first signal line is located and the layer where the first electrode is located.

14. The display substrate according to any one of claims 1-10 and 12, wherein Each sub-pixel further includes a pixel driving circuit, the pixel driving circuit includes a storage capacitor and at least one thin film transistor, each of the thin film transistors includes a semiconductor layer, a gate, a source electrode and a drain electrode, and the storage capacitor includes a first capacitor electrode and a second capacitor electrode; And wherein, the display substrate further comprises: A first conductive layer is disposed on a side of the semiconductor layer away from the substrate, wherein the gate and the first capacitor electrode are located in the first conductive layer; A second conductive layer disposed on a side of the first conductive layer away from the base substrate, wherein the second capacitor electrode is located on the second conductive layer; and A third conductive layer is arranged on a side of the second conductive layer away from the base substrate, and the source and the drain are located in the third conductive layer.

15. The display substrate according to claim 14, wherein, The signal line transfer structure and the first signal line are located in one selected from the first conductive layer, the second conductive layer, and the third conductive layer.

16. The display substrate according to claim 14, wherein, The display substrate further includes: a connecting conductive portion disposed between the third conductive layer and the layer where the first electrode is located, the connecting conductive portion being used to electrically connect one of the source electrode and the drain electrode to the first electrode.

17. The display substrate according to claim 16, wherein, The signal line transfer structure and the first signal line are located in the layer where the connecting conductive part is located.

18. The display substrate according to any one of claims 1-10, 12, 15-17, wherein, At least one of the signal line lead and the second signal line is located at a different layer from the signal line transfer structure.

19. The display substrate according to claim 18, wherein, The signal line lead and the second signal line are located on the same layer, and both the signal line lead and the second signal line are on different layers from the signal line transfer structure; the display substrate further includes an insulating layer located between the layer where the signal line lead and the second signal line are located and the layer where the signal line transfer structure is located, and the insulating layer includes a first via and a second via; a part of the signal line transfer structure is connected to the second signal line through a first conductive plug formed in the first via, and another part of the signal line transfer structure is connected to the signal line lead through a second conductive plug formed in the second via; Or, The signal line lead and the second signal line are on different layers, and the signal line lead and the signal line transfer structure are on the same layer; the display substrate further includes an insulating layer located between the layer where the signal line lead and the signal line transfer structure are located and the layer where the second signal line is located, and the insulating layer includes a first via; a part of the signal line transfer structure is connected to the second signal line through a first conductive plug formed in the first via, and another part of the signal line transfer structure is directly connected to the signal line lead; Or, The signal line lead and the second signal line are on different layers, and the second signal line and the signal line transfer structure are on the same layer; the display substrate further includes an insulating layer located between the layer where the second signal line and the signal line transfer structure are located and the layer where the signal line lead is located, and the insulating layer includes a second via; a part of the signal line transfer structure is directly connected to the second signal line, and another part of the signal line transfer structure is connected to the signal line lead through a second conductive plug formed in the second via.

20. The display substrate according to claim 10, wherein, The display substrate further includes a gate driving circuit disposed on the substrate and in the non-display area, the signal line lead includes a signal output line of the gate driving circuit, the signal output line is used to output a gate scanning signal, and the second signal line includes a scanning signal line for transmitting the gate scanning signal.

21. The display substrate according to claim 20, wherein, The display substrate further includes an initial voltage signal line disposed on the substrate and in the non-display area, the signal output line is electrically connected to the signal line transfer structure through a plurality of third vias, and the plurality of third vias are arranged in a direction parallel to the extending direction of the initial voltage signal line.

22. The display substrate according to claim 21, wherein, The scanning signal line is electrically connected to the signal line transfer structure through a plurality of fourth vias, and the plurality of fourth vias are arranged in a direction perpendicular to the extending direction of the initial voltage signal line.

23. The display substrate according to claim 22, wherein, The signal line transfer structure includes a widened portion, and the orthographic projections of the plurality of third vias and the plurality of fourth vias on the substrate all fall within the orthographic projection of the widened portion on the substrate; And The orthographic projection of the first edge portion of the first electrode on the substrate at least partially overlaps with the orthographic projection of the widened portion of the signal line transfer structure on the substrate.

24. The display substrate according to claim 22, wherein, The first signal line includes a driving voltage line for transmitting a driving voltage, and a positive projection of the second edge portion of the first electrode on the substrate substrate at least partially overlaps with a positive projection of the driving voltage line on the substrate substrate.

25. The display substrate according to claim 22, wherein, The first signal line further includes a data line for transmitting a data signal, and a positive projection of the second edge portion of the first electrode on the substrate substrate also at least partially overlaps with a positive projection of the data line on the substrate substrate.

26. The display substrate according to claim 22, wherein, Each sub-pixel further includes a pixel driving circuit, the pixel driving circuit includes at least one thin film transistor, and each thin film transistor includes a semiconductor layer; the display substrate further includes: a first conductive layer disposed on a side of the semiconductor layer away from the substrate substrate; a second conductive layer disposed on a side of the first conductive layer away from the substrate substrate; and a third conductive layer disposed on a side of the second conductive layer away from the substrate substrate, the scanning signal line is located in the first conductive layer, the signal output line is located in the second conductive layer, and the signal line transfer structure is located in the third conductive layer.

27. The display substrate according to claim 22, wherein, The display substrate further includes a reset control signal line disposed on the substrate substrate, the reset control signal line is electrically connected to the signal line transfer structure through a plurality of fifth vias, and the plurality of fifth vias are arranged in a direction perpendicular to an extending direction of the initial voltage signal line.

28. The display substrate according to claim 22, wherein, The signal output line includes a first signal output line sub-segment, a second signal output line sub-segment, and a third signal output line sub-segment connected in sequence, a positive projection of the first signal output line sub-segment on the substrate substrate falls within a positive projection of the signal line transfer structure on the substrate substrate, a positive projection of the second signal output line sub-segment on the substrate substrate at least partially overlaps with a positive projection of the initial voltage signal line on the substrate substrate, and the third signal output line sub-segment is located on a side of the initial voltage signal line away from the signal line transfer structure; and In a direction parallel to an extending direction of the initial voltage signal line, a size of the second signal output line sub-segment is smaller than a size of the first signal output line sub-segment, and the size of the first signal output line sub-segment is smaller than a size of the third signal output line sub-segment.

29. The display substrate according to claim 28, wherein, Each sub-pixel further includes a pixel driving circuit, the pixel driving circuit includes a storage capacitor, the storage capacitor includes a second capacitor electrode, the second capacitor electrode includes a second capacitor electrode main body portion and a second capacitor electrode connection portion, and the second capacitor electrode connection portion is located between two adjacent second capacitor electrode main body portions; and A projection of the second signal output line sub-segment in a direction perpendicular to an extending direction of the initial voltage signal line at least partially overlaps with a projection of the second capacitor electrode connection portion in a direction perpendicular to an extending direction of the initial voltage signal line.

30. The display substrate according to claim 22, wherein, The display substrate further includes another initial voltage signal line disposed on the substrate substrate and located in the non-display area, the another initial voltage signal line and the first electrode are located on the same layer; and The another initial voltage signal line and the initial voltage signal line are electrically connected.

31. The display substrate according to claim 22, wherein, The display substrate further includes an initialization voltage line disposed on the substrate, and the initialization voltage signal line is electrically connected to the initialization voltage line through a plurality of sixth vias, and the plurality of sixth vias are arranged in a direction parallel to the extending direction of the initialization voltage signal line.

32. The display substrate according to any one of claims 1-10, 12, 15-17, 19-31, wherein, The light-emitting device includes an organic light-emitting diode, and the first electrode is the anode of the organic light-emitting diode.

33. The display substrate according to any one of claims 2-5 and 9-10, wherein The at least one row of edge sub-pixels includes a plurality of red sub-pixels and a plurality of blue sub-pixels alternately arranged in the column direction.

34. A display panel, comprising the display substrate according to any one of claims 1-33.

35. A display device, comprising the display substrate according to any one of claims 1-33 or the display panel according to claim 34.

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