Quality-Based Dynamic Scheduling LDPC Decoder

Abstract

The present disclosure describes a technique related to improving the power consumption of an LDPC decoder. In an example, the LDPC decoder uses a message passing algorithm between variable nodes and check nodes. A check node processing unit that generates check node-to-variable node messages implements multiple check node processing modes. The operations in each mode consume a certain amount of power while providing a certain level of accuracy. Based on the reliability of the variable node-to-check node messages received by the check node processing unit, a suitable check node processing mode is selected and used to generate the corresponding check node-to-variable node messages. The reliability of a set of variable node-to-check node messages can be estimated based on, for example, a parameter related to a syndrome.

Description

Technical Field

[0001] The present disclosure relates to a quality-based dynamic scheduling LDPC decoder. Background Art

[0002] Error correction codes (ECCs) are commonly used in various types of data storage devices, including NAND flash memories. ECCs are also often used during data transmission. An ECC is a code in which redundant data or parity data is added to a message such that even if many errors are introduced during transmission or storage, the receiver can recover the message. Generally, an ECC can correct errors according to the capabilities of the code used. ECC decoding can include soft decoding, such as low density parity check code (LDPC) decoding, where the logical values stored in memory cells can be represented as probability distributions.

[0003] Generally, for ECC decoding, including LDPC decoding, a trade-off is made between error correction capability and power consumption. Generally, the higher the error correction capability, the more complex the decoding process and the higher the power consumption. Summary of the Invention

[0004] Techniques related to improving the power consumption of an ECC decoder are described herein, where the power consumption can be reduced while maintaining the error correction capability of the ECC decoder.

[0005] In an example, a method for decoding a low density parity check code (LDPC) codeword is disclosed. The method is implemented on a computing device and includes determining variable node to check node (V2C) messages, where the V2C messages correspond to variable nodes connected to a check node; determining the reliability of a set of V2C messages including the V2C messages; selecting a check node processing mode from a plurality of different check node processing modes based on the reliability; determining check node to variable node (C2V) messages based on the selected check node processing mode; and decoding the LDPC codeword based on the C2V messages.

[0006] In an example, the method further includes, during a decoding iteration: determining the syndrome of the LDPC codeword; increasing the number of decoding iterations; determining that the increased number of decoding iterations does not exceed a maximum number; and determining that the syndrome of the LDPC codeword is not zero.

[0007] In the above example, the method may further include, during the next decoding iteration corresponding to the increased number of decoding iterations: (a) updating the V2C messages corresponding to the variable nodes; (b) determining that the variable node is associated with a "j" variable node circulant matrix; (c) determining that the check node connected to the variable node is associated with a "k" check node circulant matrix; (d) determining that the reliability of the set of V2C messages is r k，j = Sk The number of 1s in r / CS, where r k，j is reliability, S k is a partial checksum calculated based on the "k" check node cyclic matrix, and CS is the checksum determined according to the syndrome of the LDPC codeword; (e) comparing r k，j with a reliability threshold, where the check node processing mode is selected based on this comparison; and (f) updating the partial checksum S k .

[0008] In the above example, the method may further include, during the corresponding next decoding iteration, repeating steps (a) to (f) for the remaining variable node cyclic matrix and the remaining check node cyclic matrix.

[0009] In the example, the reliability of the set of V2C messages is determined based on the syndrome of the LDPC codeword.

[0010] In the above example, the reliability of the set of V2C messages is further determined based on a partial syndrome associated with the cyclic matrix, where the check node is associated with the cyclic matrix.

[0011] In the example, each V2C message in the set of V2C messages corresponds to a variable node different from a set of variable nodes. The set of variable nodes corresponds to the variable node cyclic matrix.

[0012] In the above example, the check node is associated with the check node cyclic matrix, where the reliability is determined based on the syndrome of the LDPC codeword and the partial syndrome, and the partial syndrome is calculated based on the check node cyclic matrix.

[0013] In the above example, the reliability is determined as r = S k The number of 1s in r / CS, where r is reliability, S k is the partial syndrome, and CS is the checksum determined according to the syndrome of the LDPC codeword.

[0014] In the example, the method further includes: comparing the reliability with a reliability threshold, where the check node processing mode is selected based on this comparison.

[0015] In the above example, multiple different check node processing modes include a first check node processing mode and a second check node processing mode, where the first check node processing mode approximates the log-likelihood ratio of a variable node based on a first quantization level, where the second check node processing mode approximates the log-likelihood ratio of a variable node based on a second quantization level, where the second quantization level is greater than the first quantization level, where if the reliability is less than a reliability threshold, the first check node processing mode is selected, and where, if the reliability is greater than the reliability threshold, the second check node processing mode is selected.

[0016] In the above example, the reliability threshold is defined based on the number of decoding iterations.

[0017] In the above example, the reliability threshold is defined based on the variable node degree.

[0018] In the above example, the reliability threshold is defined based on the check node degree.

[0019] In an example, an apparatus is disclosed. The apparatus includes: a memory storing a low density parity check (LDPC) codeword; and a set of processing units configured to: determine a variable node to check node (V2C) message, where the V2C message corresponds to a variable node connected to a check node; determine the reliability of a set of V2C messages including the V2C message; select a check node processing mode from multiple different check node processing modes based on the reliability; and determine a check node to variable node (C2V) message based on the selected check node processing mode, where the LDPC codeword is decoded based on the C2V message.

[0020] In the above example, the set of processing units is further configured to, during a decoding iteration: determine the syndrome of the LDPC codeword; increment the number of decoding iterations; determine that the incremented number of decoding iterations does not exceed a maximum number; and determine that the syndrome of the LDPC codeword is not zero.

[0021] In the above example, the set of processing units may further be configured to, during the next decoding iteration corresponding to the incremented number of decoding iterations: (a) update the V2C message corresponding to the variable node; (b) determine that the variable node is associated with a "j" variable node circulant matrix; (c) determine that the check node connected to the variable node is associated with a "k" check node circulant matrix; (d) determine the reliability of the set of V2C messages as r k，j = S k the number of 1s in / CS, where r k，j is the reliability, S k is a partial syndrome calculated based on the "k" check node circulant matrix, and CS is a checksum determined based on the syndrome of the LDPC codeword; (e) set r k，jCompare with a reliability threshold, wherein a check node processing mode is selected based on this comparison; and (f) update a partial syndrome S k 。

[0022] In the above example, the set of processing units can be further configured to repeat steps (a) to (f) for the remaining variable node circulant matrix and the remaining check node circulant matrix during the corresponding next decoding iteration.

[0023] In an example, an error correction (ECC) system is disclosed. The ECC system includes a set of processing units configured to: receive an LDPC codeword from a memory; determine variable node to check node (V2C) messages, where the V2C messages correspond to variable nodes connected to a check node; determine the reliability of a set of V2C messages including the V2C messages; select a check node processing mode from multiple different check node processing modes based on the reliability; and determine check node to variable node (C2V) messages based on the selected check node processing mode, where the LDPC codeword is decoded based on the C2V messages.

[0024] In the above example, the reliability of the set of V2C messages is determined based on the syndrome of the LDPC codeword and based on a partial syndrome associated with a circulant matrix, where the check node is associated with the circulant matrix.

[0025] These illustrative examples are not mentioned to limit or define the present disclosure, but to provide examples to aid in its understanding. Additional embodiments and examples are discussed in the detailed description and further descriptions are provided there. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The nature and advantages of the various embodiments can be understood by reference to the following drawings.

[0027] Figure 1 Shows an example high-level block diagram of an error correction system according to certain embodiments of the present disclosure.

[0028] Figures 2A to 2B Shows an example parity check matrix according to certain embodiments of the present disclosure and an example graph representing the parity check matrix.

[0029] Figure 3 Shows an example circulant matrix and an example reliability matrix according to certain embodiments of the present disclosure.

[0030] Figure 4 Shows an example decoder including a plurality of variable node processing units and a plurality of check node processing units according to certain embodiments of the present disclosure.

[0031] Figure 5Shows an example process of codeword decoding based on message reliability estimation according to certain embodiments of the present disclosure.

[0032] Figure 6 Shows a more detailed example process of codeword decoding based on message reliability estimation according to certain embodiments of the present disclosure.

[0033] Figure 7 Is an example of a computer system capable of implementing the present disclosure. Detailed implementation

[0034] Techniques related to improving the power consumption of an ECC decoder are described herein, where the power consumption can be reduced with little or no impact on the error correction ability of the ECC decoder. In an example, the ECC decoder decodes data by partially using a message passing algorithm that processes messages, where the message output is based on, for example, "0" and "1". The ECC decoder can include one or more processing units. In turn, each processing unit can implement different processing modes. At least two processing modes of the processing unit support different error correction capabilities by differently implementing one or more operations of the message passing algorithm. Each different implementation is associated with a different set of processing cycles and / or hardware components, and thus results in different power consumption. The reliability of the messages received by the processing unit is estimated, where the estimate is based on, for example, one or more parameters related to the syndrome. Based on the reliability, one of the processing modes is selected and used to generate a response message. Specifically, when the reliability indicates that the received message is reliable, a low-complexity processing mode (e.g., a mode that consumes relatively low power) is selected for the response message. If the reliability indicates that the received message is unreliable, a high-complexity processing mode (e.g., a mode that consumes relatively high power) is selected for the response message. Overall, most of the transmitted messages are considered reliable, and thus, the high-complexity processing mode is used less frequently. However, when needed due to unreliability, this high-complexity processing mode is selectively used. Therefore, the overall power consumption of the ECC decoder is reduced, while maintaining the error correction ability relative to other ECC decoders that do not implement multiple processing modes and one of the multiple processing modes selected based on message reliability. When each of the processing modes is implemented in hardware by the processing unit, the ECC decoder may occupy a larger decoder silicon area relative to other ECC decoders. In other words, a trade-off is made between silicon area and power consumption while still maintaining the error correction ability.

[0035] For illustration, consider an example of an LDPC decoder. In a decoding iteration, a variable node processing unit sends variable node to check node (V2C) messages to a check node processing unit, where the V2C messages correspond to variable nodes connected to the check node. The reliability of a set of V2C messages including the V2C messages is estimated based on a parameter related to the syndrome. The check node processing unit implements different check node processing modes. Each of these modes is used to generate check node to variable node (C2V) messages with different precisions (e.g., different degrees of approximation). Based on the comparison of the reliability of the V2C messages with one or more reliability thresholds, the check node processing unit selects the most suitable check node processing mode and thus generates the C2V messages. The C2V messages are sent back to the variable node processing unit, and the iterative decoding continues, including running a message passing algorithm until a maximum number of decoding iterations is reached or the syndrome is zero.

[0036] In a further illustration, the LDPC code is a quasi-cyclic (QC) LDPC code. In this illustration, LDPC decoding relies on cyclic submatrices. In particular, each variable node can be associated with a variable node cyclic matrix, and each check node can be associated with a check node cyclic matrix. The message passing algorithm is executed at the level of the cyclic matrices. In other words, the variable node processing unit processes the information of the variable nodes associated with the variable node cyclic matrix. Similarly, the check node processing unit processes the information of the check nodes associated with the check node cyclic matrix. This processing can follow a vertical shuffle schedule (VSS). At the start of the current decoding iteration, the syndrome of the LDPC codeword is known (e.g., according to a previous decoding iteration or initialized if the current decoding iteration is the first decoding iteration). When updating the V2C messages corresponding to the variable nodes connected to the check node, the variable node cyclic matrix associated with the variable node is determined (for clear explanation, its index is "j" in this text; the variable node can be any one of the variable nodes "n" associated with the variable node cyclic matrix; in the example, the variable node is the first one (e.g., "n = 1")). The check node cyclic matrix associated with the connected check node is determined (its index is "k" in this text for clear explanation). Instead of estimating the reliability of each V2C message of the variable nodes associated with the "j" variable node cyclic matrix and each check node of the "k" check node cyclic matrix, it is sufficient to estimate the reliability of one of the V2C messages (e.g., one of the "n" variable nodes) and the same reliability applies to the remaining V2C messages. Doing so reduces the processing and power consumption of the LDPC decoder. Thus, the reliability of "r k，j " is estimated. This estimate can be a partial checksum (e.g., the number of "1"s in the partial syndrome "S k ", where the partial syndrome "S kThe ratio of the number of unsatisfied check nodes corresponding to the "k" check node circulant matrix to the LDPC codeword checksum "CS" determined from the syndrome "S" of the LDPC codeword. If unreliable (e.g., less than a reliability threshold), each of the C2V messages for the check nodes associated with the "k" check node circulant matrix is generated by using a high-complexity processing mode of the check node processing unit. If reliable (e.g., greater than the same or a different reliability threshold), each of the C2V messages for these check nodes is generated by using a low-complexity processing mode of the check node processing unit. The C2V messages are sent to the variable node processing unit, etc., until decoding is complete (e.g., reaching the maximum number of decoding iterations or until the syndrome "S" is zero).

[0037] Embodiments of the present disclosure provide several advantages related to conventional ECC decoders. On the one hand, the error correction capability of the ECC decoder is not affected or is minimally affected. This is because the ECC decoder includes a processing mode that supports the error correction capability and uses this processing mode as needed. On the other hand, the power consumption of the ECC decoder is reduced. That is because the ECC decoding includes at least one other processing mode that supports a lower error correction capability and processes messages more efficiently (which translates into power savings), and this processing mode is used when a higher error correction capability is not required. When implemented in hardware, the decoder silicon area may increase. Nevertheless, by adopting a specific code structure (e.g., QC-LDPC), this increase can be minimized (e.g., the total number of check node processing units can be reduced by processing messages at the level of the check node circulant matrix).

[0038] For clarity of explanation, various embodiments of the present disclosure are described in the context of LDPC decoders. Nevertheless, the embodiments can also be similarly applied to other decoder types that rely on message-passing algorithms. Additionally, various embodiments of the present disclosure are described in the context of QC-LDPC codes. Nevertheless, the embodiments can also be similarly applied to other code types, including other types of LDPC codes.

[0039] Figure 1 An example of a high-level block diagram of an error correction system 100 according to certain embodiments of the present disclosure is shown. In this example, LDPC codes are described in the context of data storage. However, embodiments of the present disclosure are not limited thereto. Instead, the embodiments are similarly applicable to other uses of LDPC codes, including, for example, data transmission.

[0040] LDPC codes are linear block codes defined by a sparse parity-check matrix H, which consists of 0s and 1s. The term "sparse matrix" is used herein to refer to a matrix in which the number of non-zero values in each column and each row is much smaller than its dimension. The term "column weight" is used herein to refer to the number of non-zero values in a particular column of the parity-check matrix H. The term "row weight" is used herein to refer to the number of non-zero values in a particular row of the parity-check matrix H. Generally, if the column weights of all columns in the parity-check matrix corresponding to an LDPC code are similar, the code is called a "regular" LDPC code. On the other hand, if at least one of the column weights is different from the other column weights, the LDPC code is called an "irregular" LDPC code. Generally, irregular LDPC codes provide better error correction capabilities than regular LDPC codes.

[0041] LDPC codes are also described according to how they are constructed. Random computer search or algebraic construction is possible. Random computer search construction describes LDPC codes with a parity-check matrix designed by a random computer-based program. Algebraic construction means that the parity-check matrix has been constructed based on combinatorial methods. Quasi-cyclic LDPC (QC-LDPC) codes belong to the latter construction method. One advantage of QC-LDPC codes is that in terms of the encoding process, the implementation of QC-LDPC codes is relatively easy. The main feature of QC-LDPC codes is that the parity-check matrix consists of cyclic submatrices, which can be based on the identity matrix or a smaller random matrix. Permutation vectors can also be used to create cyclic submatrices.

[0042] As shown in the figure, the LDPC encoder 110 receives information bits including data that is desired to be stored in the storage system 120. The LDPC-encoded data is output by the LDPC encoder 110 and written to the storage system 120.

[0043] In various embodiments, the storage system 120 can include various storage types or media, such as (for example, magnetic, solid-state) disk drive storage, flash memory, etc. In some embodiments, these technologies are used in transceivers, and instead of writing data to or reading data from a storage device, data is transmitted and received through wired and / or wireless channels. In this case, during the transmission of a codeword, errors may be introduced into the received codeword.

[0044] When the data stored is requested or otherwise needed (e.g., by an application or user storing data), the detector 130 receives the data from the storage system 120. The received data may include some noise or errors. The detector 130 performs detection on the received data and outputs a decision and / or reliability information. For example, a soft output detector outputs reliability information and a decision for each detected bit (e.g., the logical value of "1" or "0"). On the other hand, a hard output detector outputs a decision for each bit without providing the corresponding reliability information. As an example, a hard output detector may output a decision that a particular bit is "1" or "0" without indicating the certainty or confidence of the detector in that decision. In contrast, a soft output detector outputs a decision along with the reliability information associated with that decision. Generally, the reliability value indicates the certainty of the detector for a given decision. In one example, a soft output detector outputs a log-likelihood ratio (LLR), where the sign indicates the decision (e.g., a positive value corresponds to a "1" decision and a negative value corresponds to a "0" decision), and the magnitude indicates the confidence or certainty of the detector in that decision (e.g., a large magnitude indicates high reliability or high certainty).

[0045] The decision and / or reliability information is passed to the LDPC decoder 140 that uses the decision and reliability information to perform LDPC decoding. A soft-input decoder uses both the decision and reliability information to decode the codeword. A hard decoder uses only the decision value in the decoder to decode the codeword. The decoded bits generated by the LDPC decoder 140 are passed to the appropriate entity (e.g., the user or application requesting the decoded bits). Through appropriate encoding and decoding, the information bits match the decoded bits.

[0046] In various embodiments, the illustrated system can be implemented using a variety of techniques, including application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and / or general purpose processors (e.g., advanced RISC machines (ARM) cores).

[0047] LDPC codes are usually represented by a bipartite graph. One set of nodes, variable or bit nodes, corresponds to the elements of the codeword, and another set of nodes, such as check nodes, corresponds to a set of parity-check constraints that the codeword satisfies. Usually, the edge connections are randomly selected. If cycles of short lengths are avoided in the graph, the error-correction ability of the LDPC code can be improved. In an (r, c) regular code, each of the n variable nodes (V1, V2, ..., Vn) is connected to r check nodes, and each of the m check nodes (C1, C2, ..., Cm) is connected to c bit nodes. In an irregular LDPC code, the check-node degrees are not uniform. Similarly, the variable-node degrees are not uniform. In a QC-LDPC code, the parity-check matrix H is constructed as blocks of p×p matrices such that the bits in a block only participate in one check equation in that block, and each check equation in a block only involves one bit from the block. In a QC-LDPC code, a cyclic shift of the codeword by p generates another codeword. Here, p is the size of the square matrix, which can be a zero matrix or a circulant matrix. This is a generalization of cyclic codes, where a cyclic shift of the codeword by 1 generates another codeword. The blocks of p×p matrices can be zero matrices or circulant shift identity matrices of size p×p.

[0048] Figure 2A An example parity-check matrix H200 is shown, Figure 2B An example bipartite graph corresponding to the parity-check matrix 200 is shown. In this example, the parity-check matrix 200 has six column vectors and four row vectors, but embodiments of the present disclosure are not limited thereto and can be similarly applied to parity-check matrices having hundreds or even thousands of column vectors and row vectors. Network 202 shows the network corresponding to the parity-check matrix 200 and represents the bipartite graph. There can be various types of bipartite graphs, including, for example, Tanner graphs.

[0049] Generally, the variable nodes in network 202 correspond to the column vectors in the parity-check matrix 200. The check nodes in network 202 correspond to the row vectors in the parity-check matrix 200. The interconnections between the nodes are determined by the values of the parity-check matrix 200. Specifically, "1" indicates that the corresponding check node and variable node have a connection. "0" indicates no connection. For example, the "1" in the leftmost column vector and the second row vector from the top in the parity-check matrix 200 corresponds to the connection between the variable node 204 and the check node 210.

[0050] Message-passing algorithms are generally used to decode LDPC codes. There are several variants of message-passing algorithms in the prior art, such as the min-sum algorithm, the scaled min-sum algorithm, etc. Generally, any variant of the message-passing algorithm can be used in an LDPC decoder without departing from the teachings of the present disclosure. Message passing uses a network of variable nodes and check nodes, as Figure 2BAs shown. The connection between variable nodes and check nodes is described by the values of the parity check matrix 200, and the connection between variable nodes and check nodes corresponds to the values of the parity check matrix 200, as Figure 2A shown.

[0051] A hard decision message passing algorithm can be executed. In the first step, each of the variable nodes sends a message to one or more check nodes connected thereto. In this case, the message is the value that each of the variable nodes believes to be its correct value.

[0052] In the second step, each of the check nodes uses the information it previously received from the variable nodes to calculate the response sent to the variable nodes connected thereto. The response message corresponds to the value that the check node believes the variable node should have based on the information received from other variable nodes connected to this check node. This response is calculated using the parity check equation, which forces the sum of the values of all variable nodes connected to a specific check node to be zero (modulo 2).

[0053] At this time, if all equations at all check nodes are satisfied, the decoding algorithm declares that the correct codeword has been found and terminates. If the correct codeword is not found, the iteration continues with another update from the variable nodes using the messages received from the check nodes to determine whether the bits in their positions are 0 or 1 by the majority rule. The variable nodes then send this hard decision message to the check nodes connected to them. The iteration continues until the correct codeword is found, or the maximum number of iterations is performed without finding the correct codeword. It should be noted that the soft decision decoder works similarly, however, each message passed between the check nodes and the variable nodes also includes the reliability of each bit.

[0054] An example message passing algorithm can be executed. In this example, L(qij) represents the message sent from variable node v i to check node c j (e.g., V2C message); L(r ji ) represents the message sent from check node c j to variable node v i (e.g., C2V message); L(c i ) represents the initial LLR value of each variable node v i .

[0055] The variable node processing for each L(q ij ) can be completed through the following steps:

[0056] (1) Read L(c i ) and L(r ji ) from the memory.

[0057] (2) Calculate

[0058] (3) Calculate each L(Qi-sum) - L(r ij ).

[0059] (4) Output L(Qi-sum) and write it back to the memory.

[0060] (5) If this is not the last column of the memory, go to step 1 and increment i by 1.

[0061] (6) Calculate the parity check sum (e.g., syndrome), and stop if they are all equal to 0, the number of iterations reaches a threshold, and the parity check sum is greater than another threshold, or the number of iterations is equal to the maximum limit value; otherwise, perform check node processing.

[0062] The check node processing for each L(r ji ) can be performed as follows:

[0063] (7) Read a row q from the memory ij .

[0064] (8) Calculate L(Rj-sum) as follows:

[0065]

[0066] α ij = sign(L(q ij ))), β ij = |L(q ij )|,

[0067]

[0068] (9) Calculate a separate one for the check node

[0069]

[0070] (10) Write L(r ji ) back to the memory.

[0071] (11) If this is not the last row of the memory, go to the first step and increment j by 1.

[0072] Figure 3 Shows an example cyclic matrix and an example reliability matrix according to certain embodiments of the present disclosure. In the example, a parity check matrix 300 is defined. As described above, the parity check matrix 300 can include multiple columns (e.g., hundreds if not thousands) and multiple rows (e.g., hundreds if not thousands). Each column represents a variable node, and each row represents a check node.

[0073] In the case of QC-LDPC codes, the parity check matrix 300 follows a cyclic structure. In particular, the parity check matrix 300 includes a plurality of cyclic sub-matrices, where these cyclic sub-matrices can have the same size or different sizes (e.g., the size of each cyclic sub-matrix can be 256×256, or the size can vary). Generally, the cyclic sub-matrices can correspond to variable node cyclic matrices and check node cyclic matrices.

[0074] The variable node cyclic matrix is a matrix from the parity check matrix 300 that has a cyclic property for variable nodes. The columns of the cyclic matrix correspond to a set of variable nodes. Further, the cyclic matrix is completely specified by a vector, e.g., the first column, and the remaining columns are cyclic permutations of this vector, where the offset is equal to the column index.

[0075] Similarly, the check node cyclic matrix is a matrix from the parity check matrix 300 that has a cyclic property for check nodes. The rows of the cyclic matrix correspond to a set of check nodes. Further, the cyclic matrix is completely specified by a vector, e.g., the first row, and the remaining rows are cyclic permutations of this vector, where the offset is equal to the row index.

[0076] In Figure 3 the illustration, the first eight columns and the first eight rows of the parity check matrix 300 correspond to two variable node cyclic matrices (labeled as variable node cyclic matrix 310A and variable node cyclic matrix 310B in the figure) and two check node cyclic matrices (shown as check node cyclic matrix 320A and check node cyclic matrix 320B). The size of each of these cyclic matrices 310A, 310B, 320A, and 320B is 4×4. As described above, the size can be much larger (e.g., 256×256) and / or can vary (e.g., the size of variable node cyclic matrix 310A can be 256×256, while the size of variable node cyclic matrix 310B can be 128×128). Additionally, the number of variable node cyclic matrices can be different from the number of check node cyclic matrices (e.g., in an example where the size of the parity check matrix 300 is 100×30 and 10×10 cyclic sub-matrices are used to define it, there can be ten variable node cyclic matrices and three check node cyclic matrices).

[0077] Considering the example of the shown variable node cyclic matrix 310A, each column corresponds to one of the first four variable nodes (e.g., variable nodes 0 to 3), and each row corresponds to one of the first four check nodes (e.g., check nodes 0 to 3). The vector of this variable node cyclic matrix 310A is

[0078] Consider the example of the check node cyclic matrix 320B shown, where each column corresponds to one of the first four check nodes (e.g., check nodes 0 to 3), and each row corresponds to one of the first four variable nodes (e.g., variable nodes 3 to 7). The vectors of this check node cyclic matrix 320B are

[0079] As seen in the parity check matrix 300, the first variable node (variable node 0) is connected to the first check node and the fourth check node (e.g., check nodes 0 and 3 respectively). The first variable node is associated with the variable node cyclic matrix 310A but not with the variable node cyclic matrix 310B. Each of the first and fourth check nodes is associated with both the check node cyclic matrix 320A and the check node cyclic matrix 320B. Through these associations, it can be said that the variable node cyclic matrix 310A is associated with both the check node cyclic matrix 320A and the check node cyclic matrix 320B. When considering each of the second, third, and fourth variable nodes given the cyclic property of the variable node cyclic matrix 310A, the same conclusion can be drawn in the Figure 3 illustrative example. In contrast, when considering the fifth variable node (variable node 4) in the Figure 3 illustrative example, it can be concluded that the variable node cyclic matrix 310B is associated with both the check node cyclic matrix 320A and the check node cyclic matrix 320B. Here, when considering each of the sixth, seventh, and eighth variable nodes given the cyclic property of the variable node cyclic matrix 310B, the same conclusion can also be drawn in the Figure 3 illustrative example.

[0080] As further described in the figure below, message processing can be improved in terms of power consumption while maintaining the error correction capability performance based on message reliability estimation. An estimation of a single reliability can be performed on a set of messages. The set can consist of one element (e.g., performing the estimation for each message). However, to further reduce power consumption, the set can include multiple messages. In one example, the set consists of V2C messages corresponding to variable nodes associated with the same variable node cyclic matrix. In this example, the message reliability estimation is performed at the level of the variable node cyclic matrix. Compared with performing message reliability estimation at the level of variable nodes (e.g., each set consists of one V2C message), the processing of message reliability estimation saves a multiple (factor) equal to the size of the variable node cyclic matrix.

[0081] In Figure 3In the detailed description, and as explained above, each of the variable node circulant matrices 310A and 310B is associated with both the check node circulant matrices 320A and 320B. Let "j" be the index of the variable node circulant matrix (e.g., "j = 1" for the variable node circulant matrix 310A and "j = 2" for the variable node circulant matrix 310B). Let "k" be the index of the check node circulant matrix (e.g., "k = 1" for the check node circulant matrix 330A and "k = 2" for the check node circulant matrix 330B). In this example, for the first eight variable nodes and the first four check nodes of the parity check matrix, it is sufficient to estimate four message reliabilities "r k，j ", where "k" varies between 1 and 2 and "j" varies between 1 and 2. These four message reliabilities are illustrated using a reliability matrix 330 of size 2×2.

[0082] In contrast, if the message reliability is estimated on a variable node-by-variable node basis, 16 different reliabilities must be estimated for the first eight variable nodes and the first four check nodes (each variable node corresponds to two check nodes because each variable node is connected to two check nodes). Thus, by using a 4×4 variable node matrix, the number of estimates is reduced by a factor of 4 from 16 to 4.

[0083] In addition, by using a QC-LDPC code (e.g., the circulant submatrices in the parity check matrix 300), VSS scheduling can be performed. According to the VSS scheduling, multiple groups of variable nodes can be processed in parallel (each group corresponding to a different one in the variable node circulant matrix), and multiple groups of check nodes can be processed in parallel (each group corresponding to a different one in the check node circulant matrix) to speed up the processing of the message passing algorithm.

[0084] Figure 4Shows an example decoder including a plurality of variable node processing units 410 (shown as VNPU 410) and a plurality of check node processing units 420 (shown as CNPU 420) according to certain embodiments of the present disclosure. In the example, the decoder is an LDPC decoder supporting QC-LDPC decoding according to the VSS schedule. In this example, the number of variable node processing units 410 can be based on the size of the variable node circulant matrix and the check node degree. Similarly, the number of check node processing units 420 can be based on the size of the check node circulant matrix and the variable node degree. Additionally, the decoder includes a plurality of reliability estimators 430. The number can be equal to or less than the number of check node processing units 420. Although shown as separate components, the reliability estimators 430 can also be integrated with the variable node processing units 410 and / or the check node processing units 420. The reliability estimators 430 can be implemented in hardware and / or software on a dedicated processing unit, or in software on a general-purpose processor.

[0085] Generally, the reliability estimators 430 calculate the reliability of the messages passed between nodes. When the reliability estimators 430 are used to estimate the reliability of the V2C messages to assist in calculating the C2V messages, relatively higher processing and power savings can be achieved because the calculation of the C2V messages is relatively more complex than the calculation of the V2C messages (e.g., using "tanh (tangent)" calculation instead of "sum (summation)" calculation, as Figures 2A to 2B described). In other words, although reliability estimators for estimating the reliability of both types of messages (e.g., C2V and V2C) can be implemented, sufficient processing and power savings are achieved by implementing reliability estimators for estimating the reliability of the V2C messages, such that reliability estimators for estimating the reliability of the C2V messages may not be required.

[0086] There are different techniques for calculating the reliability of the V2C messages. One approach is to use the belief propagation (BP) method. However, the BP method uses a large hardware area, consumes more power (compared to the syndrome-based method disclosed below) and requires a long decoding waiting time. Generally, a trade-off is made among correction performance, hardware area, power consumption, and decoding delay. In the present disclosure, the syndrome-based method provides an improved balance. In particular, additional hardware area can be used to implement a plurality of approximations, which can then be used to dynamically reduce power consumption without degrading the correction performance. To achieve low latency, an estimation of the reliability of each circulant matrix (e.g., applicable to QC-LDPC codes) and a comparison with degree-related thresholds are used. The reliability estimation uses few calculations, and when using vertical scheduling, the calculations can be performed in parallel. The reliability estimation depends on the information in the check nodes and does not require additional reads of the variable node memory. This allows for low-latency decoding.

[0087] In an example of the syndrome-based method, the reliability of the V2C message is estimated based on parameters related to the syndrome. For example, when using QC-LDPC decoding with a VSS schedule, the reliability of the V2C message is "r k，j = S k number of 1s in / CS", where r k，j is the reliability of the V2C message, "S k " is the partial syndrome calculated based on the "k" check node circulant matrix, "number of 1s in S k " is the partial checksum, and "CS" is the checksum of the LDPC codeword.

[0088] For illustration, referring back to Figure 3 , for "k = 1" and "j = 1", the reliability "r 1，1 " is equal to the ratio of the number of 1s in the partial syndrome "S1" to the checksum of the LDPC codeword. The partial syndrome "S1" is calculated based on the check node circulant matrix for "k = 1" (e.g., check node circulant matrix 320A), for example, based on the number of unsatisfied check nodes associated with this check node circulant matrix (e.g., the number of unsatisfied check nodes is 0 to 3). For any variable node associated with the variable node circulant matrix for "j = 1" (e.g., variable node circulant matrix 310A; in this case, any one of variable nodes 0 to 3) and connected to a check node associated with the check node circulant matrix for "k = 1" (e.g., connected to one of check nodes 0 to 3), the estimated reliability "r 1，1 " is applied to the V2C message from this variable node to the connected check node.

[0089] The variable node processing unit 410 can be implemented in hardware and / or software on a dedicated processing unit that performs operations corresponding to or approximating the operations (1) to (6) described in conjunction with Figure 2A and Figure 2B . Optionally, the variable node processing unit 410 can be implemented as software on a general-purpose processor to perform operations (1) to (6). In both examples, the variable node processing unit 410 generates a V2C message for the variable node, where the V2C message is L(qij).

[0090] The check node processing unit 420 can be implemented in hardware and / or software on a dedicated processing unit that performs operations corresponding to or approximating the operations described in conjunction with Figure 2A and Figure 2BOperations corresponding to or approximating the described operations (7) to (10). Optionally, the check node processing unit 420 may be implemented as software on a general-purpose processor to perform operations (7) to (10). In both examples, the check node processing unit 420 generates a C2V message for a check node, where the C2V message is L(r ji ).

[0091] In addition, the check node processing unit 420 may implement multiple check node processing modes. The check node processing modes compute or approximate some or all of the functions used to generate the C2V message, including, for example, those described in connection with operations (8) and (9) either the "tanh" or "log" function. For example, the check node processing modes may quantize the functions at a particular quantization level (e.g., two-bit quantization for four LLR levels, four-bit quantization for sixteen LLR levels, etc.).

[0092] In Figure 4 an illustrative example, the check node processing unit 420 implements two check node processing modes: a simple mode 422A and an exact mode 424A (although there may be a greater number of check processing modes). The simple mode 422A uses two-bit quantization to approximate the functions (e.g., in order to compute ), while the exact mode 424A uses four-bit quantization to approximate the functions (e.g., in order to compute ). In this way, the simple mode 422A has a relatively smaller processing volume (and thus higher power efficiency) compared to the exact mode 424A, while the exact mode 424A is more accurate than the simple mode 422A. Thus, if the reliability associated with the incoming V2C message is low, the exact mode 424A can be used to accurately compute the corresponding C2V message. Conversely, if the reliability associated with the incoming V2C message is high, the simple mode 422A can be used to efficiently compute the corresponding C2V message. Of course, two-bit and four-bit quantization are merely examples, and there may be other ways to efficiently or accurately compute the C2V message.

[0093] In Figure 4 a further illustration, when following the VSS schedule, the check node processing unit 420 includes multiple check node processing modes of each type (e.g., multiple simple modes shown as simple mode 422A to simple mode 422L, and multiple exact modes shown as exact mode 424A to exact mode 424L). In this way, the check node processing unit 420 can process multiple check nodes in parallel (e.g., the number of multiple check nodes is "L").

[0094] For illustration, returning to referFigure 3 , consider an example where variable node 0 sends a V2C message to check node 0. In this case, the reliability "r" is used 1，1 " and compared with the reliability threshold "θ". If "r" 1，1 < θ", then the simple mode 422A is used to calculate Otherwise, the exact mode 424A is used to calculate The reliability threshold "θ" can be defined tentatively and / or experimentally. The reliability threshold "θ" can also be dynamic, where its value can vary according to the number of decoding iterations, the variable node degree (or the degree of the variable node cyclic matrix associated with the variable node) and / or the check node degree (or the degree of the check node cyclic matrix associated with the check node).

[0095] Figures 5 to 6 An example flow of decoding a codeword using a message passing algorithm in part is shown. An error correction system including a decoder such as an LDPC decoder is described as performing the specific operations of the example flow. The system is Figure 1 an example of the error correction system 100. In the example, the error correction system includes one or more processors and one or more memories. The memory stores computer-readable instructions to implement the specific functions of the error correction system. When run by the processors of the system, the instructions cause the system to perform the functions. The instructions stored in the memory together with the underlying processors represent the means for performing the functions. Further, the decoder includes a set of variable node processing units, a set of check node processing units, and a set of reliability estimators. At least one or more of the check node processing units implement multiple check node processing units, and one of these modes can be selected based on the message reliability estimated by one or more of the reliability estimators. The message passing algorithm is implemented by a set of variable node processing units, a set of check node processing units, and a set of reliability estimators, where the implementation can be in dedicated hardware and / or software running on a general-purpose processor. Here, the dedicated hardware and / or executable instructions on the general-purpose processor also represent the means for performing the functions. Although the operations are shown in a specific order, the operations can also be arranged otherwise, and it will be obvious to those skilled in the art that some operations can be skipped.

[0096] Figure 5 An example flow 500 of codeword decoding based on message reliability estimation according to certain embodiments of the present disclosure is shown. The LDPC codeword is stored in the memory of a device implementing the error correction system. The LDPC codeword is read from the memory (e.g., by a detector, such as Figure 1 detector 120), and the LDPC codeword may include multiple errors. The decoder iteratively decodes the LDPC codeword to correct the errors and outputs the decoded bits.

[0097] As shown in the figure, process 500 includes operation 502, in which the error correction system determines variable node to check node (V2C) messages. In an example, the V2C messages correspond to variable nodes that are connected to check nodes and determined by the variable node processing unit of the decoder. In an example of an LDPC codeword, the V2C messages are determined by performing operations (1) to (6) as described in conjunction with Figure 2A and Figure 2B and the V2C messages are passed to the check nodes (e.g., sent to the check node processing unit of the decoder that disposes of the check nodes).

[0098] Process 500 also includes operation 504, in which the error correction system determines the reliability of a set of V2C messages that includes the V2C messages. In an example, the set consists of only one V2C message (e.g., the V2C message determined in operation 502). In this example, the reliability can be determined based on the variable node degree, the syndrome of the LDPC codeword, and other parameters. In another example, the set includes multiple elements. For example, the set corresponds to a variable node cyclic submatrix. Here, the reliability is determined based on the syndrome and partial syndrome of the LDPC codeword. The partial syndrome is calculated based on the check node cyclic matrix associated with the check node. In a specific illustration, the reliability is determined as "r = number of 1s in S k / CS", where "r" is the reliability, "S k " is the partial syndrome calculated based on the check node cyclic matrix (e.g., the number of unsatisfied check nodes associated with the check node cyclic matrix), "number of 1s in S k " is the partial checksum, and "CS" is the checksum of the LDPC codeword.

[0099] Process 500 also includes operation 506, in which the error correction system selects a check node processing mode from multiple different check node processing modes based on the reliability. For example, the reliability is compared with one or more reliability thresholds "θ". The number of reliability thresholds "θ" can be based on the number of check node processing modes (e.g., if the number is "L", the number of reliability thresholds "θ" is "L - 1"; in an example of a simple mode and an exact mode, the number of reliability thresholds "θ" is 1). The reliability threshold "θ" can be defined based on the number of decoding iterations, the variable node degree, and / or the check node degree. According to the comparison, the check node processing mode is selected as the mode corresponding to the range of reliability results (e.g., in an example of a simple mode and an exact mode, if the reliability is less than the reliability threshold "θ", the simple mode is selected; otherwise, the exact mode is selected).

[0100] Process 500 further includes operation 508, in which the error correction system determines check node to variable node (C2V) messages based on a check node processing mode. In an example, the check node processing mode approximates operations (7) to (10) described above in connection with Figure 2A and Figure 2B Typically, the higher the reliability (as determined based on the comparison described in connection with operation 506), the more accurate the approximation of the check node processing mode, but the lower the power efficiency of the check node processing mode. Conversely, the lower the reliability (as determined based on the comparison described in connection with operation 506), the less accurate the approximation of the check node processing mode, but the higher the power efficiency of the check node processing mode. In an example of a simple mode and an exact mode, the simple mode is the first check node processing mode and the exact mode is the second check node processing mode. The first check node processing mode approximates the log-likelihood ratio of a variable node based on a first quantization level. The second check node processing mode approximates the log-likelihood ratio of a variable node based on a second quantization level. The second quantization level (e.g., four-bit quantization) is greater than the first quantization level (e.g., two-bit quantization).

[0101] Process 500 further includes operation 510, in which the error correction system decodes the LDPC codeword based on the C2V messages. For example, the C2V messages are sent to a variable node processing unit, operations 502 to 508 are performed for different variable nodes and check nodes, and operations 502 to 508 are iteratively repeated for multiple decoding iterations until the maximum number of iterations is reached or the syndrome of the LDPC codeword is zero. At this time, the error correction system outputs the decoded bits as the decoded LDPC codeword.

[0102] For illustration, in the case of QC-LDPC decoding, during a decoding iteration, the syndrome of the LDPC codeword is calculated, the number of decoding iterations is incremented, and it is determined whether the incremented number of decoding iterations does not exceed the maximum number and whether the syndrome is not zero. If the maximum number is reached or the syndrome is zero, decoding ends. Otherwise, decoding proceeds to the next decoding iteration. During the next decoding iteration corresponding to the incremented number of decoding iterations, the V2C messages corresponding to the variable nodes are updated (e.g., each time operation 502), it is determined that the variable node is associated with a "j" variable node circulant matrix, it is determined that the check node connected to the variable node is associated with a "k" check node circulant matrix, the reliability of the set of V2C messages is determined as "r k，j = S k where the number of 1s in / CS", where "r k，j " is the reliability, "S k " is a partial syndrome calculated based on the "k" check node circulant matrix, and "CS" is the checksum of the LDPC codeword. Additionally, the reliability "r k，j” is compared with a reliability threshold “θ”. Based on the comparison, a check node processing mode is selected (e.g., if only one reliability threshold “θ” is used, in the case of using the simple mode and the exact mode, if the reliability “r k，j ” is less than the reliability threshold “θ”, the simple mode is selected; otherwise, the exact mode is selected). When calculating various C2V messages corresponding to the check nodes associated with the check node cyclic matrix, the partial syndrome “S k ” is updated (e.g., as a function of the number of such non - satisfied check nodes). During this next decoding iteration, some or all of the sub - operations can be repeated for the remaining variable node cyclic matrix and the remaining check node cyclic matrix.

[0103] Figure 6 FIG. shows a more detailed example flow 600 of codeword decoding based on message reliability estimation according to certain embodiments of the present disclosure. The operations of flow 600 can be implemented as sub - operations of some or all of the operations of flow 500, particularly in the case of QC - LDPC decoding.

[0104] As shown, flow 600 begins at operation 602, where the error correction system initializes decoding. For example, the number of decoding iterations “i” is set to zero. And the syndrome “S” of the LDPC codeword is initialized to “S (-1) ”, where “S (-1) = yH T ”, where “y” corresponds to the output of the detector (e.g., hard decoding based on the read voltage level), and “H T ” is the transpose of the parity - check matrix. Generally, the syndrome “S (i) ” at decoding iteration “i” is calculated as where represents the decision of variable node “m” at decoding iteration “i”.

[0105] Flow 600 also includes operation 604, where the error correction system increments the number of decoding iterations (e.g., increments “i” by 1 such that “i = i + 1”).

[0106] Flow 600 also includes operation 606, where the error correction system determines whether the number of decoding iterations after the increment in operation 604 has reached the maximum number. The error correction system also determines whether the syndrome “S (i) ” of the LDPC codeword is zero. If the maximum number is reached or the syndrome “S (i) ” is zero, operation 608 is performed after operation 606. Otherwise, flow 600 proceeds to operation 610.

[0107] Flow 600 also includes operation 608, where the error correction system stops decoding. If the syndrome “S(i) is zero, then output the decoded LDPC codeword, where the output is If the syndrome "S( i＝最大次数 )" is not zero and the maximum number of iterations is reached, decoding failure can be declared.

[0108] Process 600 also includes operation 610, where the error correction system sets "j" to 1. Here, "j" is the index of the variable node cyclic matrix. For example, in the case of a 100×300 parity-check matrix, using a 10×10 cyclic submatrix, "j" can vary between 1 and "n circ ", where "n circ " is the total number of variable node cyclic matrices, and in this example, "n circ " is ten to one-hundred (one-hundred over ten) (e.g., ten).

[0109] Process 600 also includes operation 612, where the error correction system determines whether "j" is less than or equal to the total number of variable node cyclic matrices "n circ ". If so, operation 614 is performed after operation 610. Otherwise, process 600 loops back to operation 604 to increment the decoding iteration count "i".

[0110] Process 600 also includes operation 614, where the error correction system updates the V2C messages of each variable node associated with the variable node cyclic matrix having index "j". Specifically, each of these V2C messages can be updated by the variable node processing unit according to operations (1) to (6) described above in conjunction with Figure 2A and Figure 2B described.

[0111] Process 600 also includes operation 616, where the error correction system determines a set of check node cyclic matrices, where each of these matrices is associated with the variable node cyclic matrix having index "j" (e.g., as described for the cyclic matrix in conjunction with Figure 3 ). This set is denoted as "M(j)". Each of the check node cyclic matrices in the set "M(j)" has an index "k". In operation 616, the error correction system further determines whether each of the check node cyclic matrices in the set "M(j)" has been processed (shown in the figure as "k ∈ M(j)"). If so, operation 618 is performed after operation 616. Otherwise, process 600 proceeds to operation 620 to process the unprocessed check node cyclic matrices of the set "M(j)".

[0112] Process 600 also includes operation 618, where all the check node cyclic matrices of group "M(j)" have been processed. Therefore, the error correction system increments index "j" and process 600 loops back to operation 612.

[0113] Process 600 also includes operation 620, where some or all of the check node cyclic matrices of group "M(j)" have not been processed. Therefore, for each unprocessed check node cyclic matrix with a specific value of index "k", the error correction system calculates the reliability as "r k，j = S k number of 1s in / CS", where "r k，j " is the reliability, "S k " is the partial syndrome calculated based on the "k" check node cyclic matrix, and "CS" is the checksum of the LDPC codeword and corresponds to the number of 1s in the syndrome "S (i-1) ".

[0114] Process 600 also includes operation 622, where the error correction system compares the reliability with a set of reliability thresholds "θ". In Figure 6 the illustrative example, the set consists of a single "θ" that supports both a simple mode and an exact mode. If it is less than the reliability threshold "θ", then operation 624 is performed after operation 622, whereby the simple mode is selected. Otherwise, operation 626 is performed after operation 622, whereby the exact mode is selected.

[0115] Process 600 also includes operation 624, where the error correction system updates the C2V message corresponding to the check node associated with the "k" check node cyclic matrix. This update includes using the simple mode, where for example a simple function is calculated Operation 628 is performed after operation 624.

[0116] Process 600 also includes operation 626, where the error correction system also updates the C2V message corresponding to the check node associated with the "k" check node cyclic matrix. However, here the update includes using the exact mode, where for example an exact function is calculated Operation 628 is performed after operation 626.

[0117] Process 600 also includes operation 628, where the error correction system calculates and updates the syndrome "S (i) ". In the example, instead of updating the entire syndrome "S (i) " every time the "k" check node cyclic matrix is processed, the update is performed for the partial syndrome "S k (i) ". The partial syndrome "S k (i)” is the syndrome calculated based on the unsatisfied check nodes corresponding to the “k” check node cyclic matrix during decoding iteration “i”. In this case, process 600 loops back to operation 616 (however, if the syndrome “S (i) ” is updated in one go instead of through multiple updates, each update targeting a partial syndrome, then process 600 can loop back to operation 604).

[0118] Figure 7 is an example of a computer system 700 capable of implementing the present disclosure. Figure 7 This is merely an illustration of embodiments of the present disclosure and does not limit the scope of the present disclosure as recited in the claims. In one embodiment, the system is a computer system 700, which generally includes a display screen 710, a computer 720, a user output device 730, a user input device 740, a communication interface 750, etc. Figure 1 The error correction system 100 implements some or all of the components of the computer system 700.

[0119] As Figure 7 shown, the computer 720 may include a processor 760, which communicates with a plurality of peripheral devices via a bus subsystem 790. These peripheral devices may include a user output device 730, a user input device 740, a communication interface 750, and a storage subsystem, such as a random access memory (RAM) 770 and a disk drive 780.

[0120] The user input device 740 includes all possible types of devices and mechanisms for inputting information into the computer system 720. These may include a keyboard, a keypad, a touch screen incorporated into a display, an audio input device (e.g., a voice recognition system, a microphone), and other types of input devices. In various embodiments, the user input device 740 is typically implemented as a computer mouse, a trackball, a trackpad, a joystick, a wireless remote control, a graphics tablet, a voice command system, an eye tracking system, etc. The user input device 740 generally allows a user to select objects, icons, text, etc. that appear on the display screen 710 via commands such as clicking buttons.

[0121] The user output device 730 includes all possible types of devices and mechanisms for outputting information from the computer 720. These may include a display (e.g., the display screen 710), a non-visual display such as an audio output device, etc.

[0122] The communication interface 750 provides an interface with other communication networks and devices. The communication interface 750 can be used as an interface for receiving data from other systems and transmitting data to other systems. Examples of the communication interface 750 generally include Ethernet cards, modems (telephone, satellite, cable, ISDN), (asynchronous) digital subscriber line (DSL) units, FireWire interfaces, USB interfaces, etc. For example, the communication interface 750 can be connected to a computer network, a FireWire bus, etc. In other embodiments, the communication interface 750 can be physically integrated on the motherboard of the computer 720 and can be a software program, such as a soft DSL, etc.

[0123] In various embodiments, the computer system 700 can also include software capable of communicating over a network such as the HTTP, TCP / IP, RTP / RTSP protocols, etc. In alternative embodiments of the present disclosure, other communication software and transport protocols can also be used, such as IPX, UDP, etc. In some embodiments, the computer 720 includes one or more Xeon microprocessors from Intel as the processor 760. Additionally, in one embodiment, the computer 720 includes a UNIX-based operating system.

[0124] RAM 770 and the disk drive 780 are examples of tangible media configured to store data, including executable computer code, human-readable code, etc. Other types of tangible media include floppy disks, removable hard disks, optical storage media (e.g., CD-ROMs, DVDs, and barcodes), semiconductor memories (e.g., flash memories), non-transitory read-only memories (ROMs), battery-powered volatile memories, network storage devices, etc. RAM 770 and the disk drive 780 can be configured to store the basic programming and data structures that provide the functions of the present disclosure.

[0125] The software code modules and instructions that provide the functions of the present disclosure can be stored in RAM 770 and the disk drive 780. These software modules can be run by the processor 760. RAM 770 and the disk drive 780 can also provide a repository for storing data used in accordance with the present disclosure.

[0126] RAM 770 and the disk drive 780 can include multiple memories, including a main random access memory (RAM) that stores instructions and data during program execution and a read-only memory (ROM) that stores fixed non-transitory instructions. RAM 770 and the disk drive 780 can include a file storage subsystem that provides persistent (non-volatile) storage for program and data files. RAM 770 and the disk drive 780 can also include a removable storage system, such as a removable flash memory.

[0127] The bus subsystem 790 provides a mechanism for enabling the various components and subsystems of computer 720 to communicate with each other as expected. Although the bus subsystem 790 is schematically shown as a single bus, alternative embodiments of the bus subsystem may also utilize multiple buses.

[0128] Figure 7 is an example of a computer system capable of implementing the present disclosure. It will be apparent to those of ordinary skill in the art that many other hardware and software configurations are suitable for the present disclosure. For example, the computer can be a desktop, portable, rack-mounted, or tablet configuration. Additionally, the computer can be a series of networked computers. Further, consideration is given to using other microprocessors, such as Pentium TM or Itanium TM microprocessors; Opteron TM or AthlonXP TM microprocessors from Advanced Micro Devices, Inc., etc. Further, consideration is given to other types of operating systems, such as those from Microsoft Corporation etc., Solaris from Sun Microsystems, LINUX, UNIX, etc. In other embodiments, the above techniques can be implemented on a chip or an auxiliary processing board.

[0129] The various embodiments of the present disclosure can be implemented in a logical form of software or hardware or a combination of both. This logic can be stored as a set of instructions in a computer-readable or machine-readable non-transitory storage medium, the set of instructions being adapted to direct a processor of a computer system to execute a set of steps disclosed in the embodiments of the present disclosure. This logic can form a part of a computer program product, the computer program product being adapted to direct an information processing device to execute a set of steps disclosed in the embodiments of the present disclosure. Based on the disclosure and teachings provided herein, those of ordinary skill in the art will understand other ways and / or methods of implementing the present disclosure.

[0130] The data structures and code described herein can be stored, in whole or in part, in a computer-readable storage medium and / or hardware modules and / or hardware devices. Computer-readable storage media include, but are not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices (e.g., disk drives, tapes, CDs (compact discs), DVDs (digital versatile discs or digital video discs)), or other media now known or later developed that are capable of storing code and / or data. The hardware modules or devices described herein include, but are not limited to, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated or shared processors, and / or other hardware modules or devices now known or later developed.

[0131] The methods and processes described herein may be implemented, in part or in whole, as code and / or data stored in a computer-readable storage medium or device such that, when a computer system reads and executes the code and / or data, the computer system performs the associated methods and processes. These methods and processes may also be implemented, in part or in whole, as hardware modules or devices such that, when the hardware modules or devices are activated, they perform the associated methods and processes. The methods and processes disclosed herein may be implemented using a combination of code, data, and hardware modules or devices.

[0132] Although some detailed descriptions have been made of the foregoing embodiments for the purpose of clear understanding, the present disclosure is not limited to the details provided. There are many alternative ways to implement the present disclosure. The disclosed embodiments are illustrative rather than restrictive.

Claims

1. A method for decoding a Low-Density Parity-Check (LDPC) codeword, the method being implemented on a computing device and comprising: Determining variable node to check node messages, i.e., V2C messages, where the V2C messages correspond to variable nodes connected to a check node; Determining the reliability of a set of V2C messages including the V2C messages, the reliability representing the certainty of decoding the LDPC codeword, where each V2C message in the set of V2C messages corresponds to a different variable node from a set of variable nodes, and where the set of variable nodes corresponds to a variable node circulant matrix; Selecting a check node processing mode from multiple check node processing modes with different correction capabilities based on the reliability; Determining check node to variable node messages, i.e., C2V messages, based on the selected check node processing mode; and Decoding the LDPC codeword based on the C2V messages.

2. The method according to claim 1, further comprising: During a decoding iteration: Determining the syndrome of the LDPC codeword; Increasing the number of decoding iterations; Determining that the increased number of decoding iterations does not exceed a maximum number; And Determining that the syndrome of the LDPC codeword is not zero.

3. The method according to claim 2, further comprising: During the next decoding iteration corresponding to the increased number of decoding iterations: (a) Updating the V2C messages corresponding to the variable nodes; (b) Determining that the variable node is associated with a "j" variable node circulant matrix; (c) Determining that the check node connected to the variable node is associated with a "k" check node circulant matrix; (d) Determine the reliability of the set of V2C messages to be r k，j = S k where the number of 1s in / CS, where r k，j is the reliability, S k is the partial checksum calculated based on the "k" check node cyclic matrix, and CS is the checksum determined according to the syndrome of the LDPC codeword; (e) Compare r k，j with a reliability threshold, wherein the check node processing mode is selected based on the comparison; and (f) Update the partial checksum S k .

4. The method according to claim 3, further comprising: During the corresponding next decoding iteration, repeating steps (a) to (f) for the remaining variable node circulant matrices and the remaining check node circulant matrices.

5. The method according to claim 1, wherein the reliability of the set of V2C messages is determined based on the syndrome of the LDPC codeword.

6. The method according to claim 5, wherein the reliability of the set of V2C messages is further determined based on a partial syndrome associated with a circulant matrix, where the check node is associated with the circulant matrix.

7. The method according to claim 1, wherein the check node is associated with a check node circulant matrix, and the reliability is determined based on the syndrome of the LDPC codeword and a partial syndrome, where the partial syndrome is calculated based on the check node circulant matrix.

8. The method according to claim 7, wherein the reliability is determined as r = S k where the number of 1s in / CS, where r is the reliability, S k is the partial syndrome, and CS is the checksum determined according to the syndrome of the LDPC codeword.

9. The method according to claim 1, further comprising: Comparing the reliability with a reliability threshold, and the check node processing mode is selected based on the comparison.

10. The method according to claim 9, wherein the plurality of different check node processing modes include a first check node processing mode and a second check node processing mode, wherein the first check node processing mode approximates the log-likelihood ratio of the variable node based on a first quantization level, wherein the second check node processing mode approximates the log-likelihood ratio of the variable node based on a second quantization level, wherein the second quantization level is greater than the first quantization level, wherein if the reliability is less than the reliability threshold, the first check node processing mode is selected, and wherein if the reliability is greater than the reliability threshold, the second check node processing mode is selected.

11. The method according to claim 9, wherein the reliability threshold is defined based on the number of decoding iterations.

12. The method according to claim 9, wherein the reliability threshold is defined based on the variable node degree.

13. The method according to claim 9, wherein the reliability threshold is defined based on the check node degree.

14. A storage device, comprising: a memory that stores low-density parity-check code words, i.e., LDPC code words; and a set of processing units: determine variable node to check node messages, i.e., V2C messages, where the V2C messages correspond to variable nodes connected to a check node; determine the reliability of a set of V2C messages including the V2C messages, the reliability representing the certainty of decoding the LDPC code word, where each V2C message in the set of V2C messages corresponds to a variable node different from a set of variable nodes, and where the set of variable nodes corresponds to a variable node cyclic matrix; select a check node processing mode from a plurality of check node processing modes having different correction capabilities based on the reliability; and determine check node to variable node messages, i.e., C2V messages, based on the selected check node processing mode, wherein the LDPC code word is decoded based on the C2V messages.

15. The storage device according to claim 14, wherein the set of processing units further: during a decoding iteration: determine the syndrome of the LDPC code word; increase the number of decoding iterations; determine that the increased number of decoding iterations does not exceed a maximum number; and determine that the syndrome of the LDPC code word is not zero.

16. The storage device according to claim 15, wherein the set of processing units further: during the next decoding iteration corresponding to the increased number of decoding iterations: (a) update the V2C messages corresponding to the variable nodes; (b) determine that the variable node is associated with a "j" variable node cyclic matrix; (c) determine that the check node connected to the variable node is associated with a "k" check node cyclic matrix; (d) Determine the reliability of the set of V2C messages to be r k，j = S k The number of 1s in / CS, where r k，j is the reliability, S k is the partial syndrome calculated based on the "k" check node cyclic matrix, and CS is the checksum determined according to the syndrome of the LDPC codeword; (e) Compare r k，j with a reliability threshold, wherein the check node processing mode is selected based on the comparison; and (f) Update the partial syndrome S k .

17. The storage device according to claim 16, wherein the set of processing units further: during the corresponding next decoding iteration, repeat steps (a) to (f) for the remaining variable node cyclic matrices and the remaining check node cyclic matrices.

18. An error correction system, i.e., an ECC system, comprising: a set of processing units: Receive an LDPC codeword from a memory; Determine variable node to check node messages, i.e., V2C messages, where the V2C messages correspond to variable nodes connected to a check node; Determine the reliability of a set of V2C messages including the V2C messages, the reliability representing the certainty of decoding the LDPC codeword, where each V2C message in the set of V2C messages corresponds to a variable node different from a set of variable nodes, and where the set of variable nodes corresponds to a variable node circulant matrix; Select a check node processing mode from multiple check node processing modes having different correction capabilities based on the reliability; and Determine check node to variable node messages, i.e., C2V messages, based on the selected check node processing mode, where the LDPC codeword is decoded based on the C2V messages.

19. The ECC system according to claim 18, wherein the reliability of the set of V2C messages is determined based on the syndrome of the LDPC codeword and based on a partial syndrome associated with the circulant matrix, where the check node is associated with the circulant matrix.

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