Display device and driving method of the same

Abstract

A display device and a driving method of the display device are disclosed. The display device of the present invention includes a processor that supplies gradation data in an active period of a frame period and stops the supply of the gradation data in a blank period of the frame period; a timing control section that generates a change signal in a case where a difference between a first blank period of a first frame period and a second blank period of a second frame period is greater than a threshold value; a power supply section that supplies a first power voltage having a voltage level changed based on the change signal to a first power line; and a pixel that is commonly connected to the first power line.

Description

Technical Field

[0001] This invention relates to a display device and a driving method for the display device. Background Technology

[0002] With the development of information technology, the importance of display devices, as the connection medium between users and information, is becoming increasingly prominent. In response, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting displays (OLEDs) is increasing.

[0003] When the rendering speed of a display device does not match the display frequency, problems such as tearing and stuttering may occur. To solve these problems, it is often proposed to apply technologies such as G-sync and Free-sync to display devices.

[0004] However, when technologies such as G-sync and Free-sync are applied to display devices, the display frequency changes frequently, which may cause flicker. Summary of the Invention

[0005] The technical challenge to be solved is to provide a display device and its driving method that can prevent problems such as tearing, stuttering, and flickering during the matching of rendering speed and display frequency.

[0006] A display device according to an embodiment of the present invention includes: a processor that supplies grayscale data during active periods of a frame time period and stops supplying the grayscale data during blank periods of the frame time period; a timing control unit that generates a change signal when the difference between a first blank period of a first frame time period and a second blank period of a second frame time period is greater than a threshold; a power supply unit that supplies a first power supply voltage having a voltage level that changes based on the change signal to a first power line; and pixels that are connected to the first power line.

[0007] The first frame time period can be the previous frame time period of the second frame time period.

[0008] The cathodes of the pixels can be connected together to the first power line. When the second blank time period is longer than the first blank time period, the power supply unit can supply the first power supply voltage with an increased voltage level.

[0009] When the second blank time period is shorter than the first blank time period, the power supply unit can supply the first power supply voltage with a reduced voltage level.

[0010] The anodes of the pixels can be connected together to the first power line. When the second blank time period is longer than the first blank time period, the power supply unit can supply the first power supply voltage with a reduced voltage level.

[0011] When the second blank time period is shorter than the first blank time period, the power supply unit can supply the first power supply voltage with an increased voltage level.

[0012] The power supply unit can supply a second power voltage to the second power line. The cathodes of the pixels can be connected to the first power line, and the anodes of the pixels can be connected to the second power line. When the second blank time period is longer than the first blank time period, the power supply unit can supply the first power voltage and the second power voltage in such a way that the difference between the first power voltage and the second power voltage decreases.

[0013] When the second blank time period is shorter than the first blank time period, the power supply unit can supply the first power supply voltage and the second power supply voltage by increasing the difference between the first power supply voltage and the second power supply voltage.

[0014] The timing control unit may include: a blank time period calculation unit that uses a clock signal to count the second blank time period and calculate a blank count value; a memory that provides a previous count value for the first blank time period; and a blank time period comparison unit that generates the change signal when the difference between the blank count value and the previous count value is greater than the threshold.

[0015] The processor can provide a data enable signal that is enabled during the supply of grayscale data and disabled during the blank time period. The blank time period calculation unit can count the second blank time period during the period when the data enable signal is disabled.

[0016] The memory can update the previous count value to the blank count value.

[0017] A driving method for a display device according to an embodiment of the present invention may include the following steps: stopping the supply of grayscale data during a first blank time period of a first frame time period; calculating the first blank time period; stopping the supply of grayscale data during a second blank time period of a second frame time period after the first frame time period; calculating the second blank time period; generating a change signal if the difference between the first blank time period and the second blank time period is greater than a threshold; supplying a first power supply voltage having a voltage level changed based on the change signal to a first power line; and having pixels connected to the first power line receive the first power supply voltage.

[0018] The cathodes of the pixels can be connected together to the first power line, and when the second blank time period is longer than the first blank time period, the first power supply voltage with an increased voltage level can be supplied.

[0019] When the second blank time period is shorter than the first blank time period, the first power supply voltage with a reduced voltage level can be supplied.

[0020] The anodes of the pixels can be connected together to the first power line, and when the second blank time period is longer than the first blank time period, the first power supply voltage with a reduced voltage level can be supplied.

[0021] When the second blank time period is shorter than the first blank time period, the first power supply voltage with an increased voltage level can be supplied.

[0022] The driving method may further include the following steps: supplying a second power supply voltage to a second power line; and the pixel, which is connected to the second power line, receiving the second power supply voltage, wherein the cathode of the pixel may be connected to the first power line, and the anode of the pixel may be connected to the second power line. When the second blank time period is longer than the first blank time period, the first power supply voltage and the second power supply voltage may be supplied in such a way that the difference between the first power supply voltage and the second power supply voltage decreases.

[0023] When the second blank time period is shorter than the first blank time period, the first power supply voltage and the second power supply voltage can be supplied by increasing the difference between the first power supply voltage and the second power supply voltage.

[0024] The driving method may further include the following steps: using a clock signal to count the first blank time period to calculate a previous count value; using the clock signal to count the second blank time period to calculate a blank count value, wherein the step of generating the change signal may include: generating the change signal when the difference between the blank count value and the previous count value is greater than the threshold.

[0025] The driving method may further include the following steps: providing a data enable signal that is at an enable level during the period of supplying the grayscale data and at a disable level during the first blank time period and the second blank time period, wherein the first blank time period and the second blank time period may be counted during the period when the data enable signal is at the disable level.

[0026] The display device and driving method of the present invention can prevent problems such as tearing, stuttering, and flickering during the matching of rendering speed and display frequency. Attached Figure Description

[0027] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present invention.

[0028] Figure 2 This is a diagram used to illustrate pixels according to an embodiment of the present invention.

[0029] Figure 3 This is a diagram illustrating a pixel driving method according to an embodiment of the present invention.

[0030] Figure 4 This is a diagram illustrating a driving method for a display device according to an embodiment of the present invention.

[0031] Figure 5 This is a diagram illustrating a driving method for a display device according to another embodiment of the present invention.

[0032] Figure 6 This is a diagram illustrating a method for matching rendering speed with display frequency according to an embodiment of the present invention.

[0033] Figure 7 It is a graph used to illustrate the change in pixel brightness when the display frequency is relatively small.

[0034] Figure 8 It is a graph used to illustrate the change in pixel brightness when the display frequency is relatively high.

[0035] Figure 9 This is a graph used to illustrate the brightness of a display device as identified when the power supply voltage is varied based on the display frequency.

[0036] Figure 10 This is a diagram illustrating a timing control unit according to an embodiment of the present invention.

[0037] Figure 11 This is a diagram illustrating the algorithm of the timing control unit according to an embodiment of the present invention.

[0038] Figure 12 It is a graph used to illustrate the brightness of a display device as identified when the power supply voltage is changed based on the rate and magnitude of change of the display frequency. Detailed Implementation

[0039] Hereinafter, several embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art to which this invention pertains can easily implement it. The present invention can be implemented in many different forms and is not limited to the embodiments described herein.

[0040] To clearly illustrate the invention, irrelevant details have been omitted, and the same reference numerals have been used throughout the specification to refer to the same or similar constituent elements. Therefore, the reference numerals described above can also be used in different figures.

[0041] Furthermore, for ease of explanation, the size and thickness of the various components shown in the accompanying drawings are arbitrarily illustrated; therefore, the present invention is not limited to the content shown in the drawings. The thickness is enlarged in the drawings to clearly illustrate the multiple layers and regions.

[0042] Furthermore, the description of "identical" in the text means "substantially identical," that is, identical to the degree that would be acceptable to someone with ordinary knowledge. Other descriptions may omit the word "substantially."

[0043] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present invention.

[0044] Reference Figure 1 According to an embodiment of the present invention, the display device DD may include a processor 10, a timing control unit 11, a data driving unit 12, a scanning driving unit 13, a pixel unit 14, a sensing unit 15, and a power supply unit 16.

[0045] Processor 10 can supply a data enable signal (DE) and grayscale data (RGB). According to an embodiment, processor 10 can also supply a vertical synchronization signal (Vsync) and a horizontal synchronization signal (Hsync). Processor 10 can be constructed using a graphics processing unit (GPU), a central processing unit (CPU), an application processor (AP), etc. Processor 10 can refer to a single integrated chip (IC) or a group of multiple ICs.

[0046] Processor 10 can perform rendering to generate grayscale data (RGB) for each image.

[0047] Processor 10 can supply grayscale data RGB during the active periods of frame periods and can stop supplying grayscale data RGB during blank periods of frame periods. At this time, processor 10 can use a data enable signal DE to indicate whether to supply grayscale data RGB. For example, the data enable signal DE can be at an enable level during the supply of grayscale data RGB and at a disable level during the blank periods. For example, the data enable signal DE can include pulses of the enable level in each active period, on a horizontal period basis. Grayscale data RGB can be supplied in horizontal line units, corresponding to the pulses of the enable level of the data enable signal DE. Horizontal lines can represent pixels connected to the same scan line (e.g., pixel rows).

[0048] Each period of the vertical synchronization signal Vsync can correspond to a frame time period. For example, a logic high level in Vsync can indicate the valid time period of the corresponding frame time period, and a logic low level can indicate the blank time period of the corresponding frame time period. Each period of the horizontal synchronization signal Hsync can correspond to a horizontal time period.

[0049] The timing control unit 11 can receive a data enable signal DE and grayscale data RGB from the processor 10. According to an embodiment, the timing control unit 11 can also receive a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync from the processor 10.

[0050] The timing control unit 11 can supply control signals according to the specifications of the data driving unit 12, the scan driving unit 13, the power supply unit 16, the sensing unit 15, etc. Furthermore, the timing control unit 11 can provide processed or unprocessed grayscale data (RGB) to the data driving unit 12.

[0051] According to one embodiment, if the difference between the first blank time period of the first frame time period and the second blank time period of the second frame time period is greater than a threshold, the timing control unit 11 may generate a change signal. In this case, the first frame time period may be the previous frame time period of the second frame time period.

[0052] The data driving unit 12 can use grayscale data RGB and control signals to generate data voltages to be supplied to data lines D1, D2, D3...Dm. For example, the data driving unit 12 can use a clock signal to sample the grayscale data RGB, and can apply the data voltage corresponding to the grayscale data RGB to the data lines D1 to Dm in pixel row units. m can be an integer greater than 0.

[0053] The scan drive unit 13 can receive clock signals, scan start signals, etc. from the timing control unit 11 to generate first scan signals to be provided to the first scan lines S11, S12...S1n and second scan signals to be provided to the second scan lines S21, S22...S2n. n can be an integer greater than 0.

[0054] The scan drive unit 13 can sequentially supply first scan signals with pulses having a conduction level to the first scan lines S11, S12...S1n. Additionally, the scan drive unit 13 can sequentially supply second scan signals with pulses having a conduction level to the second scan lines S21, S22...S2n.

[0055] For example, the scan driver unit 13 may further include a first scan driver unit connected to the first scan lines S11, S12…S1n and a second scan driver unit connected to the second scan lines S21, S22…S2n. Each of the first and second scan driver units may include a scan stage configured as a shift register. Each of the first and second scan driver units may generate a scan signal by sequentially transmitting a scan start signal in the form of a pulse with an on-level conduction level to the next scan stage according to the control of a clock signal.

[0056] According to an embodiment, the first scan signal and the second scan signal can be the same. In this case, the first scan line and the second scan line connected to each pixel PXij can be connected to the same nodes. In this case, the scan driving unit 13 can also be configured as a single scan driving unit instead of being divided into a first scan driving unit and a second scan driving unit.

[0057] The sensing unit 15 can receive control signals from the timing control unit 11 to supply initialization voltages to the sensing lines I1, I2, I3...Ip, or receive sensing signals. For example, the sensing unit 15 can supply initialization voltages to the sensing lines I1, I2, I3...Ip during at least a portion of the display time period. For example, the sensing unit 15 can receive sensing signals through the sensing lines I1, I2, I3...Ip during at least a portion of the sensing time period. p can be an integer greater than 0.

[0058] The sensing unit 15 may include sensing channels connected to the sensing lines I1, I2, I3...Ip. For example, the sensing lines I1, I2, I3...Ip and the sensing channels may correspond one-to-one.

[0059] The pixel unit 14 includes pixels. Each pixel PXij can be connected to a corresponding data line, scan line, and sensor line. The structure of an exemplary pixel PXij will be described with reference to... Figure 2 This will be discussed later.

[0060] The power supply unit 16 can be connected to the pixel via power lines ELVDD and ELVSS. The pixel can be connected to both power lines ELVDD and ELVSS. The power supply unit 16 can supply power voltage to power lines ELVDD and ELVSS. For example, during the display period of the pixel unit 14, the power voltage of power line ELVDD can be greater than the power voltage of power line ELVSS.

[0061] In one embodiment, the power supply unit 16 may supply a power voltage having a voltage level that varies based on a change signal to the power line ELVSS. In another embodiment, the power supply unit 16 may also supply a power voltage having a voltage level that varies based on a change signal to the power line ELVDD. In yet another embodiment, the power supply unit 16 may further supply power voltages having voltage levels that vary based on a change signal to the power lines ELVSS and LVDD.

[0062] Figure 2 This is a diagram used to illustrate pixels according to an embodiment of the present invention. Figure 3 This is a diagram illustrating a pixel driving method according to an embodiment of the present invention.

[0063] refer to Figure 2Pixel PXij may include transistors T1, T2, T3, storage capacitor Cst, and light-emitting diode LD.

[0064] Transistors T1, T2, and T3 can be constructed using N-type transistors. In another embodiment, transistors T1, T2, and T3 can also be constructed using P-type transistors. In yet another embodiment, transistors T1, T2, and T3 can also be constructed using a combination of N-type and P-type transistors. Transistors in which the amount of current flowing increases when the voltage difference between the gate and source electrodes increases in the negative direction are collectively referred to as P-type transistors. Transistors in which the amount of current flowing increases when the voltage difference between the gate and source electrodes increases in the positive direction are collectively referred to as N-type transistors. Transistors can be configured in various forms, such as thin-film transistors (TFTs), field-effect transistors (FETs), and bipolar junction transistors (BJTs).

[0065] The gate electrode of the first transistor T1 can be connected to the first node N1, the first electrode can be connected to the power line ELVDD, and the second electrode can be connected to the second node N2. The first transistor T1 can be referred to as the driving transistor.

[0066] The gate electrode of the second transistor T2 can be connected to the first scan line S1i, the first electrode can be connected to the data line Dj, and the second electrode can be connected to the first node N1. The second transistor T2 can be referred to as the scan transistor.

[0067] The gate electrode of the third transistor T3 can be connected to the second scan line S2i, the first electrode can be connected to the second node N2, and the second electrode can be connected to the sensing line Ik. The third transistor T3 can be referred to as the sensing transistor.

[0068] The first electrode of the storage capacitor Cst can be connected to the first node N1, and the second electrode can be connected to the second node N2.

[0069] The anode of a light-emitting diode (LD) can be connected to the second node N2, and the cathode can be connected to the power line ELVSS. LDs can be constructed using materials such as organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (OLEDs), and quantum dot / well light-emitting diodes (QDs). Furthermore, LDs can be constructed using multiple OLEDs connected in series, parallel, or series-parallel connections.

[0070] During the display period, the power supply voltage of power line ELVDD can be greater than the power supply voltage of power line ELVSS. However, in special cases such as preventing the light-emitting diode (LD) from emitting light, the power supply voltage of power line ELVSS can also be set to be greater than the power supply voltage of power line ELVDD.

[0071] Reference Figure 3 The diagram illustrates an exemplary waveform of the signals applied to the scan lines S1i and S2i, data line Dj, and sensing line Ik connected to pixel PXij during the horizontal time intervals corresponding to scan lines S1i and S2i. k can be an integer greater than 0. A frame time interval may include multiple horizontal time intervals corresponding to pixel rows.

[0072] An initialization voltage VINT can be applied to the sensing line Ik.

[0073] Data line Dj can be sequentially supplied with data voltages DS(i-1)j, DSij, and DS(i+1)j in horizontal time intervals. During the corresponding horizontal time interval, a first scan signal with a conduction level (logic high level) can be applied to the first scan line S1i. Furthermore, synchronized with the first scan line S1i, a second scan signal with a conduction level can also be applied to the second scan line S2i.

[0074] For example, if a scan signal with a conduction level is applied to the first scan line S1i and the second scan line S2i, then the second transistor T2 and the third transistor T3 can be in the conducting state. Therefore, the storage capacitor Cst of pixel PXij will receive a voltage corresponding to the difference between the data voltage DSij and the initialization voltage VINT.

[0075] At this point, the difference between the initialization voltage VINT applied to the second node N2 and the power supply voltage of the power line ELVSS can be less than the threshold voltage of the light-emitting diode LD. Therefore, at this point in time, the light-emitting diode LD can be in a non-emission state.

[0076] Subsequently, if a cutoff level (logic low level) scan signal is applied to the first scan line S1i and the second scan line S2i, the second transistor T2 and the third transistor T3 can be in the cutoff state. Therefore, regardless of the voltage change of the data line Dj, the voltage difference between the gate electrode and the source electrode of the first transistor T1 can be maintained by the storage capacitor Cst.

[0077] Accordingly, a driving path can be formed connecting the power line ELVDD, the first transistor T1, the light-emitting diode LD, and the power line ELVSS. The luminous intensity of the light-emitting diode LD can be determined based on the driving current flowing in the driving path.

[0078] The driving current can be represented by the following mathematical formula 1.

[0079] [Mathematical Expression 1]

[0080] Ids=(1 / 2)*(W / L0*u*Cox*((Vdata-Vanode-Vth)^2)*(1+1md*(Velvdd-Vanode))

[0081] Here, Ids can be the drive current flowing between the drain and source electrodes of the first transistor T1, W can be the channel width of the first transistor T1, L can be the channel length of the first transistor T1, u can be the mobility of the first transistor T1, Cox can be the capacitance formed by the channel, insulating layer and gate electrode of the first transistor T1, Vdata can be the data voltage DSij, Vanode can be the anode voltage of the light-emitting diode LD, Vth can be the threshold voltage of the first transistor T1, lmd can be a constant, and Velvdd can be the power supply voltage of the power supply line ELVDD.

[0082] Furthermore, Vanode can be represented by the following mathematical formula 2.

[0083] [Mathematical Expression 2]

[0084] Vanode = Velvss + Vel

[0085] Here, Velvss can be the power supply voltage of the power line ELVSS, and Vel can be the voltage difference across the light-emitting diode LD.

[0086] Reference Figures 1 to 3 The structure and driving method of pixel PXij described below correspond to one embodiment. The embodiments described later can also be applied to the structure and driving method of any pixel according to the prior art. For example, in the absence of the sensing unit 15 and the second scan lines S21, S22...S2n, the third transistor T3 of pixel PXij can be omitted to apply the embodiments described later.

[0087] Figure 4 This is a diagram illustrating a driving method for a display device according to an embodiment of the present invention.

[0088] Reference Figure 4The illustration exemplarily depicts a continuous first frame time period FP1 and a second frame time period FP2. The first frame time period FP1 may include a first active time period APP1 and a first blank time period BLK1. The second frame time period FP2 may include a second active time period APP2 and a second blank time period. The following description uses the first frame time period FP1 as a reference; however, such a description can also be applied to other frame time periods.

[0089] During the first effective time period, APP1 can supply a data enable signal DE at an enable level (e.g., logic high level) in horizontal time period units. At this time, grayscale data RGB1, RGB2, RGB3...RGBn in horizontal line units can be supplied synchronously with the data enable signal DE at the enable level.

[0090] The data driving unit 12 can receive processed or unprocessed grayscale data RGB1, RGB2, RGB3...RGBn from the timing control unit 11. According to one embodiment, the data driving unit 12 can receive grayscale data RGB1 in horizontal line units serially and, upon completion of reception, latch it in parallel to generate data voltages. The j-th data voltage DS1j of such data voltages can be applied to the j-th data line Dj. Similarly, a portion of the grayscale data RGB2 can be output as data voltage DS2j in the next horizontal time period, and a portion of the grayscale data RGBn can be output as data voltage DSnj in the next horizontal time period.

[0091] As scan lines S11, S21, S12, S22...S1n, S2n are sequentially given a pass-through level (e.g., a logic high level) scan signal, the data voltage applied to the data lines can be input to the corresponding pixel. For example, if a pass-through level scan signal is applied to scan lines S11, S21, then data voltages DS1j,... can be input to the pixel of the first horizontal line (or pixel row). Subsequently, if a pass-through level scan signal is applied to scan lines S12, S22, then data voltages DS2j,... can be input to the pixel of the second horizontal line. This operation is repeated, and if a pass-through level scan signal is applied to scan lines S1n, S2n, then data voltages DSnj,... can be input to the pixel of the last horizontal line.

[0092] During the first blank period BLK1, a data enable signal DE with a disable level (e.g., logic low) can be supplied. At this time, the supply of grayscale data can be stopped.

[0093] Figure 5 This is a diagram illustrating a driving method for a display device according to another embodiment of the present invention.

[0094] Reference Figure 5 The processor 10 can supply the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync to the timing control unit 11.

[0095] For example, the first frame time period FP1 may include a first front shoulder time period FPP1, a first effective time period APP1, a first back shoulder time period BPP1, and a first blank time period BLK1. For example, the second frame time period FP2 may include a second front shoulder time period FPP2, a second effective time period APP2, a second back shoulder time period, and a second blank time period.

[0096] For example, the first pre-shoulder time period FPP1 is the time period when the vertical synchronization signal Vsync is at a logic high level and the data enable signal DE is at a logic low level, and it can be the time period before the supply of grayscale data RGB1, RGB2, RGB3...RGBn begins.

[0097] For example, the first effective time period APP1 is the time period during which the vertical synchronization signal Vsync is at a logic high level and the data enable signal DE includes a pulse with an enable level, and it can be the time period during which grayscale data RGB1, RGB2, RGB3...RGBn are supplied.

[0098] For example, the first back shoulder time period BPP1 is the time period when the vertical synchronization signal Vsync is at a logic high level and the data enable signal DE is at a logic low level, and it can be the time period after the supply of grayscale data RGB1, RGB2, RGB3...RGBn ends.

[0099] For example, the first blank time period BLK1 can be the time period when the vertical synchronization signal Vsync is at a logic low level and the data enable signal DE is at a logic low level.

[0100] Due to the explanations regarding the data enable signal DE, grayscale data RGB, data voltages DS1j, DS2j…DSnj, and the scan signal... Figure 4 The descriptions are the same as those in the previous section, so repeated descriptions will be omitted.

[0101] Figure 6 This is a diagram illustrating a method for matching rendering speed with display frequency according to an embodiment of the present invention.

[0102] Reference Figure 6The upper part of the diagram illustrates a comparative example used to match the rendering speed with the display frequency when the rendering speed does not match. In the comparative example, the lengths of the blank time intervals BLK1', BLK2', BLK3', and BLK4' are the same. Therefore, in the comparative example, the lengths of the frame time intervals FP1', FP2', FP3', FP4', and FP5' are the same. For illustration, it is assumed that the rendering time intervals Render_A', Render_C', and Render_D' are shorter than the frame time intervals, and that the rendering time interval Render_B' is longer than the frame time interval.

[0103] For example, the processor 10 can render the image A' during the rendering time period Render_A'. At time point t1a' after the rendering time period Render_A' ends, the grayscale data RGB_A' of the image A' can be provided to the timing control unit 11. Corresponding to such grayscale data RGB_A', the first effective time period APP1' and the first blank time period BLK1' of the first frame time period FP1' can be performed (see reference). Figure 4 or Figure 5 (The driving method). That is, the first frame can display the A' image.

[0104] After time point t1a', processor 10 can render the B' image during the rendering time period Render_B'. For example, the rendering time period Render_B' can end after time point t2a', which is the start time of the second frame time period FP2'. If grayscale data RGB_B' is provided during the second effective time period APP2', the second frame will display both the A' and B' images simultaneously, potentially causing a tearing issue. Therefore, processor 10 does not provide grayscale data RGB_B' during the second frame time period FP2', thus displaying the A' image in the second frame. Consequently, a stuttering issue occurs where the same A' image is displayed in both the first and second frames.

[0105] The processor 10 can provide grayscale data RGB_B' for the B' image at time t3a', which is the start of the third frame time period FP3'. Based on this, the third frame will display the B' image.

[0106] Similarly, at time point t4a', grayscale data RGB_C' for image C' is provided, so that image C' can be displayed in the fourth frame, and at time point t5a', grayscale data RGB_D' for image D' is provided, so that image D' can be displayed in the fifth frame.

[0107] Reference Figure 6The lower part illustrates an embodiment for matching the rendering speed to the display frequency when the rendering speed does not match the display frequency. In this embodiment, the lengths of the blank time intervals BLK1, BLK2, and BLK3 can be different from each other. Therefore, in this embodiment, the lengths of the frame time intervals FP1, FP2, FP3, and FP4 can be different from each other. Similarly, it is assumed that the rendering time intervals Render_A, Render_C, and Render_D are shorter than the frame time intervals, and that the rendering time interval Render_B is longer than the frame time interval.

[0108] The processor 10 can provide grayscale data RGB_A for image A at time point t1a', so that image A can be displayed in the first frame.

[0109] If the rendering time period Render_B for image B has not ended at time point t2a', processor 10 may extend the length of the first blank time period BLK1. For example, processor 10 may extend the length of the first blank time period BLK1 by extending the time period during which the data enable signal DE is held at the disabled level (see reference). Figure 4 and Figure 5 Additionally, processor 10 can extend the length of the first blank time period BLK1 by extending the period during which the vertical synchronization signal Vsync is kept at a logic low level (see reference). Figure 5 ).

[0110] Processor 10 can provide grayscale data RGB_B at time point t2a after the end of the rendering time period Render_B. Based on this, the second frame can display image B. Additionally, the third frame can display image C, and the fourth frame can display image D.

[0111] According to this embodiment, it has the advantage of being able to display images faster than the comparative example without tearing or stuttering issues.

[0112] Figure 7 It is a graph used to illustrate the change in pixel brightness when the display frequency is relatively small. Figure 8 It is a graph used to illustrate the change in pixel brightness when the display frequency is relatively high.

[0113] Reference Figure 7 For example, time point t1b could be the time when the initialization voltage VINT is applied to the second node N2 of pixel PXij within a horizontal time period. As mentioned above, at this time, the light-emitting diode LD is in a non-emitting state, so the brightness of pixel PXij may be reduced.

[0114] Time point t2b can be the time when the initialization voltage VINT is applied to the second node N2 of pixel PXij in the next horizontal time interval. As mentioned above, at this time, the light-emitting diode LD is in a non-emitting state, so the brightness of pixel PXij may decrease.

[0115] Figure 8 The situation is similar; time points t1c and t2c can be the times when the LED (LD) is in a non-emitting state during its respective horizontal time period. Because... Figure 7 When the display frequency is relatively low, Figure 8 To display cases with relatively high frequency, the time period t1c~t2c is shorter than the time period t1b~t2b. Using the same time period as a baseline, Figure 8 Compared to Figure 7 In this case, the non-emitting period of a light-emitting diode (LD) is longer. Therefore, Figure 8 The average luminance AVG2 is less than Figure 7 The average brightness is AVG1 under certain conditions. That is, the higher the display frequency, the lower the average brightness, and the lower the display frequency, the higher the average brightness. Therefore, compensation is needed for these conditions.

[0116] As the display frequency increases, compensation is needed to increase brightness. Referring to Formulas 1 and 2, decreasing the power supply voltage Velvss of the power supply line ELVSS increases the drive current Ids, thereby increasing the brightness of pixel PXij. Furthermore, increasing the power supply voltage Velvdd of the power supply line ELVDD also increases the drive current Ids. Additionally, increasing the difference between the power supply voltage Velvdd and the power supply voltage Velvss also increases the drive current Ids.

[0117] Conversely, when the display frequency decreases, compensation is needed, resulting in a reduction in brightness. Increasing the power supply voltage Velvss of the ELVSS power line may decrease the drive current Ids, thereby potentially reducing the brightness of pixel PXij. Furthermore, decreasing the power supply voltage Velvdd of the ELVDD power line can also reduce the drive current Ids. Additionally, reducing the difference between the power supply voltage Velvdd and the power supply voltage Velvss can also reduce the drive current Ids.

[0118] Figure 9 This is a graph used to illustrate the brightness of a display device as identified when the power supply voltage is varied based on the display frequency.

[0119] Reference Figure 9The following method can be used to compensate: when the display frequency increases, reduce the power supply voltage of the ELVSS power line, and when the display frequency decreases, increase the power supply voltage of the ELVSS power line.

[0120] In such cases, average brightness can be compensated; however, flickering caused by frequent changes in power supply voltage can be identified (refer to observation area PCL1). Especially in situations like... Figure 6 Similar to the previous implementation, when the lengths of the frame time intervals FP1, FP2, FP3, and FP4 change frequently, that is, when the display frequency changes frequently, this flickering problem may occur more frequently.

[0121] Figure 10 This is a diagram illustrating a timing control unit according to an embodiment of the present invention.

[0122] Reference Figure 10 According to an embodiment of the present invention, the timing control unit 11 may include a blank time period calculation unit 111, a blank time period comparison unit 112, and a memory 113.

[0123] The blank time period calculation unit 111 can use the clock signal CLK to count the current blank time period (e.g., the second blank time period BLK2) and calculate the blank count value blk_cnt. During the period when the data enable signal DE is at the disabled level, the blank time period calculation unit 111 can count the current blank time period (e.g., the second blank time period BLK2).

[0124] The period of the clock signal CLK can be shorter than a horizontal time interval. For example, a horizontal time interval can be an integer multiple of the period of the clock signal CLK. For example, the clock signal CLK can be a clock signal used to sample grayscale data RGB.

[0125] The memory 113 can provide a previous count value pre_cnt for a previous blank time period (e.g., the first blank time period BLK1).

[0126] If the difference between the blank count value blk_cnt and the previous count value pre_cnt is greater than the threshold TH1, the blank time period comparison unit 112 can generate a change signal VVA. At this time, the absolute value of the difference between the blank count value blk_cnt and the previous count value pre_cnt can be compared with the threshold TH1.

[0127] The threshold TH1 can be appropriately set according to the product. Therefore, the change signal VVA is generated only in the event of a sharp change in display frequency, thereby mitigating flicker. That is, according to this embodiment, the power supply voltage can be changed not only based on the magnitude of the display frequency, but also based on the rate of change of the display frequency.

[0128] In one embodiment, the change signal VVA may include information about the voltage level of the power supply voltage, either directly or indirectly. The voltage level of the power supply voltage may be pre-configured as a look-up table (LUT) according to the display frequency.

[0129] In one embodiment, the power supply unit 16 can supply a power voltage to the power line ELVSS with a voltage level that varies based on the change signal VVA. For example, if the second blank time period BLK2 is longer than the first blank time period BLK1, the power supply unit 16 can supply a power voltage with an increased voltage level to the power line ELVSS. Conversely, if the second blank time period BLK2 is shorter than the first blank time period BLK1, the power supply unit 16 can supply a power voltage with a decreased voltage level to the power line ELVSS.

[0130] In another embodiment, the power supply unit 16 can supply a power voltage to the power line ELVDD with a voltage level that varies based on the change signal VVA. For example, if the second blank time period BLK2 is longer than the first blank time period BLK1, the power supply unit 16 can supply a power voltage with a reduced voltage level to the power line ELVDD. Conversely, if the second blank time period BLK2 is shorter than the first blank time period BLK1, the power supply unit 16 can supply a power voltage with an increased voltage level to the power line ELVDD.

[0131] In another embodiment, the power supply unit 16 can supply power voltages to power lines ELVDD and ELVSS, with voltage levels varying based on the change signal VVA. For example, if the second blank time period BLK2 is longer than the first blank time period BLK1, the power supply unit 16 can supply power voltages in a manner that decreases the difference between the power voltage of power line ELVDD and the power voltage of power line ELVSS. Conversely, if the second blank time period BLK2 is shorter than the first blank time period BLK1, the power supply unit 16 can supply power voltages in a manner that increases the difference between the power voltage of power line ELVDD and the power voltage of power line ELVSS.

[0132] After the comparison operation of the blank time period comparison unit 112, the memory 113 can update the previous count value pre_cnt to the blank count value blk_cnt.

[0133] Figure 11 This is a diagram illustrating the algorithm of the timing control unit according to an embodiment of the present invention.

[0134] The blank time period calculation unit 111 can increment the clock count value clk_cnt by 1 in each cycle of the clock signal CLK (S101). Steps S101 (S102) can be repeated until the clock count value clk_cnt corresponds to a horizontal time period H_total.

[0135] When the clock count value clk_cnt corresponds to a horizontal time period H_total, the blank time period calculation unit 111 can confirm whether the data enable signal DE is at the enable level (S103).

[0136] If the current time point is within a blank time period, the data enable signal DE is at a disabled level, and the blank time period calculation unit 111 can initialize the clock count value clk_cnt (S104). Furthermore, the blank time period calculation unit 111 can increment the blank count value blk_cnt by 1 (S105).

[0137] The blank count value blk_cnt corresponding to the current blank time period can be calculated by repeating steps S101 to S105. The blank time period calculation unit 111 can confirm the end of the blank time period by confirming that the data enable signal DE is at the enable level (S103).

[0138] If the blank time period calculation unit 111 confirms that the blank count value blk_cnt is not 0 (S106), the blank time period comparison unit 112 can confirm whether the difference (e.g., absolute value) between the previous count value pre_cnt and the blank count value blk_cnt is greater than the threshold TH1 (S107). If the blank count value blk_cnt is 0, it means that the current time point is within the valid time period, and step S101 can be repeated again.

[0139] If the difference between the previous count value pre_cnt and the blank count value blk_cnt is greater than the threshold TH1, the blank time period comparison unit 112 can provide a change signal VVA (S108).

[0140] The memory 113 can update the previous count value pre_cnt to the blank count value blk_cnt (S109). Furthermore, the blank time period calculation unit 111 can initialize the clock count value clk_cnt to 0 (S110) and can initialize the blank count value blk_cnt to 0 (S111).

[0141] Figure 12It is a graph used to illustrate the brightness of a display device as identified when the power supply voltage is changed based on the rate and magnitude of change of the display frequency.

[0142] Figure 12 It is applied to Figure 10 and Figure 11 An exemplary graph illustrating the situation in the embodiments.

[0143] Reference Figure 12 During a period of time when the display frequency gradually changes (e.g., SAW waveform), if the difference (e.g., absolute value) between the previous count value pre_cnt and the blank count value blk_cnt is less than the threshold TH1, the power supply voltage of the power line ELVSS will not change.

[0144] Additionally, during periods of rapid frequency change (e.g., vertical rise or fall), if the difference (e.g., absolute value) between the previous count value pre_cnt and the blank count value blk_cnt exceeds a threshold TH1, the power supply voltage of the power line ELVSS will change. However, the power supply voltage of the power line ELVSS can be set to change only within a predetermined range (Min to Max).

[0145] When with Figure 9 When comparing the observation area PCL1 with the observation area PCL2, it can be confirmed that the average brightness is compensated and the frequency of flickering is low.

[0146] exist Figure 12 In one embodiment, the power supply voltage of the power supply line ELVSS is exemplarily described. In another embodiment, the power supply voltage of the power supply line ELVDD can be changed to achieve the effects of the invention. In yet another embodiment, the power supply voltages of the power supply lines ELVDD and ELVSS can be changed to achieve the effects of the invention (see [reference]). Figure 10 (Explanation).

[0147] The accompanying drawings and detailed description of the invention described above are merely examples of the present invention and are intended to illustrate the purpose of the invention only. They are not intended to limit the meaning or scope of the invention as set forth in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments exist. Consequently, the true scope of protection of the present invention should be determined by the technical concept outlined in the claims.

Claims

1. A display device, comprising: The processor supplies grayscale data during the valid time period of the frame time period and stops supplying grayscale data during the blank time period of the frame time period. The timing control unit generates a change signal when the difference between the first blank time period of the first frame time period and the second blank time period of the second frame time period is greater than a threshold. The power supply unit supplies a first power supply voltage to the first power line, having a voltage level that changes based on the change signal; and The pixels are all connected to the first power line. The cathode or anode of the pixel is connected to the first power line. The first frame time period is the frame time period preceding the second frame time period. When the cathodes of the pixels are all connected to the first power line, and when the second blank time period is longer than the first blank time period, the power supply unit supplies the first power supply voltage with an increased voltage level. When the anodes of the pixels are connected to the first power line, and when the second blank time period is longer than the first blank time period, the power supply unit supplies the first power supply voltage with a reduced voltage level.

2. The display device as claimed in claim 1, wherein, When the cathodes of the pixels are all connected to the first power line, When the second blank time period is shorter than the first blank time period, the power supply unit supplies the first power supply voltage with a reduced voltage level.

3. The display device as claimed in claim 1, wherein, When the anodes of the pixels are all connected to the first power line, When the second blank time period is shorter than the first blank time period, the power supply unit supplies the first power supply voltage with an increased voltage level.

4. The display device as claimed in claim 1, wherein, The power supply unit supplies a second power voltage to the second power line. When the cathodes of the pixels are commonly connected to the first power line and the anodes of the pixels are commonly connected to the second power line, When the second blank time period is longer than the first blank time period, the power supply unit supplies the first power supply voltage and the second power supply voltage in such a way that the difference between the first power supply voltage and the second power supply voltage decreases.

5. The display device as claimed in claim 4, wherein, When the second blank time period is shorter than the first blank time period, the power supply unit supplies the first power supply voltage and the second power supply voltage by increasing the difference between the first power supply voltage and the second power supply voltage.

6. The display device as claimed in claim 1, wherein, The timing control unit includes: The blank time period calculation unit uses a clock signal to count the second blank time period and calculate the blank count value; The memory provides a previous count value for the first blank time period; and The blank time period comparison unit generates the change signal when the difference between the blank count value and the previous count value is greater than the threshold.

7. The display device as claimed in claim 6, wherein, The processor provides a data enable signal that is at an enabled level during the supply of the grayscale data and at a disabled level during the blank time period. The blank time period calculation unit counts the second blank time period during the period when the data enable signal is at the disabled level.

8. The display device as claimed in claim 7, wherein, The memory updates the previous count value to the blank count value.

9. A method for driving a display device, comprising the following steps: The supply of grayscale data is stopped during the first blank time period of the first frame time period; Calculate the first blank time period; The supply of grayscale data is stopped during the second blank period of the second frame time period following the first frame time period; Calculate the second blank time period; A change signal is generated if the difference between the first blank time period and the second blank time period is greater than a threshold. A first power supply voltage having a voltage level that changes based on the change signal is supplied to the first power line; and The pixels that are connected to the first power line receive the first power supply voltage. The cathode or anode of the pixel is connected to the first power line. When the cathodes of the pixels are all connected to the first power line, and when the second blank time period is longer than the first blank time period, the first power supply voltage with an increased voltage level is supplied. When the anodes of the pixels are connected to the first power line, and when the second blank time period is longer than the first blank time period, the first power supply voltage with a reduced voltage level is supplied.

10. The driving method for the display device as claimed in claim 9, wherein, When the cathodes of the pixels are all connected to the first power line, When the second blank time period is shorter than the first blank time period, the first power supply voltage with a reduced voltage level is supplied.

11. The driving method for the display device as claimed in claim 9, wherein, When the anodes of the pixels are all connected to the first power line, When the second blank time period is shorter than the first blank time period, the first power supply voltage with an increased voltage level is supplied.

12. The driving method for the display device as described in claim 9, further comprising the following steps: Supply a second power supply voltage to the second power supply line; and The pixels that are connected to the second power line receive the second power supply voltage. in, When the cathodes of the pixels are commonly connected to the first power line and the anodes of the pixels are commonly connected to the second power line, When the second blank time period is longer than the first blank time period, the first power supply voltage and the second power supply voltage are supplied in such a way that the difference between the first power supply voltage and the second power supply voltage decreases.

13. The driving method for the display device as claimed in claim 12, wherein, When the second blank time period is shorter than the first blank time period, the first power supply voltage and the second power supply voltage are supplied in such a way that the difference between the first power supply voltage and the second power supply voltage increases.

14. The driving method for the display device as described in claim 9, further comprising the following steps: The previous count value is calculated by counting the first blank time period using a clock signal; and The blank count value is calculated by counting the second blank time period using the clock signal. in, The steps for generating the change signal include: The change signal is generated when the difference between the blank count value and the previous count value is greater than the threshold.

15. The driving method for the display device as claimed in claim 14, further comprising the following steps: A data enable signal is provided that is at an enable level during the supply of the grayscale data and at a disable level during the first blank time period and the second blank time period. in, The first blank time period and the second blank time period are counted during the period when the data enable signal is at the disabled level.

Images