Display device

Abstract

A display device according to one embodiment includes: a display panel including a plurality of pixels and a plurality of touch electrodes disposed in a display area; a display driver that outputs a data voltage in a display period of the active period and outputs a touch driving signal in a touch period of the active period; and a demultiplexer disposed between the display area and the display driver and connected between a first output terminal of the display driver and data lines of the display panel, in which the demultiplexer includes: a first transistor electrically connecting the first output terminal to a first data line among the data lines based on a first control signal; and a second transistor electrically connecting the first output terminal to a second data line among the data lines based on a second control signal, in which each of the first control signal and the second control signal alternately has a first gate high voltage and a first gate low voltage in a display period, and has a second gate low voltage less than the first gate low voltage in a blank period after the active period.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0164379, filed on November 18, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0002] This disclosure relates to a display device. Background Technology

[0003] With the development of the information society, the demand for display devices for displaying images is constantly increasing, and various types of display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (LED) displays are being adopted.

[0004] The image displayed on the display device can be a still image or a moving image, and moving images can include various types, such as motion pictures, game images, and movies. The display device can include multiple pixels and multiple switching elements for driving the pixels. Summary of the Invention

[0005] This disclosure relates to a display device in which the size and power consumption of transistors can be reduced by minimizing the degradation of transistors in the demultiplexer.

[0006] The purpose of this disclosure is not limited to the above-described purposes, and other technical purposes can be inferred from the following embodiments.

[0007] According to one embodiment, a display device is provided, the display device comprising: a display panel including a plurality of pixels and a plurality of touch electrodes disposed in a display area; a display driver that outputs a data voltage during a display period of an effective time period and outputs a touch driving signal during a touch period of the effective time period; and a demultiplexer disposed between the display area and the display driver and connected between a first output terminal of the display driver and a data line of the display panel, wherein the demultiplexer comprises: a first transistor that electrically connects the first output terminal to a first data line among the data lines based on a first control signal; and a second transistor that electrically connects the first output terminal to a second data line among the data lines based on a second control signal, wherein each of the first control signal and the second control signal alternately has a first gate high voltage and a first gate low voltage during the display period, and has a second gate low voltage lower than the first gate low voltage during a blank period after the effective time period.

[0008] According to another embodiment, a display device is provided, the display device comprising: a display panel including a plurality of pixels and a plurality of touch electrodes disposed in a display area; a display driver that outputs a data voltage during a display period of an effective time period and outputs a touch driving signal during a touch period of the effective time period; and a demultiplexer disposed between the display area and the display driver and connected between an output terminal of the display driver and a data line of the display panel, wherein the demultiplexer comprises: a first transistor that electrically connects the output terminal to a first data line among the data lines based on a first control signal; and a second transistor that electrically connects the output terminal to the first data line among the data lines based on a touch control signal, wherein the first control signal alternately has a first gate high voltage and a first gate low voltage during the display period, has a first gate low voltage during the touch period, and has a second gate low voltage lower than the first gate low voltage during a blank period after the effective time period.

[0009] According to another embodiment, a display device is provided, the display device including a display panel, the display panel including a plurality of pixels and a plurality of touch electrodes disposed in a display area; a display driver, the display driver outputting a data voltage during a display time period of an effective time period and outputting a touch drive signal during a touch time period of the effective time period; and a demultiplexer disposed between the display area and the display driver, and connected between the output terminal of the display driver and a data line of the display panel, wherein the demultiplexer includes: a first transistor, the first transistor electrically connecting the output terminal to a first data line among the data lines based on an odd-number control signal; and a second transistor, the second transistor electrically connecting the output terminal to the first data line based on an even-number control signal, wherein the odd-number control signal alternately has a first gate high voltage and a first gate low voltage during the display time period of an odd-number frame, has a second gate high voltage during the touch time period of the odd-number frame, and has a second gate low voltage lower than the first gate low voltage during the blank time period of the odd-number frame.

[0010] Details of other embodiments are included in the specific embodiments and the accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a plan view showing a display device according to one embodiment.

[0012] Figure 2 This is a block diagram illustrating a display device according to one embodiment.

[0013] Figure 3 This is a plan view showing the display panel of a display device according to one embodiment.

[0014] Figure 4 This is a waveform diagram showing the driving signals of the display panel in a display device according to one embodiment.

[0015] Figure 5 This is a circuit diagram illustrating a demultiplexer for a display device according to one embodiment.

[0016] Figure 6 It is shown Figure 5 The waveform diagram of the input / output signals of the demultiplexer in the display device.

[0017] Figure 7 It is shown Figure 5 A block diagram illustrating the output process of the first and second control signals in the display device.

[0018] Figure 8 This is a circuit diagram showing a demultiplexer for a display device according to another embodiment.

[0019] Figure 9 It is shown Figure 8 An example of a waveform diagram of the input / output signals of a demultiplexer in a display device.

[0020] Figure 10 It is shown Figure 8 Another example of a waveform diagram of the input / output signals of a demultiplexer in a display device.

[0021] Figure 11 It is shown Figure 8 Another example of the waveform diagram of the input / output signals of the demultiplexer in the display device.

[0022] Figure 12 It is shown Figure 8 A block diagram illustrating the output process of the first control signal, the second control signal, and the touch control signal in the display device.

[0023] Figure 13 This is a circuit diagram showing a demultiplexer for a display device according to yet another embodiment.

[0024] Figure 14 It is shown Figure 13 The waveform diagram of the input / output signals of the demultiplexer in the display device.

[0025] Figure 15 It is shown Figure 13 A block diagram illustrating the output process of odd and even control signals in a display device. Detailed Implementation

[0026] In the following description, embodiments will be referenced to the accompanying drawings. In this disclosure, when a first component (or region, layer, portion, etc.) is described as being "on," "connected," or "coupled to" a second component, this means that the first component can be directly connected / coupled to the second component, or that a third component can be disposed between the two.

[0027] The same reference numerals denote the same parts. Furthermore, in the drawings, the thickness, scale, and dimensions of the parts are exaggerated for the purpose of effectively describing the technical content. The term "and / or" includes all or one combination that can be defined by the associated configuration.

[0028] Terms such as "first" and "second" may be used to describe various components, but components are not limited by the terms. These terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the embodiments, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly specifies otherwise, the singular includes the plural.

[0029] Terms such as “below,” “on the lower side,” “above,” and “on the upper side” are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are described relative to the directions indicated by the markings in the drawings.

[0030] It should be understood that terms such as “comprising” or “having” are intended to specify the presence of the features, quantities, steps, operations, components, parts or combinations thereof described in this disclosure, and do not preclude the possibility of the existence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof.

[0031] Figure 1 This is a plan view showing a display device according to one embodiment.

[0032] refer to Figure 1 The display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-readers, portable multimedia players (PMPs), navigation devices, ultra-mobile PCs (UMPCs), etc. For example, the display device 10 can be applied to display units in televisions, laptops, monitors, billboards, or the Internet of Things (IoT). As another example, the display device 10 can be applied to wearable devices such as smartwatches, smartwatch phones, glasses displays, and head-mounted displays (HMDs).

[0033] The display device 10 may include a display panel 100, a display driver 200, a flexible film 210, a source circuit board 300, a flexible cable 310, a control circuit board 400, a timing controller 500, a power supply unit 600, and a memory 700.

[0034] Display panel 100 may include a display area DA and a non-display area NDA. The display area DA may include a plurality of pixels for displaying an image. Each of the plurality of pixels may emit light from a light-emitting area or an opening area. For example, the display area DA may include pixel circuitry with switching elements, a pixel defining film defining the light-emitting area, and a light-emitting element.

[0035] The display driver 200 supplies data voltage to the data lines of the display panel 100. The display driver 200 can be electrically connected to the data lines of the display panel 100 via a flexible film 210 and pad portions of the display panel 100. The display driver 200 can be formed as an integrated circuit (IC). For example, the display driver 200 can be attached to a surface of the flexible film 210 in a chip-on-film (COF) manner. The flexible film 210 can include lines that electrically connect the display driver 200 to the display panel 100. One side of the flexible film 210 can be electrically connected to the pad portions of the display panel 100, and the other side of the flexible film 210 can be electrically connected to the source circuit board 300.

[0036] The source circuit board 300 can electrically connect the control circuit board 400 to the flexible film 210. The source circuit board 300 can be a printed circuit board including lines that electrically connect the display driver 200 to other devices. The source circuit board 300 can be electrically connected to the control circuit board 400 via a flexible cable 310. For example, the flexible cable 310 can be a flexible flat cable (FFC), but is not limited thereto.

[0037] The control circuit board 400 can be a printed circuit board on which a timing controller 500, a power supply unit 600, and a memory 700 are mounted. The control circuit board 400 is not limited to... Figure 1 The control circuit board, and may have control components and various electrical devices mounted on it.

[0038] The timing controller 500 can be attached to one surface of the control circuit board 400. The timing controller 500 can control the driving timing of the display driver 200 by sending digital video data to the display driver 200.

[0039] The power supply unit 600 can generate a power supply voltage and supply the generated power supply voltage to the display panel 100. Here, the power supply voltage may include, but is not limited to, the drive voltage EVDD, the low potential voltage EVSS, the initialization voltage Vint, the reference voltage Vref, and the bias voltage Vbias.

[0040] The memory 700 can store pixel sensing information. For example, the memory 700 can store threshold voltage information of transistors received from the display driver 200 and supply the threshold voltage information to the timing controller 500.

[0041] Figure 2 This is a block diagram illustrating a display device according to one embodiment.

[0042] refer to Figure 2 The display panel 100 may include a display area DA and a non-display area NDA. The display area DA may include multiple pixels SP and power lines VL, scan lines SL and data lines DL connected to the pixels SP.

[0043] Each of the multiple pixels SP can be connected to a scan line SL, a data line DL, and a power line VL. Each of the multiple pixels SP may include a transistor, a light-emitting element, and a capacitor.

[0044] Scan lines SL can extend along a first direction DR1 and can be spaced apart from each other along a second direction DR2 that intersects with the first direction DR1. Scan lines SL can sequentially supply scan signals to multiple pixels SP.

[0045] The data lines DL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. The data lines DL supply data voltage to the pixel SP. The data voltage determines the brightness of the pixel SP.

[0046] The power lines VL can extend along the second direction DR2 and can be spaced apart from each other along the first direction DR1. The power lines VL can supply power voltages to multiple pixels SP. Here, the power voltages may include, but are not limited to, the drive voltage EVDD, the low-level voltage EVSS, the initialization voltage Vint, the reference voltage Vref, and the bias voltage Vbias.

[0047] Scan driver 220 may include multiple transistors and generate scan signals based on scan control signals SCS. Scan driver 220 may use a shift register to shift the scan signals and sequentially supply the shifted scan signals to scan lines SL. The scan signals of scan driver 220 can select pixels SP to be supplied with data voltages, and the selected pixels SP can receive data voltages through data lines DL. Scan driver 220 may be disposed on one or both sides of the non-display area NDA in a gate-in-panel (GIP) manner.

[0048] The timing controller 500 can receive digital video data DATA and timing signals from a display driving system or graphics device (not shown). The timing controller 500 can generate a data control signal DCS based on the timing signals. The timing controller 500 can control the operation timing of the display driver 200 by supplying digital video data DATA and the data control signal DCS to the display driver 200. The display driver 200 can convert the digital video data DATA into an analog data voltage and supply the analog data voltage to the data line DL. The timing controller 500 can generate a scan control signal SCS based on the timing signals. The timing controller 500 can control the operation timing of the scan driver 220 by supplying the scan control signal SCS to the scan driver 220. The timing controller 500 can change the driving frequency of the display panel 100 based on the input frequency received from the display driving system or graphics device.

[0049] The power supply unit 600 can supply a power supply voltage to the power line VL. The power supply voltage may include, but is not limited to, a drive voltage EVDD, a low-level voltage EVSS, an initialization voltage Vint, a reference voltage Vref, and a bias voltage Vbias. The power supply unit 600 can generate the drive voltage EVDD and supply it to the drive voltage line, generate the initialization voltage Vint and supply it to the initialization voltage line, generate the bias voltage Vbias and supply it to the bias voltage line, generate the reference voltage Vref and supply it to the reference voltage line, and generate the low-level voltage EVSS and supply it to the low-level line.

[0050] Figure 3 This is a plan view showing the display panel of a display device according to one embodiment, and Figure 4 This is a waveform diagram showing the driving signals of the display panel in a display device according to one embodiment.

[0051] refer to Figure 3 and Figure 4 The display panel 100 may include a display area DA and a non-display area NDA. The display area DA may include pixels SP and touch electrodes TE. The display area DA may have display function and touch sensing function. The display area DA may include multiple pixels SP arranged in a matrix and display an image. The display area DA may include touch electrodes TE overlapping with the pixels SP and sense whether the user touches the screen in a capacitive manner. For example, the touch electrodes TE may sense the user's touch in a self-capacitance manner or a mutual capacitance manner. In the following, the self-capacitance manner will be described as an example.

[0052] The pixel SP can be connected to the scan line SL and the data line DL. The pixel SP can receive the scan signal from the scan line SL and the data voltage from the data line DL.

[0053] Touch electrodes TE can be electrically connected to the display driver 200 via touch lines TL. The touch lines TL can extend in the second direction DR2 and can be set parallel to the data lines DL. Multiple touch electrodes TE can be formed by dividing a common electrode disposed in the display area DA into multiple segments, and each touch electrode TE can be formed to a specific size including multiple pixels SP based on the size of the touch point. The touch electrodes TE can act as a common electrode for multiple overlapping pixels SP and as a touch sensor that generates capacitance when a user touches the screen.

[0054] The display panel 100 can be driven by dividing the display time period DP and touch time period TP in a time-division manner. One frame can be driven in a time-division manner, while the display time period DP and touch time period TP are alternated by a touch synchronization signal. For example, the display panel 100 can be scanned once in multiple display time periods DP during one frame, and the touch electrode TE can be driven and sensed multiple times in multiple touch time periods TP.

[0055] During the display time period DP, the scan driver 220 can supply a scan signal to the pixel SP, and the display driver 200 can supply a data voltage to the pixel SP. During the display time period DP, the display driver 200 can supply a data voltage Vdata to the data line DL via the demultiplexer DMX, and a common voltage VDC to the touch electrode TE via the touch line TL.

[0056] During the touch duration TP, the display driver 200 can supply the touch drive signal VCOM to the touch electrode TE and read and sense capacitance changes from the touch electrode TE to which the touch drive signal VCOM is applied. Here, in the touch drive signal VCOM, the high common voltage VCH and the low common voltage VCL alternate. The display driver 200 can supply the touch drive signal VCOM to the touch line TL during the touch duration TP and supply the touch drive signal VCOM to the data line DL via the demultiplexer DMX. Therefore, the display panel 100 can minimize the parasitic capacitance between the touch electrode TE and the data line DL during the touch duration TP, thereby minimizing the resistive-capacitive (RC) load on the touch electrode TE and improving touch sensing sensitivity. For example, the touch drive signal VCOM can be represented by a common voltage modulation signal or a no-load drive (LFD) signal.

[0057] The demultiplexer DMX can be located on one side of the non-display area NDA. The demultiplexer DMX can also be located between the display area DA and the display driver 200. The demultiplexer DMX can divide the data voltage Vdata supplied from the display driver 200 through multiple output terminals CH in a time-division manner within the display time period DP, and distribute and supply the time-division data voltage Vdata to multiple data lines DL. Therefore, the number of output terminals CH of the display driver 200 can be reduced compared to the number of data lines DL.

[0058] The demultiplexer DMX can supply the touch drive signal VCOM from the display driver 200 through multiple output terminals CH to multiple data lines DL during the touch time period TP.

[0059] The demultiplexer DMX may include a 1:n demultiplexer (DEMUX) circuit that transmits the output of the display driver 200's output terminal CH to n data lines DL (n is an integer greater than 2). Therefore, the number of output terminals CH of the display driver 200 can be reduced to 1 / n of the number of data lines DL.

[0060] The scan driver 220 can be located on the side of the non-display area NDA where the demultiplexer DMX is not located. For example, the scan driver 220 can be located on the left or right side of the non-display area NDA, or both, to supply scan signals. The scan driver 220 can be embedded in the display panel 100 in a gate-in-panel (GIP) type, wherein the scan driver 220 includes transistors formed using the same process as the transistors of the display area DA.

[0061] The scan driver 220 can generate gate pulses or scan pulses according to the gate control signal during the display time period DP, thereby sequentially and line by line driving the scan lines SL. The scan driver 220 can supply a scan signal with a gate on voltage during a horizontal time period of the display time period DP and supply a gate off voltage after a horizontal time period.

[0062] The display driver 200 can drive the data line DL and touch line TL of the display panel 100 respectively. For example, the display driver 200 can be provided by integrating a source driver and a touch readout circuit, wherein the source driver supplies a data signal to the data line DL and a common voltage VDC to the touch electrode TE during the display time period DP, and the touch readout circuit supplies a touch drive signal VCOM to the data line DL and the touch electrode TE and senses the capacitance change of each touch electrode TE during the touch time period TP.

[0063] Figure 5This is a circuit diagram illustrating a demultiplexer for a display device according to one embodiment, and Figure 6 It is shown Figure 5 The waveform diagram of the input / output signals of the demultiplexer in the display device.

[0064] refer to Figure 5 and Figure 6 The demultiplexer DMX may include a 1:n demultiplexer (DEMUX) circuit, which transmits the output of the display driver 200's output terminal CH to n data lines DL (n is an integer greater than 2). The number of transistors included in the demultiplexer DMX and the number of data lines DL connected to the demultiplexer DMX are not limited to... Figure 5 Those shown.

[0065] The demultiplexer DMX may include first transistors through fourth transistors T1, T2, T3, and T4. First transistor T1 and second transistor T2 may be connected to the first output terminal CH1 of the display driver 200, and may sequentially transmit the data voltage Vdata received from the first output terminal CH1 to the first data line DL1 and the second data line DL2 in a time-division manner. Third transistor T3 and fourth transistor T4 may be connected to the second output terminal CH2 of the display driver 200, and may sequentially transmit the data voltage Vdata received from the second output terminal CH2 to the third data line DL3 and the fourth data line DL4 in a time-division manner.

[0066] The first transistor T1 can be turned on based on the first control signal MUX1 to supply the output signal of the first output terminal CH1 to the first data line DL1. The second transistor T2 can be turned on based on the second control signal MUX2 to supply the output signal of the first output terminal CH1 to the second data line DL2. The third transistor T3 can be turned on based on the first control signal MUX1 to supply the output signal of the second output terminal CH2 to the third data line DL3. The fourth transistor T4 can be turned on based on the second control signal MUX2 to supply the output signal of the second output terminal CH2 to the fourth data line DL4.

[0067] The first to fourth transistors T1, T2, T3, and T4 can be configured as n-channel oxide transistors. The first to fourth transistors T1, T2, T3, and T4 can be turned on based on first and second gate high voltages VGH1 and VGH2, and turned off based on first and second gate low voltages VGL1 and VGL2. For example, the first gate high voltage VGH1 can be greater than the second gate high voltage VGH2 (VGH1>VGH2), and the first gate low voltage VGL1 can be greater than the second gate low voltage VGL2 (VGL1>VGL2). As another example, the first gate high voltage VGH1 and the second gate high voltage VGH2 can be the same (VGH1=VGH2).

[0068] When turned on by either the first gate high voltage VGH1 or the second gate high voltage VGH2, the n-channel oxide transistor can receive positive bias temperature stress (PBTS) through a positive drive voltage (Vgs) and high drain current stress (HDCS) through a high drain current. As the positive bias temperature stress (PBTS) and high drain current stress (HDCS) accumulate, the oxide transistor may degrade, and the threshold voltage (Vth) may thus shift.

[0069] When turned off by the first or second gate low voltage VGL1 or VGL2, the n-channel oxide transistor can receive negative bias temperature radiation stress (NBTiS) through a negative drive voltage (Vgs) and counteract positive bias temperature stress (PBTS) and high drain current stress (HDCS), thereby recovering the threshold voltage (Vth) shift caused by transistor degradation. Here, as the recovery time increases and the gate low voltage decreases, the degradation of the n-channel oxide transistor can be reduced.

[0070] The first frame (Frame1) may include an active time period (ACT) and a passive time period (BLK). The display driver 200 may supply the data voltage Vdata to the data line DL during the active time period (ACT). When the first to fourth transistors T1, T2, T3, and T4 are turned off during the active time period (ACT), they may perform recovery during the first recovery time period (Recovery1). Additional recovery may be performed during the second recovery time period (Recovery2) of the passive time period (BLK).

[0071] The effective time period ACT can include a display time period DP and a touch time period TP. The first to fourth transistors T1, T2, T3, and T4 can alternately repeat the on-time period of the first gate high voltage VGH1 and the off-time period of the first gate low voltage VGL1 during the display time period DP. The first to fourth transistors T1, T2, T3, and T4 can be turned on based on the first gate high voltage VGH1 to supply data voltage Vdata to the first to fourth data lines DL1, DL2, DL3, and DL4 respectively during the display time period DP. The first to fourth transistors T1, T2, T3, and T4 can perform recovery during the first recovery time period Recovery1 of the display time period DP, wherein they are turned off by the first gate low voltage VGL1.

[0072] The first to fourth transistors T1, T2, T3 and T4 can be turned on based on the second gate high voltage VGH2 to supply touch drive signals VCOM to the first to fourth data lines DL1, DL2, DL3 and DL4 respectively during the touch time period TP.

[0073] The first to fourth transistors T1, T2, T3 and T4 can perform recovery during the second recovery period Recovery2 in the blank period BLK, where they are turned off by the second gate low voltage VGL2.

[0074] Therefore, the first to fourth transistors T1, T2, T3, and T4 can offset the positive bias temperature stress (PBTS) and high drain current stress (HDCS) applied by the first gate low voltage VGH1 during the on-time of the display time period DP by the negative bias temperature illumination stress (NBTiS) applied by the first gate low voltage VGL1 during the first recovery time period Recovery1 of the display time period DP, and further offset the positive bias temperature stress (PBTS) and high drain current stress (HDCS) by the negative bias temperature illumination stress (NBTiS) applied by the second gate low voltage VGL2 during the second recovery time period Recovery2 of the blank time period BLK. Thus, the first to fourth transistors T1, T2, T3, and T4 can ensure sufficient recovery time, thereby reducing stress and degradation.

[0075] Figure 7 It is shown Figure 5 A block diagram illustrating the output process of the first and second control signals in the display device.

[0076] refer to Figure 7The power supply unit 600 can generate a power supply voltage and supply the generated power supply voltage to the display panel 100. The power supply unit 600 can supply power supply voltage to the first control signal output unit MO1 and the second control signal output unit MO2, and the first control signal output unit MO1 and the second control signal output unit MO2 can output a first control signal MUX1 and a second control signal MUX2.

[0077] The power supply unit 600 can supply a first gate high voltage VGH1 and a second gate high voltage VGH2 to the first switching unit SW1, and a first gate low voltage VGL1 and a second gate low voltage VGL2 to the second switching unit SW2. For example, the first gate high voltage VGH1 can be greater than the second gate high voltage VGH2 (VGH1>VGH2), and the first gate low voltage VGL1 can be greater than the second gate low voltage VGL2 (VGL1>VGL2). As another example, the first gate high voltage VGH1 and the second gate high voltage VGH2 can be the same (VGH1=VGH2).

[0078] The first switching unit SW1 can supply a first gate high voltage VGH1 and a second gate high voltage VGH2 to the first control signal output unit MO1 and the second control signal output unit MO2. The second switching unit SW2 can supply a first gate low voltage VGL1 and a second gate low voltage VGL2 to the first control signal output unit MO1 and the second control signal output unit MO2.

[0079] Therefore, the first control signal output unit MO1 can output the first control signal MUX1 during the display time period DP of the effective time period ACT, wherein the first gate high voltage VGH1 and the first gate low voltage VGL1 alternate. The first control signal output unit MO1 can also output the first control signal MUX1 with a second gate high voltage VGH2 during the touch time period TP of the effective time period ACT. The first control signal output unit MO1 can also output the first control signal MUX1 with a second gate low voltage VGL2 during the blank time period BLK.

[0080] The second control signal output unit MO2 can output a second control signal MUX2 during the display time period DP of the effective time period ACT, wherein the first gate high voltage VGH1 and the first gate low voltage VGL1 alternate. The second control signal output unit MO2 can also output a second control signal MUX2 with a second gate high voltage VGH2 during the touch time period TP of the effective time period ACT. Finally, the second control signal output unit MO2 can output a second control signal MUX2 with a second gate low voltage VGL2 during the blank time period BLK.

[0081] Figure 8This is a circuit diagram illustrating a demultiplexer for a display device according to another embodiment, and Figure 9 It is shown Figure 8 An example of a waveform diagram of the input / output signals of a demultiplexer in a display device.

[0082] refer to Figure 8 and Figure 9 The demultiplexer DMX may include the first transistor to the fourth transistor T1, T2, T3 and T4.

[0083] A first transistor T1 and a second transistor T2 can be connected in parallel between the output terminal CH of the display driver 200 and the first data line DL1. The first transistor T1 and the second transistor T2 can be connected to the output terminal CH of the display driver 200 and can supply the data voltage Vdata received from the output terminal CH to the first data line DL1. A third transistor T3 and a fourth transistor T4 can be connected in parallel between the output terminal CH of the display driver 200 and the second data line DL2. The third transistor T3 and the fourth transistor T4 can be connected to the output terminal CH of the display driver 200 and can supply the data voltage Vdata received from the output terminal CH to the second data line DL2.

[0084] The first transistor T1 can be turned on based on the first control signal MUX1 to supply the output signal of the output terminal CH to the first data line DL1. The second transistor T2 can be turned on based on the touch control signal MUXT to supply the output signal of the first output terminal CH to the first data line DL1. The third transistor T3 can be turned on based on the second control signal MUX2 to supply the output signal of the output terminal CH to the second data line DL2. The fourth transistor T4 can be turned on based on the touch control signal MUXT to supply the output signal of the output terminal CH to the second data line DL2.

[0085] The first to fourth transistors T1, T2, T3, and T4 can be configured as n-channel oxide transistors. The first transistor T1 and the third transistor T3 can be turned on based on a first gate high voltage VGH1 and turned off based on a first gate low voltage VGL1 and a third gate low voltage VGL3. The second transistor T2 and the fourth transistor T4 can be turned on based on a second gate high voltage VGH2 and turned off based on a second gate low voltage VGL2 and a fourth gate low voltage VGL4. For example, the first gate high voltage VGH1 can be greater than the second gate high voltage VGH2 (VGH1>VGH2), the first gate low voltage VGL1 can be greater than the third gate low voltage VGL3 (VGL1>VGL3), and the second gate low voltage VGL2 can be greater than the fourth gate low voltage VGL4 (VGL2>VGL4). Here, the first gate low voltage VGL1 and the second gate low voltage VGL2 can be different, and the third gate low voltage VGL3 and the fourth gate low voltage VGL4 can be different.

[0086] As another example, the first gate high voltage VGH1 and the second gate high voltage VGH2 can be the same (VGH1=VGH2). As another example, the first gate low voltage VGL1 and the second gate low voltage VGL2 can be the same (VGL1=VGL2), and the third gate low voltage VGL3 and the fourth gate low voltage VGL4 can be the same (VGL3=VGL4).

[0087] When turned on by either the first gate high voltage VGH1 or the second gate high voltage VGH2, the n-channel oxide transistor can receive positive bias temperature stress (PBTS) through a positive drive voltage (Vgs) and high drain current stress (HDCS) through a high drain current. As the positive bias temperature stress (PBTS) and high drain current stress (HDCS) accumulate, the oxide transistor may degrade, and the threshold voltage (Vth) may thus shift.

[0088] When turned off by one of the first to fourth gate low voltages VGL1, VGL2, VGL3, and VGL4, the n-channel oxide transistor can receive negative bias temperature illumination stress (NBTiS) through a negative drive voltage (Vgs) and counteract positive bias temperature stress (PBTS) and high drain current stress (HDCS), thereby recovering the threshold voltage (Vth) shift caused by transistor degradation. Here, as the recovery time increases and the gate low voltage decreases, the degradation of the n-channel oxide transistor can be reduced.

[0089] The first frame (Frame1) may include an active time period (ACT) and a passive time period (BLK). The display driver 200 may supply the data voltage Vdata to the data line DL during the active time period (ACT). When the first to fourth transistors T1, T2, T3, and T4 are turned off during the active time period (ACT), they may perform recovery during the first recovery time period (Recovery1). Additional recovery may be performed during the second recovery time period (Recovery2) of the passive time period (BLK).

[0090] The effective time period ACT can include a display time period DP and a touch time period TP. First transistor T1 and third transistor T3 can alternately repeat the on-time period of the first gate high voltage VGH1 and the off-time period of the first gate low voltage VGL1 during the display time period DP. First transistor T1 and third transistor T3 can be turned on based on the first gate high voltage VGH1 to supply data voltage Vdata to the first data line DL1 and the second data line DL2, respectively, during the display time period DP. First transistor T1 and third transistor T3 can perform recovery during the first recovery time period Recovery1 of the display time period DP, wherein they are turned off by the first gate low voltage VGL1. Second transistor T2 and fourth transistor T4 can perform recovery during the first recovery time period Recovery1 of the display time period DP, wherein they are turned off by the second gate low voltage VGL2.

[0091] The first transistor T1 and the third transistor T3 can perform recovery during the first recovery period (Recovery1) of the touch time period (TP), wherein they are turned off by the first gate low voltage VGL1. The second transistor T2 and the fourth transistor T4 can be turned on based on the second gate high voltage VGH2 to supply the touch drive signal VCOM to the first data line DL1 and the second data line DL2, respectively, during the touch time period (TP).

[0092] The first transistor T1 and the third transistor T3 can perform recovery during the second recovery period (Recovery2) in the blank period BLK, wherein they are turned off by the third gate low voltage VGL3. The second transistor T2 and the fourth transistor T4 can perform recovery during the second recovery period (Recovery2) in the blank period BLK, wherein they are turned off by the fourth gate low voltage VGL4.

[0093] Therefore, the first transistor T1 and the third transistor T3 can offset the positive bias temperature stress (PBTS) and high drain current stress (HDCS) applied by the first gate low voltage VGH1 during the on-time of the display time period DP by the negative bias temperature illumination stress (NBTiS) applied by the first gate low voltage VGL1 during the first recovery time period Recovery1 of the display time period DP and the touch time period TP, and additionally offset the positive bias temperature stress (PBTS) and high drain current stress (HDCS) by the negative bias temperature illumination stress (NBTiS) applied by the third gate low voltage VGL3 during the second recovery time period Recovery2 of the blank time period BLK. The second transistor T2 and the fourth transistor T4 can offset the positive bias temperature stress (PBTS) and high drain current stress (HDCS) applied by the second gate low voltage VGL2 during the on-time of the touch time period TP by the negative bias temperature illumination stress (NBTiS) applied by the second gate low voltage VGL2 during the first recovery time period Recovery1 of the display time period DP, and additionally offset the positive bias temperature stress (PBTS) and high drain current stress (HDCS) by the negative bias temperature illumination stress (NBTiS) applied by the fourth gate low voltage VGL4 during the second recovery time period Recovery2 of the blank time period BLK. Therefore, the first to fourth transistors T1, T2, T3 and T4 can ensure sufficient recovery time, thereby reducing stress and degradation.

[0094] Figure 10 It is shown Figure 8 Another example of a waveform diagram of the input / output signals of a demultiplexer in a display device. Figure 10 The display device has the same Figure 9 The different touch control signals MUXT configurations for the display devices will be briefly described or omitted.

[0095] refer to Figure 10The effective time period ACT can include a display time period DP and a touch time period TP. The first transistor T1 and the third transistor T3 can alternately repeat the on-time period of the first gate high voltage VGH1 and the off-time period of the first gate low voltage VGL1 during the display time period DP. The first transistor T1 and the third transistor T3 can be turned on based on the first gate high voltage VGH1 during the display time period DP to supply data voltage Vdata to the first data line DL1 and the second data line DL2, respectively. The first transistor T1 and the third transistor T3 can perform recovery during the first recovery time period Recovery1 of the display time period DP, wherein they are turned off by the first gate low voltage VGL1. The second transistor T2 and the fourth transistor T4 can perform recovery during the first recovery time period Recovery1 of the display time period DP, wherein they are turned off by the second gate low voltage VGL2.

[0096] The first transistor T1 and the third transistor T3 can perform recovery during the first recovery period (Recovery1) of the touch time period TP, wherein they are turned off by the first gate low voltage VGL1. The second transistor T2 and the fourth transistor T4 can alternately repeat the on-time period of the second gate high voltage VGH2 and the off-time period of the second gate low voltage VGL2 during the touch time period TP. Here, the high pulse width and low pulse width of the touch control signal MUXT can be the same during the touch time period TP. The second transistor T2 and the fourth transistor T4 can be turned on based on the second gate high voltage VGH2 to supply the touch drive signal VCOM to the first data line DL1 and the second data line DL2, respectively, during the touch time period TP.

[0097] The first transistor T1 and the third transistor T3 can perform recovery during the second recovery period (Recovery2) in the blank time period BLK, where they are turned off by the third gate low voltage VGL3. The second transistor T2 and the fourth transistor T4 can also perform recovery during the second recovery period (Recovery2) in the blank time period BLK, where they are turned off by the fourth gate low voltage VGL4. Therefore, the first to fourth transistors T1, T2, T3, and T4 can ensure sufficient recovery time, thereby reducing stress and degradation.

[0098] Figure 11 It is shown Figure 8 Another example of the waveform diagram of the input / output signals of the demultiplexer in the display device. Figure 11 The display device has the same Figure 9 The different touch control signals MUXT configurations for the display devices will be briefly described or omitted.

[0099] refer to Figure 11 The effective time period ACT can include a display time period DP and a touch time period TP. The first transistor T1 and the third transistor T3 can alternately repeat the on-time period of the first gate high voltage VGH1 and the off-time period of the first gate low voltage VGL1 during the display time period DP. The first transistor T1 and the third transistor T3 can be turned on based on the first gate high voltage VGH1 to supply data voltage Vdata to the first data line DL1 and the second data line DL2, respectively, during the display time period DP. The first transistor T1 and the third transistor T3 can perform recovery during the first recovery time period Recovery1 of the display time period DP, wherein they are turned off by the first gate low voltage VGL1. The second transistor T2 and the fourth transistor T4 can perform recovery during the first recovery time period Recovery1 of the display time period DP, wherein they are turned off by the second gate low voltage VGL2.

[0100] The first transistor T1 and the third transistor T3 can perform recovery during the first recovery period (Recovery1) of the touch time period TP, wherein they are turned off by the first gate low voltage VGL1. The second transistor T2 and the fourth transistor T4 can alternately repeat the on-time period of the second gate high voltage VGH2 and the off-time period of the second gate low voltage VGL2 during the touch time period TP. Here, the high pulse width of the touch control signal MUXT during the touch time period TP can be two or more times the low pulse width. The second transistor T2 and the fourth transistor T4 can be turned on based on the second gate high voltage VGH2 to supply the touch drive signal VCOM to the first data line DL1 and the second data line DL2, respectively, during the touch time period TP.

[0101] The first transistor T1 and the third transistor T3 can perform recovery during the second recovery period (Recovery2) in the blank time period BLK, where they are turned off by the third gate low voltage VGL3. The second transistor T2 and the fourth transistor T4 can also perform recovery during the second recovery period (Recovery2) in the blank time period BLK, where they are turned off by the fourth gate low voltage VGL4. Therefore, the first to fourth transistors T1, T2, T3, and T4 can ensure sufficient recovery time, thereby reducing stress and degradation.

[0102] Figure 12 It is shown Figure 8 A block diagram illustrating the output process of the first control signal, the second control signal, and the touch control signal in the display device.

[0103] refer to Figure 12The power supply unit 600 can generate a power supply voltage and supply the generated power supply voltage to the display panel 100. The power supply unit 600 can supply power supply voltage to the first control signal output unit MO1 and the second control signal output unit MO2. The first control signal output unit MO1 can output a first control signal MUX1 and a second control signal MUX2, and the second control signal output unit MO2 can output a touch control signal MUXT.

[0104] The power supply unit 600 can supply first and second gate high voltages VGH1 and VGH2 to the first switching unit SW1, and supply first to fourth gate low voltages VGL1, VGL2, VGL3 and VGL4 to the second switching unit SW2.

[0105] For example, the first gate high voltage VGH1 can be greater than the second gate high voltage VGH2 (VGH1>VGH2), the first gate low voltage VGL1 can be greater than the third gate low voltage VGL3 (VGL1>VGL3), and the second gate low voltage VGL2 can be greater than the fourth gate low voltage VGL4 (VGL2>VGL4). Here, the first gate low voltage VGL1 and the second gate low voltage VGL2 can be different, and the third gate low voltage VGL3 and the fourth gate low voltage VGL4 can be different.

[0106] As another example, the first gate high voltage VGH1 and the second gate high voltage VGH2 can be the same (VGH1=VGH2). As another example, the first gate low voltage VGL1 and the second gate low voltage VGL2 can be the same (VGL1=VGL2), and the third gate low voltage VGL3 and the fourth gate low voltage VGL4 can be the same (VGL3=VGL4).

[0107] The first switching unit SW1 can supply a first gate high voltage VGH1 to the first control signal output unit MO1 and a second gate high voltage VGH2 to the second control signal output unit MO2. The second switching unit SW2 can supply a first gate low voltage VGL1 and a third gate low voltage VGL3 to the first control signal output unit MO1. The second switching unit SW2 can supply a second gate low voltage VGL2 and a fourth gate low voltage VGL4 to the second control signal output unit MO2.

[0108] refer to Figures 9 to 11The first control signal output unit MO1 can output a first control signal MUX1 and a second control signal MUX2 during the display time period DP of the effective time period ACT, wherein the first gate high voltage VGH1 and the first gate low voltage VGL1 alternate. The first control signal output unit MO1 can also output a first control signal MUX1 and a second control signal MUX2 with a first gate low voltage VGL1 during the touch time period TP of the effective time period ACT. Finally, the first control signal output unit MO1 can output a first control signal MUX1 and a second control signal MUX2 with a third gate low voltage VGL3 during the blank time period BLK.

[0109] refer to Figure 9 The second control signal output unit MO2 can output a touch control signal MUXT with a second gate low voltage VGL2 during the display time period DP of the effective time period ACT. The second control signal output unit MO2 can also output a touch control signal MUXT with a second gate high voltage VGH2 during the touch time period TP of the effective time period ACT. Finally, the second control signal output unit MO2 can output a touch control signal MUXT with a fourth gate low voltage VGL4 during the blank time period BLK.

[0110] refer to Figure 10 and Figure 11 The second control signal output unit MO2 can output a touch control signal MUXT during the touch time period TP of the effective time period ACT, wherein the second gate high voltage VGH2 and the second gate low voltage VGL2 alternate.

[0111] Figure 13 This is a circuit diagram showing a demultiplexer for a display device according to yet another embodiment, and Figure 14 It is shown Figure 13 The waveform diagram of the input / output signals of the demultiplexer in the display device.

[0112] refer to Figure 13 and Figure 14 The demultiplexer DMX may include the first transistor to the fourth transistor T1, T2, T3 and T4.

[0113] A first transistor T1 and a second transistor T2 can be connected in parallel between the output terminal CH of the display driver 200 and the first data line DL1. The first transistor T1 and the second transistor T2 can be connected to the output terminal CH of the display driver 200 and can supply the data voltage Vdata received from the output terminal CH to the first data line DL1. A third transistor T3 and a fourth transistor T4 can be connected in parallel between the output terminal CH of the display driver 200 and the second data line DL2. The third transistor T3 and the fourth transistor T4 can be connected to the output terminal CH of the display driver 200 and can supply the data voltage Vdata received from the output terminal CH to the second data line DL2.

[0114] The first transistor T1 can be turned on based on the odd-number control signal OMUX to supply the output signal of the output terminal CH to the first data line DL1. The second transistor T2 can be turned on based on the even-number control signal EMUX to supply the output signal of the output terminal CH to the first data line DL1. The third transistor T3 can be turned on based on the odd-number control signal OMUX to supply the output signal of the output terminal CH to the second data line DL2. The fourth transistor T4 can be turned on based on the even-number control signal EMUX to supply the output signal of the output terminal CH to the second data line DL2.

[0115] The first to fourth transistors T1, T2, T3, and T4 can be configured as n-channel oxide transistors. The first to fourth transistors T1, T2, T3, and T4 can be turned on based on a first gate high voltage VGH1 and a second gate high voltage VGH2, and turned off based on first to third gate low voltages VGL1, VGL2, and VGL3. For example, the first gate high voltage VGH1 can be greater than the second gate high voltage VGH2 (VGH1>VGH2), and the first gate low voltage VGL1 can be greater than either the second gate low voltage VGL2 or the third gate low voltage VGL3 (VGL1>VGL2 or VGL1>VGL3). The second gate low voltage VGL2 and the third gate low voltage VGL3 can be different.

[0116] As another example, the first gate high voltage VGH1 and the second gate high voltage VGH2 can be the same (VGH1=VGH2). As yet another example, the second gate low voltage VGL2 and the third gate low voltage VGL3 can be the same (VGL2=VGL3).

[0117] When turned on by a first gate high voltage VGH1 or a second gate high voltage VGH2, the n-channel oxide transistor can receive positive bias temperature stress (PBTS) through a positive drive voltage (Vgs) and high drain current stress (HDCS) through a high drain current. As the positive bias temperature stress (PBTS) and high drain current stress (HDCS) accumulate, the oxide transistor may degrade, and the threshold voltage (Vth) may thus shift.

[0118] When turned off by one of the first to third gate low voltages VGL1, VGL2, and VGL3, the n-channel oxide transistor can receive negative bias temperature radiation stress (NBTiS) through a negative drive voltage (Vgs) and counteract positive bias temperature stress (PBTS) and high drain current stress (HDCS), thereby recovering the threshold voltage (Vth) shift caused by transistor degradation. Here, as the recovery time increases and the gate low voltage decreases, the degradation of the n-channel oxide transistor can be reduced.

[0119] An odd-numbered ODD frame can include an active time period (ACT) and a passive time period (BLK). An odd-numbered ODD frame can be an odd-numbered frame among multiple frames. When the first transistor T1 and the third transistor T3 are turned off during the active time period (ACT) of the odd-numbered ODD frame, the first transistor T1 and the third transistor T3 can perform recovery during the first recovery time period (Recovery1). The first transistor T1 and the third transistor T3 can perform additional recovery during the second recovery time period (Recovery2) of the passive time period (BLK) of the odd-numbered ODD frame. The first transistor T1 and the third transistor T3 can perform additional recovery during the second recovery time period (Recovery2) of the even-numbered EVEN frame during both the active time period (ACT) and the passive time period (BLK).

[0120] An even-numbered EVEN Frame can include an active time period (ACT) and a passive time period (BLK). An even-numbered EVEN Frame can be one of multiple even-numbered frames. When the second transistor T2 and the fourth transistor T4 are turned off during the active time period (ACT) of the even-numbered EVEN Frame, the second transistor T2 and the fourth transistor T4 can perform recovery during the first recovery time period (Recovery1). The second transistor T2 and the fourth transistor T4 can perform additional recovery during the second recovery time period (Recovery2) of the passive time period (BLK) of the odd-numbered ODD Frame.

[0121] The effective time period ACT in the odd-numbered ODD Frame can include a display time period DP and a touch time period TP. The first transistor T1 and the third transistor T3 can alternately repeat the on-time period of the first gate high voltage VGH1 and the off-time period of the first gate low voltage VGL1 during the display time period DP of the odd-numbered ODD Frame. During the display time period DP of the odd-numbered ODD Frame, the first transistor T1 and the third transistor T3 can be turned on based on the first gate high voltage VGH1 to supply the data voltage Vdata to the first data line DL1 and the second data line DL2, respectively. The first transistor T1 and the third transistor T3 can perform recovery during the first recovery time period Recovery1 in the display time period DP of the odd-numbered ODD Frame, where they are turned off by the first gate low voltage VGL1.

[0122] During the touch time period TP of an odd-numbered ODD Frame, the first transistor T1 and the third transistor T3 can be turned on based on the second gate high voltage VGH2 to supply the touch drive signal VCOM to the first data line DL1 and the second data line DL2, respectively.

[0123] The first transistor T1 and the third transistor T3 can perform recovery during the second recovery period (Recovery2) in the blank time period (BLK) of the odd-numbered ODD frames, where they are turned off by the second gate low voltage (VGL2). The first transistor T1 and the third transistor T3 can also perform recovery during the second recovery period (Recovery2) in the display time period (ACT) and the blank time period (BLK) of the even-numbered EVEN frames, where they are turned off by the third gate low voltage (VGL3).

[0124] The effective time period ACT in the even-numbered EVEN Frame can include a display time period DP and a touch time period TP. The second transistor T2 and the fourth transistor T4 can alternately repeat the on-time period of the first gate high voltage VGH1 and the off-time period of the first gate low voltage VGL1 during the display time period DP of the even-numbered EVEN Frame. The second transistor T2 and the fourth transistor T4 can be turned on based on the first gate high voltage VGH1 to supply the data voltage Vdata to the first data line DL1 and the second data line DL2, respectively, during the display time period DP of the even-numbered EVEN Frame. The second transistor T2 and the fourth transistor T4 can perform recovery during the first recovery time period Recovery1 in the display time period DP of the even-numbered EVEN Frame, where they are turned off by the first gate low voltage VGL1.

[0125] The second transistor T2 and the fourth transistor T4 can be turned on based on the second gate high voltage VGH2 to supply the touch drive signal VCOM to the first data line DL1 and the second data line DL2 respectively during the touch time period TP of the even-numbered frame EVEN.

[0126] The second transistor T2 and the fourth transistor T4 can perform recovery during the second recovery period (Recovery2) in the blank time period (BLK) of the even-numbered EVEN Frame, where they are turned off by the second gate low voltage (VGL2). The second transistor T2 and the fourth transistor T4 can also perform recovery during the second recovery period (Recovery2) in the display time period (ACT) and the blank time period (BLK) of the odd-numbered ODD Frame, where they are turned off by the third gate low voltage (VGL3).

[0127] Therefore, the first transistor T1 and the third transistor T3 can offset the positive bias temperature stress (PBTS) and high drain current stress (HDCS) applied by the first gate high voltage VGH1 and the second gate high voltage VGH2 during the on-time of the display time period DP and the touch time period TP in the odd-numbered ODD Frame by the negative bias temperature illumination stress (NBTiS) applied by the first gate low voltage VGL1 during the first recovery time period Recovery1 of the display time period DP. The first transistor T1 and the third transistor T3 can also offset the positive bias temperature stress (PBTS) and high drain current stress (HDCS) by the negative bias temperature illumination stress (NBTiS) applied by the second gate low voltage VGL2 during the second recovery time period Recovery2 of the blank time period BLK in the odd-numbered ODD Frame. The first transistor T1 and the third transistor T3 can further offset the positive bias temperature stress (PBTS) and high drain current stress (HDCS) by the negative bias temperature illumination stress (NBTiS) applied by the third gate low voltage VGL3 during the second recovery period of the even-numbered frame EVEN Frame active time period ACT and blank time period BLK Recovery 2.

[0128] The second transistor T2 and the fourth transistor T4 can offset the positive bias temperature stress (PBTS) and high drain current stress (HDCS) applied by the first gate high voltage VGH1 and the second gate high voltage VGH2 during the on-time of the display time period DP and the touch time period TP in the even-numbered frame by the negative bias temperature illumination stress (NBTiS) applied by the first gate low voltage VGL1 during the first recovery time period Recovery1 of the display time period DP. The second transistor T2 and the fourth transistor T4 can also offset the positive bias temperature stress (PBTS) and high drain current stress (HDCS) by the negative bias temperature illumination stress (NBTiS) applied by the second gate low voltage VGL2 during the second recovery time period Recovery2 of the blank time period BLK in the even-numbered frame EVEN Frame. The second transistor T2 and the fourth transistor T4 can further offset the positive bias temperature stress (PBTS) and high drain current stress (HDCS) by the negative bias temperature illumination stress (NBTiS) applied by the third gate low voltage VGL3 during the second recovery period of Recovery2 in the effective time period ACT of the odd frame ODD Frame and the blank time period BLK.

[0129] Therefore, the first to fourth transistors T1, T2, T3 and T4 can ensure sufficient recovery time, thereby reducing stress and degradation.

[0130] Figure 15 It is shown Figure 13 A block diagram illustrating the output process of odd and even control signals in a display device.

[0131] refer to Figure 15 The power supply unit 600 can generate a power supply voltage and supply the generated power supply voltage to the display panel 100. The power supply unit 600 can supply power supply voltage to the first control signal output unit MO1 and the second control signal output unit MO2, and the first control signal output unit MO1 and the second control signal output unit MO2 can output an odd control signal OMUX and an even control signal EMUX.

[0132] The power supply unit 600 can supply a first gate high voltage VGH1 and a second gate high voltage VGH2 to the first switching unit SW1, and supply first to third gate low voltages VGL1, VGL2, and VGL3 to the second switching unit SW2. For example, the first gate high voltage VGH1 can be greater than the second gate high voltage VGH2 (VGH1>VGH2), and the first gate low voltage VGL1 can be greater than the second gate low voltage VGL2 or the third gate low voltage VGL3 (VGL1>VGL2 or VGL1>VGL3). The second gate low voltage VGL2 and the third gate low voltage VGL3 can be different.

[0133] As another example, the first gate high voltage VGH1 and the second gate high voltage VGH2 can be the same (VGH1=VGH2). As yet another example, the second gate low voltage VGL2 and the third gate low voltage VGL3 can be the same (VGL2=VGL3).

[0134] The first switching unit SW1 can supply a first gate high voltage VGH1 and a second gate high voltage VGH2 to the first control signal output unit MO1 and the second control signal output unit MO2. The second switching unit SW2 can supply first to third gate low voltages VGL1, VGL2 and VGL3 to the first control signal output unit MO1 and the second control signal output unit MO2.

[0135] Therefore, the first control signal output unit MO1 can output an odd control signal OMUX during the display time period DP of the odd-numbered ODD Frame, wherein the first gate high voltage VGH1 and the first gate low voltage VGL1 alternate. The first control signal output unit MO1 can also output an odd control signal OMUX with a second gate high voltage VGH2 during the touch time period TP of the odd-numbered ODD Frame. The first control signal output unit MO1 can also output an odd control signal OMUX with a second gate low voltage VGL2 during the blank time period BLK of the odd-numbered ODD Frame. Finally, the first control signal output unit MO1 can output an odd control signal OMUX with a third gate low voltage VGL3 during the active time period ACT and the blank time period BLK of the even-numbered EVEN Frame.

[0136] The second control signal output unit MO2 can output an even-numbered control signal EMUX during the display time period DP of an even-numbered EVEN Frame, wherein the first gate high voltage VGH1 and the first gate low voltage VGL1 alternate. The second control signal output unit MO2 can also output an even-numbered control signal EMUX with a second gate high voltage VGH2 during the touch time period TP of an even-numbered EVEN Frame. The second control signal output unit MO2 can also output an even-numbered control signal EMUX with a second gate low voltage VGL2 during the blank time period BLK of an even-numbered EVEN Frame. Finally, the second control signal output unit MO2 can output an even-numbered control signal EMUX with a third gate low voltage VGL3 during the active time period ACT and the blank time period BLK of an odd-numbered ODD Frame.

[0137] The display device 10 according to various embodiments of the present disclosure can be described as follows.

[0138] According to various embodiments of the present disclosure, a display device is provided, the display device comprising: a display panel including a plurality of pixels and a plurality of touch electrodes disposed in a display area; a display driver that outputs a data voltage during a display period of an effective time period and outputs a touch driving signal during a touch period of the effective time period; and a demultiplexer disposed between the display area and the display driver and connected between a first output terminal of the display driver and a data line of the display panel, wherein the demultiplexer comprises: a first transistor that electrically connects the first output terminal to a first data line in the data line based on a first control signal; and a second transistor that electrically connects the first output terminal to a second data line in the data line based on a second control signal, wherein each of the first control signal and the second control signal alternately has a first gate high voltage and a first gate low voltage during the display period, and has a second gate low voltage lower than the first gate low voltage during a blank period after the effective time period.

[0139] In the display device according to various embodiments of the present disclosure, each of the first control signal and the second control signal may have a second gate high voltage that is less than the first gate high voltage during the touch time period.

[0140] The display device according to various embodiments of the present disclosure may further include: a first control signal output unit, which outputs a first control signal; a second control signal output unit, which outputs a second control signal; a first switching unit, which supplies a first gate high voltage and a second gate high voltage to each of the first control signal output unit and the second control signal output unit; a second switching unit, which supplies a first gate low voltage and a second gate low voltage to each of the first control signal output unit and the second control signal output unit; and a power supply unit, which supplies the first gate high voltage and the second gate high voltage to the first switching unit and supplies the first gate low voltage and the second gate low voltage to the second switching unit.

[0141] In the display device according to various embodiments of the present disclosure, each of the first control signal and the second control signal may have a second gate high voltage equal to the first gate high voltage during the touch time period.

[0142] In the display device according to various embodiments of the present disclosure, the first transistor and the second transistor can respectively supply data voltage to the first data line and the second data line during the display time period, and respectively supply touch drive signals to the first data line and the second data line during the touch time period.

[0143] In the display device according to various embodiments of the present disclosure, the demultiplexer may further include: a third transistor, which electrically connects a second output terminal of the display driver to a third data line in the data lines based on a first control signal; and a fourth transistor, which electrically connects a second output terminal to a fourth data line in the data lines based on a second control signal.

[0144] According to various embodiments of this disclosure, a display device is provided, comprising: a display panel including a plurality of pixels and a plurality of touch electrodes disposed in a display area; a display driver that outputs a data voltage during a display period of an effective time period and outputs a touch driving signal during a touch period of the effective time period; and a demultiplexer disposed between the display area and the display driver, and connected between an output terminal of the display driver and a data line of the display panel, wherein the demultiplexer comprises: a first transistor that electrically connects the output terminal to a first data line among the data lines based on a first control signal; and a second transistor that electrically connects the output terminal to the first data line among the data lines based on a touch control signal, wherein the first control signal alternately has a first gate high voltage and a first gate low voltage during the display period, has a first gate low voltage during the touch period, and has a second gate low voltage lower than the first gate low voltage during a blank period after the effective time period.

[0145] In the display device according to various embodiments of the present disclosure, the touch control signal may have a third gate low voltage during the display period, a second gate high voltage during the touch period, and a fourth gate low voltage less than the third gate low voltage during the blank period.

[0146] The display device according to various embodiments of the present disclosure may further include: a first control signal output unit, which outputs a first control signal; a second control signal output unit, which outputs a touch control signal; a first switching unit, which supplies a first gate high voltage to the first control signal output unit and a second gate high voltage to the second control signal output unit; a second switching unit, which supplies a first gate low voltage and a third gate low voltage to the first control signal output unit and a second gate low voltage and a fourth gate low voltage to the second control signal output unit; and a power supply unit, which supplies the first gate high voltage and the second gate high voltage to the first switching unit and the first to fourth gate low voltages to the second switching unit.

[0147] In the display device according to various embodiments of the present disclosure, the second gate high voltage may be lower than the first gate high voltage, the first gate low voltage and the third gate low voltage may be different, and the second gate low voltage and the fourth gate low voltage may be different.

[0148] In the display device according to various embodiments of the present disclosure, the first gate high voltage and the second gate high voltage may be the same, the first gate low voltage and the third gate low voltage may be the same, and the second gate low voltage and the fourth gate low voltage may be the same.

[0149] In the display device according to various embodiments of the present disclosure, the touch control signal may have a third gate low voltage during the display period, alternately have a second gate high voltage and a third gate low voltage during the touch period, and have a fourth gate low voltage that is lower than the third gate low voltage during the blank period.

[0150] In the display device according to various embodiments of the present disclosure, the high pulse width of the touch control signal during the touch time period may be two or more times the low pulse width of the touch control signal.

[0151] In the display device according to various embodiments of the present disclosure, the demultiplexer may further include: a third transistor that electrically connects the output terminal to a second data line among the data lines based on a second control signal; and a fourth transistor that electrically connects the output terminal to the second data line based on a touch control signal.

[0152] In the display device according to various embodiments of the present disclosure, the second control signal may alternately have a first gate high voltage and a first gate low voltage during the display time period, a first gate low voltage during the touch time period, and a second gate low voltage during the blank time period.

[0153] According to various embodiments of the present disclosure, a display device is provided, the display device comprising: a display panel including a plurality of pixels and a plurality of touch electrodes disposed in a display area; a display driver that outputs a data voltage during a display period of an effective time period and outputs a touch drive signal during a touch period of the effective time period; and a demultiplexer disposed between the display area and the display driver and connected between an output terminal of the display driver and a data line of the display panel, wherein the demultiplexer comprises: a first transistor that electrically connects the output terminal to a first data line among the data lines based on an odd-number control signal; and a second transistor that electrically connects the output terminal to the first data line based on an even-number control signal, wherein the odd-number control signal alternately has a first gate high voltage and a first gate low voltage during the display period of an odd-number frame, a second gate high voltage during the touch period of the odd-number frame, and a second gate low voltage lower than the first gate low voltage during a blank period of the odd-number frame.

[0154] In the display device according to various embodiments of the present disclosure, the odd control signal may have a third gate low voltage less than the first gate low voltage during the display time period, touch time period, and blank time period of the even frame following the odd frame.

[0155] In the display device according to various embodiments of the present disclosure, the even-number control signal may alternately have a first gate high voltage and a first gate low voltage during the display time period of the even-number frames, a second gate high voltage during the touch time period of the even-number frames, and a second gate low voltage during the blank time period of the even-number frames.

[0156] In the display device according to various embodiments of the present disclosure, the even-numbered control signal may have a third gate low voltage during the display time period, touch time period, and blank time period of the odd-numbered frames.

[0157] The display device according to various embodiments of the present disclosure may further include: a first control signal output unit, which outputs an odd-numbered control signal; a second control signal output unit, which outputs an even-numbered control signal; a first switching unit, which supplies a first gate high voltage and a second gate high voltage to each of the first and second control signal output units; a second switching unit, which supplies a first gate low voltage to a third gate low voltage to each of the first and second control signal output units; and a power supply unit, which supplies the first gate high voltage and the second gate high voltage to the first switching unit and supplies the first gate low voltage to the third gate low voltage to the second switching unit.

[0158] The display device according to embodiments of the present disclosure can perform recovery by applying a first gate low voltage to the transistor of the demultiplexer during an effective time period, and can perform additional recovery by applying a second gate low voltage, which is less than the first gate low voltage, to the transistor of the demultiplexer during a blank time period, thereby reducing stress and degradation.

[0159] The display device according to embodiments of the present disclosure can reduce the size and power consumption of the transistors in the demultiplexer.

[0160] However, the effects that can be obtained from this disclosure are not limited to those described above, and based on the following description, those skilled in the art to which this disclosure pertains will be able to clearly understand other effects not mentioned.

[0161] Although embodiments have been described above with reference to the accompanying drawings, those skilled in the art to which this disclosure pertains will understand that the above-described technical configurations of the invention can be implemented in other specific forms without altering its technical spirit or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. Furthermore, the scope of this disclosure is defined by the appended claims rather than the detailed descriptions. Moreover, the meaning and scope of the claims, as well as all changes or modifications derived from equivalent concepts, should be interpreted as being included within the scope of this disclosure.

Claims

1. A display device, comprising: The display panel includes a plurality of pixels and a plurality of touch electrodes disposed in the display area; The display driver outputs a data voltage during the display time period of the effective time period and outputs a touch drive signal during the touch time period of the effective time period; as well as A demultiplexer is disposed between the display area and the display driver, and connected between the first output terminal of the display driver and the data line of the display panel. The demultiplexer includes: A first transistor, the first transistor electrically connecting the first output terminal to a first data line in the data line based on a first control signal; and The second transistor electrically connects the first output terminal to the second data line in the data line based on the second control signal, and Each of the first control signal and the second control signal alternately has a first gate high voltage and a first gate low voltage during the display time period, and has a second gate low voltage lower than the first gate low voltage during a blank time period after the effective time period.

2. The display device according to claim 1, wherein, Each of the first control signal and the second control signal has a second gate high voltage that is lower than the first gate high voltage during the touch time period.

3. The display device according to claim 2, further comprising: A first control signal output unit outputs the first control signal; The second control signal output unit outputs the second control signal. A first switching unit supplies the first gate high voltage and the second gate high voltage to each of the first control signal output unit and the second control signal output unit; The second switching unit supplies the first gate low voltage and the second gate low voltage to each of the first control signal output unit and the second control signal output unit. as well as A power supply unit supplies the first gate high voltage and the second gate high voltage to the first switching unit, and supplies the first gate low voltage and the second gate low voltage to the second switching unit.

4. The display device according to claim 1, wherein, Each of the first control signal and the second control signal has a second gate high voltage equal to the first gate high voltage during the touch time period.

5. The display device according to claim 1, wherein, The first transistor and the second transistor supply data voltage to the first data line and the second data line respectively during the display period, and supply touch drive signals to the first data line and the second data line respectively during the touch period.

6. The display device according to claim 1, wherein, The demultiplexer further includes: A third transistor, which electrically connects the second output terminal of the display driver to a third data line in the data lines based on the first control signal; and A fourth transistor, which electrically connects the second output terminal to the fourth data line among the data lines based on the second control signal.

7. The display device according to claim 6, wherein, The first to the fourth transistors are configured as n-channel oxide transistors.

8. A display device, comprising: The display panel includes a plurality of pixels and a plurality of touch electrodes disposed in the display area; The display driver outputs a data voltage during the display time period of the effective time period and outputs a touch drive signal during the touch time period of the effective time period; as well as A demultiplexer is disposed between the display area and the display driver, and connected between the output terminal of the display driver and the data line of the display panel. The demultiplexer includes: A first transistor, wherein the output terminal is electrically connected to a first data line in the data line based on a first control signal; and The second transistor electrically connects the output terminal to the first data line in the data line based on the touch control signal, and The first control signal alternately has a first gate high voltage and a first gate low voltage during the display time period, has the first gate low voltage during the touch time period, and has a second gate low voltage lower than the first gate low voltage during the blank time period after the effective time period.

9. The display device according to claim 8, wherein, The touch control signal has a third gate low voltage during the display period, a second gate high voltage during the touch period, and a fourth gate low voltage that is lower than the third gate low voltage during the blank period.

10. The display device according to claim 9, further comprising: A first control signal output unit outputs the first control signal; The second control signal output unit outputs the touch control signal. The first switching unit supplies the first gate high voltage to the first control signal output unit and the second gate high voltage to the second control signal output unit; The second switching unit supplies the first gate low voltage and the second gate low voltage to the first control signal output unit, and supplies the third gate low voltage and the fourth gate low voltage to the second control signal output unit. as well as A power supply unit supplies the first gate high voltage and the second gate high voltage to the first switching unit, and supplies the first gate low voltage to the fourth gate low voltage to the second switching unit.

11. The display device according to claim 9, wherein, The second gate high voltage is lower than the first gate high voltage, the first gate low voltage is different from the third gate low voltage, and the second gate low voltage is different from the fourth gate low voltage.

12. The display device according to claim 9, wherein, The first gate high voltage is the same as the second gate high voltage, the first gate low voltage is the same as the third gate low voltage, and the second gate low voltage is the same as the fourth gate low voltage.

13. The display device according to claim 8, wherein, The touch control signal has a third gate low voltage during the display period, alternates between a second gate high voltage and the third gate low voltage during the touch period, and has a fourth gate low voltage that is lower than the third gate low voltage during the blank period.

14. The display device according to claim 13, wherein, The high pulse width of the touch control signal during the touch time period is two or more times the low pulse width of the touch control signal.

15. The display device according to claim 8, wherein, The demultiplexer further includes: A third transistor, which electrically connects the output terminal to a second data line in the data line based on the second control signal; and A fourth transistor electrically connects the output terminal to the second data line based on the touch control signal.

16. The display device according to claim 15, wherein, The second control signal alternately has the first gate high voltage and the first gate low voltage during the display time period, the first gate low voltage during the touch time period, and the second gate low voltage during the blank time period.

17. The display device according to claim 15, wherein, The first to the fourth transistors are configured as n-channel oxide transistors.

18. A display device, comprising: The display panel includes a plurality of pixels and a plurality of touch electrodes disposed in the display area; The display driver outputs a data voltage during the display time period of the effective time period and outputs a touch drive signal during the touch time period of the effective time period; as well as A demultiplexer is disposed between the display area and the display driver, and connected between the output terminal of the display driver and the data line of the display panel. The demultiplexer includes: A first transistor, the first transistor electrically connecting the output terminal to a first data line in the data line based on an odd-number control signal; and The second transistor electrically connects the output terminal to the first data line based on an even-numbered control signal, and The odd control signal alternately has a first gate high voltage and a first gate low voltage during the display time period of the odd frame, a second gate high voltage during the touch time period of the odd frame, and a second gate low voltage lower than the first gate low voltage during the blank time period of the odd frame.

19. The display device according to claim 18, wherein, The odd control signal has a third gate low voltage that is less than the first gate low voltage during the display time period, the touch time period, and the blank time period of the even frames following the odd frame.

20. The display device according to claim 19, wherein, The even-number control signal alternately has the first gate high voltage and the first gate low voltage during the display time period of the even-number frame, the second gate high voltage during the touch time period of the even-number frame, and the second gate low voltage during the blank time period of the even-number frame.

21. The display device according to claim 19, wherein, The even-numbered control signal has the third gate low voltage during the display time period, the touch time period, and the blank time period of the odd-numbered frame.

22. The display device according to claim 19, further comprising: A first control signal output unit outputs the odd-numbered control signals. The second control signal output unit outputs the even-numbered control signal. A first switching unit supplies the first gate high voltage and the second gate high voltage to each of the first control signal output unit and the second control signal output unit; A second switching unit supplies the first gate low voltage to the third gate low voltage to each of the first control signal output unit and the second control signal output unit. as well as A power supply unit supplies the first gate high voltage and the second gate high voltage to the first switching unit, and supplies the first gate low voltage to the third gate low voltage to the second switching unit.

23. The display device according to claim 18, wherein, The demultiplexer further includes: A third transistor, which electrically connects the output terminal to a second data line in the data lines based on the odd-number control signal; and A fourth transistor electrically connects the output terminal to the second data line based on the even-numbered control signal.

24. The display device according to claim 23, wherein, The first to the fourth transistors are configured as n-channel oxide transistors.

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