Array substrate, display panel and display device

Abstract

The present disclosure relates to the field of display technologies, and discloses an array substrate, a display panel, and a display device. The array substrate includes a substrate, a first wire, an insulating layer, and a second wire. The first wire is disposed on one side of the substrate. The insulating layer is disposed on a side of the first wire away from the substrate, and a first via hole is provided in the insulating layer and communicates with the first wire. The second wire is disposed on a side of the insulating layer away from the substrate, and the second wire is connected to the first wire through the first via hole. The second wire includes a first portion and a second portion, the first portion and the second portion are connected to each other in a first direction, and the width of the second portion is greater than the width of the first portion in a second direction intersecting with the first direction. A positive projection of the first via hole on the substrate is located within a positive projection of the second portion on the substrate. The array substrate avoids etching the metal material in the first via hole, avoids affecting the conductive effect, and does not affect the aperture ratio.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel including the array substrate, and a display device including the display panel. Background Art

[0002] AMOLED (Active-matrix organic light-emitting diode) display devices have a wider viewing angle, a higher refresh rate, and a thinner size, and thus are widely used in various fields.

[0003] With the improvement of resolution, the distribution of various signal lines becomes denser, and the width of the signal lines becomes thinner; it is easy to have poor connection of the signal lines, thus affecting the display effect.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of poor connection of signal lines in the prior art, and to provide an array substrate with better connection of signal lines, a display panel including the array substrate, and a display device including the display panel.

[0006] According to one aspect of the present disclosure, there is provided an array substrate, including:

[0007] A substrate substrate;

[0008] A first wire, disposed on one side of the substrate substrate;

[0009] An insulating layer, disposed on the side of the first wire away from the substrate substrate, and a first via is provided on the insulating layer, and the first via communicates with the first wire;

[0010] A second wire, disposed on the side of the insulating layer away from the substrate substrate, the second wire is connected to the first wire through the first via, the second wire includes a first part and a second part, the first part and the second part are connected to each other in a first direction, the width of the second part in a second direction is greater than the width of the first part in the second direction, the second direction intersects with the first direction, and the orthographic projection of the first via on the substrate substrate is located within the orthographic projection of the second part on the substrate substrate.

[0011] In an exemplary embodiment of the present disclosure, the first wire and the second wire extend along the first direction, and a plurality of the first vias are arranged along the first direction to form at least two columns of via groups. At least two columns of the via groups are arranged adjacent to each other in the second direction, and at least some of the first vias in adjacent two columns of the via groups are arranged in a staggered manner.

[0012] In an exemplary embodiment of the present disclosure, one column of the via group corresponds to one first wire and one second wire, and at least some of the second parts of adjacent two second wires are arranged in a staggered manner.

[0013] In an exemplary embodiment of the present disclosure, the second part includes:

[0014] A body part, whose opposite ends are correspondingly connected to the two first parts, and the width of the body part is equal to the width of the first part;

[0015] Two protruding parts, which are connected to the body part and are located on opposite sides in the width direction of the body part.

[0016] In an exemplary embodiment of the present disclosure, the edge line of the protruding part away from the body part is set as a curve, and the curve protrudes towards the side away from the body part.

[0017] In an exemplary embodiment of the present disclosure, the curve is an arc line or an elliptical arc line.

[0018] In an exemplary embodiment of the present disclosure, the second wire is one or two of a data line and a power line.

[0019] In an exemplary embodiment of the present disclosure, the array substrate further includes:

[0020] A light-shielding layer, which is arranged on one side of the substrate;

[0021] A buffer layer, which is arranged on the side of the light-shielding layer away from the substrate;

[0022] An active layer, which is arranged on the side of the buffer layer away from the substrate;

[0023] A gate insulating layer, which is arranged on the side of the active layer away from the substrate;

[0024] A gate, which is arranged on the side of the gate insulating layer away from the substrate, and the insulating layer is arranged on the side of the gate away from the substrate;

[0025] A source electrode and a drain electrode, which are arranged on the side of the insulating layer away from the substrate.

[0026] In an exemplary embodiment of the present disclosure, the first wire is disposed on the same layer and made of the same material as the gate.

[0027] In an exemplary embodiment of the present disclosure, the second wire is disposed on the same layer and made of the same material as the source and the drain.

[0028] According to another aspect of the present disclosure, there is provided a display panel, including: the array substrate described in any one of the above.

[0029] According to still another aspect of the present disclosure, there is provided a display device, including: the display panel described above.

[0030] In the array substrate of the present disclosure, the second wire is connected to the first wire through a first via. The second wire includes a first portion and a second portion, and the width of the second portion is greater than the width of the first portion. The orthographic projection of the first via on the substrate is located within the orthographic projection of the second portion on the substrate. On the one hand, the resistance of the connection structure between the first wire and the second wire is greatly reduced relative to the resistance of the second wire, thereby improving the conductive effect and further improving the display effect. On the other hand, during the process of etching to form the second wire, even when the mask is slightly offset, since the width of the second portion is set to be relatively wide, the second portion of the second wire to be formed can completely cover the first via, avoiding etching the metal material in the first via, thereby avoiding poor connection between the second wire and the first wire, avoiding affecting the conductive effect, and further avoiding affecting the display effect. On still another hand, only the width of the second portion of the second wire is widened, which does not affect the opening area and thus does not affect the aperture ratio.

[0031] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0033] Figure 1 It is a schematic structural diagram of an array substrate in which the inventor found that there is a poor connection of signal lines.

[0034] Figure 2 It is a schematic structural diagram of an exemplary embodiment of the array substrate of the present disclosure.

[0035] Figure 3 It is a schematic structural diagram of the second wire of the array substrate of the present disclosure being slightly offset.

[0036] Figure 4 This is a top - view structural schematic diagram of another exemplary embodiment of the disclosed array substrate.

[0037] Figure 5 is Figure 4 a structural schematic diagram of the adjacent cooperation of two second conductors in

[0038] Figure 6 This is a top - view structural schematic diagram of another exemplary embodiment of the cooperation of two second conductors in the disclosed array substrate.

[0039] Figure 7 This is a top - view structural schematic diagram of yet another exemplary embodiment of the cooperation of two second conductors in the disclosed array substrate.

[0040] Figure 8 This is a structural schematic diagram of an exemplary embodiment of the disclosed display panel.

[0041] Explanation of reference numerals:

[0042] 1. Array substrate; 101. Substrate; 102. Light - shielding layer; 103. Buffer layer; 104. Active layer; 1041. Conductor part; 1042. Channel part; 105. Gate insulating layer; 106. Gate; 107. First conductor; 108. Insulating layer; 1081. First via; 1082. Second via; 109. Source; 110. Drain; 111. Second conductor; 1111. First part; 1112. Second part; 1112a. Body part; 1112b. Protruding part; 112. Protective layer; 1121. Third via; 113. Gate line; 114. Data line; 115. Power line;

[0043] 2. First electrode;

[0044] 3. Pixel defining layer; 31. Fourth via;

[0045] 4. Light - emitting layer; 5. Second electrode; 6. Encapsulation layer group;

[0046] X. Second direction; Y. First direction. Detailed implementation manners

[0047] Now, the exemplary embodiments will be described more comprehensively with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0048] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0049] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second" and "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0050] Referring to Figure 1 As shown, the inventors found that the reason for the poor connection of the signal line is that when the second wire 111 is etched and formed, since the second wire 111 is designed to be relatively narrow, the second wire 111 that needs to be retained does not completely cover the first via 1081. When the second wire 111 is etched and formed, the metal material in the first via 1081 and the first wire 107 will be etched, resulting in a poor connection of the signal line and affecting the conductive effect.

[0051] The exemplary embodiments of the present disclosure provide an array substrate, as Figures 2 - 6 shown, the array substrate 1 may include a substrate 101, a first wire 107, an insulating layer 108, and a second wire 111; the first wire 107 is disposed on one side of the substrate 101; the insulating layer 108 is disposed on the side of the first wire 107 away from the substrate 101, and a first via 1081 is provided on the insulating layer 108, and the first via 1081 communicates with the first wire 107; the second wire 111 is disposed on the side of the insulating layer 108 away from the substrate 101, the second wire 111 is connected to the first wire 107 through the first via 1081, the second wire 111 includes a first portion 1111 and a second portion 1112, the first portion 1111 and the second portion 1112 are connected to each other in the first direction Y, the width K2 of the second portion 1112 in the second direction is greater than the width K1 of the first portion 1111 in the second direction X, the first direction Y intersects the second direction X, and the orthographic projection of the first via 1081 on the substrate 101 is located within the orthographic projection of the second portion 1112 on the substrate 101.

[0052] For the array substrate 1 of the present disclosure, on the one hand, the resistance of the connection structure between the first wire 107 and the second wire 111 is much smaller than the resistance of the second wire 111, thereby improving the conductive effect and further improving the display effect. On the other hand, as shown in Figure 3 During the process of etching to form the second wire 111, even when the mask is slightly offset, since the width of the second part 1112 is relatively wide, the second part 1112 of the second wire 111 to be formed can completely block the first via 1081, avoiding etching the metal material in the first via 1081, thereby avoiding poor connection between the second wire 111 and the first wire 107, avoiding affecting the conductive effect, and further avoiding affecting the display effect. On the other hand, only the width of the second part 1112 of the second wire 111 is widened, which will not affect the opening area and thus will not affect the aperture ratio.

[0053] In the present exemplary embodiment, the material of the substrate 101 may include inorganic materials. For example, the inorganic material may be glass, quartz, or metal, etc. The material of the substrate 101 may also include organic materials. For example, the organic material may be resin materials such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The substrate 101 may be formed by multiple material layers. For example, the substrate 101 may include multiple base layers, and the material of the base layer may be any of the above materials. Of course, the substrate 101 may also be provided as a single layer, which may be any of the above materials.

[0054] In the present exemplary embodiment, a light-shielding layer 102 is provided on one side of the substrate 101, and the material of the light-shielding layer 102 may be metal. The orthographic projection of the thin-film transistor on the substrate 101 is located within the orthographic projection of the light-shielding layer 102 on the substrate 101. Light incident from the substrate 101 will generate photo-generated carriers, which will have a huge impact on the characteristics of the thin-film transistor and ultimately affect the display quality of the display device. By the light-shielding layer 102, the light incident from the substrate 101 can be blocked, thereby avoiding affecting the characteristics of the thin-film transistor and avoiding affecting the display quality of the display device.

[0055] In the present exemplary embodiment, a buffer layer 103 is provided on the side of the light-shielding layer 102 away from the substrate 101. The buffer layer 103 functions to block moisture and impurity ions in the substrate 101 (especially organic materials), and also functions to increase hydrogen ions for the subsequent formed active layer 104. The material of the buffer layer 103 is an insulating material, which can insulate and isolate the light-shielding layer 102 from the active layer 104.

[0056] On one side of the buffer layer 103 away from the substrate 101, a plurality of thin film transistors arranged in an array are provided. The thin film transistors may include an active layer 104, a gate 106, a source 109, and a drain. The gate 106 is connected to the gate line 113, and the source 109 or the drain is connected to the data line 114. The specific structure of the thin film transistor will be described in detail below.

[0057] In the present exemplary embodiment, an active layer 104 is provided on one side of the buffer layer 103 away from the substrate 101. The material of the active layer 104 may be amorphous silicon, polycrystalline silicon, organic semiconductor material, undoped metal oxide, etc. The active layer 104 may include a channel portion 1042 and conductor portions 1041. The conductor portions 1041 may be provided in two, and the two conductor portions 1041 may be provided on opposite sides of the channel portion 1042.

[0058] In the present exemplary embodiment, a gate insulating layer 105 is provided on one side of the active layer 104 away from the substrate 101. Specifically, a gate insulating layer 105 is provided on the side of the channel portion 1042 away from the substrate 101. The orthographic projection of the channel portion 1042 on the substrate 101 is located within the orthographic projection of the gate insulating layer 105 on the substrate 101, or the orthographic projection of the channel portion 1042 on the substrate 1 is coincident with the orthographic projection of the gate insulating layer 105 on the substrate 1; that is, the gate insulating layer 105 covers at least the channel portion 1042. Of course, the gate insulating layer 105 may also cover the entire array substrate.

[0059] In the present exemplary embodiment, a gate 106 is provided on one side of the gate insulating layer 105 away from the substrate 101. The material of the gate 106 may be metal. The orthographic projection of the gate 106 on the substrate 101 is located within the orthographic projection of the gate insulating layer 105 on the substrate 101, or the orthographic projection of the gate 106 on the substrate 101 is coincident with the orthographic projection of the gate insulating layer 105 on the substrate 101. The channel portion 1042 is insulated from the gate 106 through the gate insulating layer 105.

[0060] A first wire 107 is formed simultaneously with the formation of the gate 106, that is, the first wire 107 is provided on the same layer and of the same material as the gate 106; the first wire 107 is not connected to the gate 106. Specifically: a gate material layer is formed on the side of the gate insulating layer 105 away from the substrate 101 through processes such as coating and deposition; then a photoresist is coated on the side of the gate material layer away from the substrate 101, a mask plate is placed on the side of the photoresist away from the substrate 101, the mask plate and the photoresist are irradiated with light, the mask plate is removed, and the irradiated photoresist is developed. The gate material layer is etched using the remaining photoresist as a mask layer to form the gate line 113, the gate 106, and the first wire 107. The gate 106 is connected to the gate line 113. However, the gate 106 is not connected to the first wire 107.

[0061] Referring to Figure 4 As shown, the first wire 107 can be disposed between two adjacent sub-pixels, and one first wire 107 can be disposed between two adjacent sub-pixels. The first wire 107 extends along the first direction Y. The width of the first wire 107 is greater than or equal to 4 microns and less than or equal to 10 microns. The first wire 107 can be used as the lower layer wire of the power supply line 115 (VDD).

[0062] Referring to Figure 4 As shown, two first wires 107 can also be disposed between two adjacent sub-pixels. The two first wires 107 both extend along the first direction Y. The two first wires 107 are disposed adjacent to each other in the second direction X. A first gap P1 is disposed between two adjacent first wires 107. The width of the first gap P1 is greater than or equal to 2 microns and less than or equal to 7 microns. The two first wires 107 can correspondingly serve as the lower layer wires of two data lines 114. Of course, more first wires 107 can also be disposed between two adjacent sub-pixels as needed.

[0063] In the present exemplary embodiment, an insulating layer 108 is disposed on a side of the gate 106 away from the substrate 101. A first via 1081 and a second via 1082 are disposed on the insulating layer 108. The first via 1081 communicates with the first wire 107 to expose a part of the first wire 107. The second via 1082 communicates with the conductor portion 1041 to expose a part of the conductor portion 1041. The insulating layer 108 can be an interlayer dielectric layer. The first via 1081 and the second via 1082 can be formed by photolithography. The specific process of photolithography has been described in detail above. Therefore, it will not be elaborated here.

[0064] The first via 1081 can be provided in multiple numbers. When one first wire 107 is disposed between two adjacent sub-pixels, a column of via groups can be formed by arranging multiple first vias 1081 along the first direction Y. Multiple first vias 1081 all communicate with the first wire 107. The cross-sectional shape of the first via 1081 parallel to the substrate 101 can be rectangular, circular, elliptical, etc.

[0065] Referring to Figure 5As shown, when two first conductive lines 107 are provided between two adjacent sub-pixels, a plurality of first vias 1081 arranged along the first direction Y can form two columns of via groups. The two columns of via groups are arranged adjacent to each other in the second direction X, and one column of via groups is correspondingly arranged with one first conductive line 107. At least some of the first vias 1081 in two adjacent columns of via groups are arranged in a staggered manner, that is, a second gap P2 is provided between two adjacent first vias 1081 in the same column. At least some of the first vias 1081 in the other column of via groups are arranged opposite to the second gap P2. The width of the second gap P2 is greater than or equal to 8 micrometers and less than or equal to 12 micrometers. Of course, the data here is only for illustrative purposes, and the width of the second gap P2 can also be other values, which are specifically determined according to the size of the product and the line width of the first conductive line 107. When the distance between two columns of via groups is relatively large, the first vias 1081 in two adjacent columns of via groups can also be arranged without staggering, that is, the first vias 1081 in two adjacent columns of via groups can also be arranged opposite to each other.

[0066] With such an arrangement, it can be avoided that two adjacent first vias 1081 in the second direction X are formed on a straight line extending along the second direction X. When the width of the first gap P1 is the same, the distance between two adjacent first vias 1081 in the second direction X can be increased, and it can be avoided that the distance between two first vias 1081 is too small to cause connection, thereby resulting in signal disorder; moreover, arranging the first vias 1081 in a staggered manner can increase the strength of the array substrate 1.

[0067] In the present exemplary embodiment, a source electrode 109 and a drain electrode 110 are provided on a side of the insulating layer 108 away from the substrate 101. The materials of the source electrode 109 and the drain electrode 110 can be metals. A second conductive line 111 is formed simultaneously with the formation of the source electrode 109 and the drain electrode 110, that is, the second conductive line 111 is provided on the same layer and made of the same material as the source electrode 109 and the drain electrode 110. The source electrode 109 and the drain electrode 110 are correspondingly connected to two conductor portions 1041 through second vias 1082. The manufacturing process of the source electrode 109 and the drain electrode 110 is the same as that of the gate electrode 106. Therefore, it will not be elaborated here.

[0068] The second wire 111 is connected to the first wire 107 through the first via 1081 on the insulating layer 108. The second wire 111 can be used as the upper-layer wire of the data line 114, and the second wire 111 is connected to the source electrode 109 or the drain electrode 110. The second wire 111 can also be used as the upper-layer wire of the power supply line 115 (VDD). That is, the first wire 107 and the second wire 111 jointly form the data line 114 or the power supply line 115. The access of the first wire 107 reduces the resistance of the data line 114 and the power supply line 115, thereby improving the conductivity effect and further improving the display effect. Moreover, multiple first vias 1081 enable multiple connections between the first wire 107 and the second wire 111, further reducing the resistance of the data line 114 and the power supply line 115, further improving the conductivity effect, and improving the display effect.

[0069] The second wire 111 extends along the first direction Y, that is, the length direction of the second wire 111 is the first direction Y, the width direction of the second wire 111 is the second direction X, and the first direction Y intersects the second direction X. For example, the first direction Y and the second direction X can be perpendicular.

[0070] The second wire 111 can include a first part 1111 and a second part 1112, and the first part 1111 and the second part 1112 are connected to each other in the first direction Y. The number of the second parts 1112 can be the same as the number of the first vias 1081. The width of the first part 1111 is greater than or equal to 3 microns and less than or equal to 6 microns. The width of the second part 1112 is greater than or equal to 5 microns and less than or equal to 9 microns.

[0071] Referring to Figure 5 As shown, the width K2 of the second part 1112 is greater than the width K1 of the first part 1111, and the orthographic projection of the first via 1081 on the substrate 101 is located within the orthographic projection of the second part 1112 on the substrate 101, which means that the second part 1112 and the first via 1081 are oppositely arranged, and the area of the second part 1112 is greater than the cross-sectional area of the first via 1081, so that the second part 1112 completely shields the first via 1081; during the process of etching the source-drain material layer to form the source electrode 109, the drain electrode 110 and the second wire 111, even when the mask is slightly offset, due to the relatively wide width of the second part 1112 provided, the second part 1112 of the second wire 111 to be formed can completely shield the first via 1081, avoiding etching the metal material in the first via 1081 and the first wire 107, thereby avoiding the influence on the conductivity effect and avoiding affecting the display effect.

[0072] It should be noted that the orthographic projection of the first via 1081 on the substrate 101 is located within the orthographic projection of the second part 1112 on the substrate 101. Alternatively, the second part 1112 and the first via 1081 are oppositely arranged, and part or all of the edges of the orthographic projection of the second part 1112 on the substrate 101 overlap with the edges of the orthographic projection of the first via 1081 on the substrate 101. For example, the first via 1081 is a square hole, and the four corners of the first via 1081 just overlap with the edges of the second part 1112. Similarly, etching of the metal material in the first via 1081 and the first wire 107 can also be avoided, thereby avoiding the influence on the conductive effect and the display effect.

[0073] When the first wire 107 between two adjacent sub-pixels is set to one, and multiple first vias 1081 are set to a column of via groups, the second wire 111 can be set to one, that is, there is a one-to-one correspondence among the second wire 111, the via group, and the first wire 107.

[0074] When the first wire 107 between two adjacent sub-pixels is set to two, and multiple first vias 1081 are set to two columns of via groups, the second wire 111 can be set to two. At least part of the second parts 1112 of two adjacent second wires 111 are arranged in a staggered manner, that is, a third gap P3 is provided between two adjacent second parts 1112 on the same second wire 111, and the second part 1112 of the other second wire 111 is arranged opposite to the third gap P3; that is, relative arrangement of the second parts 1112 on two adjacent second wires 111 is avoided. The width of the third gap P3 is greater than or equal to 8 μm and less than or equal to 12 μm.

[0075] Since the width of the second part 1112 is wider than that of the first part 1111, after the second parts 1112 on two adjacent second wires 111 are relatively arranged, the second parts 1112 on two adjacent second wires 111 are very likely to be connected as a whole, resulting in signal confusion; if it is necessary to ensure that the second parts 1112 on two adjacent second wires 111 are not connected to each other, the manufacturing process needs to be improved, resulting in higher costs and lower efficiency. The second parts 1112 of two adjacent second wires 111 are arranged in a staggered manner, which can ensure that the second parts 1112 on two adjacent second wires 111 are not connected to each other, and there is no need to improve the manufacturing process, thus not resulting in higher costs and lower efficiency. Moreover, the opening area can be ensured, so that the aperture ratio is not affected. Of course, when the distance between two adjacent second wires 111 is large, the second parts 1112 of two adjacent second wires 111 can also be not arranged in a staggered manner, that is, the second parts 1112 of two adjacent second wires 111 can also be relatively arranged.

[0076] The second part may include a body portion 1112a and two protruding portions 1112b; opposite ends of the body portion 1112a are correspondingly connected to the two first parts 1111, and the width of the body portion 1112a is equal to the width of the first part 1111; that is, opposite ends of the body portion 1112a in the first direction Y are correspondingly connected to the two first parts 1111, and the width of the body portion 1112a in the second direction X is equal to the width of the first part 1111 in the second direction X.

[0077] The two protruding portions 1112b are connected to the body portion 1112a and are located on opposite sides in the width direction of the body portion 1112a, that is, the two protruding portions 1112b are connected to opposite sides of the body portion 1112a in the second direction X.

[0078] The edge line of the protruding portion 1112b away from the body portion 1112a may be set as a curve, that is, the edge line of the protruding portion 1112b consistent with the extending direction of the second wire 111 may be set as a curve; the curve protrudes away from the body portion 1112a, such that the width of the second part 1112 is greater than the width of the first part 1111. Specifically, the edge line of the protruding portion 1112b may be set as an arc line or an elliptical arc line.

[0079] It should be noted that Figure 4 only for exemplary illustration, two adjacent first wires 107 and two adjacent second wires 111 may be disposed between two adjacent pixels, and at least one 2T1C circuit is required to drive one pixel. Only the structure of the thin film transistor is briefly drawn in the figure.

[0080] It should be noted that, with reference to Figure 6 as shown, the edge lines of the two protruding portions 1112b may be the same or different; the above curves include not only arc curves but also curves formed by connecting straight lines. Therefore, in other exemplary embodiments of the present disclosure, with reference to Figure 7 as shown, the edge line of the protruding portion 1112b may be set as a trapezoidal edge line formed by connecting multiple straight lines, and of course it may also be a rectangular edge line; it may also be set as other shapes formed by connecting straight lines and arc lines or elliptical arc lines.

[0081] In the present exemplary embodiment, a protective layer 112 is provided on the side of the source electrode 109, the drain electrode 110, and the second wire 111 away from the substrate 101. The protective layer 112 can protect the source electrode 109, the drain electrode 110, and the second wire 111. A third via 1121 is provided on the protective layer 112, and the third via 1121 communicates with the source electrode 109 or the drain electrode 110.

[0082] It should be noted that the above specifically describes the top-gate thin-film transistor. The array substrate 1 may also include a bottom-gate thin-film transistor or a double-gate thin-film transistor. The specific structures of the first wire 107 and the second wire 111 can also be used for the bottom-gate thin-film transistor or the double-gate thin-film transistor. Moreover, the above data is only for illustration, and the above data can also take other values, which are specifically determined according to the size of the product.

[0083] It can be understood that in the case of using thin-film transistors with opposite polarities or when the current direction changes during the operation of the circuit, etc., the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0084] Based on the same inventive concept, the exemplary embodiments of the present disclosure provide a display panel. Referring to Figure 8 as shown, the display panel may include the array substrate 1 described in any one of the above. The specific structure of the array substrate 1 has been described in detail above, and therefore, it will not be elaborated here.

[0085] The display panel may further include a first electrode 2, a pixel defining layer 3, a light-emitting layer 4, a second electrode 5, and a packaging layer group 6. The first electrode 2 is disposed on the side of the protective layer 112 away from the substrate 101. The first electrode 2 is connected to the source electrode 109 or the drain electrode 110 through a third via 1121 on the protective layer 112. The first electrode 2 may be an anode, and the material of the first electrode 2 may be a transparent conductive material. For example, it may be ITO (indium tin oxide), IZO (indium zinc oxide), etc. The pixel defining layer 3 is disposed on the side of the first electrode 2 away from the substrate 101. A fourth via 31 is provided on the pixel defining layer 3, and the fourth via 31 communicates with the first electrode 2, and the fourth via 31 exposes a part of the first electrode 2. The light-emitting layer 4 is disposed in the fourth via 31, and the light-emitting layer 4 is connected to the first electrode 2. The second electrode 5 is disposed on the side of the light-emitting layer 4 away from the substrate 101, and the second electrode 5 may be a cathode.

[0086] The packaging layer group 6 is disposed on the side of the second electrode 5 away from the substrate 101. The packaging layer group 6 may include an organic layer and an inorganic layer, and the number of layers and the stacking manner of the organic layer and the inorganic layer can be set as needed, and will not be elaborated here one by one.

[0087] Based on the same inventive concept, the exemplary embodiments of the present disclosure provide a display device, which may include the display panel described above. The specific structure of the display panel has been described in detail above, and therefore, it will not be elaborated here.

[0088] The specific type of the display device is not particularly limited, and any type of display device commonly used in the art may be used. Specifically, for example, mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc. Those skilled in the art can make corresponding selections according to the specific use of the display device, which will not be elaborated here.

[0089] It should be noted that in addition to the display panel, the display device also includes other necessary components and compositions. Taking a display as an example, specifically, for example, a housing, a circuit board, a power cord, etc. Those skilled in the art can make corresponding supplements according to the specific usage requirements of the display device, which will not be elaborated here.

[0090] Compared with the prior art, the beneficial effects of the display panel and the display device provided by the exemplary embodiments of the present invention are the same as those of the array substrate 1 provided by the above exemplary embodiments, which will not be elaborated here.

[0091] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed herein. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. An array substrate, characterized in that, Comprising: A substrate; A first wire disposed on one side of the substrate; An insulating layer disposed on the side of the first wire away from the substrate, with a first via formed in the insulating layer, and the first via communicating with the first wire; A second wire disposed on the side of the insulating layer away from the substrate, the second wire being connected to the first wire through the first via, the second wire including a first portion and a second portion, the first portion and the second portion being connected to each other in a first direction, the width of the second portion in a second direction being greater than the width of the first portion in the second direction, the second direction intersecting the first direction, and the orthographic projection of the first via on the substrate being located within the orthographic projection of the second portion on the substrate; The first wire and the second wire extend along the first direction, and a plurality of the first vias are arranged along the first direction to form at least two columns of via groups, at least two columns of the via groups being adjacent to each other in the second direction, and at least some of the first vias in adjacent two columns of the via groups being offset; One column of the via groups corresponds to one first wire and one second wire, and at least some of the second portions of adjacent two second wires are offset.

2. The array substrate according to claim 1, wherein The second portion includes: A body portion, the opposite ends of which are correspondingly connected to the two first portions, and the width of the body portion being equal to the width of the first portion; Two protruding portions connected to the body portion and located on opposite sides in the width direction of the body portion.

3. The array substrate according to claim 2, wherein The edge line of the protruding portion away from the body portion is set as a curve protruding away from the body portion.

4. The array substrate according to claim 3, wherein The curve is an arc line or an elliptical arc line.

5. The array substrate according to claim 1, characterized in that The second wire is one or two of a data line and a power line.

6. The array substrate according to claim 1, wherein The array substrate further includes: A light-shielding layer disposed on one side of the substrate; A buffer layer disposed on the side of the light-shielding layer away from the substrate; An active layer disposed on the side of the buffer layer away from the substrate; A gate insulating layer disposed on the side of the active layer away from the substrate; A gate disposed on the side of the gate insulating layer away from the substrate, and the insulating layer is disposed on the side of the gate away from the substrate; A source electrode and a drain electrode disposed on the side of the insulating layer away from the substrate.

7. The array substrate according to claim 6, wherein The first wire is provided with the same layer and the same material as the gate.

8. The array substrate according to claim 6, wherein The second wire is provided with the same layer and the same material as the source electrode and the drain electrode.

9. A display panel, characterized in that, Comprising: The array substrate according to any one of claims 1 to 8.

10. A display device, characterized in that, Comprising: The display panel according to claim 9.

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