Display panel and display device

Abstract

The present application provides a display panel and a display device. The display panel includes a first display area and a second display area, wherein the sub-pixel density of the first display area is less than that of the second display area; the first display area includes a routing area and a pixel row extending along a first direction, wherein the pixel row includes multiple pixel areas, each pixel area includes n sub-pixels and n pixel circuits, and the first routing area is located between two adjacent pixel areas in a second direction; a signal line extending along a second direction includes a first line segment located in the first routing area and a second line segment located in the pixel area, wherein the second line segment is electrically connected to the pixel circuit; adjacent first and second pixel rows, wherein the first pixel row includes N sub-pixels and the second pixel row includes M sub-pixels, where N ≤ M; and the total number of first line segments between the first and second pixel rows is less than N. The present application can increase the area of ​​the light-transmitting region of the first display area and improve the diffraction phenomenon when light passes through the first display area.

Description

[0001] This application is a divisional application with the application date of November 29, 2019, application number 201911207034.7, and invention name “Display panel and display device”. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] With the advancement of display technology, people are demanding not only a smooth user experience but also an increasingly advanced visual experience from their electronic products. High screen-to-body ratios have become a current research focus. Optical components like front-facing cameras inevitably take up a certain amount of space in electronic products, thus impacting the screen-to-body ratio. To increase this screen-to-body ratio and achieve a full-screen display, researchers are considering implementing under-display optical components.

[0004] The optical device is placed below the display panel's light-emitting device film layer, meaning it's placed within the display area. When display is required, the optical device's location allows for normal display; when the optical device is needed, light passes through the display panel to reach the optical device, ultimately being utilized by the device. With the optical device placed under the screen, light must pass through the display panel's film structure to be utilized by the optical device. An evaluation of current under-screen optical device placement solutions has revealed poor image quality, failing to meet user needs. Summary of the Invention

[0005] Embodiments of the present invention provide a display panel and a display device to solve the technical problem that the imaging quality of the under-screen optical devices in the prior art is poor and difficult to meet user needs.

[0006] In order to solve the above technical problems, in a first aspect, the present invention provides a display panel, wherein a display area of ​​the display panel includes a first display area and a second display area, the display area includes a plurality of sub-pixels, and the density of the plurality of sub-pixels in the first display area is less than the density of the plurality of sub-pixels in the second display area;

[0007] The first display area includes a plurality of routing areas and a plurality of pixel rows extending along a first direction, wherein a pixel row includes a plurality of pixel areas arranged in the first direction, a pixel area includes n sub-pixels and n pixel circuits, where n is a positive integer, and the sub-pixels are electrically connected to the pixel circuits, the plurality of routing areas include a plurality of first routing areas, a first routing area is located between two adjacent pixel areas in a second direction, and the second direction intersects the first direction;

[0008] The first display area further includes a plurality of signal lines extending along the second direction. When the display panel is driven to display, a constant voltage signal is provided to the signal lines. The signal lines include a first line segment and a second line segment. The first line segment is located in the first routing area, and the second line segment is located in the pixel area. In the pixel area, the second line segment is electrically connected to the pixel circuit.

[0009] The pixel rows include an adjacent first pixel row and a second pixel row, the first pixel row includes N sub-pixels, the second pixel row includes M sub-pixels, N and M are both positive integers, and N≤M; the total number of first line segments in multiple first routing areas between the first pixel row and the second pixel row is less than N.

[0010] Based on the same inventive concept, in a second aspect, the present invention further provides a display device, comprising any one of the display panels provided by the present invention.

[0011] The display panel and display device provided by the embodiments of the present invention have the following beneficial effects:

[0012] The design of this application reduces the number of signal lines between the adjacent first pixel row and the second pixel row, which can reduce the area of ​​the non-transparent area in the first display area, that is, it can correspondingly increase the area of ​​the light-transmitting area of ​​the first display area, thereby improving the transmittance of the first display area. When applied to the solution of the under-screen optical device, it can increase the amount of light received by the under-screen optical device and improve the optical performance of the optical device. In addition, when light passes through the first display area, the various wiring arranged in the first display area can form a diffraction grating, which will diffract the light. For example, when the under-screen optical device is a camera, the diffraction phenomenon will affect the imaging quality of the camera. By reducing the number of signal lines between two adjacent pixel rows, the embodiment of the present application can also improve the diffraction phenomenon when light passes through the first display area to a certain extent, further improving the optical performance of the optical device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0014] Figure 1 A schematic diagram of an optional implementation of a display panel provided in an embodiment of the present application;

[0015] Figure 2 for Figure 1 Enlarged view of position Q in the middle area;

[0016] Figure 3A partial schematic diagram of a first display area of ​​a display panel provided in an embodiment of the present application;

[0017] Figure 4 A partial schematic diagram of a display panel in the related art;

[0018] Figure 5 A partial schematic diagram of an optional implementation of the first display area of ​​the display panel provided in an embodiment of the present application;

[0019] Figure 6 A partial schematic diagram of another optional implementation of the first display area of ​​the display panel provided in an embodiment of the present application;

[0020] Figure 7 A partial schematic diagram of another optional implementation of the first display area of ​​the display panel provided in an embodiment of the present application;

[0021] Figure 8 A partial schematic diagram of another optional implementation of the first display area of ​​the display panel provided in an embodiment of the present application;

[0022] Figure 9 A partial schematic diagram of another optional implementation of the first display area of ​​the display panel provided in an embodiment of the present application;

[0023] Figure 10 A partial schematic diagram of another optional implementation of the first display area provided in an embodiment of the present application;

[0024] Figure 11 A partial schematic diagram of another optional implementation of the first display area provided in an embodiment of the present application;

[0025] Figure 12 A partial schematic diagram of another optional implementation of the first display area of ​​the display panel provided in an embodiment of the present application;

[0026] Figure 13 A partial schematic diagram of another optional implementation of the first display area of ​​the display panel provided in an embodiment of the present application;

[0027] Figure 14 A schematic diagram of another optional implementation of the first display area of ​​the display panel provided in an embodiment of the present application;

[0028] Figure 15 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0030] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0031] To address the technical issues in related technologies, embodiments of the present application provide a display panel and display device. By reducing the number of line segments between two adjacent pixel rows within the display area corresponding to the optical device (the first display area in this application), the area of ​​the light-transmitting region within the first display area is increased, thereby improving the light transmittance of the first display area. This means that when an under-screen optical device solution is employed, the amount of light received by the optical device is increased. Furthermore, the diffraction phenomenon of light penetrating the first display area is reduced, thereby improving the optical performance of the under-screen optical device.

[0032] Figure 1 A schematic diagram of an optional implementation of the display panel provided in an embodiment of the present application. Figure 2 for Figure 1 The enlarged image of the Q position in the middle area. Figure 1 As shown, the display area AA of the display panel includes a first display area AA1 and a second display area AA2, and the display area includes a plurality of sub-pixels sp, such as Figure 2 As shown, the density of the plurality of sub-pixels sp in the first display area AA1 is smaller than the density of the plurality of sub-pixels sp in the second display area AA2; Figure 1The figure only schematically shows that the second display area AA2 surrounds the first display area AA1. Optionally, the second display area AA2 may also semi-surround the first display area AA1. In the embodiment of the present invention, the shape of the first display area AA1 is not limited and may be any of circular, elliptical, triangular, or polygonal. The display panel provided in the embodiment of the present application may be an organic light-emitting display panel, which includes an array layer and a light-emitting layer located above the array layer. The light-emitting layer includes multiple light-emitting devices, and each sub-pixel sp includes one light-emitting device. The density of the multiple sub-pixels sp in the first display area AA1 is less than the density of the multiple sub-pixels sp in the second display area AA2, that is, the density of the multiple light-emitting devices in the first display area AA1 is less than the density of the multiple light-emitting devices in the second display area AA2. Therefore, the transmittance per unit area of ​​the first display area AA1 is greater than the transmittance per unit area of ​​the second display area AA2. In the under-screen optical device solution, the optical device can be disposed below the first display area AA1 to ensure that the optical device can receive sufficient light when the optical device is enabled. During display, the first display area AA1 can be used to display information such as notification symbols, power symbols, network symbols, and time.

[0033] Figure 3 A partial schematic diagram of the first display area of ​​the display panel provided in an embodiment of the present application, such as Figure 3 As shown, the first display area AA1 includes multiple routing areas ZQ and multiple pixel rows PH extending along a first direction x. Each pixel row PH includes multiple pixel areas PQ arranged in the first direction x. Each pixel area includes n sub-pixels sp and n pixel circuits DL, where n is a positive integer. n can be an integer such as 1, 2, 3, or 4. The sub-pixels sp are electrically connected to the pixel circuits DL accordingly. Figure 3 In the figure, only one pixel region includes three sub-pixels sp and three pixel circuits DL for illustration. Optionally, one pixel region may include one sub-pixel and one pixel circuit, or one pixel region may include four sub-pixels and four pixel circuits. The division of the pixel region is related to the arrangement of the sub-pixels in the first display region, and the arrangement of the sub-pixels may be related to the display method of the display panel. The embodiments of the present invention are applicable to display panels designed with any sub-pixel arrangement.

[0034] The multiple routing areas ZQ include multiple first routing areas ZQ1, and a first routing area ZQ is located between two adjacent pixel areas PQ in the second direction y, where the second direction y intersects the first direction x; the routing area ZQ is also an area used to set routing, and the routing between two adjacent pixel areas PQ in the second direction y can be concentrated in the routing area ZQ.

[0035] The first display area AA1 further includes a plurality of signal lines X extending along the second direction y. When the display panel is driven to display, a constant voltage signal is provided to the signal lines X. In one embodiment, the signal lines X are positive power supply signal lines. When the sub-pixels are driven to display, the positive power supply signal lines provide a constant voltage signal to the pixel circuit. In one embodiment, the signal lines X are reset signal lines. When the sub-pixels are driven to display, the reset signal lines provide a constant reset signal to the pixel circuit.

[0036] The signal line X includes a first line segment D1 and a second line segment D2. The first line segment D1 is located in the first routing area ZQ1, and the second line segment D2 is located in the pixel area PQ. In the pixel area PQ, the second line segment D2 is electrically connected to the pixel circuit DL. In the figure, the black solid circle indicates that the second line segment D2 is electrically connected to the pixel circuit DL.

[0037] The pixel rows PH include a first pixel row PH1 and a second pixel row PH2, the first pixel row PH1 including N sub-pixels, and the second pixel row PH2 including M sub-pixels, where N and M are both positive integers and N≤M; the total number of first line segments D1 of ZQ1 in the plurality of first routing areas between the first pixel row PH1 and the second pixel row PH2 is less than N. Depending on the shape of the first display area, the number of sub-pixels in two adjacent pixel rows within the first display area may be the same or different. In an embodiment of the present invention, when the number of sub-pixels in the first pixel row PH1 and the number of sub-pixels in the second pixel row PH2 are equal, the total number of first line segments D1 between the two pixel rows is less than the number of sub-pixels in one pixel row; when the number of sub-pixels in the first pixel row PH1 is less than the number of sub-pixels in the second pixel row PH2, the total number of first line segments D1 between the two pixel rows is less than the number of sub-pixels in the first pixel row PH1. Figure 3 The complete first pixel row PH1 and the complete second pixel row PH2 in the first display area AA1 are not shown. Only the local position shown in the figure is shown, and the local area illustrates 12 sub-pixels sp in the first pixel row PH1 and 12 sub-pixels sp in the second pixel row PH2. In this local area, there are 8 first line segments D1 between the first pixel row PH1 and the second pixel row PH2, that is, the design of the embodiment of the present application reduces the number of first line segments D1 between two adjacent pixel rows.

[0038] In one embodiment, signal line X is a positive power signal line. When driving a sub-pixel for display, the positive power signal line provides a constant voltage signal to the pixel circuit. The first display area also includes a data line extending in the same direction as signal line X. When driving a sub-pixel for display, the data line provides a data signal to the pixel circuit. The first wiring area ZQ1 also includes a data line, which is not shown in the figure.

[0039] In another embodiment, signal line X is a reset signal line that provides a constant reset signal to the pixel circuit when driving a subpixel for display. The first display area also includes a gate scan line and a light-emission control signal line extending in the same direction as signal line X. The first routing area ZQ1 also includes a gate scan line and a light-emission control signal line, which are not shown in the figure.

[0040] Figure 4 FIG. 1 is a partial schematic diagram of a display panel in the related art. Figure 4 As shown, a signal line X' extending in the second direction y and a pixel row PH' extending in the first direction x are schematically shown. The pixel row PH' includes a plurality of sub-pixels sp' arranged in the first direction x and a pixel circuit DL' electrically connected to the sub-pixels sp'. A conventional design of those skilled in the art is that the plurality of pixel circuits DL' arranged in the second direction y are electrically connected to the same signal line X'. The signal line X' includes a first line segment D1' and a second line segment D2'. The second line segment D2' is electrically connected to the pixel circuit DL', and the first line segment D1' is located between two adjacent pixel rows PH'. In the local area shown in the figure, two adjacent pixels and an area each including 12 sub-pixels sp', and the corresponding two pixel rows include 12 first line segments D1'.

[0041] When applied to a display panel in which the display area includes a first display area and a second display area as shown in the embodiment of the present application (i.e., a solution of an under-screen optical device), a design solution that can be easily thought of by a person skilled in the art without creative work is to still use the above-mentioned optical device in the first display area with a smaller sub-pixel density. Figure 4The design method in the present application. The inventors of the present application have improved the design in the related art through creative work, and the design reduces the number of signal lines (that is, the first line segments in the present application) between two adjacent pixel rows. Since the signal lines are usually made of metal materials, when the light penetrates the display panel from the first display area, the area where the signal lines are located has the property of shading, that is, the area occupied by the signal lines belongs to the non-light-transmitting area. The embodiment of the present application can reduce the area of ​​the non-light-transmitting area in the first display area, that is, it can correspondingly increase the area of ​​the light-transmitting area of ​​the first display area (that is, the area through which light can penetrate. When understanding, the light-transmitting area and the non-light-transmitting area are two relative concepts, and the transmittance of the light-transmitting area is greater than the transmittance of the non-light-transmitting area), thereby improving the transmittance of the first display area. When applied to the solution of the under-screen optical device, it can increase the amount of light received by the under-screen optical device and improve the optical performance of the optical device. Furthermore, when light passes through the first display area, the various wiring arranged within the first display area can form a diffraction grating, which diffracts the light. For example, when the under-screen optical device is a camera, this diffraction phenomenon can affect the camera's imaging quality. By reducing the number of signal lines between two adjacent pixel rows, the embodiments of the present application can also, to a certain extent, improve the diffraction phenomenon of light passing through the first display area, further enhancing the optical performance of the optical device.

[0042] In the first display area of ​​the display panel provided by the embodiment of the present application, by reducing the number of first line segments between two adjacent pixel areas, the area of ​​the light-transmitting area of ​​the first display area can be increased, and the diffraction phenomenon caused by light penetrating the first display area can be improved. After reducing the number of first line segments (partial line segments of the signal line) in the first wiring area, it can be as described above. Figure 3 Schematically, the second line segment D2 within the pixel region PQ is electrically connected to the same first line segment D1, enabling input of a signal to the second line segment D2 to drive the corresponding sub-pixel to display, thereby ensuring that all sub-pixels in the first display region can display normally. The following embodiments will provide detailed examples of the technical solutions provided by this application.

[0043] In some optional embodiments, the plurality of first routing regions between the first pixel row and the second pixel row include: a first routing region A; and within the first pixel row and the second pixel row, a pixel region A adjacent to the first routing region A, the pixel region A including n second line segments; wherein the first routing region A includes p first line segments, where p is an integer and n>p≥0. That is, the number of first line segments within the first routing region A adjacent to the pixel region A is less than the number of second line segments within the pixel region A. The pixel region A may be located in the first pixel row, or the second pixel row, or may include the pixel region A in both the first pixel row and the second pixel row. When p=0, no first line segments are provided within the first routing region A. By setting the number of first line segments within the first routing region adjacent to the pixel region to be less than the number of second line segments within the pixel region, i.e., less than the number of sub-pixels within the pixel region, the number of first line segments between two adjacent pixel rows is reduced, thereby increasing the light-transmitting area of ​​the first display region and improving diffraction caused by light penetrating the first display region.

[0044] In one embodiment, a pixel area includes 1 sub-pixel and 1 pixel circuit, that is, n=1, and the multiple first routing areas in the first display area include the first routing area A, and no first line segment is set in the first routing area A, that is, p=0. Figure 5 This is a partial schematic diagram of an optional implementation of the first display area of ​​the display panel provided in the embodiment of the present application. Figure 5 As shown, a pixel region PQ includes one subpixel sp and one pixel circuit DL, and thus includes one second line segment D2 within the pixel region PQ. The figure illustrates a first trace ZX in the first display area, extending in the same direction as the signal line X. When the signal line X is a positive power line, the first trace ZX is a data line; when the signal line X is a reset signal line, the first trace ZX is a gate scan line or a light-emission control signal line. The figure illustrates the signal line X as a thick line and the first trace ZX as a thin line. This is merely to distinguish the two lines and does not limit the line width in actual products. The first routing area ZQ1 extending in the second direction y includes a first routing area A ZQ1a. No first line segment D1 is provided in the first routing area A ZQ1. A second line segment D2 is provided in the pixel area A PQa adjacent to the first routing area A ZQ1a. In other words, at least some signal lines X are terminated at the first routing area A ZQ1a. This reduces the number of signal lines X (i.e., first line segments D1) between two adjacent pixel rows, thereby increasing the light-transmitting area of ​​the first display area and improving the diffraction phenomenon caused by light penetrating the first display area.

[0045] Figure 5In the corresponding embodiment, the signal line X that provides signals to the pixel circuit in pixel region A PQa is terminated at the first wiring region A ZQ1 a. How to input signals to the second line segment D2 in pixel region A PQa during the display phase? In order to ensure that the sub-pixels in pixel region A PQa can still display normally, this application further proposes a solution. Figure 5 As shown, the routing area also includes a plurality of second routing areas ZQ2, and one second routing area ZQ2 is located between two pixel areas PQ adjacent to each other in the first direction x; the first display area also includes a plurality of auxiliary signal lines FX extending along the first direction x, and part of the line segment of the auxiliary signal line FX is located in the second routing area ZQ2. The pixel row PH also includes: a pixel area PQb adjacent to the pixel area PQa, and the pixel area PQa and the pixel area PQb are located in the same pixel row PH; the second line segments D2 located in the pixel area PQa and the pixel area PQb are electrically connected through the auxiliary signal line FX. The black solid dots in the figure indicate that the two second line segments D2 are electrically connected through the auxiliary signal line FX. The extension direction of the auxiliary signal line FX intersects with the extension direction of the signal line X, and the auxiliary signal line FX is electrically connected at the position where it overlaps with the signal line X (that is, with the second line segment D2 defined in this application), so that the auxiliary signal line FX and the signal line X transmit the same voltage signal. The auxiliary signal line FX is connected in parallel with the signal line X, which reduces the overall resistance and thus the power loss. At the same time, when driving the sub-pixels for display, the auxiliary signal line FX can input a voltage signal to the second line segment D2 in the pixel region A PQa, enabling the sub-pixels in the pixel region A PQa to display normally.

[0046] In some optional embodiments, p≠0, at least two second line segments within pixel region A are electrically connected to the same first line segment within routing region A. When the number of sub-pixels within the pixel region is greater than or equal to 2, two or more second line segments are required within the pixel region. By electrically connecting at least two second line segments within pixel region A to the same first line segment, the number of first line segments provided between two adjacent pixel rows can be reduced.

[0047] In one embodiment, n=3, that is, pixel area A includes 3 second line segments, and 2 second line segments in pixel area A are electrically connected to the same first line segment in the first wiring area A, then the first wiring area A adjacent to pixel area A includes 2 first line segments, that is, p=2.

[0048] Specifically, Figure 6 For example, Figure 6 This is a partial schematic diagram of an optional implementation of the first display area of ​​the display panel provided in the embodiment of the present application. Figure 6As shown, pixel region A PQa includes three second line segments D2, i.e., n=3. Two adjacent pixel rows (i.e., the first and second pixel rows) in the figure both include pixel region A PQa. To clarify the various wiring diagrams, only the pixel circuit DL is shown within the pixel region. The two second line segments D2 within pixel region A are electrically connected to the same first line segment D1 within first wiring region A ZQ1a. Another second line segment D2 within pixel region A PQa is electrically connected to another first line segment D1 within first wiring region A ZQ1a. First wiring region A ZQ1a includes two first line segments. The figure illustrates first wiring ZX in the first display area, extending in the same direction as signal line X. The number of first wiring ZX within a pixel region is the same as the number of sub-pixels within that pixel region. In this embodiment, a pixel region includes three first wiring ZX. In this embodiment, by setting two second line segments in the A pixel area to connect the same first line segment, the number of first line segments in the first A wiring area adjacent to the A pixel area is reduced, that is, the area of ​​the non-display area of ​​the first display area is reduced, and the area of ​​the light-transmitting area of ​​the first display area is correspondingly increased. At the same time, reducing the number of first line segments in the first A wiring area is also beneficial to improving the diffraction phenomenon caused by light penetrating the first display area.

[0049] Figure 6 The local area of ​​the first display area shown in the figure includes a conventional pixel area and a conventional first routing area, wherein the number of second line segments in the conventional pixel area, i.e., the number of second line segments in the pixel area, is the same as the number of first line segments in the corresponding conventional first routing area, i.e., only the number of first line segments in some first routing areas is less. Optionally, in one embodiment, all pixel areas in the first display area may be pixel area A, and all first routing areas may be first routing area A, which is not illustrated in the figure here.

[0050] In one embodiment, n=3, that is, the A pixel area includes 3 second line segments, and the 3 second line segments in the A pixel area are electrically connected to the same first line segment in the first A routing area, then the first A routing area adjacent to the A pixel area includes 1 first line segment, that is, p=1.

[0051] Specifically, Figure 7 For example, Figure 7 This is a partial schematic diagram of another optional implementation of the first display area of ​​the display panel provided in the embodiment of the present application. Figure 7 As shown, the pixel area PQa includes three second line segments D2, that is, n=3. Figure 6The corresponding embodiments are the same, and the figure schematically illustrates a first routing line ZX in the first display area extending in the same direction as the signal line X. The three second line segments D2 in the A pixel area are electrically connected to the same first line segment D1 in the first A routing area ZQ1a, and the first A routing area ZQ1a includes one first line segment D1. In this embodiment, by setting the three second line segments in the A pixel area to connect to the same first line segment, the number of first line segments in the first A routing area adjacent to the A pixel area is reduced, which also reduces the area of ​​the non-display area of ​​the first display area and correspondingly increases the area of ​​the light-transmitting area of ​​the first display area. At the same time, reducing the number of first line segments in the first A routing area is also beneficial to improving the diffraction phenomenon caused by light penetrating the first display area.

[0052] Figure 7 The local area of ​​the first display area shown in the figure includes a conventional pixel area and a conventional first routing area, wherein the number of second line segments in the conventional pixel area, i.e., the number of second line segments in the pixel area, is the same as the number of first line segments in the corresponding conventional first routing area, i.e., only the number of first line segments in some first routing areas is less. Optionally, in one embodiment, all pixel areas in the first display area may be pixel area A, and all first routing areas may be first routing area A, which is not illustrated in the figure here.

[0053] Furthermore, the pixel region further includes connecting lines, and the connecting lines include a first connecting line; the first connecting line is located in pixel region A, and at least two second line segments in pixel region A are electrically connected to the first connecting line through vias, and the same first line segment electrically connected to the at least two second line segments is electrically connected to the first connecting line through vias. Thus, at least two second line segments in pixel region A are electrically connected to the same first line segment. You can continue to refer to the above Figure 6 or Figure 7 As shown. Figure 6 As shown, the connection line includes a first connection line L1, the first connection line L1 is located in the pixel area PQa A, and the two second line segments D2 in the pixel area PQa A are electrically connected to the first connection line L1 through vias, and the same first line segment D1 electrically connected to the two second line segments D2 is electrically connected to the first connection line L1 through vias. The vias in the figure are indicated by black solid dots. Figure 7 As shown, the connecting lines include a first connecting line L1 located in pixel region A PQa. Three second line segments D2 in pixel region A are electrically connected to the first connecting line L1 through vias. Furthermore, the same first line segment D1 electrically connected to the three second line segments D2 is electrically connected to the first connecting line L1 through vias. The vias in the figure are indicated by black solid circles. The provision of the first connecting lines electrically connects at least two second line segments in pixel region A to the same first line segment, thereby reducing the number of first line segments provided in the first routing region A adjacent to pixel region A.

[0054] In some embodiments, a pixel region includes 4 sub-pixels sp and 4 pixel circuits. Optionally, the 4 second line segments in pixel region A are electrically connected to the same first line segment in the first wiring region A, and only 1 first line segment needs to be set in the first wiring region A. Optionally, the 3 second line segments in pixel region A are electrically connected to the same first line segment in the first wiring region A, and 2 first line segments can be set in the first wiring region A. Optionally, the 2 second line segments in pixel region A are electrically connected to the same first line segment in the first wiring region A, and 2 first line segments can be set in the first wiring region A. In the above embodiment, the connection method of the second line segment in pixel region A and the first line segment in the first wiring region A adopts the same principle as above. Figure 6 or Figure 7 The same can be understood by referring to the above embodiments, which will not be described again here.

[0055] In some optional implementations, p=0, that is, no first line segment is provided in the first wiring region A adjacent to pixel region A. Still assuming that one pixel region includes three sub-pixels and three pixel circuits, that is, n=3. Figure 8 This is a partial schematic diagram of another optional implementation of the first display area of ​​the display panel provided in the embodiment of the present application. Figure 8 As shown, pixel region PQ further includes connecting lines, including a second connecting line L2. Second connecting line L2 is located in pixel region A PQa, and the three second line segments D2 in pixel region A are all electrically connected to the second connecting line L2. In this embodiment, no first line segments are provided in the first routing region A adjacent to pixel region A, which can significantly reduce the number of first line segments (i.e., signal lines) in two adjacent pixel regions.

[0056] Furthermore, in this embodiment, the first line segment is not provided in the first A wiring region adjacent to pixel A, and a voltage signal can be input to the second line segment in the A pixel region through an auxiliary signal line in the display panel, so that when displaying, the second line segment can provide a voltage signal to the pixel circuit to drive the sub-pixel to display. Figure 8As shown, the routing area also includes a plurality of second routing areas ZQ2, and a second routing area ZQ2 is located between two pixel areas PQ adjacent to each other in the first direction x; the first display area also includes a plurality of auxiliary signal lines FX extending along the first direction x, and some segments of the auxiliary signal lines FX are located in the second routing area ZQ2; in the first pixel row and the second pixel row (not marked in the figure, that is, two adjacent pixel rows), it also includes: pixel area B PQb adjacent to pixel area A PQa, and pixel area A PQa and pixel area B PQb are located in the same pixel row; second line segments D2 located in pixel area A PQa and pixel area B PQab, respectively, are electrically connected through the auxiliary signal line FX. The auxiliary signal line FX extends in a direction that intersects with the signal line X. At the intersection of the auxiliary signal line FX and the signal line X, that is, at the intersection of the auxiliary signal line FX and the second line segment D2, the auxiliary signal line FX is electrically connected to the second line segment D2. During the display panel operation, a voltage signal is transmitted to the second line segment D2 via the auxiliary signal line FX, thereby enabling normal display of the sub-pixels within pixel region A. Furthermore, the auxiliary signal line FX is connected in parallel with the signal line X, which reduces overall resistance and helps reduce power consumption.

[0057] In some optional embodiments, the multiple first routing regions between the first pixel row and the second pixel row include: a first routing region B adjacent to the first routing region A; the first pixel row and the second pixel row also include: a pixel region B adjacent to the pixel region A, the pixel region B adjacent to the first routing region B; the pixel region B includes n second line segments, and the first routing region B includes q first line segments, where q is an integer and n ≥ q > p. When q = n, the number of first line segments in the first routing region B is the same as the number of second line segments in the pixel region B, i.e., the number of first line segments in the first routing region B is not reduced. When n > q, the number of first line segments in the first routing region B is less than the number of second line segments in the pixel region B, i.e., by reducing the number of first line segments in the first routing region B, the area of ​​the non-transparent region in the first display area is further reduced, thereby correspondingly increasing the area of ​​the translucent region in the first display area. This can also further improve the diffraction phenomenon caused by light passing through the first display area.

[0058] In one embodiment, q=n; the n second line segments in the B pixel area are electrically connected to the q first line segments in the first B wiring area. Still assuming that a pixel area includes 3 sub-pixels and 3 pixel circuits, that is, n=3. Please continue to refer to the above Figure 6 Schematically, the second pixel region PQb adjacent to the first pixel region PQa includes three second line segments, and the first second wiring region ZQ1b adjacent to the second pixel region PQb includes three first line segments, that is, q=n. Figure 7As shown in the figure, the second pixel region PQb adjacent to the first pixel region PQa includes three second line segments, and the first second wiring region ZQ1b adjacent to the second pixel region PQb includes three first line segments, that is, q = n. In this embodiment, by reducing the number of first line segments in some of the first wiring regions in the first display region, the area of the non-light-transmitting region in the first display region is reduced, and correspondingly, the area of the light-transmitting region in the first display region is increased. When applied to the under-screen optical device solution, the amount of light received by the under-screen optical device can be improved. At the same time, reducing the number of first line segments can also improve the diffraction phenomenon generated when light penetrates the first display region to a certain extent.

[0059] In one embodiment, q < n; at least two second line segments in the second pixel region are electrically connected to the same first line segment in the first second wiring region. Still taking a pixel region including three sub-pixels and three pixel circuits as an example, that is, n = 3. Figure 9 This is a partial schematic diagram of another optional embodiment of the first display region of the display panel provided by the embodiment of the present application. As Figure 9 shown, the three second line segments D2 in the first pixel region PQa are electrically connected to the same first line segment D1 in the first first wiring region ZQ1a, and the first first wiring region ZQ1a includes one first line segment D1. Two second line segments D2 in the second pixel region PQb are electrically connected to the same first line segment D1 in the first second wiring region ZQ1b, and another second line segment D2 in the second pixel region PQb is electrically connected to another first line segment D1 in the first second wiring region ZQ1b, and the first second wiring region ZQ1b includes two first line segments D1. In this embodiment, the number of first line segments in the first wiring regions corresponding to two adjacent pixel regions is reduced respectively to reduce the area of the non-light-transmitting region in the first display region, thereby correspondingly increasing the area of the light-transmitting region in the first display region. At the same time, the diffraction phenomenon generated when light penetrates the first display region can be improved.

[0060] Figure 9 It is shown that the setting manner of the second line segments in the second pixel region and the first line segments in the first second wiring region is different from the setting manner of the second line segments in the first pixel region and the first line segments in the first first wiring region. Optionally, it may also be that the three second line segments D2 in the first pixel region PQa are electrically connected to the same first line segment D1 in the first first wiring region ZQ1a, and the first first wiring region ZQ1a includes one first line segment D1. At the same time, the three second line segments D2 in the second pixel region PQb are electrically connected to the same first line segment D1 in the first second wiring region ZQ1b, and the first second wiring region ZQ1b includes one first line segment D1.

[0061] Further, reference may continue to be made to the above Figure 9As shown, the pixel area also includes connecting lines, and the connecting lines include a third connecting line L3; the third connecting line L3 is located in the B pixel area PQb, and at least two second line segments D2 in the B pixel area PQb are electrically connected to the third connecting line L3 through vias, respectively, and the same first line segment D21 electrically connected to the at least two second line segments D2 is electrically connected to the third connecting line L3 through vias. In the figure, only black solid dots are used to indicate the via connection. Through the setting of the third connecting line, at least two second line segments in the B pixel area are electrically connected to the same first line segment. In the display area, it is ensured that signals can be normally provided to the second line segments, thereby ensuring that each sub-pixel in the B pixel area can be displayed normally.

[0062] Furthermore, in the above Figure 6 Based on the corresponding embodiment, auxiliary signal lines may also be provided in the first display area. Figure 10 This is a partial schematic diagram of another optional implementation of the first display area provided in the embodiment of the present application. Figure 10 As shown, the routing area also includes multiple second routing areas ZQ2, one of which is located between two adjacent pixel areas PQ in the first direction x. The first display area also includes multiple auxiliary signal lines FX extending along the first direction x, with portions of the auxiliary signal lines FX located in the second routing area ZQ2. Pixel area A PQa and pixel area B PQb are located in the same pixel row, and second segments D2 located in pixel area A PQa and pixel area B PQb, respectively, are electrically connected via the auxiliary signal line FX. The extension direction of the auxiliary signal line FX intersects with the extension direction of the signal line X. At the location where the auxiliary signal line FX overlaps with the signal line X, that is, at the location where the auxiliary signal line FX overlaps with the second segment D2, the auxiliary signal line FX is electrically connected to the second segment D2. The auxiliary signal line FX is effectively connected in parallel with the signal line X, which reduces overall resistance and helps reduce power loss.

[0063] In one embodiment, q = 1 and p = 0. That is, within the two first routing areas corresponding to two adjacent pixel areas, one first routing area is provided with a first line segment, while the other first routing area is not provided with a first line segment. Still taking the example of a pixel area including three sub-pixels and three pixel circuits, that is, n = 3. Figure 11 This is a partial schematic diagram of another optional implementation of the first display area provided in the embodiment of the present application. Figure 11As shown, the three second line segments D2 within pixel region A PQa are electrically connected via a second connection line L2, and no first connection line D1 is provided within the first wiring region A. In pixel region B adjacent to pixel region A PQa, the three second line segments D2 are electrically connected to the same first line segment D21 via a third connection line L3, and one first line segment D21 is provided within the first wiring region B. This reduces the total number of first line segments within two adjacent first wiring regions by more than 80%, significantly reducing the area of ​​the non-transparent region within the first display area and correspondingly increasing the area of ​​the transmissive region. This also effectively reduces the diffraction phenomenon caused by light penetrating the first display area.

[0064] In the display panel provided in the embodiment of the present application, the display area also includes a plurality of scan lines and a plurality of data lines; the pixel circuit also includes a pixel capacitor. The display panel includes a base substrate and a first metal layer, a capacitor metal layer, and a second metal layer located on the base substrate, the scan line is located in the first metal layer, one plate of the pixel capacitor is located in the capacitor metal layer, and the data line is located in the second metal layer. The signal line can be a positive power line or a reset signal line. For different situations, the signal line has different positions in the film layer of the panel. When setting the connecting line (i.e., the first connecting line, the second connecting line, and the third connecting line in the above embodiment), it is also necessary to set the film layer position where the connecting line is located accordingly.

[0065] In one embodiment, the signal line is a positive power line, the signal line is located in the second metal layer, and the connection line is located in the first metal layer. Figure 12 A partial schematic diagram of another optional implementation of the first display area of ​​the display panel provided in an embodiment of the present application, as shown in FIG. Figure 12 The figure shows three pixel circuits within a pixel region, using the example of three second line segments D2 within the pixel region being electrically connected via a connecting line L. Scan line S is located in the first metal layer M1, where the scan lines include gate scan lines and light control signal lines, which are not distinguished in the figure. A plate C of the pixel capacitor is located in the capacitor metal layer MC. Data line D is located in the second metal layer M2. The figure also illustrates a reset signal line Ref, which extends along a first direction x and is located in the capacitor metal layer MC. Signal line X (i.e., second line segment D2) is located in the second metal layer M2, while connecting line L is located in the first metal layer M1. Second line segment D2 is electrically connected to connecting line L via a via O1. Connecting line L electrically connects to second line segments D2 arranged in the first direction x, extending in the first direction x. By placing connecting line L in the first metal layer M1, connecting line L electrically connects at least two second line segments D2 within the pixel region while preventing a short circuit between connecting line L and data lines D extending in the second direction y.

[0066] In another embodiment, the connection line L may also be located in the capacitor metal layer MC; this can also ensure that the connection line L extending in the first direction x is not short-circuited with the data line D extending in the second direction y.

[0067] Furthermore, when the signal line is a positive power line and the signal line is located in the second metal layer, the first display area is further provided with an auxiliary signal line, and the auxiliary signal line is located in the capacitor metal layer. Figure 13 A partial schematic diagram of another optional implementation of the first display area of ​​the display panel provided in an embodiment of the present application, as shown in FIG. Figure 13 As shown, three pixel circuits in a pixel area are schematically shown. The auxiliary signal line FX is electrically connected to the signal line X through the second via O2, and the auxiliary signal line FX is located in the capacitor metal layer MC. The extension direction of the auxiliary signal line FX intersects with the extension direction of the signal line X. The capacitor metal layer MC is usually used to set a plate of the pixel capacitor and the reset signal line Ref. Setting the auxiliary signal line FX in the capacitor metal layer MC will not affect the original wiring setting in the display panel. At the same time, forming a parallel circuit structure between the auxiliary signal line FX and the signal line X is conducive to reducing resistance and thus reducing power loss. In addition, in an embodiment in which the first line segment is not set in the corresponding first A wiring area adjacent to the A pixel area, the auxiliary signal line FX can be electrically connected to the corresponding second line segment in the A pixel area, and in the display area, a voltage signal is provided to the second line segment, thereby ensuring that each sub-pixel in the A pixel area can be displayed normally.

[0068] In another embodiment, the signal line is a reset signal line, the signal line is located in the capacitor metal layer, and the connecting line is located in the second metal layer. In this embodiment, when the connecting line connects at least two second line segments in the same pixel area, it overlaps with the scan line in the pixel area. Through reasonable design, the connecting line is located in the second metal layer to avoid short circuits between the connecting line and the scan line.

[0069] In an embodiment in which the signal line is a reset signal line and the signal line is located in the capacitor metal layer, further, an auxiliary signal line can be provided in the display panel, and the auxiliary signal line is provided in the second metal layer. The auxiliary signal line is electrically connected to the signal line through a via. The extension direction of the auxiliary signal line intersects with the extension direction of the signal line, and the auxiliary signal line can form a parallel circuit structure with the signal line, which is beneficial to reduce resistance and thus reduce power consumption loss. In addition, in an embodiment in which the first line segment is not provided in the corresponding first wiring area adjacent to the pixel area A, the auxiliary signal line can be electrically connected to the corresponding second line segment in the pixel area A, and in the display area, a voltage signal is provided to the second line segment, thereby ensuring that each sub-pixel in the pixel area A can be displayed normally.

[0070] Furthermore, the first display area of ​​the display panel provided in the embodiment of the present application further includes a light shielding layer. Figure 14This is a schematic diagram of another optional implementation of the first display area of ​​the display panel provided in the embodiment of the present application, as shown in FIG. Figure 14 As described, in the direction perpendicular to the display panel, the light-shielding layer covers the wiring area (not shown in the figure), and actually includes a second wiring area between two adjacent pixel areas PQ in the first direction x, and includes a first wiring area between two adjacent pixel areas PQ in the second direction y. The figure shows that the light-shielding layer includes a first light-shielding layer SD1 covering the first wiring area and a second light-shielding layer SD2 covering the second wiring area. When applied in the under-screen optical device solution, there are gaps between the wirings in the wiring area. When light penetrates the first display area, these wiring gaps will cause the light to diffract, thereby affecting the optical performance of the optical device. The light-shielding layer provided in the embodiment of the present application can block the wiring area, thereby improving the diffraction effect of light when penetrating the first display area and improving the optical performance of the optical device. In addition, in the embodiment of the present application, the total number of first line segments set between two adjacent pixel rows is reduced, thereby reducing the area of ​​at least part of the first wiring area. When setting the shading layer, the area of ​​the shading layer can be reduced accordingly, thereby increasing the area of ​​the light-transmitting area of ​​the first display area accordingly. When applied to the under-screen optical device solution, the amount of light received by the optical device can be increased.

[0071] In one embodiment, only the first light shielding layer may be provided to shield the first wiring area. In another embodiment, only the second light shielding layer may be provided to shield the second wiring area.

[0072] The display panel provided in an embodiment of the present application includes a base substrate, an array layer on the base substrate, and a display layer on the array layer. The pixel circuit is located in the array layer. The light-shielding layer can be located on the side of the array layer away from the base substrate. Alternatively, the light-shielding layer can be located in the display layer, and the display layer includes an anode, a light-emitting layer, and a cathode. The light-shielding layer can be located in the same film layer as the anode, and the light-shielding layer can be manufactured in the same etching process as the anode during manufacturing. Alternatively, a metal film layer can be added to the display panel film layer structure to separately manufacture the light-shielding layer.

[0073] It should be noted that the display panel provided in any of the above embodiments of the present application can apply the arrangement of the light-shielding layer, which will not be described in detail here.

[0074] Based on the same inventive concept, the present application also provides a display device, Figure 15 A schematic diagram of a display device provided in an embodiment of the present application, such as Figure 15 The display device includes the display panel 100 provided in any of the above embodiments. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Figure 15The display device shown is for illustrative purposes only. The display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader, or a television.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: The display area of ​​the display panel includes a first display area and a second display area, the display area includes a plurality of sub-pixels, and the density of the plurality of sub-pixels in the first display area is smaller than the density of the plurality of sub-pixels in the second display area; The first display area includes a plurality of routing areas and a plurality of pixel rows extending along a first direction, wherein one pixel row includes a plurality of pixel areas arranged in the first direction, one pixel area includes n sub-pixels and n pixel circuits, where n is a positive integer, and the sub-pixels are electrically connected to the pixel circuits. The plurality of routing areas include a plurality of first routing areas, and one first routing area is located between two adjacent pixel areas in a second direction, and the second direction intersects the first direction. The first display area further includes a plurality of signal lines extending along the second direction. When the display panel is driven to display, a constant voltage signal is provided to the signal lines. The signal lines include a first line segment and a second line segment. The first line segment is located in the first routing area, and the second line segment is located in the pixel area. In the pixel area, the second line segment is electrically connected to the pixel circuit. The pixel rows include a first pixel row and a second adjacent pixel row, the first pixel row includes N sub-pixels, and the second pixel row includes M sub-pixels, where N and M are both positive integers and N≤M; a total number of the first line segments in the plurality of first routing areas between the first pixel row and the second pixel row is less than N; The plurality of first routing areas between the first pixel row and the second pixel row include: a first routing area A; The first pixel row and the second pixel row include: a pixel region A adjacent to the first wiring region A, the pixel region A including n second line segments; The first routing area A includes p first line segments, where p is an integer and n>p≥0; The plurality of first routing areas between the first pixel row and the second pixel row include: a first routing area B adjacent to the first routing area A; The first pixel row and the second pixel row further include: a B pixel region adjacent to the A pixel region, and the B pixel region is adjacent to the first B wiring region; The B pixel area includes n second line segments, and the first B routing area includes q first line segments, where q is an integer and n≥q>p.

2. The display panel according to claim 1, wherein: p≠0, at least two second line segments in the A pixel region are electrically connected to the same first line segment in the first A wiring region.

3. The display panel according to claim 2, wherein: The pixel area further includes a connecting line, and the connecting line includes a first connecting line; The first connecting line is located in the pixel area A, and at least two of the second line segments in the pixel area A are electrically connected to the first connecting line through vias respectively, and the same first line segment electrically connected to the at least two second line segments is electrically connected to the first connecting line through a via.

4. The display panel according to claim 1, wherein: p＝0； The pixel area further includes connecting lines, the connecting lines include a second connecting line, the second connecting line is located in the pixel area A, and the n second line segments in the pixel area A are all electrically connected to the second connecting line; The routing area further includes a plurality of second routing areas, and one of the second routing areas is located between two adjacent pixel areas in the first direction; The first display area further includes a plurality of auxiliary signal lines extending along the first direction, and some segments of the auxiliary signal lines are located in the second routing area; The first pixel row and the second pixel row further include: a pixel region B adjacent to the pixel region A, and the pixel region A and the pixel region B are located in the same pixel row; The second line segments respectively located in the pixel area A and the pixel area B are electrically connected through the auxiliary signal line.

5. The display panel according to claim 1, wherein: q = n; The n second line segments in the B pixel area are electrically connected to the q first line segments located in the first B wiring area respectively.

6. The display panel according to claim 1, wherein: q <n; At least two second line segments in the B pixel region are electrically connected to the same first line segment in the first B wiring region.

7. The display panel according to claim 6, wherein: The pixel area further includes a connecting line, and the connecting line includes a third connecting line; The third connecting line is located in the B pixel area, and at least two of the second line segments in the B pixel area are electrically connected to the third connecting line through vias respectively, and the same first line segment electrically connected to the at least two second line segments is electrically connected to the third connecting line through a via.

8. The display panel according to any one of claims 3, 4 and 7, wherein: The display area further includes a plurality of scan lines and a plurality of data lines; The pixel circuit further includes a pixel capacitor; The display panel includes a base substrate and a first metal layer, a capacitor metal layer, and a second metal layer located on the base substrate, wherein the scan line is located on the first metal layer, one plate of the pixel capacitor is located on the capacitor metal layer, and the data line is located on the second metal layer; wherein The signal line is located in the second metal layer, and the connection line is located in the first metal layer or in the capacitor metal layer; or; The signal line is located in the capacitor metal layer, and the connection line is located in the second metal layer.

9. The display panel according to claim 1, wherein: The routing area further includes a plurality of second routing areas, and one of the second routing areas is located between two adjacent pixel areas in the first direction; The first display area further includes a plurality of auxiliary signal lines extending along the first direction, and some segments of the auxiliary signal lines are located in the second routing area; The pixel region A and the pixel region B are located in the same pixel row, and the second line segments respectively located in the pixel region A and the pixel region B are electrically connected through the auxiliary signal line.

10. The display panel according to claim 4 or 9, characterized in that: The display area further includes a plurality of scan lines and a plurality of data lines; The pixel circuit further includes a pixel capacitor; The display panel includes a base substrate and a first metal layer, a capacitor metal layer, and a second metal layer located on the base substrate, wherein the scan line is located on the first metal layer, one plate of the pixel capacitor is located on the capacitor metal layer, and the data line is located on the second metal layer; wherein The signal line is located in the second metal layer, and the auxiliary signal line is located in the capacitor metal layer; or the signal line is located in the capacitor metal layer, and the auxiliary signal line is located in the second metal layer.

11. The display panel according to claim 1, wherein q=1, p=0.

12. The display panel according to claim 1, wherein The first display area further includes a light shielding layer, and in a direction perpendicular to the display panel, the light shielding layer covers the wiring area.

13. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 12.

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