Static Random Access Memory Structure

Abstract

The present invention provides a static random access memory structure, which includes a plurality of transistor units arranged in an array. Two adjacent transistor units in the same column are mirror - arranged. The first transistor unit or the second transistor in a column of the transistor units includes a first transfer transistor and a second common - gate complementary field - effect transistor arranged in sequence along a first direction, and a first common - gate complementary field - effect transistor and a second transfer transistor arranged in sequence along a second direction. The first direction and the second direction are both parallel to the direction of the column. Two adjacent first transfer transistors in the same column of the transistor units are stacked and share a common gate, and two adjacent second transfer transistors in the same column of the transistor units are stacked and share a common gate. The stacked arrangement and common - gate of the transfer transistors reduce the array area, improve the integration degree of the circuit, and reduce the manufacturing cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a static random access memory structure. Background Art

[0002] A static random access memory (SRAM) is a type of random access memory. The memory cell of a static random access memory usually consists of a pull-up transistor (PU), a pull-down transistor (PD), and a pass-gate transistor (PG). In practical applications, the SRAM occupies a relatively large circuit area, and the low integration degree will significantly increase the chip cost.

[0003] Therefore, it is necessary to provide a new static random access memory structure to solve the above problems existing in the prior art. Summary of the Invention

[0004] The purpose of the present invention is to provide a static random access memory structure, which can improve the integration degree of the circuit and reduce the manufacturing cost.

[0005] To achieve the above purpose, the static random access memory structure of the present invention includes a plurality of transistor units arranged in an array. Two adjacent transistor units in the same column are mirror-symmetrically arranged. The first transistor unit or the second transistor unit in a column of the transistor units includes a first pass-gate transistor and a second common-gate complementary field-effect transistor arranged in sequence along a first direction, and a first common-gate complementary field-effect transistor and a second pass-gate transistor arranged in sequence along a second direction. Two adjacent first pass-gate transistors in the same column of the transistor units are stacked and share a common gate, and two adjacent second pass-gate transistors in the same column of the transistor units are stacked and share a common gate. The channel direction of the first pass-gate transistor is parallel to the channel direction of the first common-gate complementary field-effect transistor, and the channel direction of the second pass-gate transistor is parallel to the channel direction of the second common-gate complementary field-effect transistor. Both the first direction and the second direction are parallel to the direction of the column.

[0006] The beneficial effect of the static random access memory structure is that two adjacent first pass-gate transistors in the same column of the transistor units are stacked and share a common gate, and two adjacent second pass-gate transistors in the same column of the transistor units are stacked and share a common gate. The stacked and common-gate arrangement of the pass-gate transistors reduces the array area, improves the integration degree of the circuit, and reduces the manufacturing cost.

[0007] Optionally, the first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked. The beneficial effects are as follows: sharing a gate reduces both the process difficulty and the occupied area, and greatly improves the integration degree.

[0008] Optionally, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on one side of the gate of the first common-gate complementary field-effect transistor, and the sources of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the other side of the gate of the first common-gate complementary field-effect transistor. The beneficial effects are as follows: facilitating the connection between the drains of the first N-type field-effect transistor and the first P-type field-effect transistor, greatly improving the circuit integration degree, and reducing the process difficulty at the same time.

[0009] Optionally, in the same transistor unit, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the side of the gate of the first common-gate complementary field-effect transistor facing the first transfer transistor. The beneficial effect is as follows: facilitating the connection between the drains of the first N-type field-effect transistor and the first P-type field-effect transistor.

[0010] Optionally, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on one side of the gate of the second common-gate complementary field-effect transistor, and the sources of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the other side of the gate of the second common-gate complementary field-effect transistor.

[0011] Optionally, in the same transistor unit, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the side of the gate of the second common-gate complementary field-effect transistor facing the second transfer transistor. The beneficial effects are as follows: facilitating the connection between the drains of the second N-type field-effect transistor and the second P-type field-effect transistor and the second transfer transistor, greatly improving the circuit integration degree, and reducing the process difficulty at the same time.

[0012] Optionally, the number of channels of the first transfer transistor, the second transfer transistor, the first N-type field-effect transistor, the second N-type field-effect transistor, the first P-type field-effect transistor, and the second P-type field-effect transistor is greater than or equal to 1. The beneficial effects are as follows: facilitating the realization of low power consumption or high speed.

[0013] Optionally, both the first transfer transistor and the second transfer transistor are field-effect transistors.

[0014] Optionally, both the first transmission tube and the second transmission tube are N-type field effect transistors or P-type field effect transistors.

[0015] Optionally, the static random access memory structure further includes a plurality of connection units, which correspond to the transistor units one by one, and the connection units are used to realize the internal connection and external connection of the transistor units.

[0016] Optionally, the connection unit includes a word line, a first bit line, a second bit line, a first interconnecting line, a second interconnecting line, a first power supply line and a second power supply line. The word line is used to control the first transmission tube and the second transmission tube. The first bit line and the second bit line are used to realize the signal transmission of the transistor unit. The first interconnecting line and the second interconnecting line are used to realize the internal connection of the transistor unit. The first power supply line and the second power supply line are used to supply power or ground the transistor unit.

[0017] Optionally, the word line, the first bit line, the second bit line, the first interconnecting line, the second interconnecting line, the first power supply line and the second power supply line are all metal interconnecting lines on the top of the device.

[0018] Optionally, the first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device. The first bit line, the second bit line and the second power supply line are located in the second metal interconnecting layer on the top of the device. The word line and the first power supply line are located in the third metal interconnecting layer on the top of the device.

[0019] Optionally, the first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device. The word line and the first power supply line are located in the second metal interconnecting layer on the top of the device. The first bit line, the second bit line and the second power supply line are located in the third metal interconnecting layer on the top of the device.

[0020] Optionally, the transistor unit is provided with a metal buried line layer perpendicular to the column direction between the first common-gate complementary field effect transistor and the first transmission tube, and the transistor unit is provided with a metal buried line layer perpendicular to the column direction between the second common-gate complementary field effect transistor and the second transmission tube.

[0021] Optionally, the first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device. The first bit line and the second bit line are located in the second metal interconnecting layer on the top of the device. The word line is located in the third metal interconnecting layer on the top of the device. The first power supply line and the second power supply line are located in the metal buried line layer.

[0022] Optionally, the first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on top of the device, the word line is located in the second metal interconnecting layer on top of the device, the first bit line and the second bit line are located in the third metal interconnecting layer on top of the device, and the first power supply line and the second power supply line are located in the metal buried line layer.

[0023] Optionally, the first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on top of the device, the first power supply line and the second power supply line are located in the second metal interconnecting layer on top of the device, the word line is located in the third metal interconnecting layer on top of the device, and the first bit line and the second bit line are located in the metal buried line layer.

[0024] Optionally, the first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on top of the device, the word line is located in the second metal interconnecting line on top of the metal, the first power supply line and the second power supply line are located in the third metal interconnecting layer on top of the device, and the first bit line and the second bit line are located in the metal buried line layer. Description of the Drawings

[0025] Figure 1 Is a front view of the static random access memory structure in some embodiments of the present invention;

[0026] Figure 2 Is a rear view of the static random access memory structure in some embodiments of the present invention;

[0027] Figure 3 Is a left view of the static random access memory structure in some embodiments of the present invention;

[0028] Figure 4 Is a right view of the static random access memory structure in some embodiments of the present invention;

[0029] Figure 5 Is a top view of the static random access memory structure in some embodiments of the present invention;

[0030] Figure 6 Is a circuit schematic diagram of the memory cell structure of the static random access memory in some embodiments of the present invention;

[0031] Figure 7 Is a structural schematic diagram of two trench field effect transistors in some embodiments of the present invention. Detailed Embodiments

[0032] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present invention pertains. As used herein, words such as "including" and the like mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items.

[0033] In view of the problems existing in the prior art, an embodiment of the present invention provides a static random access memory structure.

[0034] Figure 1 It is a front view of the static random access memory structure in some embodiments of the present invention. Figure 2 It is a rear view of the static random access memory structure in some embodiments of the present invention. Figure 3 It is a left view of the static random access memory structure in some embodiments of the present invention. Figure 4 It is a right view of the static random access memory structure in some embodiments of the present invention. Figure 5 It is a top view of the static random access memory structure in some embodiments of the present invention.

[0035] Referring to Figures 1 to 5 , the static random access memory structure includes a plurality of transistor units arranged in an array. Two adjacent transistor units in the same column are arranged in a mirror image. The first transistor unit or the second transistor in a column of the transistor units includes a first transmission tube 101 and a second common-gate complementary field-effect transistor 103 arranged in sequence along a first direction, and a first common-gate complementary field-effect transistor 102 and a second transmission tube 104 arranged in sequence along a second direction. Two adjacent first transmission tubes 101 in the same column of the transistor units are stacked and share a gate. Two adjacent second transmission tubes 104 in the same column of the transistor units are stacked and share a gate. The channel direction of the first transmission tube 101 is parallel to the channel direction of the first common-gate complementary field-effect transistor 102. The channel direction of the second transmission tube 104 is parallel to the channel direction of the second common-gate complementary field-effect transistor 103. Both the first direction and the second direction are parallel to the direction of the column.

[0036] In some embodiments, both the first transmission tube and the second transmission tube are field effect transistors. In some other embodiments, both the first transmission tube and the second transmission tube are N-type field effect transistors or P-type field effect transistors.

[0037] In some embodiments, the static random access memory structure further includes a plurality of connection units, which correspond to the transistor units one by one, and the connection units are used to realize the internal connection and external connection of the transistor units.

[0038] Referring to Figures 1 to 5 , the connection unit includes a word line 201, a first bit line 202, a second bit line 203, a first interconnecting line 204, a second interconnecting line 205, a first power supply line 206 and a second power supply line 207. The word line 201 is used to control the first transmission tube 101 and the second transmission tube 104. The first bit line 202 and the second bit line 203 are used to realize signal transmission. The first interconnecting line 204 and the second interconnecting line 205 are used to realize the internal connection of the transistor unit. The first power supply line 206 and the second power supply line 207 are used to supply power or ground the transistor unit.

[0039] Referring to Figures 1 to 5 , the first bit line 202 is connected to the first end of the first transmission tube 101, the second bit line 203 is connected to the first end of the second transmission tube 104. The word line 201 is connected to the gates of the first transmission tube 101 and the second transmission tube 104 through a metal via. The first interconnecting line 204 is connected to the second end of the first transmission tube 101, the two drains of the first common-gate complementary field effect transistor 102 and the gate of the second common-gate complementary field effect transistor 103 through a metal via. The second interconnecting line 205 is connected to the second end of the second transmission tube 104, the two drains of the second common-gate complementary field effect transistor 103 and the gate of the first common-gate complementary field effect transistor 102 through a metal via. One of the first power supply lines 206 is connected to the source of the N-type field effect transistor of the first common-gate complementary field effect transistor 102 through a metal via, and the other first power supply line 206 is connected to the source of the N-type transistor of the second common-gate complementary field effect transistor 103 through a metal via. The second power supply line 207 is connected to the sources of the P-type field effect transistors of the first common-gate complementary field effect transistor 102 and the second common-gate complementary field effect transistor 103 through a metal via.

[0040] In some embodiments, both the first transmission tube and the second transmission tube are N-type field effect transistors. In some other embodiments, both the first transmission tube and the second transmission tube are P-type field effect transistors.

[0041] In some embodiments, the first end of the first transmission tube is the drain, and the second end of the first transmission tube is the source.

[0042] In some embodiments, the first end of the first transmission tube is the source, and the second end of the first transmission tube is the drain.

[0043] In some embodiments, the first end of the second transmission tube is the drain, and the second end of the second transmission tube is the source.

[0044] In some embodiments, the first end of the second transmission tube is the source, and the second end of the second transmission tube is the drain.

[0045] In some embodiments, the word line, the first bit line, the second bit line, the first interconnecting line, the second interconnecting line, the first power supply line, and the second power supply line are all metal interconnecting lines on the top of the device.

[0046] In some embodiments, the first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device, the first bit line, the second bit line, and the second power supply line are located in the second metal interconnecting layer on the top of the device, and the word line and the first power supply line are located in the third metal interconnecting layer on the top of the device.

[0047] In some embodiments, the first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device, the word line and the first power supply line are located in the second metal interconnecting layer on the top of the device, and the first bit line, the second bit line, and the second power supply line are located in the third metal interconnecting layer on the top of the device.

[0048] In some embodiments, the transistor unit is provided with a metal buried line layer perpendicular to the column direction between the first common-gate complementary field-effect transistor and the first transmission tube, and the transistor unit is provided with a metal buried line layer perpendicular to the column direction between the second common-gate complementary field-effect transistor and the second transmission tube.

[0049] In some embodiments, the first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device, the first bit line and the second bit line are located in the second metal interconnecting layer on the top of the device, the word line is located in the third metal interconnecting layer on the top of the device, and the first power supply line and the second power supply line are located in the metal buried line layer.

[0050] In some embodiments, the first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device, the word line is located in the second metal interconnecting layer on the top of the device, the first bit line and the second bit line are located in the third metal interconnecting layer on the top of the device, and the first power supply line and the second power supply line are located in the metal buried line layer.

[0051] In some embodiments, the first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on top of the device, the first power supply line and the second power supply line are located in the second metal interconnecting layer on top of the device, the word line is located in the third metal interconnecting layer on top of the device, and the first bit line and the second bit line are located in the metal buried line layer.

[0052] In some embodiments, the first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on top of the device, the word line is located in the second metal interconnecting line on top of the metal, the first power supply line and the second power supply line are located in the third metal interconnecting layer on top of the device, and the first bit line and the second bit line are located in the metal buried line layer.

[0053] In some embodiments, the word line, the first bit line, the second bit line, the first interconnecting line, the second interconnecting line, the first power supply line, and the second power supply line are all metal interconnecting lines on top of the device.

[0054] Referring to Figures 1 to 5 , the number of the first power supply lines 206 is 2. The word line 201, the first power supply line 206, the first interconnecting line 204, and the second interconnecting line 205 are parallel to the column direction. The first bit line 202, the second bit line 203, and the second power supply line 207 are perpendicular to the column direction. Among them, the first power supply line 206 is grounded, and the second power supply line 207 is connected to the operating voltage.

[0055] Referring to Figures 1 to 5 , the first interconnecting line 204 and the second interconnecting line 205 are located in the first metal interconnecting layer on top of the device. The first bit line 202, the second bit line 203, and the second power supply line 207 are located in the second metal interconnecting layer on top of the device. The word line 201 and the first power supply line 206 are located in the third metal interconnecting layer on top of the device.

[0056] In some embodiments, the first common-gate complementary field-effect transistor includes a first N-type field-effect transistor and a first P-type field-effect transistor stacked, and the second common-gate complementary field-effect transistor includes a second N-type field-effect transistor and a second P-type field-effect transistor stacked.

[0057] In some embodiments, the first N-type field-effect transistor of the first common-gate complementary field-effect transistor is stacked above the first P-type field-effect transistor. In some other embodiments, the first P-type field-effect transistor of the first common-gate complementary field-effect transistor is stacked above the first N-type field-effect transistor.

[0058] In some embodiments, the second N-type field-effect transistor of the second common-gate complementary field-effect transistor is stacked above the second P-type field-effect transistor. In still other embodiments, the second P-type field-effect transistor of the second common-gate complementary field-effect transistor is stacked above the second N-type field-effect transistor.

[0059] In some embodiments, the first transfer transistor, the first common-gate complementary field-effect transistor, the second common-gate complementary field-effect transistor, and the second transfer transistor share the same substrate.

[0060] In some embodiments, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on one side of the gate of the first common-gate complementary field-effect transistor, and the sources of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the other side of the gate of the first common-gate complementary field-effect transistor.

[0061] In some embodiments, within the same transistor unit, the drains of the first N-type field-effect transistor and the first P-type field-effect transistor are both disposed on the side of the gate of the first common-gate complementary field-effect transistor facing the first transfer transistor.

[0062] In some embodiments, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on one side of the gate of the second common-gate complementary field-effect transistor, and the sources of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the other side of the gate of the second common-gate complementary field-effect transistor.

[0063] In some embodiments, within the same transistor unit, the drains of the second N-type field-effect transistor and the second P-type field-effect transistor are both disposed on the side of the gate of the second common-gate complementary field-effect transistor facing the second transfer transistor.

[0064] Referring to Figures 1 to 5 , the drain of the first P-type field-effect transistor 102 faces the source of the first transfer transistor 101. The drains of the first N-type field-effect transistor 1021 and the first P-type field-effect transistor 1022 are located on the same side of the gate of the first common-gate complementary field-effect transistor 102. The drain of the second P-type field-effect transistor 1032 faces the source of the second transfer transistor 104. The drains of the second N-type field-effect transistor 1031 and the second P-type field-effect transistor 1032 are located on the same side of the gate of the second common-gate complementary field-effect transistor 103.

[0065] Referring to Figures 1 to 5, a gate dielectric layer 105 is provided between the channels and gates of the first transfer tube 101, the second transfer tube 104, the first N-type field effect transistor 1021, the first P-type field effect transistor 1022, the second N-type field effect transistor 1031, and the second P-type field effect transistor 1032.

[0066] In some embodiments, the number of channels of the first transfer tube, the second transfer tube, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor, and the second P-type field effect transistor is greater than or equal to 1.

[0067] Figure 6 It is a circuit schematic diagram of the storage cell structure of the static random access memory in some embodiments of the present invention. Refer to Figure 6 , the field effect transistor PD1 is equivalent to the first N-type field effect transistor, the field effect transistor PD2 is equivalent to the second N-type field effect transistor, the field effect transistor PG1 is equivalent to the first transfer tube, the field effect transistor PG2 is equivalent to the second transfer tube, the field effect transistor PU1 is equivalent to the first P-type field effect transistor, the P-type field effect transistor PU2 is equivalent to the second P-type field effect transistor, the bit line BL is equivalent to the first bit line, and the bit line BLB is equivalent to the second bit line.

[0068] In some embodiments, the first transfer tube, the second transfer tube, the first N-type field effect transistor, the second N-type field effect transistor, the first P-type field effect transistor, and the second P-type field effect transistor can all be referred to as field effect transistors. When the number of channels of a field effect transistor is greater than or equal to 2, the sources of all channels are epitaxially grown together to form the source of the transistor, and the drains of all channels are epitaxially grown together to form the drain of the field effect transistor.

[0069] In still other embodiments, when the number of channels of a field effect transistor is greater than or equal to 2, the sub-sources of all channels are interconnected by metal to form the source of the transistor, and the sub-drains of all channels are interconnected by metal to form the drain of the field effect transistor.

[0070] Figure 7 It is a schematic structural diagram of a two-channel field effect transistor in some embodiments of the present invention. Refer to Figure 5, the field effect transistor includes two channels 301, a gate 302, a source 303, a drain 304, a gate dielectric layer 105, and a substrate (not shown in the figure). The sub-sources 3031 of the two channels are interconnected by a first metal 3032 to form the source 303 of the field effect transistor. The sub-drains 3041 of the two channels are interconnected by a second metal 3042 to form the drain 304 of the field effect transistor. The gate dielectric layer 105 is disposed between the channel 301 and the gate.

[0071] In some embodiments, the shape of the metal through-hole is not limited in any way, as long as it can achieve the connection between the source, drain, gate, word line, first bit line, second bit line, first interconnecting line, second interconnecting line, first power supply line, and second power supply line. Among them, in this application, the directions of the word line, first bit line, second bit line, first interconnecting line, second interconnecting line, first power supply line, and second power supply line all refer to the extending direction of the longest part.

[0072] Although the embodiments of the present invention have been described in detail above, it is obvious to those skilled in the art that various modifications and changes can be made to these embodiments. However, it should be understood that such modifications and changes are all within the scope and spirit of the present invention described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A static random access memory structure, characterized in that, It includes multiple transistor units distributed in an array. Two adjacent transistor units in the same column are mirror - set. The first or the second transistor in a column of the transistor units includes a first transfer transistor and a second common - gate complementary field - effect transistor arranged in sequence along a first direction, and a first common - gate complementary field - effect transistor and a second transfer transistor arranged in sequence along a second direction. Two adjacent first transfer transistors in the same column of the transistor units are stacked and share a gate. Two adjacent second transfer transistors in the same column of the transistor units are stacked and share a gate. The channel direction of the first transfer transistor is parallel to the channel direction of the first common - gate complementary field - effect transistor, and the channel direction of the second transfer transistor is parallel to the channel direction of the second common - gate complementary field - effect transistor. Both the first direction and the second direction are parallel to the direction of the column.

2. The static random access memory structure according to claim 1, characterized in that, The first common - gate complementary field - effect transistor includes a first N - type field - effect transistor and a first P - type field - effect transistor stacked. The second common - gate complementary field - effect transistor includes a second N - type field - effect transistor and a second P - type field - effect transistor stacked.

3. The static random access memory structure according to claim 2, characterized in that, The drains of the first N - type field - effect transistor and the first P - type field - effect transistor are both arranged on one side of the gate of the first common - gate complementary field - effect transistor, and the sources of the first N - type field - effect transistor and the first P - type field - effect transistor are both arranged on the other side of the gate of the first common - gate complementary field - effect transistor.

4. The static random access memory structure according to claim 3, characterized in that, In the same transistor unit, the drains of the first N - type field - effect transistor and the first P - type field - effect transistor are both arranged on the side of the gate of the first common - gate complementary field - effect transistor facing the first transfer transistor.

5. The static random access memory structure according to claim 2, characterized in that, The drains of the second N - type field - effect transistor and the second P - type field - effect transistor are both arranged on one side of the gate of the second common - gate complementary field - effect transistor, and the sources of the second N - type field - effect transistor and the second P - type field - effect transistor are both arranged on the other side of the gate of the second common - gate complementary field - effect transistor.

6. The static random access memory structure according to claim 5, characterized in that, In the same transistor unit, the drains of the second N - type field - effect transistor and the second P - type field - effect transistor are both arranged on the side of the gate of the second common - gate complementary field - effect transistor facing the second transfer transistor.

7. The static random access memory structure according to claim 2, characterized in that, The number of channels of the first transfer transistor, the second transfer transistor, the first N - type field - effect transistor, the second N - type field - effect transistor, the first P - type field - effect transistor, and the second P - type field - effect transistor is greater than or equal to 1.

8. The static random access memory structure according to claim 1, characterized in that, Both the first transfer transistor and the second transfer transistor are field - effect transistors.

9. The static random access memory structure according to claim 8, characterized in that, Both the first transfer transistor and the second transfer transistor are N - type field - effect transistors or P - type field - effect transistors.

10. The static random access memory structure according to claim 1, characterized in that, It further includes multiple connection units. The connection units correspond to the transistor units one by one. The connection units are used to realize internal connection and external connection of the transistor units.

11. The static random access memory structure according to claim 10, characterized in that, The connection unit includes a word line, a first bit line, a second bit line, a first interconnecting line, a second interconnecting line, a first power supply line, and a second power supply line. The word line is used to control the first transfer transistor and the second transfer transistor. The first bit line and the second bit line are used to implement signal transmission of the transistor unit. The first interconnecting line and the second interconnecting line are used to implement internal connection of the transistor unit. The first power supply line and the second power supply line are used to supply power or ground the transistor unit.

12. The static random access memory structure according to claim 11, characterized in that, The word line, the first bit line, the second bit line, the first interconnecting line, the second interconnecting line, the first power supply line, and the second power supply line are all metal interconnecting lines on the top of the device.

13. The static random access memory structure according to claim 12, characterized in that, The first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device. The first bit line, the second bit line, and the second power supply line are located in the second metal interconnecting layer on the top of the device. The word line and the first power supply line are located in the third metal interconnecting layer on the top of the device.

14. The static random access memory structure according to claim 12, characterized in that, The first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device. The word line and the first power supply line are located in the second metal interconnecting layer on the top of the device. The first bit line, the second bit line, and the second power supply line are located in the third metal interconnecting layer on the top of the device.

15. The static random access memory structure according to claim 11, characterized in that, The transistor unit is provided with a metal buried line layer perpendicular to the column direction between the first common-gate complementary field-effect transistor and the first transfer transistor, and the transistor unit is provided with a metal buried line layer perpendicular to the column direction between the second common-gate complementary field-effect transistor and the second transfer transistor.

16. The static random access memory structure according to claim 15, characterized in that, The first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device. The first bit line and the second bit line are located in the second metal interconnecting layer on the top of the device. The word line is located in the third metal interconnecting layer on the top of the device. The first power supply line and the second power supply line are located in the metal buried line layer.

17. The static random access memory structure according to claim 15, characterized in that, The first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device. The word line is located in the second metal interconnecting layer on the top of the device. The first bit line and the second bit line are located in the third metal interconnecting layer on the top of the device. The first power supply line and the second power supply line are located in the metal buried line layer.

18. The static random access memory structure according to claim 15, characterized in that,The first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device. The first power supply line and the second power supply line are located in the second metal interconnecting layer on the top of the device. The word line is located in the third metal interconnecting layer on the top of the device. The first bit line and the second bit line are located in the metal buried line layer.

19. The static random access memory structure according to claim 15, wherein, The first interconnecting line and the second interconnecting line are located in the first metal interconnecting layer on the top of the device. The word line is located in the second metal interconnecting line on the top of the metal. The first power supply line and the second power supply line are located in the third metal interconnecting layer on the top of the device. The first bit line and the second bit line are located in the metal buried line layer.

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