Design-aided verification for DRAM and 3D NAND devices

Abstract

The disclosed system and method for DRAM and 3D NAND inspection receive images of a wafer based on the output of an inspection tool. Geometric measurements of the design of multiple memory devices on the wafer are received. Regions of interest with higher inspection sensitivity are determined based on these geometric measurements.

Description

Technical Field

[0001] This disclosure relates to the inspection of semiconductor devices. Background Technology

[0002] The evolution of the semiconductor manufacturing industry places increasingly higher demands on yield management and, specifically, metrology and inspection systems. Critical dimensions continue to shrink, but the industry needs to reduce the time required to achieve high-yield, high-value production. Minimizing the total time from detecting a yield problem to resolving it determines the return on investment for semiconductor manufacturers.

[0003] Semiconductor devices, such as logic and memory devices, typically involve processing semiconductor wafers using numerous manufacturing processes to form the various features and multiple layers of the semiconductor device. For example, photolithography is a semiconductor manufacturing process involving transferring a pattern from a photomask to a photoresist disposed on a semiconductor wafer. Additional examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices can be fabricated in an arrangement on a single semiconductor wafer, or the semiconductor devices can be separated into individual semiconductor devices.

[0004] Inspection processes are used at various stages of semiconductor manufacturing to detect defects on wafers, leading to higher yields and therefore higher profits. Inspection has always been a crucial part of manufacturing semiconductor devices such as integrated circuits (ICs). However, as semiconductor device sizes shrink, inspection becomes even more critical for the successful manufacture of acceptable semiconductor devices because even small defects can cause device malfunctions. For example, as semiconductor device sizes decrease, the detection of smaller defects becomes necessary because even relatively small defects can introduce unwanted aberrations into the semiconductor device.

[0005] However, as design rules shrink, semiconductor manufacturing processes can operate closer to the performance limits of the process. Furthermore, with shrinking design rules, even smaller defects can affect the electrical parameters of the device, driving more sensitive inspection. As design rules shrink, the population of potential yield-related defects detected by inspection increases dramatically, as does the population of nuisance defects detected by inspection. Therefore, more defects can be detected on the wafer, and correcting the process to eliminate all defects can be difficult and expensive. Determining which defects actually affect the device's electrical parameters and yield allows process control methods to focus on those defects while largely ignoring others. Moreover, under smaller design rules, process-induced failures tend to be systematic in some cases. That is, process-induced failures tend to occur at predetermined design patterns that are typically repeated many times within the design. The elimination of spatial system defects and electrically related defects can affect yield. Due to the nature of the device process, the noise characteristics of where defects reside and / or the probability of defect occurrence vary depending on the geometric distance from a particular design pattern. For example, the boundaries of DRAM or 3D NAND cell regions tend to be much noisier than the inner cell regions, and the defect density tends to be much higher in these regions. Therefore, new strategies are needed for defect detection related to geometric location.

[0006] Memory devices, such as Dynamic Random Access Memory (DRAM) and 3D NAND devices, can be particularly difficult to inspect. Memory devices may lack several alignment targets present in the logic devices. There is also no simple way to determine what the design is from an image of the memory device. For example, it may be difficult to locate the center of a structure or certain edges of a structure. Previously, inspection was performed across all structures with the same sensitivity. Performing legacy array inspection on DRAM can be difficult because semiconductor manufacturers may not share design documents for DRAM devices. Furthermore, logic areas around the array are often saturated due to light scarcity in the array area. This can lead to poor pixel design alignment (PDA). Using this technique, there may be no distinction between defects of interest (DOI) and scrambling points.

[0007] Figure 1 illustrates an exemplary DRAM memory block containing lines and spatial patterns. The goal is to separate defects outside the trimmed area (i.e., the thick dashed line shown in the lower right corner of Figure 1). Each cell can have a micrometer-scale size 300. The binning size 301 can range from tens of nanometers to hundreds of nanometers or micrometers. The goal can be to separate defects located at the cell edges (on both the x and y sides) from defects located on the cell body.

[0008] Figure 2 illustrates an exemplary DRAM memory block including contact holes or plugs. Each cell may have a micrometer-scale size 300. And the image size 301 may range from tens of nanometers to hundreds of nanometers or be in the micrometer scale. An objective may be to separate the two contacts at the edge from the center. Another objective may be to separate defects located at the cell edge (on both the x and y sides) from defects located on the cell body.

[0009] Legacy array inspection is also performed on 3D NAND, but it cannot identify which contact rows the defects originate from. Due to the large size of 3D NAND cells, certain inspection techniques may not be available for 3D NAND cell inspection. Image-based inspection may not be able to handle process variations across wafers with 3D NAND cells. DOIs can be separated at build time because DOIs from different contact rows can be mixed together when the classifier is applied across the entire wafer.

[0010] Figure 3 illustrates an exemplary 3D NAND block containing contact holes or plugs. The goal can be to separate the two contacts at the edge from the central area, and this can be done in different ways for each row. Another goal can be to separate defects located on the contact points of the edge rows from those located on the contact points of the inner rows. The periphery can provide good patterning but at a different height than the cells. Therefore, the periphery cannot be used for PDAs. The dimensions of cells 1 and 2 in Figure 3 can be on the scale of several thousand micrometers in the X and Y directions.

[0011] Therefore, there is a need for improved methods and systems for testing memory devices. Summary of the Invention

[0012] In a first embodiment, a system is provided. The system includes an inspection tool and a processor in electronic communication with the inspection tool. The inspection tool includes: an energy source configured to generate energy directed to a wafer; and a detector configured to detect the energy from the wafer and generate an output in response to the detected energy. The processor is configured to: receive an image of the wafer based on the output; receive geometric measurements of a design of a plurality of memory devices on the wafer; and determine a region of interest with higher inspection sensitivity based on the geometric measurements.

[0013] In this example, each of the memory devices is a 3D NAND cell. The geometric measurement may be one or more of the following: the distance between contact rows, the distance between trenches, or the location of a dummy region. The processor may be configured to apply the region of interest to the contact rows of the memory device.

[0014] In this example, each of the memory devices is a DRAM cell. The geometric measurement may be one or more of the cell profile distances from the center of the periphery. The region of interest may be applied to trimmed areas or areas with critical defects. The processor may be configured to apply the region of interest to the memory device. The processor may also be further configured to: expand the job size in the X direction to cover at least two array cells; determine sub-scan bands that cover paging and identify cell boundaries; and determine the patterning alignment distortion and position of the cell boundaries relative to another sub-scan band that does not intersect with the periphery.

[0015] In a second embodiment, a method is provided. The method includes: inspecting a wafer using an inspection tool; receiving an image of the wafer from the inspection tool at a processor; receiving geometric measurements of a design of a plurality of memory devices on the wafer at the processor; and using the processor to determine a region of interest with higher inspection sensitivity based on the geometric measurements.

[0016] In this example, each of the memory devices is a 3D NAND cell. The geometric measurement may be one or more of the distance between contact rows, the distance between trenches, or the location of a dummy region. The method may further include using the processor to apply the region of interest to the contact rows of the memory device.

[0017] In the example, each of the memory devices is a DRAM cell. The geometric measurement may be one or more of the cell profile distances from the center of the periphery. The region of interest may be applied to a trimmed area or an area with critical defects. The method may further include applying the region of interest to the memory device using the processor. The method may further include: using the processor to expand the working scale in the X direction to cover at least two array cells; using the processor to determine a sub-scan band covering the paging and identifying cell boundaries; and using the processor to determine the patterning alignment distortion and position of the cell boundaries relative to another sub-scan band that does not have a periphery intersection. Attached Figure Description

[0018] For a more complete understanding of the nature and purpose of this disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0019] Figure 1 illustrates an exemplary DRAM memory block;

[0020] Figure 2 illustrates an exemplary DRAM memory block;

[0021] Figure 3 shows an exemplary 3D NAND block;

[0022] Figure 4This is a flowchart illustrating an embodiment of the method according to the present disclosure;

[0023] Figure 5 This describes an embodiment of a DRAM device tested according to the present disclosure;

[0024] Figure 6 These are embodiments of the system according to this disclosure;

[0025] Figure 7 Explain the different contact lines assigned to different areas; and

[0026] Figure 8 This indicates the calculated page break center. Detailed Implementation

[0027] Although the claimed subject matter will be described with reference to specific embodiments, other embodiments (including those not providing all the advantages and features set forth herein) are also within the scope of this disclosure. Various structural, logical, process, and electronic changes may be made without departing from the scope of this disclosure. Therefore, the scope of this disclosure is defined only with reference to the appended claims.

[0028] The embodiments disclosed herein provide improved sensitivity for the inspection of memory devices, such as DRAM and 3D NAND structures. Using the design-aided inspection disclosed herein, different thresholds can be applied to different structures. The improved sensitivity for DRAM can utilize limited design information from the semiconductor manufacturer. For 3D NAND, design information can be used to separate different contact rows with better sensitivity.

[0029] Figure 4 This is a flowchart of an embodiment of method 100. At 101, the wafer is inspected using an inspection tool. At 102, an image of the wafer is received at the processor. The image may include apparatus, such as those shown in Figures 1 to 3 or... Figure 5 The apparatus described herein. At 103, geometric measurements of the design of the memory device on the wafer are received at the processor. At 104, the processor uses the geometric measurements to determine the region of interest with higher inspection sensitivity.

[0030] In the example, each of the memory devices in method 100 is a 3D NAND cell. Geometric measurements may be one or more of the following: distance between contact rows, distance between trenches, or location of dummy regions, or other information. The location of the dummy regions may be relative to the trenches. These geometric measurements may be based on device or wafer design data.

[0031] In instances using 3D NAND, the cell spacing in the Y direction can be determined based on design information. Optical images can be used to determine the location and periodicity of grooves (i.e., the blank areas between two cell blocks), for example, by using image intensity or image grayscale variations along the X direction at each point in the Y direction. The cell spacing in the Y direction based on the design information should match the periodicity extracted from the optical image.

[0032] A processor can be used to apply the region of interest to the contact rows of a memory device. Therefore, cell spacing can be determined from the design in the Y direction, and periodicity can be determined from the image in the Y direction. The region of interest can be positioned based, for example, where a trench is located.

[0033] This embodiment of a 3D NAND cell utilizes design information when available. During setup, one or more geometric measurements of one or more 3D NAND cells can be provided. Using the design information for inspection, a process-invariant algorithm identifies which contact row a defect originates from and applies different sensitivities to different contact rows. Therefore, sub-regions can be inspected. By identifying, for example, trenches, dummy areas, and the location of each contact row, and by organizing the sensitivity regions into sub-regions, better sensitivity for 3D NAND cell inspection can be achieved. Better sensitivity and more relevant 3D NAND inspection can lead to improved yield.

[0034] Figure 7 This describes an implementation example of assigning different contact rows to different zones. Contact rows can be assigned based on geometric measurement data.

[0035] In this example, each element in the memory device is a DRAM cell. The geometric measurement can be one or more of the cell profile distances from the center of the periphery. A processor can be used to apply a region of interest to the memory device.

[0036] This embodiment of the DRAM cell utilizes design information when it is available. During setup, information about the cell outline distance to the center can be provided for one or more cell regions. This information can be determined based on the design information. Using the design information, the work scale is expanded in the X direction to cover more than two array cells. Sub-scan bands covering pages can be located. Pages are spaces in the middle of cell blocks. Cell boundaries can be identified in real-time (on-the-fly). PDA distortion and location of cell boundaries can be propagated in real-time to sub-scan bands that do not have peripheral intersections. In this example, "real-time" means during runtime or during the inspection process. Trimming areas and / or areas of interest (AOI) for critical defects can be placed. Trimming areas and / or AOIs can be assigned higher sensitivity. A processor can be used to perform these functions.

[0037] In this example, the center position of the DRAM cell block is determined from the frame image. Next, the offset between the paging center from the design and the calculated paging center from the image can be determined. This offset can be applied to a runtime content background mask, providing clarity for the areas of interest (AOI) and cell edges.

[0038] In the example, the center of the cross-street on the DRAM structure can be used to identify the four corners of the four different unit blocks forming the cross-street. This is in Figure 8 This is shown in the image. This information can be used to anchor the region of interest at the edge of a cell. Different sensitivities can be applied to the region of interest relative to the rest of the image.

[0039] This technique for DRAM cells can still be used even with incomplete or limited design information. Cell block size can be used to replace or supplement design data. Improved sensitivity in DRAM cell inspection is achieved by identifying the outline of cell regions under lighting conditions with poor PDA quality, even without detailed design information. This improved sensitivity leads to more relevant DRAM inspections for yield improvement.

[0040] When applying a region of interest to a DRAM memory device, the working scale can be expanded in the X direction to cover at least two array cells. In this example, the region of interest can be applied to trimmed areas and / or areas with critical defects.

[0041] Figure 5 This describes an embodiment of DRAM device inspection. Cell outline distance information to the center of the periphery is provided for each cell region. For inspection, the working scale is expanded in the X direction to cover more than two array cells. This... Figure 5 The sub-scan band 0 is indicated by a shaded rectangle, with one of the shaded rectangles outlined by a dashed line. Sub-scan bands covering the page are located, and cell boundaries are identified in real time. For example, sub-scan band 3 (one of which is outlined by a dashed line) covers the page. PDA distortion and position of cell boundaries are propagated in real time to sub-scan bands that do not have peripheral intersections. Trimming areas (one of which is outlined by a dashed line in sub-scan band 1) can be placed and assigned higher sensitivity.

[0042] Figure 6 This is an embodiment of system 200, which can be a testing tool. System 200 includes an optically based subsystem 201. Generally, the optically based subsystem 201 is configured to generate an optically based output for sample 202 by directing light to sample 202 (or scanning light over sample 202) and detecting the light from sample 202. In one embodiment, sample 202 includes a wafer. The wafer may include any wafer known in the art.

[0043] exist Figure 6 In the embodiment of system 200 shown, the optical-based subsystem 201 includes an illumination subsystem configured to direct light to sample 202. The illumination subsystem includes at least one energy source capable of directing energy to sample 202. For example, such as... Figure 6 As shown, the illumination subsystem includes a light source 203. In one embodiment, the illumination subsystem is configured to direct light to the sample 202 at one or more incident angles, said incident angles may include one or more tilt angles and / or one or more normal angles. For example, as... Figure 6 As shown, light from light source 203 is guided at an angle of incidence through optical element 204 and then lens 205 to sample 202. The angle of incidence can include any suitable angle of incidence, which can vary depending on, for example, the characteristics of sample 202.

[0044] The optical-based subsystem 201 can be configured to guide light to the sample 202 at different incident angles at different times. For example, the optical-based subsystem 201 can be configured to modify one or more characteristics of one or more elements of the illumination subsystem, such that the light can be directed at different angles than... Figure 6 The incident angle shown in the figure is guided to the sample 202. In one example, the optical subsystem 201 can be configured to move the light source 203, optical element 204 and lens 205 so that light is guided to the sample 202 at different tilting incident angles or normal (or near-normal) incident angles.

[0045] In some examples, the optical-based subsystem 201 can be configured to direct light to the sample 202 at more than one incident angle at the same time. For example, the illumination subsystem may include more than one illumination channel, one of which may include, for example, Figure 6 The light source 203, optical element 204, and lens 205 shown herein, and another element in the illumination channel (not shown), may contain similar elements (which may be configured differently or in the same manner) or may contain at least a light source and possibly one or more other components (such as those further described herein). If this light is directed to the sample at the same time as other light, then one or more characteristics (e.g., wavelength, polarization, etc.) of the light directed to the sample 202 at different incident angles may be different, such that the source can be distinguished from each other at (several) detectors from the light illuminating the sample 202 at different incident angles.

[0046] In another example, the lighting subsystem may contain only one light source (e.g., Figure 6The light source 203 shown in the diagram can be split into different optical paths (e.g., based on wavelength, polarization, etc.) by one or more optical elements (not shown) of the illumination subsystem. The light from each of these different optical paths can then be directed to the sample 202. Multiple illumination channels can be configured to direct light to the sample 202 at the same time or at different times (e.g., when using different illumination channels to sequentially illuminate the sample). In another example, the same illumination channel can be configured to direct light with different characteristics to the sample 202 at different times. For example, in some examples, optical element 204 can be configured as a spectral filter, and the properties of the spectral filter can be changed in various ways (e.g., by changing the spectral filter) so that light of different wavelengths can be directed to the sample 202 at different times. The illumination subsystem can have any other suitable configuration known in the art for sequentially or simultaneously directing light with different or the same characteristics to the sample 202 at different or the same incident angles.

[0047] In one embodiment, light source 203 may comprise a broadband plasma (BBP) source. In this way, the light generated by light source 203 and directed to sample 202 may comprise broadband light. However, the light source may comprise any other suitable light source, such as a laser. The laser may comprise any suitable laser known in the art and may be configured to generate light at any or more suitable wavelengths known in the art. Additionally, the laser may be configured to generate monochromatic or near-monochromatic light. In this way, the laser may be a narrowband laser. Light source 203 may also comprise a multicolor source that generates light at multiple discrete wavelengths or bands.

[0048] Light from optical element 204 can be focused onto sample 202 by lens 205. Although lens 205 is... Figure 6 While shown as a single refractive optical element, it should be understood that, in practice, lens 205 may comprise a combination of refractive and / or reflective optical elements that focus light from the optical element onto the sample. Figure 6 The illumination subsystem shown and described herein may include any other suitable optical elements (not shown). Examples of such optical elements include, but are not limited to, several polarizing components, several spectral filters, several spatial filters, several reflective optics, several apodizers, several beam splitters (e.g., beam splitter 213), several apertures, and the like, which may include any such suitable optical elements known in the art. Additionally, the optical-based subsystem 201 may be configured to modify one or more of the elements of the illumination subsystem based on the type of illumination to be used to generate the optical-based output.

[0049] The optical-based subsystem 201 may also include a scanning subsystem configured to cause light to scan over the sample 202. For example, the optical-based subsystem 201 may include a stage 206 on which the sample 202 is positioned during optical-based output generation. The scanning subsystem may include any suitable mechanical and / or robotic assembly (which includes the stage 206) that can be configured to move the sample 202 such that light can scan over the sample 202. Alternatively or additionally, the optical-based subsystem 201 may be configured such that one or more optical elements of the optical-based subsystem 201 perform some scanning of light over the sample 202. The light may scan over the sample 202 in any suitable manner (e.g., in a serpentine or helical path).

[0050] The optical-based subsystem 201 further includes one or more detection channels. At least one of the detection channels includes a detector configured to detect light originating from the sample 202 attributable to illumination of the sample 202 by the subsystem, and to generate an output in response to the detected light. For example, Figure 6 The optical-based subsystem 201 shown includes two detection channels: one channel is formed by a light collector 207, an element 208, and a detector 209, and the other channel is formed by a light collector 210, an element 211, and a detector 212. Figure 6 As shown, two detection channels are configured to collect and detect light at different collection angles. In some examples, the two detection channels are configured to detect scattered light, and the detection channel is configured to detect light scattered from sample 202 at different angles. However, one or more of the detection channels may be configured to detect another type of light from sample 202 (e.g., reflected light). Detector 209 may generate an output in response to the detected energy.

[0051] like Figure 6 The diagram further illustrates that two detection channels are positioned in the plane of the paper, and the illumination subsystem is also positioned in the plane of the paper. Therefore, in this embodiment, the two detection channels are positioned (e.g., centered) in the plane of incidence. However, one or more of the detection channels may be positioned outside the plane of incidence. For example, the detection channel formed by the light collector 210, element 211, and detector 212 may be configured to collect and detect light scattered from the plane of incidence. Therefore, this detection channel may generally be referred to as a "side" channel, and this side channel may be centered in a plane substantially perpendicular to the plane of incidence.

[0052] although Figure 6An embodiment of an optically based subsystem 201 comprising two detection channels is shown, but the optically based subsystem 201 may comprise several different detection channels (e.g., only one detection channel or two or more detection channels). In one example, the detection channel formed by the light collector 210, element 211, and detector 212 may form a side channel as described above, and the optically based subsystem 201 may comprise an additional detection channel (not shown) formed as another side channel positioned on the opposite side of the incident plane. Thus, the optically based subsystem 201 may comprise a detection channel comprising a light collector 207, element 208, and detector 209 and centered in the incident plane, and configured to collect and detect light at (a number of) scattering angles normal to or near normal to the surface of sample 202. Therefore, this detection channel may generally be referred to as the “top” channel, and the optically based subsystem 201 may also comprise two or more side channels configured as described above. Therefore, the optical-based subsystem 201 may include at least three channels (i.e., a top channel and two side channels), and each of the at least three channels has its own light collector, each of the light collectors being configured to collect light at a different scattering angle than each of the other light collectors.

[0053] As further described above, each of the detection channels contained in the optical-based subsystem 201 can be configured to detect scattered light. Therefore, Figure 6 The optical-based subsystem 201 shown herein can be configured for generating dark-field (DF) output from sample 202. However, the optical-based subsystem 201 may also, or alternatively, include several detection channels configured for generating bright-field (BF) output from sample 202. In other words, the optical-based subsystem 201 may include at least one detection channel configured to detect light reflected from the specular surface of sample 202. Therefore, the optical-based subsystem 201 described herein can be configured for DF-only imaging, BF-only imaging, or both DF and BF imaging. Although each of the light collectors is... Figure 6 While shown as a single refractive optical element, it should be understood that each of the light collectors may contain one or more refractive optical blanks and / or one or more reflective optical elements.

[0054] One or more detection channels may contain any suitable detector known in the art. For example, the detector may include a photomultiplier tube (PMT), a charge-coupled device (CCD), a time-delay integration (TDI) camera, and any other suitable detector known in the art. The detector may also include a non-imaging detector or an imaging detector. In this way, if the detector is a non-imaging detector, each of the detectors may be configured to detect specific characteristics (e.g., intensity) of the scattered light, but may not be configured to detect such characteristics that vary depending on the position within the imaging plane. Thus, the output generated by each of the detectors in each of the detection channels contained in the optical-based subsystem may be a signal or data rather than an image signal or image data. In such examples, a processor (e.g., processor 214) may be configured to generate an image of sample 202 from the non-imaging output of the detector. However, in other examples, the detector may be configured as an imaging detector configured to generate an imaging signal or image data. Therefore, the optical-based subsystem may be configured to generate optical images or other optical-based outputs as described herein in several ways.

[0055] It should be noted that the information provided in this article... Figure 6 This document generally describes the configuration of an optically based subsystem 201 that may be included in or used by the system embodiments described herein to generate optically based output. As is typically done when designing commercial output acquisition systems, the configuration of the optically based subsystem 201 described herein may be modified to optimize its performance. Additionally, the systems described herein can be implemented using existing systems (e.g., by adding the functionality described herein to an existing system). For some such systems, the methods described herein may be provided as optional functionality of the system (e.g., in addition to other system functionalities). Alternatively, the systems described herein may be designed as entirely new systems.

[0056] Processor 214 may be coupled to components of system 200 in any suitable manner (e.g., via one or more transmission media, which may include wired and / or wireless transmission media) so that processor 214 can receive output. Processor 214 may be configured to perform certain functions using the output. System 200 may receive instructions or other information from processor 214. Processor 214 and / or electronic data storage unit 215 may, as appropriate, communicate electronically with wafer inspection tools, wafer metrology tools, or wafer re-inspection tools (not described) to receive additional information or send instructions. For example, processor 214 and / or electronic data storage unit 215 may communicate electronically with SEM.

[0057] The processor 214, (a number of) other systems, or (a number of) other subsystems described herein may be part of a variety of systems, including personal computer systems, graphics computers, mainframe computer systems, workstations, network appliances, Internet appliances, or other devices. The (a number of) subsystems or (a number of) systems may also include any suitable processor known in the art, such as a parallel processor. Additionally, the (a number of) subsystems or (a number of) systems may include a platform with high-speed processing and software as either a standalone tool or a networked tool.

[0058] The processor 214 and electronic data storage unit 215 may be housed in or otherwise become part of the system 200 or another device. In examples, the processor 214 and electronic data storage unit 215 may be part of a separate control unit or in a centralized quality control unit. Multiple processors 214 or electronic data storage units 215 may be used.

[0059] In practice, processor 214 can be implemented by any combination of hardware, software, and firmware. Similarly, its functions as described herein can be performed by a single unit or divided among different components, each of which can then be implemented by any combination of hardware, software, and firmware. The program code or instructions for processor 214 to implement various methods and functions can be stored in a readable storage medium (e.g., memory in electronic data storage unit 215 or other memory).

[0060] If system 200 includes more than one processor 214, then different subsystems can be coupled to each other, enabling the transmission of images, data, information, instructions, etc., between the subsystems. For example, a subsystem can be coupled to (several) additional subsystems via any suitable transmission medium, which can include any suitable wired and / or wireless transmission medium known in this art. Two or more of such subsystems can also be effectively coupled via a shared computer-readable storage medium (not shown).

[0061] Processor 214 may be configured to perform certain functions using the output of system 200 or other outputs. For example, processor 214 may be configured to send output to electronic data storage unit 215 or another storage medium. Processor 214 may be further configured as described herein.

[0062] Processor 214 may be configured according to any of the embodiments described herein. Processor 214 may also be configured to perform other functions or additional steps using the output of system 200 or using images or data from other sources.

[0063] The various steps, functions, and / or operations of system 200, as well as the methods disclosed herein, are implemented by one or more of the following: electronic circuits, logic gates, multiplexers, programmable logic devices, ASICs, analog or digital controllers / switches, microcontrollers, or computing systems. Program instructions for implementing the methods (such as those described herein) may be transmitted via or stored on a carrier medium. The carrier medium may include storage media, such as read-only memory, random access memory, magnetic disks or optical disks, non-volatile memory, solid-state memory, magnetic tape, and the like. The carrier medium may include transmission media, such as wires, cables, or wireless transmission links. For example, the various steps described throughout this disclosure may be implemented by a single processor 214 or alternatively by multiple processors 214. Furthermore, different subsystems of system 200 may comprise one or more computing or logic systems. Therefore, the foregoing description should not be construed as a limitation of this disclosure but is merely illustrative.

[0064] In this example, processor 214 communicates with system 200. Processor 214 is configured to: receive an image of the output wafer; receive geometric measurements of the design of a plurality of memory devices on the wafer; and determine a region of interest with higher inspection sensitivity based on the geometric measurements. Each of the memory devices may be a 3D NAND cell or a DRAM cell. For a 3D NAND cell, the geometric measurement is one or more of the distance between contact rows, the distance between trenches, or the location of a dummy region. Processor 214 is configured to apply the region of interest to the contact rows of the memory device. For a DRAM cell, the geometric measurement is one or more of the cell profile distance from the center of the periphery. Processor 214 is configured to apply the region of interest to the memory device. Processor 214 may be further configured to: expand the working scale in the X direction to cover at least two array cells; determine a sub-scan band that covers the paging and identifies cell boundaries; and determine PDA distortion and location of cell boundaries for another sub-scan band that does not have periphery intersections. The region of interest may be applied to trimmed areas or areas with critical defects. Other operations described herein may also be performed.

[0065] Additional embodiments relate to a non-transitory computer-readable medium storing program instructions executable on a controller for performing computer-implemented methods of verification as disclosed herein. Specifically, as... Figure 6 As shown herein, electronic data storage unit 215 or other storage media may contain a non-transitory computer-readable medium containing program instructions executable on processor 214. The computer-implemented method may include any steps of any of the methods(s) described herein (including method 100).

[0066] Program instructions can be implemented in any way possible, including programmatic, component-based, and / or object-oriented technologies. For example, ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (MFC), Streaming SIMD Extensions (SSE), or other technologies or methods may be used as needed to implement program instructions.

[0067] Although disclosed as having optical inspection tools, the embodiments disclosed herein can also be used in conjunction with electron beam inspection tools. Therefore, the energy source can generate an electron beam rather than a light beam.

[0068] Although disclosed as having 3D NAND and DRAM devices, other memory devices or other semiconductor structures may also benefit from the embodiments disclosed herein.

[0069] The X and Y directions can be reversed as described in the examples in this article.

[0070] Although this disclosure has been described with reference to one or more specific embodiments, it will be understood that other embodiments of this disclosure may be made without departing from the scope of this disclosure. Therefore, this disclosure is to be considered limited only by the appended claims and their reasonable interpretation.

Claims

1. A system for inspecting a semiconductor device, comprising: Inspection tools, which include: An energy source configured to generate energy directed to the chip; and A detector configured to detect energy from the wafer and generate an output in response to the detected energy; and A processor that communicates electronically with the inspection tool, wherein the processor is configured to: The image of the chip is received based on the output; Receive geometric measurements of a design for a plurality of memory devices on the wafer, wherein the geometric measurements of the design are provided in the design data of the devices on the wafer, and wherein each of the memory devices is a DRAM cell; and Based on the geometric measurements, a region of interest with higher testing sensitivity is determined; Apply the region of interest to the memory device; Expand the working scale in the X direction to cover at least two array cells; Determine the sub-scan bands that cover the pagination and identify cell boundaries; and For another sub-scanning band that does not have an outer intersection, the pattern design alignment distortion and position of the unit boundary are determined.

2. The system of claim 1, wherein the geometric measurement is one or more of the unit profile distances from the center of the periphery.

3. The system of claim 1, wherein the region of interest is applied to the trimming region.

4. The system of claim 1, wherein the region of interest is applied to a region with a critical defect.

5. A method for inspecting a semiconductor device, comprising: Use inspection tools to inspect the wafers; The processor receives an image of the wafer from the inspection tool. The processor receives geometric measurements of a design for a plurality of memory devices on the wafer, wherein the geometric measurements of the design are provided in the design data of the devices on the wafer, and wherein each of the memory devices is a DRAM cell; and The processor is used to determine the region of interest with higher inspection sensitivity based on the geometric measurements; The processor is used to apply the region of interest to the memory device; The processor is used to expand the working scale in the X direction to cover at least two array cells; The processor is used to determine sub-scan bands that cover pagination and identify cell boundaries; and The processor is used to determine the pattern design alignment distortion and position of the cell boundary for another sub-scan band that does not have a peripheral intersection.

6. The method of claim 5, wherein the geometric measurement is one or more of the unit profile distances from the center of the periphery.

7. The method according to claim 5, wherein the region of interest is applied to the trimming region.

8. The method of claim 5, wherein the region of interest is applied to a region having a critical defect.

9. A system for inspecting a semiconductor device, comprising: Inspection tools, which include: An energy source configured to generate energy directed to the chip; and A detector configured to detect energy from the wafer and generate an output in response to the detected energy; and A processor that communicates electronically with the inspection tool, wherein the processor is configured to: The image of the chip is received based on the output; Receive geometric measurements of the design of a plurality of memory devices on the wafer, each of which is a 3D NAND cell; Determine the location of the trenches on the wafer; and Based on the geometric measurements and the location of the trench, a region of interest with higher inspection sensitivity is determined.

10. The system of claim 9, wherein the geometric measurement is one or more of the distance between contact rows, the distance between grooves, or the location of a dummy area.

11. The system of claim 9, wherein the processor is further configured to apply the region of interest to the contact row of the memory device.

12. The system of claim 9, wherein the processor is further configured to determine the periodicity of the trench.

13. The system of claim 12, wherein the processor is configured to compare the periodicity with the cell spacing of the design.

14. The system of claim 9, wherein the location of the trench is determined using image intensity.

15. The system of claim 9, wherein the location of the groove is determined using image grayscale variation.

16. A method for inspecting a semiconductor device, comprising: Use inspection tools to inspect the wafers; The processor receives an image of the wafer from the inspection tool. The processor receives geometric measurements of the design of a plurality of memory devices on the wafer, each of which is a 3D NAND cell. and The processor is used to determine the region of interest with higher inspection sensitivity based on the geometric measurements.

17. The method of claim 16, wherein the geometric measurement is one or more of the distance between contact rows, the distance between grooves, or the location of a dummy area.

18. The method of claim 16, further comprising using the processor to apply the region of interest to a contact row of the memory device.

19. The method of claim 17, further comprising using the processor to determine the periodicity of the trench.

20. The method of claim 19, further comprising using the processor to compare the periodicity with the cell spacing of the design.

21. The method of claim 17, wherein the location of the trench is determined using image intensity.

22. The method of claim 17, wherein the location of the groove is determined using image grayscale variation.

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