Chip ID generation device and method

Abstract

The present invention provides a chip ID generation device and method, wherein the ID generation device includes: N chip pin connection terminals, which are configured to be connected to chip pins; a chip ID generation circuit, which is configured to generate a chip ID according to different connection methods between the N chip pin terminals and chip input signals, wherein N is a natural number greater than or equal to 2.

Description

Technical Field

[0001] The present invention relates to chip ID generation, and in particular to a device and method for generating chip IDs and distinguishing chips according to a connection mode of chip pins. Background Art

[0002] As the complexity of various applications continues to increase, the number of chips used in a system continues to increase. A handheld system (such as a mobile phone) can contain dozens to hundreds of chips. Most chips operate under the control of a controller according to system instructions. To enable independent control of these chips, they must have different ID address values. This allows them to be placed simultaneously on the same system communication bus. In some applications, multiple identical chips must be used on the same communication bus, requiring separate control. In these cases, the IDs of these two or more chips must also be different to achieve independent control. To achieve this, the chip design typically uses an additional pin, commonly called a user ID pin. By connecting this pin to ground, high, or floating, the chip's internal decoding circuitry generates a unique ID to distinguish between the chips. Figure 1 This is a schematic diagram showing the pin connection method of the RF switch chip. Figure 1 , wherein the SP4T switch chip of the radio frequency switch chip is used as an example for illustration. However, those skilled in the art should understand that this example is only used for illustration and does not limit the scope of the present invention. Figure 1 In the communication bus, there are two identical RF switch chips. Figure 1 The different connection methods of the UserID pins of the RF switch chip enable the distinction between the two chips.

[0003] However, as the size of various electronic products is getting smaller and smaller, the number of pins of the chips used is also getting smaller and smaller. Figure 1 The SP4T switch chip shown in is taken as an example. Its package pins are as follows Figure 2 shown.

[0004] Figure 2 This is a schematic diagram showing the pin distribution of the RF switch chip. Figure 2 As shown in the chip pin diagram, all 9 pins have been set. If a new UserID pin is required, the chip size needs to be increased.

[0005] Therefore, it is necessary to provide a method and apparatus for distinguishing different ID addresses of a chip while maintaining the package size and the number of package pins. Summary of the Invention

[0006] One aspect of the present invention provides a chip ID generation device, comprising: N chip pin connection terminals, which are configured to be connected to chip pins; a chip ID generation circuit, which is configured to generate a chip ID according to different connection methods between the N chip pin terminals and chip input signals, wherein N is a natural number greater than or equal to 2.

[0007] One aspect of the present invention provides a chip ID generating device, wherein the chip pin connection terminal includes a power signal connection terminal and a clock signal connection terminal.

[0008] One aspect of the present invention provides a chip ID generation device, wherein the chip ID generation circuit is further configured to provide a power signal to an internal circuit of the chip.

[0009] An aspect of the present invention provides a chip ID generation device, wherein the chip ID generation circuit further includes a power-on reset signal generation circuit, and the power-on reset signal generation circuit is configured to provide a power-on reset signal.

[0010] An aspect of the present invention provides a chip ID generating device, wherein the chip ID generating circuit is configured to generate a chip ID according to a power signal, a clock signal, and a power-on reset signal.

[0011] One aspect of the present invention provides a chip ID generation device, wherein the chip ID generation circuit further includes a first comparator and a first latch, wherein the first comparator is configured to compare an input power supply signal and a clock signal and provide an output signal to the first latch, and the first latch is configured to receive the output signal from the comparator and cache it according to a power-on reset signal to generate a chip ID value.

[0012] One aspect of the present invention provides a chip ID generation device, wherein the chip ID generation circuit further includes a first switch and a second switch, wherein the first switch and the second switch are turned on and off according to the output of the first latch to provide a power signal to the internal circuit of the chip.

[0013] One aspect of the present invention provides a chip ID generation device, wherein the chip ID generation circuit further includes a third switch and a fourth switch and a first resistor and a second resistor, wherein the third switch and the first resistor are connected in series and are connected between the chip pin connection terminal and the ground node; and the fourth switch and the second resistor are connected in series and are connected between the chip pin connection terminal and the ground node, and the third switch and the fourth switch are turned on and off according to the power-on reset signal.

[0014] One aspect of the present invention provides a chip ID generation device, wherein the chip ID generation circuit further includes a second comparator, a second latch, a first counter, a second counter and a judgment circuit, wherein the second comparator is configured to compare the input power signal and clock signal and provide the output signal to the second latch, the first counter and the second counter are respectively connected to the power signal connection terminal and the clock signal connection terminal, and count the flips of the power signal and the clock signal, the judgment circuit judges whether the count in the first counter or the count in the second counter reaches a threshold, and outputs a control signal based on the judgment result, the second latch is configured to receive the output signal from the comparator, and output the latch output signal based on the control signal output by the judgment circuit to generate a chip ID value.

[0015] One aspect of the present invention provides a chip ID generation device, wherein the chip ID generation circuit further includes a first switch and a second switch, wherein the first switch and the second switch are turned on and off according to the output of the second latch to provide a power signal to the internal circuit of the chip.

[0016] One aspect of the present invention provides a method for generating a chip ID, comprising: receiving different chip input signals by connecting N chip pin connection terminals to chip pins, and generating a chip ID according to different connection methods between the N chip pin terminals and the chip input signals, wherein N is a natural number greater than or equal to 2.

[0017] Beneficial effects

[0018] According to various aspects of the present invention, a device and method for distinguishing different ID addresses of a chip while maintaining the package size and the number of package pins are realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram showing the pin connection method of the RF switch chip;

[0020] Figure 2 is a schematic diagram showing the pin distribution of the RF switch chip;

[0021] Figure 3 is a schematic diagram of distinguishing different chips by different pin connection methods according to an embodiment of the present invention;

[0022] Figure 4 is a signal waveform diagram showing a chip ID generating circuit according to an embodiment of the present invention;

[0023] Figure 5 is a schematic diagram showing a chip ID generating circuit according to an embodiment of the present invention; and

[0024] Figure 6 FIG. 1 is a schematic diagram showing a chip ID generation circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Before proceeding with the detailed description below, it may be helpful to set forth the definitions of certain words and phrases used throughout this patent document. The terms "couple," "connect," and their derivatives refer to any direct or indirect communication or connection between two or more elements, regardless of whether those elements are in physical contact with each other. The terms "transmit," "receive," and "communicate," and their derivatives, encompass both direct and indirect communication. The terms "include," "comprise," and their derivatives, mean including, but not limited to. The term "or" is inclusive, meaning and / or. The phrase "associated with..." and its derivatives mean including, included within, interconnected, containing, contained within, connected or connected with, coupled or coupled with, communicate with, cooperate with, intertwine, juxtapose, approach, bound or bound with, have, have an attribute of, have a relationship with, or have a relationship with, etc. The term "driver" refers to any device, system, or portion thereof that controls at least one operation. Such a driver may be implemented using hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular driver may be centralized or distributed, whether local or remote. The phrase "at least one of," when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one of the items in the list may be needed. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.

[0026] Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior and future uses of such defined words and phrases.

[0027] In this patent document, the application combination of modules and the division of sub-modules are for illustration only. Without departing from the scope of the present disclosure, the application combination of modules and the division of sub-modules may have different forms.

[0028] Figure 3 This is a schematic diagram of different chips distinguished by different pin connection methods according to an embodiment of the present invention.

[0029] According to an embodiment of the present invention, different chips are distinguished by using different connection modes between two pins of the chip and the system. Figure 3In the embodiment shown in FIG, an example of using two pins is shown, but those skilled in the art should understand that other number of pins can be used without departing from the scope of the present invention. Figure 3 In the example, the power supply (VIO) pin and the clock (SCLK) pin are used as examples to illustrate the present invention, but those skilled in the art should also understand that other pins can be used to implement the present invention without departing from the scope of the present invention. Figure 3 According to the different connection methods of the power (VIO) pin and the clock (SCLK) pin with the system, the different connection methods are judged by the circuit inside the chip, and different ID values are set accordingly, so as to distinguish different chips.

[0030] refer to Figure 3 , the pin1 and pin2 pins of the chip can be used as both the power pin and the clock pin of the chip. When the pin1 pin of one of the chips is connected to the system power VIO and the pin2 pin is connected to the system clock CLK, the circuit inside the chip can detect this connection and automatically set the ID value of the chip to the first value (for example, Figure 3 When the pin1 of another chip is connected to the system clock CLK and the pin2 is connected to the system power VIO, the circuit inside the chip can detect this connection and automatically set the ID value of the chip to the second value (for example, Figure 3 The first and second values are different. According to the above operation, the chip generates different ID values for communicating with the bus, so that the system can distinguish them as two different chips and then communicate and control them separately.

[0031] Figure 4 FIG. 1 is a signal waveform diagram showing a chip ID generation circuit according to an embodiment of the present invention.

[0032] The waveforms of the chip's power supply VIO and clock CLK are as follows: Figure 4 As shown in the figure. In an actual system, when the power supply voltage is applied to the chip, the VIO voltage rises from 0V to the VIO rated voltage at a certain rate. During the VIO voltage rise process, the system is not yet ready to start communicating with and controlling each chip. Therefore, CLK will not toggle during this period. For different systems, the clock CLK may be in different states. For example, in some systems, the clock CLK may be in Figure 4In the A state, the voltage of the clock CLK is approximately equal to the voltage of the power supply VIO, that is, the clock CLK rises with the rise of the power supply VIO. However, because the clock CLK signal is generated from the circuit powered by the power supply VIO, the driving capability of the clock CLK is smaller than the power supply VIO signal. In addition, in many other cases, when the power supply VIO rises, the clock CLK signal is in the "0" state, that is, Figure 4 The B state in the MCU. According to embodiments of the present invention, this characteristic is used to determine which signal is the power supply VIO signal and which signal is the clock CLK signal. Furthermore, the power-on reset (POR) signal is an internal chip logic reset signal generated during the power supply VIO rising process. When the power supply VIO signal voltage reaches a threshold voltage, a reset signal is generated to initialize the device.

[0033] Figure 5 FIG. 1 is a schematic diagram showing a chip ID generation circuit according to an embodiment of the present invention.

[0034] refer to Figure 5 , pin1 and pin2 are connected to node n1 via switches k1 and k2, respectively; in addition, node n1 is also connected to the chip internal circuit 503 and the POR generation circuit 504. Pin2 is connected to the ground node via resistor R1 and switch k3, and pin1 is connected to the ground node via resistor R2 and switch k4. The + input of comparator 501 is connected to pin2 and the - input of comparator 501 is connected to pin1, and its output is connected to node n2. Latch 502 is connected between node n2 and node n3 and receives a control signal from node n5. An inverter is connected between nodes n3 and n4 to provide an inverted signal. In addition, node n3 is connected to the control terminal of switch k2 to control the on and off of switch k2; node n4 is connected to the control terminal of switch k1 to control the on and off of switch k1. The node n5 is connected to the control terminals of the switches k3 and k4 to control the on and off of the switches k3 and k4 . In addition, the node n5 is also connected to the latch 502 to provide a control signal to the latch 502 .

[0035] refer to Figure 5 If pin1 is connected to the system power supply VIO and pin2 is connected to the system clock CLK, then when the system is powered on (the power supply VIO signal rises), Figure 5 The POR signal output of the circuit is "high" (reference Figure 4 ); so that switches k3 and k4 are turned on. In this case, pin1 and pin2 are connected to the ground node through resistors R1 and R2 (for example, R1=R2). If the initial system clock CLK is Figure 4As shown in the "B" state, that is, "0V", the comparator 501 can immediately determine that the voltage of pin1 is higher than that of pin2, and the node n2 outputs a low level; if the initial state system clock CLK is Figure 4 As shown in Figure 5, the system is in state "A," meaning that the clock CLK follows the power supply VIO. Because resistors R1 and R2 make the system clock CLK line's drive capability smaller than the power supply VIO, the voltage at pin 1 is greater than the voltage at pin 2, causing comparator 501 to detect a low output at node n2. Latch 502 is designed to be controlled by the POR output signal n5. When n5 transitions from high to low, the state of node n2 is latched in the latch, resulting in the latch output being n3. Therefore, the latch's configuration ensures that when n5 is high, n3 = n2. Furthermore, because nodes n3 and n4 control switches k1 and k2, switch k1 is turned on and switch k2 is turned off. The voltage at node n1, which connects to the chip's internal circuitry, will equal the voltage at pin 1, i.e., the system power supply VIO. When the POR completes, the reset signal transitions from high to low, meaning that node n5 is zero. At this time, switches k3 and k4 are disconnected, preventing leakage during normal operation of the chip. In addition, when the POR signal output is completed, that is, when node n5 changes from a high level to a low level, the chip has already determined which of pins 1 and 2 is the power supply VIO or the clock CLK.

[0036] Also refer to Figure 5 If pin2 is connected to the system power supply VIO and pin1 is connected to the system clock CLK, then when the system is powered on (the power supply VIO signal rises), Figure 5 The POR signal output of the circuit is "high" (reference Figure 4 ); so that switches k3 and k4 are turned on. In this case, pin1 and pin2 are connected to the ground node through resistors R1 and R2 (for example, R1=R2). If the initial system clock CLK is Figure 4 As shown in the "B" state, that is, "0V", the comparator 501 can immediately determine that the voltage of pin2 is higher than that of pin1, and the node n2 outputs a high level; if the initial state system clock CLK is Figure 4As shown in Figure 5, the system is in state "A," meaning that the clock CLK follows the power supply VIO. Because resistors R1 and R2 make the system clock CLK line's drive capability smaller than the power supply VIO, the voltage at pin 2 is greater than the voltage at pin 1, allowing comparator 501 to determine that node n2 outputs a high level. Latch 502 is designed to be controlled by the POR output signal n5. When n5 transitions from high to low, the state of node n2 is latched in the latch, resulting in the latch output being n3. Therefore, the latch's configuration ensures that when n5 is high, n3 = n2. Furthermore, because nodes n3 and n4 control switches k1 and k2, switch k2 is turned on and switch k1 is turned off. The voltage at node n1, which connects to the chip's internal circuitry, will equal the voltage at pin 2, i.e., the system power supply VIO. When the POR completes, the reset signal transitions from high to low, meaning that node n5 is at 0. At this time, switches k3 and k4 are disconnected, preventing leakage during normal operation of the chip. In addition, when the POR signal output is completed, that is, when node n5 changes from a high level to a low level, the chip has already determined which of pins 1 and 2 is the power supply VIO or the clock CLK.

[0037] As described above, the circuit structure enables determination of the pin types of pins 1 and 2. Furthermore, by using node n3 as an output signal, which outputs different values when determining the pin types of pins 1 and 2, a signal representing the chip ID value is generated. When pin 1 is connected to system power supply VIO, a first signal is output; and when pin 1 is connected to system clock CL, a second signal, different from the first signal, is output.

[0038] Figure 6 FIG. 1 is a schematic diagram showing a chip ID generation circuit according to an embodiment of the present invention.

[0039] refer to Figure 6Pin 1 and pin 2 are connected to node n1 via switches k1 and k2, respectively. Node n1 is also connected to internal chip circuit 603 and POR generation circuit 604. Pin 1 is also connected to the negative input of counter 1 and comparator 601, respectively, while pin 2 is also connected to the positive input of counter 2 and comparator 601, respectively. The output of comparator 601 is connected to node n2. Latch 602 is connected between nodes n2 and n3 and receives a control signal from node n6. An inverter is connected between nodes n3 and n4 to provide an inverted signal. Node n3 is connected to the control terminal of switch k2 to control its on / off switching, while node n4 is connected to the control terminal of switch k1 to control its on / off switching. The outputs of counters 1 and 2 are connected to judgment circuit 605, and the output of judgment circuit 605 is connected to node n6 to output a signal for controlling latch 602.

[0040] refer to Figure 6 If pin 1 is connected to the system power supply VIO and pin 2 is connected to the system clock CLK, assuming that the clock CLK is static (state B) before the system begins communication and control, comparator 601 will control switches k1 and k2 so that the voltage at node n1 is the same as that at pin 1, thereby powering the internal circuits of the chip. When the clock CLK follows the power supply VIO signal, although comparator 601 may output an erroneous comparison result, since the clock CLK follows the power supply VIO signal, the voltage at node n1 can still power the internal circuits of the chip. When the system begins communication, the system clock CLK will begin to toggle, causing counters 1 and 2 connected to pins 1 and 2 to begin counting. Determination circuit 605 is designed to determine whether the counts in counters 1 and 2 have reached a threshold. When either Counter 1 or Counter 2 has not yet reached its threshold, a signal is output at node n6, causing the latch's output n3 to equal the level of comparator 601's output n2. Furthermore, when either Counter 1 or Counter 2 reaches its threshold, a signal is output at node n6, turning off the switch connected to the pin of the counter that reached the threshold and turning on the switch connected to the other pin. Because Counter 2, connected to the system clock CLK pin, will be full first in this scenario, the determination circuit 605 outputs the voltage at node n6 to control latch 602 to latch a low level (n3 = 0), turning off switch k2 and turning on switch k1. The chip's internal circuitry is connected to pin 1 (i.e., system power supply VIO) via node n1. Simultaneously, the voltage at node n3 is used to set the chip ID value.

[0041] Similarly refer to Figure 6 In this case, when pin 2 is connected to the system power supply VIO and pin 1 is connected to the system clock CLK, the counter's determination circuit 605 causes node n6 to control latch 602 to latch a high level (n3 = 1). This turns k2 on and k1 off, and the internal circuit is connected to pin 2 (i.e., system power supply VIO) via node n1. Simultaneously, the voltage at node n3 is used to set the chip ID value. In this case, node n3 outputs a different voltage than in the previous case.

[0042] Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.

[0043] Any description in the present invention should not be construed as implying that any particular element, step, or function is essential to be included in the scope of the claims. The scope of the patented subject matter is defined solely by the claims.

Claims

1. A chip ID generating device, comprising: N chip pin connection terminals, configured to be connected to chip pins; A chip ID generation circuit is configured to generate a chip ID according to different connection modes between the N chip pin connection terminals and the chip input signals. Where N is a natural number greater than or equal to 2, Wherein, the chip input signal includes a power signal and a clock signal, The chip ID generation circuit further includes a power-on reset signal generation circuit, wherein the power-on reset signal generation circuit is configured to provide a power-on reset signal. The chip ID generation circuit is configured to generate a chip ID according to a power signal, a clock signal and a power-on reset signal. The chip ID generation circuit further includes a first comparator and a first latch. The first comparator is configured to compare an input power signal and a clock signal and provide an output signal to the first latch, and The first latch is configured to receive an output signal from the comparator and cache it according to a power-on reset signal to generate a chip ID value.

2. The chip ID generating device according to claim 1, wherein: The chip ID generation circuit is further configured to provide a power supply signal to the internal circuit of the chip.

3. The chip ID generating device according to claim 1, wherein: The chip ID generation circuit further includes a first switch and a second switch. The first switch and the second switch are turned on and off according to the output of the first latch to provide a power signal to the internal circuit of the chip.

4. The chip ID generating device according to claim 1, wherein: The chip ID generation circuit further includes a third switch, a fourth switch, a first resistor, and a second resistor. The third switch and the first resistor are connected in series and are connected between the chip pin connection terminal and the ground node; and the fourth switch and the second resistor are connected in series and are connected between the chip pin connection terminal and the ground node. The third switch and the fourth switch are turned on and off according to the power-on reset signal.

5. A chip ID generating device, comprising: N chip pin connection terminals, configured to be connected to chip pins; A chip ID generation circuit is configured to generate a chip ID according to different connection modes between the N chip pin connection terminals and the chip input signals. Where N is a natural number greater than or equal to 2, Wherein, the chip input signal includes a power signal and a clock signal, The chip ID generation circuit further includes a power-on reset signal generation circuit, wherein the power-on reset signal generation circuit is configured to provide a power-on reset signal. The chip ID generation circuit is configured to generate a chip ID according to a power signal, a clock signal and a power-on reset signal. The chip ID generation circuit further includes a second comparator, a second latch, a first counter, a second counter and a judgment circuit. The second comparator is configured to compare the input power signal and the clock signal, and provide the output signal to the second latch, The first counter and the second counter are connected to the power signal connection terminal and the clock signal connection terminal, respectively, and count the flips of the power signal and the clock signal. The judgment circuit judges whether the count in the first counter or the count in the second counter reaches a threshold, and outputs a control signal according to the judgment result. The second latch is configured to receive an output signal from the comparator and output a latch output signal according to a control signal output by the judgment circuit to generate a chip ID value.

6. The chip ID generating device according to claim 5, wherein: The chip ID generation circuit further includes a first switch and a second switch. The first switch and the second switch are turned on and off according to the output of the second latch to provide a power signal to the internal circuit of the chip.

7. A method for generating a chip ID, comprising: Receive different chip input signals by connecting N chip pin connection terminals to chip pins. The chip ID generation circuit generates the chip ID according to the different connection modes of N chip pin connection terminals and chip input signals. Where N is a natural number greater than or equal to 2, Wherein, the chip input signal includes a power signal and a clock signal, The chip ID generation circuit further includes a power-on reset signal generation circuit, wherein the power-on reset signal generation circuit is configured to provide a power-on reset signal. The chip ID generation circuit is configured to generate a chip ID according to a power signal, a clock signal and a power-on reset signal. The chip ID generation circuit includes a first comparator and a first latch, the first comparator is configured to compare the input power signal and clock signal and provide the output signal to the first latch, and the first latch is configured to receive the output signal from the comparator and cache it according to the power-on reset signal to generate a chip ID value.

8. A method for generating a chip ID, comprising: Receive different chip input signals by connecting N chip pin connection terminals to chip pins. The chip ID generation circuit generates the chip ID according to the different connection modes of N chip pin connection terminals and chip input signals. Where N is a natural number greater than or equal to 2, Wherein, the chip input signal includes a power signal and a clock signal, The chip ID generation circuit further includes a power-on reset signal generation circuit, wherein the power-on reset signal generation circuit is configured to provide a power-on reset signal. The chip ID generation circuit is configured to generate a chip ID according to a power signal, a clock signal and a power-on reset signal. Among them, the chip ID generation circuit also includes a second comparator, a second latch, a first counter, a second counter and a judgment circuit. The second comparator is configured to compare the input power signal and clock signal, and provide the output signal to the second latch. The first counter and the second counter are respectively connected to the power signal connection terminal and the clock signal connection terminal, and count the flips of the power signal and the clock signal. The judgment circuit judges whether the count in the first counter or the count in the second counter reaches a threshold, and outputs a control signal according to the judgment result. The second latch is configured to receive the output signal from the comparator, and output the latch output signal according to the control signal output by the judgment circuit to generate a chip ID value.

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