Etching method for control gate contacts of memory cell area in flash memory devices

Abstract

This invention discloses an etching method for the control gate contacts of a flash memory device's memory cell area, comprising the following steps: Step 1, partial etching using a low selectivity gas; Step 2, adjusting the etching time for the oxide regions above the word line and above the polysilicon layer of the control gate to balance the retention of oxides in both regions; Step 3, using the oxide above the polysilicon layer of the control gate as a hard mask to completely etch away the polysilicon of the word line, forming a groove; Step 4, further increasing the selectivity of polysilicon to oxide, reducing the etching rate, and removing any remaining polysilicon residue from Step 3. This invention increases the gap between floating gates, significantly expanding the photolithography process window.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an etching method for the control gate contacts of a flash memory device's memory cell area. Background Technology

[0002] As the size of the memory cell area in flash memory devices continues to shrink, the two layers FLGT (floating gate lithography layer) and CGCT (control gate via lithography layer) face challenges in achieving small size.

[0003] In the original CGCT tip bending scheme, the space between floating gates in the tip region of the floating gate lithography layer was smaller than that in the memory cell region, significantly reducing the lithography process window and making the process less stable. Furthermore, due to the reduced CGCT lithography area and the presence of steps during photoresist coating, photoresist was prone to floating, leading to lithography failure. Additionally, the close proximity of the contacts and word lines (WL) easily caused electrical bridging. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, the present invention provides an etching method for the control gate contacts of the memory cell area of ​​a flash memory device.

[0005] This invention solves the above-mentioned technical problems through the following technical solution: an etching method for control gate contacts in a flash memory device's memory cell area, characterized by comprising the following steps:

[0006] Step 1: Partial etching is performed using a low selectivity gas;

[0007] Step 2: For the two regions of oxide above the word line and above the polysilicon layer of the control gate, the etching time should be adjusted to find a balance between the retention of oxides in both regions.

[0008] Step 3: Using the oxide above the polysilicon layer of the control gate as a hard mask, completely etch away the polysilicon of the word line to form a groove.

[0009] Step four: Further selectivity of polysilicon to oxide, reduce etching rate, and remove any polysilicon residue that may remain from step three.

[0010] Preferably, in step one, the oxide layer, silicon nitride layer, and polysilicon layer on the top of the whole are etched downwards to a certain depth.

[0011] Preferably, the thickness of the oxide above the polysilicon layer of the control gate is 50-100 angstroms.

[0012] Preferably, step three involves etching a gas with a high selectivity for oxides using polycrystalline silicon.

[0013] Preferably, the etching in step one requires an etching method with a selection ratio of oxide, silicon nitride, and polysilicon of 1:1:1.

[0014] Preferably, a control gate via photolithography layer is formed before step one.

[0015] Preferably, an additional photomask is added to the control gate via photolithography layer to etch away all the word lines where the control gate contacts need to be connected.

[0016] The significant advantages of this invention are as follows: The photomask at the end of the memory cell alters the floating gate (FG) lithography pattern, eliminating the need for bending at the end, as it is entirely a straight line. This increases the gap between the floating gates and greatly expands the lithography process window. To etch out the control gate (CG) and connect it to the contacts, an additional photomask is added to the CGCT layer, etching away all the word lines where the CG contacts need to be connected, leaving only a certain length of CG for the contact connection. Attached Figure Description

[0017] Figure 1 This is a flowchart of the etching method for the control gate contacts of the flash memory device storage cell area according to the present invention. Detailed Implementation

[0018] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0019] like Figure 1 As shown, the etching method for the control gate contacts of the flash memory device storage cell area of ​​the present invention includes the following steps:

[0020] Step 1: Partial etching is performed using a low selectivity gas to etch the top oxide layer, silicon nitride layer, and polysilicon layer (OX / SIN / POLY) to a certain depth. It is essential to ensure that the oxide portion above the word line disappears (loss), while simultaneously controlling the oxide height above the CGPL (control gate polysilicon layer). This etching requires a 1:1:1 selectivity ratio for oxide, silicon nitride, and polysilicon, and a uniform etching process is necessary, simultaneously etching all three layers (oxide, silicon nitride, and polysilicon).

[0021] Step 2: For the two oxide regions above the wordline and above the CGPL, the etching time should be adjusted to balance the oxide remain in both regions. At this point, the wordline polysilicon is fully exposed, while a certain thickness (50-100 angstroms) of oxide remains above the CGPL.

[0022] Step 3: Using the oxide above the CGPL as a hard mask, completely etch away the polysilicon word line to form a groove. Here, polysilicon is used for etching with a higher selectivity gas than oxide. Polysilicon has a faster etching rate than oxide, minimizing oxide loss above the CGPL. Simultaneously, polymer deposition needs to be carefully controlled to ensure the groove sidewalls have appropriate linewidth.

[0023] Step four involves further selecting the polysilicon-oxide ratio to reduce the etch rate, remove any polysilicon residue that may have remained from step three, and ensure the stability of the etching process window.

[0024] Before step one, a CGCT (control gate via photolithography layer) is formed to facilitate subsequent use.

[0025] The end photomask of the memory cell alters the floating gate (FG) lithography pattern, eliminating the need for bending at the end; instead, it's all a straight line, increasing the gap between the floating gates and significantly expanding the lithography process window. To etch out the control gate (CG) and connect it to the contacts, an additional photomask is added to the CGCT layer. All word lines where the CG contacts need to be connected are etched away, leaving only a certain length of CG for the contact connection.

[0026] The above-described specific embodiments are preferred embodiments of the present invention and are not intended to limit the present invention. Any other changes or equivalent substitutions made without departing from the technical solution of the present invention are included within the protection scope of the present invention.

Claims

1. A method for etching control gate contacts in a flash memory device's memory cell area, characterized in that, It includes the following steps: Step 1: Form a control gate via photolithography layer. Add a photomask to the control gate via photolithography layer to etch away all the word lines where the control gate contacts need to be connected. Step two: Partial etching is performed using a low selectivity gas. Step 3: For the two regions of oxide above the word line and above the polysilicon layer of the control gate, the etching time should be adjusted to find a balance between the retention of oxides in both regions. Step 4: Using the oxide above the polysilicon layer of the control gate as a hard mask, completely etch away the polysilicon of the word line to form a groove. Step 5: Further selectivity of polysilicon to oxide, reduce etching rate, and remove any polysilicon residue that may remain from Step 3.

2. The etching method for the control gate contacts of the memory cell area of ​​a flash memory device as described in claim 1, characterized in that, Step one involves etching the oxide layer, silicon nitride layer, and polysilicon layer at the top of the entire structure downwards to a certain depth.

3. The etching method for the control gate contacts of the memory cell area of ​​a flash memory device as described in claim 1, characterized in that, The thickness of the oxide layer above the polysilicon layer of the control gate is 50-100 angstroms.

4. The etching method for the control gate contacts of the memory cell area of ​​a flash memory device as described in claim 1, characterized in that, Step three involves etching a gas with a high selectivity for oxides using polycrystalline silicon.

5. The etching method for the control gate contacts of the memory cell area of ​​a flash memory device as described in claim 1, characterized in that, The etching in step one requires designing an etching method with a selection ratio of oxide, silicon nitride, and polysilicon of 1:1:1.

Images