Display Panel and Display Device

Abstract

An embodiment of the present invention provides a display panel and a display device, relating to the field of display technologies, for improving the potential stability of nodes in a pixel circuit. The display panel includes a substrate and a plurality of pixel circuits located on the substrate. The pixel circuit includes: a driving transistor, which is connected to a connection trace; a light-transmissive conductive portion, which includes a light-transmissive conductive material and at least partially overlaps with a connection segment in a direction perpendicular to the plane where the substrate is located.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device.

Background Art

[0002] Organic Light-Emitting Diode (OLED) has the advantages of low power consumption, low cost, self-luminescence, wide viewing angle, and fast response speed, and has become a research hotspot in the current display field.

[0003] To achieve screen display, a display panel includes a pixel circuit and a light-emitting element. The pixel circuit is electrically connected to the light-emitting element to drive the light-emitting element to emit light. In the existing pixel circuit, the coupling effect between different nodes is relatively large, and the stability of the node potential is relatively low, which further has an adverse effect on the light-emitting brightness of the light-emitting element.

Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a display panel and a display device to improve the potential stability of nodes in the pixel circuit.

[0005] On the one hand, an embodiment of the present invention provides a display panel, including a substrate and a plurality of pixel circuits located on the substrate. The pixel circuit includes:

[0006] A driving transistor, which is connected to a connection trace;

[0007] A light-transmitting conductive part, which includes a light-transmitting conductive material. In the direction perpendicular to the plane of the substrate, the light-transmitting conductive part at least partially overlaps with the connection line segment.

[0008] On the other hand, an embodiment of the present invention provides a display device, including the above-mentioned display panel.

[0009] One of the above technical solutions has the following beneficial effects:

[0010] In the embodiment of the present invention, by adding a light-transmitting conductive part overlapping with the connection trace, on the one hand, a parasitic capacitance is formed between the light-transmitting conductive part and the connection trace, and this parasitic capacitance can be used to stabilize the potential of the connection trace, thereby weakening the coupling effect between the connection trace and the gate of the driving transistor and weakening the influence of the potential change on the connection trace on the gate potential of the driving transistor. In this way, the stability of the gate potential of the driving transistor can be improved, and further the reliability of the working state of the pixel circuit can be improved, making the driving current flowing into the light-emitting element tend to a standard value.

[0011] On the other hand, when a conductive portion for forming a parasitic capacitance with a connection trace is provided, if the conductive portion is formed of a metal material, the light transmittance of the display panel will be affected after the conductive portion overlaps with the connection trace. Especially for a display panel with a fingerprint recognition function or a camera function, the light transmittance decreases, and both the amount of light reflected by a finger to the sensor and the amount of external ambient light incident on the camera decrease, thereby resulting in low fingerprint recognition accuracy and poor imaging quality. In the embodiment of the present invention, by forming a light-transmissive conductive portion with a light-transmissive conductive material, even if the light-transmissive conductive portion overlaps with the connection trace, the light transmittance of the display panel will not be affected, thereby optimizing the fingerprint recognition accuracy or imaging quality of the display panel.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0013] Figure 1 A circuit structure diagram of a pixel circuit provided by an embodiment of the present invention;

[0014] Figure 2 A film layer structure diagram of a pixel circuit provided by an embodiment of the present invention;

[0015] Figure 3 is Figure 1 A corresponding signal timing diagram;

[0016] Figure 4 A structure diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 5 Another film layer structure diagram of a pixel circuit provided by an embodiment of the present invention;

[0018] Figure 6 is Figure 5 A partial enlarged view of;

[0019] Figure 7 is Figure 6 A cross-sectional view along the A1-A2 direction;

[0020] Figure 8 A structure diagram of a second light-transmissive portion provided by an embodiment of the present invention;

[0021] Figure 9 Another film layer structure diagram of a pixel circuit provided by an embodiment of the present invention;

[0022] Figure 10 is Figure 9 a partial enlarged schematic view;

[0023] Figure 11 is a schematic diagram of another film layer structure of the pixel circuit provided by an embodiment of the present invention;

[0024] Figure 12 is Figure 11 a partial enlarged schematic view;

[0025] Figure 13 is Figure 12 a cross-sectional view along the B1-B2 direction;

[0026] Figure 14 is a schematic diagram of a film layer structure of the storage capacitor provided by an embodiment of the present invention;

[0027] Figure 15 is a schematic diagram of another film layer structure of the storage capacitor provided by an embodiment of the present invention;

[0028] Figure 16 is Figure 15 a cross-sectional view along the C1-C2 direction;

[0029] Figure 17 is a schematic diagram of another film layer structure of the storage capacitor provided by an embodiment of the present invention;

[0030] Figure 18 is Figure 17 a cross-sectional view along the D1-D2 direction;

[0031] Figure 19 is a schematic diagram of yet another film layer structure of the storage capacitor provided by an embodiment of the present invention;

[0032] Figure 20 is Figure 19 a cross-sectional view along the E1-E2 direction;

[0033] Figure 21 is a schematic diagram of a structure of a display device provided by an embodiment of the present invention.

Detailed Implementation Manner

[0034] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts fall within the scope of protection of the present invention.

[0036] The terms used in the embodiments of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The singular forms "a", "the", and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise.

[0037] It should be understood that the term "and / or" used herein is merely a description of the associated relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: the situation where A exists alone, the situation where A and B exist simultaneously, and the situation where B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0038] As described in the background art, the display panel includes a pixel circuit and a light-emitting element that are electrically connected. The pixel circuit is used to transmit a driving current to the light-emitting element to drive the light-emitting element to emit light.

[0039] To more clearly illustrate the technical solution provided by the present invention, the present invention first takes Figure 1 the pixel circuit shown as an example to illustrate the working principle of the pixel circuit:

[0040] As Figure 1 and Figure 2 shown, Figure 1 FIG. is a schematic circuit diagram of a pixel circuit provided by an embodiment of the present invention, Figure 2 FIG. is a schematic film layer structure diagram of a pixel circuit provided by an embodiment of the present invention. The pixel circuit includes a driving transistor M0, a gate reset transistor M1, an anode reset transistor M2, a data writing transistor M3, a threshold compensation transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, and a storage capacitor Cst.

[0041] Among them, the gate of the gate reset transistor M1 is electrically connected to the first scan signal line Scan1, the first pole of the gate reset transistor M1 is electrically connected to the reset signal line Vref, and the second pole of the first gate reset transistor M1 is electrically connected to the gate of the driving transistor M0.

[0042] The gate of the anode reset transistor M2 is electrically connected to the second scan signal line Scan2, the first pole of the anode reset transistor M2 is electrically connected to the reset signal line Vref, and the second pole of the anode reset transistor M2 is electrically connected to the anode of the light-emitting element D.

[0043] The gate of the data writing transistor M3 is electrically connected to the second scan signal line Scan2, the first pole of the data writing transistor M3 is electrically connected to the data line Data, and the second pole of the data writing transistor M3 is electrically connected to the first pole of the driving transistor M0.

[0044] The gate of the threshold compensation transistor M4 is electrically connected to the second scan signal line Scan2. The first pole of the threshold compensation transistor M4 is electrically connected to the second pole of the driving transistor M0. The second pole of the threshold compensation transistor M4 is electrically connected to the gate of the driving transistor M0.

[0045] The gate of the first light emission control transistor M5 is electrically connected to the light emission control signal line Emit. The first pole of the first light emission control transistor M5 is electrically connected to the fixed potential signal line PVDD. The second pole of the first light emission control transistor M5 is electrically connected to the first pole of the driving transistor M0.

[0046] The gate of the second light emission control transistor M6 is electrically connected to the light emission control signal line Emit. The first pole of the second light emission control transistor M6 is electrically connected to the second pole of the driving transistor M0. The second pole of the second light emission control transistor M6 is electrically connected to the anode of the light emitting element D.

[0047] The first electrode plate of the storage capacitor Cst is electrically connected to the fixed potential signal line PVDD. The second electrode plate of the storage capacitor Cst is the gate of the driving transistor M0.

[0048] As Figure 3 shown, Figure 3 for Figure 1 a corresponding signal timing diagram, the driving period T of the pixel circuit includes a reset period t1, a charging period t2, and a light emission period t3.

[0049] During the reset period t1, the first scan signal line Scan1 provides a low level, the gate reset transistor M1 is turned on, and the reset voltage provided by the reset signal line Vref is transmitted to the gate of the driving transistor M0 to reset the gate of the driving transistor M0.

[0050] During the charging period t2, the second scan signal line Scan2 provides a low level, the anode reset transistor M2 is turned on, and the reset voltage provided by the reset signal line Vref is transmitted to the anode of the light emitting element D to reset the anode of the light emitting element D. At the same time, the data writing transistor M3 and the threshold compensation transistor M4 are turned on, and the data voltage provided by the data line Data is written into the gate of the driving transistor M0, and the threshold voltage of the driving transistor M0 is compensated.

[0051] During the light emission period t3, the light emission control signal line Emit provides a low level, the first light emission control transistor M5 and the second light emission control transistor M6 are turned on, the path between the power supply signal line PVDD and the light emitting element D is connected, and the driving current converted by the driving transistor M0 is transmitted to the light emitting element D to drive the light emitting element D to emit light.

[0052] It can be understood that the magnitude of the driving current generated by the pixel circuit depends on the magnitude of the gate-source voltage Vgs of the driving transistor M0. The smaller the gate-source voltage Vgs of the driving transistor M0, the more completely the driving transistor M0 is turned on, and the larger the driving current flowing into the light-emitting element D.

[0053] The inventors have found through research that, referring to Figure 2 , in the film layer structure of the pixel circuit, there are a large number of connecting traces between transistors or between transistors and signal lines. Inevitably, there is a coupling effect between this part of the connecting traces and the gate of the driving transistor M0. When the potential on the connecting trace changes, this potential change will cause the gate potential of the driving transistor M0 to fluctuate, thereby affecting the working state of the driving transistor M0, affecting the driving current flowing into the light-emitting element D, and causing a deviation in the light-emitting brightness of the light-emitting element D.

[0054] Therefore, the embodiment of the present invention provides a display panel, which can effectively improve the stability of the working state of the driving transistor by adjusting the film layer structure of the pixel circuit.

[0055] As Figure 4 shown, Figure 4 is a schematic structural diagram of a display panel provided by an embodiment of the present invention. The display panel includes a substrate 1 and a plurality of pixel circuits 2 located on the substrate 1. The plurality of pixel circuits 2 can be arranged in a matrix.

[0056] Combined with Figure 1 , as Figure 5 and Figure 6 shown, Figure 5 is another schematic diagram of the film layer structure of the pixel circuit provided by the embodiment of the present invention. Figure 6 is Figure 5 's partial enlarged schematic diagram. The pixel circuit 2 includes a driving transistor M0. The connection relationship and working principle of the driving transistor M0 have been described in the above embodiment and will not be elaborated here. The driving transistor M0 is connected to the connecting trace 3; the pixel circuit 2 further includes a light-transmissive conductive part 4. The light-transmissive conductive part 4 includes a light-transmissive conductive material, for example, it may include indium tin oxide (ITO) material. In the direction perpendicular to the plane of the substrate 1, the light-transmissive conductive part 4 overlaps at least partially with the connecting line segment.

[0057] It should be noted that the connecting trace 3 may include polysilicon material and is arranged on the same layer as the active layer in the transistor. In the embodiment of the present invention, the connection between the driving transistor M0 and the connecting trace 3 may include both the direct connection between the driving transistor M0 and the connecting trace 3 and the indirect connection between the driving transistor M0 and the connecting trace 3.

[0058] In the embodiment of the present invention, by adding a light-transmitting conductive part 4 that overlaps with the connection trace 3, on the one hand, a parasitic capacitance is formed between the light-transmitting conductive part 4 and the connection trace 3, and this parasitic capacitance can be used to stabilize the potential of the connection trace 3, thereby weakening the coupling effect between the connection trace 3 and the gate of the driving transistor M0 and reducing the influence of the potential change on the connection trace 3 on the gate potential of the driving transistor M0. In this way, the stability of the gate potential of the driving transistor M0 is improved, and then the reliability of the working state of the pixel circuit 2 is improved, making the driving current flowing into the light-emitting element tend to the standard value.

[0059] On the other hand, when setting the conductive part for forming the parasitic capacitance with the connection trace 3, if the conductive part is formed of a metal material, the light-transmitting performance of the display panel will be affected after the conductive part overlaps with the connection trace 3. Especially for a display panel with a fingerprint recognition function or a camera function, the light transmittance decreases, and the amount of light reflected by the finger to the sensor and the amount of external ambient light incident on the camera both decrease, resulting in low fingerprint recognition accuracy and poor imaging quality. However, in the embodiment of the present invention, by using a light-transmitting conductive material to form the light-transmitting conductive part 4, even if the light-transmitting conductive part 4 overlaps with the connection trace 3, it will not affect the light transmittance of the display panel, thereby optimizing the fingerprint recognition accuracy or imaging quality of the display panel. Exemplarily, for a 6.67-inch wide-screen high-definition (WQHD) resolution display panel, compared with forming the conductive part of a metal material, the embodiment of the present invention uses a light-transmitting conductive material to form the conductive part, which can increase the transmittance of the display panel by about 20%.

[0060] In one implementation, the light-transmitting conductive part 4 receives a constant voltage signal to keep the voltage on the light-transmitting conductive part 4 constant, which can more effectively stabilize the potential on the connection trace 3.

[0061] Furthermore, in combination with Figure 1 and Figure 6 , the display panel further includes a fixed potential signal line PVDD for providing a power supply voltage. The fixed potential signal line PVDD includes a first fixed potential signal line PVDD1 and a second fixed potential signal line PVDD2 that are electrically connected. The first fixed potential signal line PVDD1 extends along a first direction x, and the second fixed potential signal line PVDD2 extends along a second direction y. Herein, the first direction x is the extending direction of the first scan signal line Scan1 and the second scan signal line Scan2, and the first direction x intersects with the second direction y. That is to say, the first fixed potential signal line and the second fixed potential signal line PVDD2 intersect to form a grid-like structure.

[0062] The pixel circuit 2 further includes a storage capacitor Cst and a gate reset transistor M1. Among them, the first electrode plate of the storage capacitor Cst is electrically connected to the first fixed potential signal line PVDD1, and the second electrode plate of the storage capacitor Cst is the gate of the driving transistor M0; the gate of the gate reset transistor M1 is electrically connected to the first scan signal line Scan1, the first pole of the gate reset transistor M1 is electrically connected to the reset signal line, and the second pole of the gate reset transistor M1 is electrically connected to the gate of the driving transistor M0. The working principle of the gate reset transistor M1 has been described in the above embodiments and will not be elaborated here.

[0063] The transparent conductive portion 4 is electrically connected to the first fixed potential signal line PVDD1, or the transparent conductive portion 4 is electrically connected to the second fixed potential signal line PVDD2, or the transparent conductive portion 4 is electrically connected to the reset signal line. Exemplarily, as Figure 7 shown, Figure 7 is Figure 6 a cross-sectional view along the A1-A2 direction, and the transparent conductive portion 4 is electrically connected to the first fixed potential signal line PVDD1.

[0064] With such a setting, the transparent conductive portion 4 only needs to be electrically connected to the signal lines originally used to provide power voltage or reset voltage in the display panel, without additionally adding other constant voltage signal lines, simplifying the wiring of the display panel. In particular, when the transparent conductive portion 4 is electrically connected to the first fixed potential signal line PVDD1 or the second fixed potential signal line PVDD2, the power voltage transmitted on the fixed potential signal line PVDD is more stable. Therefore, the improvement effect of the transparent conductive portion 4 on the potential stability of the connection trace 3 is better.

[0065] Furthermore, the transparent conductive portion 4 is located on the side facing the substrate 1 of the signal line connected thereto, and the surface of the transparent conductive portion 4 facing away from the substrate 1 contacts the surface of the signal line connected thereto facing the substrate 1. Taking the transparent conductive portion 4 being electrically connected to the first fixed potential signal line PVDD1 as an example, refer to Figure 7 , the transparent conductive portion 4 is located on the side of the first fixed potential signal line PVDD1 facing the substrate 1, and the surface of the transparent conductive portion 4 facing away from the substrate 1 contacts the surface of the first fixed potential signal line PVDD1 facing the substrate 1.

[0066] At this time, the transparent conductive portion 4 and the signal line connected thereto are electrically connected by direct contact, which not only has higher connection reliability, but also saves the insulating layer between the transparent conductive portion 4 and the signal line compared with the connection method through vias between the transparent conductive portion 4 and the signal line, reducing the overall thickness of the film layer.

[0067] When the transparent conductive part 4 is located on the side of the signal line connected thereto facing the substrate 1, when forming the transparent conductive part 4 and the signal line connected thereto, a layer of transparent conductive material can be first formed on the substrate 1, and then a layer of metal material is formed on the transparent conductive material. After that, the metal material is etched using a first mask plate to form the signal line, and then the transparent conductive material is etched using a second mask plate to form the transparent conductive part 4. It should be noted that since the etching of the transparent conductive material is carried out after the metal etching, the orthographic projection of the transparent film layer where the transparent conductive part 4 is located covers the metal film layer where the signal line is located.

[0068] In one embodiment, in combination with Figure 1 、 Figure 5 and Figure 6 , the connection trace 3 includes a first connection segment 31. The pixel circuit 2 further includes a data writing transistor M3. The gate of the data writing transistor M3 is electrically connected to the second scan signal line Scan2. The first pole of the data writing transistor M3 is electrically connected to the data line Data. The second pole of the data writing transistor M3 is electrically connected to the first pole of the driving transistor M0 through the first connection segment 31. The working principle of the data writing transistor M3 has been described in the above embodiments and will not be elaborated here.

[0069] The transparent conductive part 4 includes a first transparent part 41. In the direction perpendicular to the plane of the substrate 1, the first transparent part 41 at least partially overlaps with the first connection segment 31.

[0070] Combined with the above analysis of the working principle of the pixel circuit 2, during the charging period t2, the data voltage on the data line Data is written into the second pole of the data writing transistor M3. At this time, the potential of the second pole of the data writing transistor M3 jumps, that is, the potential on the first connection segment 31 jumps. Based on the coupling effect between the first connection segment 31 and the gate of the driving transistor M0, the potential jump on the first connection segment 31 will cause the gate potential of the driving transistor M0 to fluctuate, thereby affecting the on-state of the driving transistor M0.

[0071] When the display panel uses low-frequency driving, the display of a picture includes multiple frames of driving. In the first frame, the pixel circuit 2 writes the data voltage, and the pixel circuit 2 transmits the driving current to the light-emitting element to drive the light-emitting element to emit light. In subsequent other frames, the pixel circuit 2 does not rewrite the data voltage again, and the second pole of the data writing transistor M3 maintains the voltage written in the writing frame. The pixel circuit 2 transmits the driving current to the light-emitting element to drive the light-emitting element to emit light. However, when the display panel switches the picture, there is a difference in the display brightness between the first frame and the other frames. For example, when the display panel switches from a black picture to a white picture, since the data voltage corresponding to the black picture is quite different from the data voltage corresponding to the white picture, therefore, in the first frame of displaying the white picture, when the pixel circuit 2 writes the data voltage, the potential on the second pole (the first connection line segment 31) of the data writing transistor M3 will jump to a large extent. Therefore, the influence degree of this potential jump on the gate potential of the driving transistor M0 is relatively large, resulting in a low brightness in the first frame.

[0072] In the embodiment of the present invention, by providing the first light-transmitting portion 41 overlapping with the first connection line segment 31, the parasitic capacitance formed between the first light-transmitting portion 41 and the first connection line segment 31 can be utilized to stabilize the potential of the first connection line segment 31, thereby weakening the influence of the potential change on the first connection line segment 31 on the gate potential of the driving transistor M0, and effectively improving the problem of low brightness in the first frame. Moreover, since the first light-transmitting portion 41 is formed of a light-transmitting conductive material, even if the first light-transmitting portion 41 overlaps with the first connection line segment 31, it will not affect the light transmittance at the position where the first connection line segment 31 is located, and can also avoid affecting the light transmittance of the display panel.

[0073] In one embodiment, combined with Figure 1 and Figure 5 , the connection trace 3 includes a second connection line segment 32. The pixel circuit 2 further includes at least one dual-gate module 5. The dual-gate module 5 includes a first transistor 51 and a second transistor 52. The gate of the first transistor 51 is electrically connected to the gate of the second transistor 52. The second connection line segment 32 is electrically connected between the second pole of the first transistor 51 and the first pole of the second transistor 52. The gate of the driving transistor M0 is connected to the second connection line segment 32 through the second transistor 52.

[0074] The light-transmitting conductive portion 4 further includes a second light-transmitting portion 42. In the direction perpendicular to the plane of the substrate 1, the second light-transmitting portion 42 at least partially overlaps with the second connection line segment 32.

[0075] When the potential on the gates of the first transistor 51 and the second transistor 52 jumps, affected by the parasitic capacitance of the transistors, this potential jump will cause the potential on the second connection line segment 32 to fluctuate. Affected by the coupling effect between the second connection line segment 32 and the gate of the driving transistor M0, the potential fluctuation on the second connection line segment 32 will further affect the gate potential of the driving transistor M0. In the embodiment of the present invention, by providing the second light-transmitting portion 42 overlapping with the second connection line segment 32, the parasitic capacitance formed between the second light-transmitting portion 42 and the second connection line segment 32 can be used to stabilize the potential of the second connection line segment 32, thereby weakening the influence of the potential fluctuation on the second connection line segment 32 on the gate potential of the driving transistor M0. Moreover, since the second light-transmitting portion 42 is formed of a light-transmitting conductive material, it can also avoid affecting the light transmittance of the display panel.

[0076] In one embodiment, in combination with Figure 1 , such as Figure 8 shown, Figure 8 FIG. is a schematic structural diagram of a second light-transmitting portion provided by an embodiment of the present invention. At least one double-gate module 5 includes a threshold compensation transistor M4. The threshold compensation transistor M4 includes a first compensation transistor M41 and a second compensation transistor M42. The gates of the first compensation transistor M41 and the second compensation transistor M42 are respectively electrically connected to the second scan signal line Scan2.

[0077] The second connection line segment 32 includes a second A connection line segment 321. The first pole of the first compensation transistor M41 is electrically connected to the second pole of the driving transistor M0. The second pole of the first compensation transistor M41 and the first pole of the second compensation transistor M42 are electrically connected through the second A connection line segment 321. The second pole of the second compensation transistor M42 is electrically connected to the gate of the driving transistor M0.

[0078] The second light-transmitting portion 42 includes a second A light-transmitting portion 421. In the direction perpendicular to the plane of the substrate 1, the second A light-transmitting portion 421 and the second A connection line segment 321 at least partially overlap.

[0079] When the second scan signal jumps from a low level to a high level, affected by the parasitic capacitance of the transistors, this potential jump will cause the potential on the second A connection line segment 321 to fluctuate. By providing the second A light-transmitting portion 421, the parasitic capacitance formed between the second A light-transmitting portion 421 and the second A connection line segment 321 can stabilize the potential on the second A connection line segment 321, avoid a large fluctuation in the potential on the second A connection line segment 321, and thereby reduce the influence of the potential fluctuation on the second A connection line segment 321 on the gate potential of the driving transistor M0. Moreover, the second A light-transmitting portion 421 has a high light transmittance and will not affect the light transmittance of the display panel.

[0080] In one embodiment, in combination with Figure 1 as Figure 9 and Figure 10 shown, Figure 9 FIG. is a schematic diagram of another film layer structure of the pixel circuit provided by the embodiment of the present invention. Figure 10 is Figure 9 a partial enlarged schematic diagram. At least one double-gate module 5 includes a gate reset transistor M1. The gate reset transistor M1 includes a first reset transistor M11 and a second reset transistor M12. The gates of the first reset transistor M11 and the second reset transistor M12 are respectively electrically connected to the first scan signal line Scan1.

[0081] The second connection line segment 32 includes a second B connection line segment 322. The first pole of the first reset transistor M11 is electrically connected to the reset signal line. The second pole of the first reset transistor M11 is electrically connected to the first pole of the second reset transistor M12 through the second B connection line segment 322. The second pole of the second reset transistor M12 is electrically connected to the gate of the driving transistor M0.

[0082] The second light-transmitting portion 42 includes a second B light-transmitting portion 422. In the direction perpendicular to the plane of the substrate 1, the second B light-transmitting portion 422 and the second B connection line segment 322 at least partially overlap.

[0083] When the first scan signal jumps from a low level to a high level, affected by the parasitic capacitance of the transistor, this potential jump will cause the potential on the second B connection line segment 322 to fluctuate. By providing the second B light-transmitting portion 422, the parasitic capacitance formed between the second B light-transmitting portion 422 and the second B connection line segment 322 can stabilize the potential on the second B connection line segment 322, avoid a large fluctuation in the potential on the second B connection line segment 322, and further reduce the influence of the potential fluctuation on the second B connection line segment 322 on the gate potential of the driving transistor M0. Moreover, the light transmittance of the second B light-transmitting portion 422 is relatively high and will not affect the light transmittance of the display panel.

[0084] In one embodiment, in combination with Figure 1 as Figure 11 and Figure 12 shown, Figure 11 FIG. is a schematic diagram of yet another film layer structure of the pixel circuit 2 provided by the embodiment of the present invention. Figure 12 is Figure 11 a partial enlarged schematic diagram. The connection trace 3 includes a third connection line segment 33 and a fourth connection line segment 34.

[0085] The pixel circuit 2 further includes a threshold compensation transistor M4 and a gate reset transistor M1. Among them, the gate of the threshold compensation transistor M4 is electrically connected to the second scan signal line Scan2. The first pole of the threshold compensation transistor M4 is electrically connected to the second pole of the driving transistor M0. The second pole of the threshold compensation transistor M4 is electrically connected to the gate of the driving transistor M0 through a third connection line segment 33. The third connection line segment 33 includes a metal material. The gate of the gate reset transistor M1 is electrically connected to the first scan signal line Scan1. The gate of the gate reset transistor M1 is electrically connected to the first scan signal line Scan1. The first pole of the gate reset transistor M1 is electrically connected to the reset signal line. The second pole of the gate reset transistor M1 is electrically connected to the third connection line segment 33 through a fourth connection line segment 34. The fourth connection line segment 34 includes a polysilicon material.

[0086] The light-transmitting conductive part 4 further includes a third light-transmitting part 43. In the direction perpendicular to the plane of the substrate 1, the third light-transmitting part 43 at least partially overlaps with the fourth connection line segment 34. And, in the first direction x, the third light-transmitting part 43 overlaps with the third connection line segment 33. The first direction x is parallel to the plane of the substrate 1, and the first direction x is the extending direction of the first scan signal line Scan1.

[0087] With such a setting, the third light-transmitting part 43 at least partially overlaps with the fourth connection line segment 34, and the parasitic capacitance formed between the third light-transmitting part 43 and the fourth connection line segment 34 can be used to stabilize the potential on the fourth connection line segment 34, and further stabilize the potential of the gate of the driving transistor M0. In addition, in the first direction x, the third light-transmitting part 43 also overlaps with the third connection line segment 33. When the third light-transmitting part 43 receives a constant voltage signal, a stable electric field will be formed between the third light-transmitting part 43 and the third connection line segment 33 to stabilize the potential of the third connection line segment 33, thereby further improving the reliability of the potential of the gate of the driving transistor M0.

[0088] It should be noted that, in the direction perpendicular to the plane of the substrate 1, the orthographic projection of the third light-transmitting part 43 is relatively close to the orthographic projection of the second fixed potential signal line PVDD2. Therefore, the third light-transmitting part 43 can be electrically connected to the second fixed potential signal line PVDD2. To improve the connection reliability between the third light-transmitting part 43 and the second fixed potential signal line PVDD2, in combination with Figure 12 , as Figure 13 shown, Figure 13 for Figure 12 the cross-sectional view along the B1-B2 direction, an auxiliary connection layer 6 can also be provided between the third light-transmitting part 43 and the second fixed potential signal line PVDD2. The auxiliary connection layer 6 is provided on the same layer as the first fixed potential signal line PVDD1.

[0089] In addition, it should also be noted that, referring to Figure 13, the third light-transmitting part 43 can communicate with the second light-transmitting part 421 of the first type, and the two are integrally formed. The third light-transmitting part 43 is electrically connected to the second fixed-potential signal line PVDD2 through the second light-transmitting part 421 of the first type.

[0090] In one embodiment, as Figure 14 shown, Figure 14 FIG. is a schematic diagram of a film layer structure of a storage capacitor provided by an embodiment of the present invention. The display panel further includes a fixed-potential signal line PVDD. The fixed-potential signal line PVDD includes a first fixed-potential signal line PVDD1 and a second fixed-potential signal line PVDD2 that are electrically connected. The first fixed-potential signal line PVDD1 extends along a first direction x, and the second fixed-potential signal line PVDD2 extends along a second direction y. The first direction x intersects the second direction y.

[0091] The pixel circuit 2 further includes a storage capacitor Cst. A first electrode plate 7 of the storage capacitor Cst is electrically connected to the first fixed-potential signal line PVDD1, and a second electrode plate 8 of the storage capacitor Cst is the gate of the driving transistor M0.

[0092] In the direction perpendicular to the plane of the substrate 1, the edge of the positive projection of the second electrode plate 8 is located within the positive projection of the first electrode plate 7, and at least part of the electrodes in the first electrode plate 7 that do not overlap with the second electrode plate 8 include a light-transmissive conductive material.

[0093] In the embodiment of the present invention, in the direction perpendicular to the plane of the substrate 1, the edge of the positive projection of the second electrode plate 8 is located within the positive projection of the first electrode plate 7, that is, the second electrode plate 8 covers the first electrode plate 7. Even if the positions of the second electrode plate 8 and / or the first electrode plate 7 are shifted due to process errors or other factors, it can still ensure that there is a sufficient overlapping area between the first electrode plate 7 and the second electrode plate 8, ensuring that the storage capacitor Cst has a sufficiently large capacitance to better ensure the stability of the gate of the driving transistor M0. Moreover, by forming at least part of the electrodes in the first electrode plate 7 that do not overlap with the second electrode plate 8 with a light-transmissive conductive material, it is also possible to avoid the light shielding caused by this part of the electrodes, thereby effectively improving the light transmittance of the display panel.

[0094] In addition, it should be noted that in the embodiment of the present invention, since at least part of the electrodes in the first electrode plate 7 are light-transmissive electrodes, on the premise of ensuring sufficient light transmittance, compared with setting the entire second electrode plate as a metal electrode, the coverage area of the second electrode plate can be further increased, so that it extends outward from the first electrode to a greater extent, thereby further avoiding the situation where the first electrode plate 7 and the second electrode plate 8 are not completely overlapped due to process errors or other factors.

[0095] In one embodiment, as Figure 15 shown, Figure 15Another schematic diagram of the film layer structure of the storage capacitor provided by the embodiment of the present invention. The first electrode plate 7 is a light-transmitting electrode. Even if the positions of the second electrode plate 8 and / or the first electrode plate 7 shift due to process errors and other factors, it can still ensure that the part of the electrode in the first electrode plate 7 that does not overlap with the second electrode plate 8 is all light-transmitting, further improving the light transmittance of the display panel.

[0096] It should be noted that, as Figure 16 shown, Figure 16 is Figure 15 a cross-sectional view along the C1-C2 direction. The first electrode plate 7 is located on the side of the first fixed potential signal line PVDD1 facing the substrate 1. And, to improve the connection reliability between the first electrode plate 7 and the first fixed potential signal line PVDD1, the surface of the first electrode plate 7 facing the substrate 1 is in contact with the surface of the substrate 1 facing away from the substrate 1.

[0097] Or, in another embodiment, as Figure 17 shown, Figure 17 Another schematic diagram of the film layer structure of the storage capacitor provided by the embodiment of the present invention. The first electrode plate 7 includes a first sub-electrode plate 71 and a second sub-electrode plate 72 that are electrically connected. The first sub-electrode plate 71 is a metal electrode, and the second sub-electrode plate 72 is a light-transmitting electrode; in the direction perpendicular to the plane of the substrate 1, the edge of the orthographic projection of the first sub-electrode plate 71 is located within the orthographic projection of the second sub-electrode plate 72, so that at least part of the electrode in the first electrode plate 7 that does not overlap with the second electrode plate 8 is a light-transmitting electrode, improving the light transmittance.

[0098] It should be noted that, to further reduce the shielding area of the second electrode plate, in the direction perpendicular to the plane of the substrate 1, the orthographic projection of the first sub-electrode plate 71 can be located within the orthographic projection of the second electrode plate 8, or the orthographic projection of the first sub-electrode plate 71 can coincide with the orthographic projection of the second electrode plate 8.

[0099] In addition, it should also be noted that, as Figure 18 shown, Figure 18 is Figure 17 a cross-sectional view along the D1-D2 direction. The second sub-electrode plate 72 is located on the side of the first sub-electrode plate 71 facing the substrate 1. And, to improve the connection reliability between the second sub-electrode plate 72 and the first sub-electrode plate 71, the surface of the second sub-electrode plate 72 facing away from the substrate 1 is in contact with the surface of the first sub-electrode plate 71 facing the substrate 1.

[0100] Furthermore, as Figure 19 and Figure 20 shown, Figure 19 Another schematic diagram of the film layer structure of the storage capacitor provided by the embodiment of the present invention. Figure 20 is Figure 19Cross-sectional view along the E1-E2 direction. In the direction perpendicular to the plane where the substrate 1 is located, the positive projection of the second sub-electrode plate 72 covers the positive projection of the first sub-electrode plate 71, so as to improve the connection reliability between the second sub-electrode plate 72 and the first sub-electrode plate 71, and ensure that the entire first electrode plate 7 is a whole-surface electrode without any hollow inside the first electrode plate 7.

[0101] Alternatively, referring to Figure 17 and Figure 18 , the second sub-electrode plate 72 has a hollow area 9. In the direction perpendicular to the plane where the substrate 1 is located, the hollow area 9 and the overlapping area between the first sub-electrode plate 71 and the second electrode plate 8 overlap at least partially. At this time, the second sub-electrode plate 72 is an annular electrode, and it can still ensure that at least part of the electrode in the first electrode plate 7 that does not overlap with the second electrode plate 8 is a light-transmitting electrode, improving the light transmittance.

[0102] In one embodiment, referring to Figure 18 and Figure 20 , to improve the connection reliability between the second sub-electrode plate 72 and the first sub-electrode plate 71, the second sub-electrode plate 72 is located on the side of the first sub-electrode plate 71 facing the substrate 1, and the surface of the second sub-electrode plate 72 facing away from the substrate 1 is in contact with the surface of the first sub-electrode plate 71 facing the substrate 1. It should be noted that the second sub-electrode plate 72 can be arranged on the same layer as the first fixed potential signal line PVDD1.

[0103] In addition, it should be emphasized that Figure 1 the types of transistors included in the pixel circuit shown are only for illustrative purposes. In other alternative embodiments of the present invention, all the transistors in the pixel circuit can also be N-type transistors, or the pixel circuit includes both N-type and P-type transistors at the same time. For example, in the pixel circuit, the gate reset transistor M1 and the threshold compensation transistor M4 can be N-type indium gallium zinc oxide (IGZO) transistors, and the other transistors are P-type low temperature poly-silicon (LTPS) transistors. At this time, the threshold compensation transistor M4 and the data writing transistor M3 are electrically connected to different scan signal lines. When the pixel circuit includes other types of transistors, the working principle of the pixel circuit is still the same as that of Figure 1 the corresponding pixel circuit, only the conduction level of the transistors changes.

[0104] Based on the same inventive concept, the embodiments of the present invention also provide a display device, as shown in Figure 21 shown. Figure 21It is a schematic structural diagram of a display device provided by an embodiment of the present invention. The display device includes the above-mentioned display panel 100. Among them, the specific structure of the display panel 100 has been described in detail in the above embodiments and will not be elaborated here. Of course, Figure 21 The display device shown is only for illustrative purposes. The display device can be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-book reader, or a television.

[0105] The foregoing is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of protection of the present invention.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, Comprising a substrate and a plurality of pixel circuits located on the substrate, the pixel circuits comprising: A driving transistor, the driving transistor being connected to a connection trace, the connection trace being a trace for connecting between transistors or between a transistor and a signal line; A light-transmitting conductive portion, the light-transmitting conductive portion comprising a light-transmitting conductive material, and in a direction perpendicular to the plane of the substrate, the light-transmitting conductive portion at least partially overlaps with the connection trace.

2. The display panel according to claim 1, wherein: The light-transmitting conductive portion receives a constant voltage signal.

3. The display panel according to claim 2, wherein: The display panel further comprises a fixed potential signal line, the fixed potential signal line comprising a first fixed potential signal line and a second fixed potential signal line which are electrically connected, the first fixed potential signal line extends in a first direction, the second fixed potential signal line extends in a second direction, and the first direction intersects with the second direction; The pixel circuit further comprises: A storage capacitor, a first electrode plate of the storage capacitor being electrically connected to the first fixed potential signal line, and a second electrode plate of the storage capacitor being the gate of the driving transistor; A gate reset transistor, the gate of the gate reset transistor being electrically connected to a first scan signal line, a first pole of the gate reset transistor being electrically connected to a reset signal line, and a second pole of the gate reset transistor being electrically connected to the gate of the driving transistor; The light-transmitting conductive portion is electrically connected to the first fixed potential signal line, or the light-transmitting conductive portion is electrically connected to the second fixed potential signal line, or the light-transmitting conductive portion is electrically connected to the reset signal line.

4. The display panel according to claim 3, wherein: The light-transmitting conductive portion is located on a side of the signal line connected thereto facing the substrate, and a surface of the light-transmitting conductive portion facing away from the substrate and a surface of the signal line connected thereto facing the substrate are in contact.

5. The display panel according to claim 1, wherein: The connection trace comprises a first connection segment; The pixel circuit further comprises a data writing transistor, the gate of the data writing transistor being electrically connected to a second scan signal line, a first pole of the data writing transistor being electrically connected to a data line, and a second pole of the data writing transistor being electrically connected to the first pole of the driving transistor through the first connection segment; The light-transmitting conductive portion comprises a first light-transmitting portion, and in a direction perpendicular to the plane of the substrate, the first light-transmitting portion at least partially overlaps with the first connection segment.

6. The display panel according to claim 1, wherein: The connection trace comprises a second connection segment; The pixel circuit further comprises at least one dual-gate module, the dual-gate module comprising a first transistor and a second transistor, the gate of the first transistor being electrically connected to the gate of the second transistor, the second connection segment being electrically connected between a second pole of the first transistor and a first pole of the second transistor, and the gate of the driving transistor being connected to the second connection segment through the second transistor; The light-transmissive conductive portion further includes a second light-transmissive portion, and in a direction perpendicular to the plane of the substrate, the second light-transmissive portion at least partially overlaps with the second connection line segment.

7. The display panel according to claim 6, wherein at least one of the dual-gate modules includes a threshold compensation transistor, the threshold compensation transistor includes a first compensation transistor and a second compensation transistor, and gates of the first compensation transistor and the second compensation transistor are electrically connected to a second scan signal line respectively; the second connection line segment includes a second A connection line segment, a first pole of the first compensation transistor is electrically connected to a second pole of the driving transistor, a second pole of the first compensation transistor and a first pole of the second compensation transistor are electrically connected through the second A connection line segment, and a second pole of the second compensation transistor is electrically connected to a gate of the driving transistor; the second light-transmissive portion includes a second A light-transmissive portion, and in a direction perpendicular to the plane of the substrate, the second A light-transmissive portion at least partially overlaps with the second A connection line segment.

8. The display panel according to claim 6, wherein at least one of the dual-gate modules includes a gate reset transistor, the gate reset transistor includes a first reset transistor and a second reset transistor, and gates of the first reset transistor and the second reset transistor are electrically connected to a first scan signal line respectively; the second connection line segment includes a second B connection line segment, a first pole of the first reset transistor is electrically connected to a reset signal line, a second pole of the first reset transistor and a first pole of the second reset transistor are electrically connected through the second B connection line segment, and a second pole of the second reset transistor is electrically connected to a gate of the driving transistor; the second light-transmissive portion includes a second B light-transmissive portion, and in a direction perpendicular to the plane of the substrate, the second B light-transmissive portion at least partially overlaps with the second B connection line segment.

9. The display panel according to claim 1, wherein the connection trace includes a third connection line segment and a fourth connection line segment; the pixel circuit further includes: a threshold compensation transistor, a gate of the threshold compensation transistor is electrically connected to a second scan signal line, a first pole of the threshold compensation transistor is electrically connected to a second pole of the driving transistor, and a second pole of the threshold compensation transistor and a gate of the driving transistor are electrically connected through a third connection line segment, and the third connection line segment includes a metal material; a gate reset transistor, a gate of the gate reset transistor is electrically connected to a first scan signal line, a first pole of the gate reset transistor is electrically connected to a reset signal line, and a second pole of the gate reset transistor and the third connection line segment are electrically connected through a fourth connection line segment, and the fourth connection line segment includes a polysilicon material; The light-transmissive conductive part further includes a third light-transmissive part. In a direction perpendicular to the plane of the substrate, the third light-transmissive part at least partially overlaps with the fourth connection line segment. Moreover, in a first direction parallel to the plane of the substrate and being the extending direction of the first scanning signal line, the third light-transmissive part overlaps with the third connection line segment.

10. The display panel according to claim 1, wherein the display panel further includes a fixed-potential signal line, which includes a first fixed-potential signal line and a second fixed-potential signal line that are electrically connected. The first fixed-potential signal line extends along the first direction, the second fixed-potential signal line extends along a second direction, and the first direction intersects with the second direction; the pixel circuit further includes: a storage capacitor, where a first electrode plate of the storage capacitor is electrically connected to the first fixed-potential signal line, and a second electrode plate of the storage capacitor is the gate of the driving transistor; In a direction perpendicular to the plane of the substrate, an edge of the positive projection of the second electrode plate is located within the positive projection of the first electrode plate. Moreover, at least part of the electrodes of the first electrode plate that do not overlap with the second electrode plate include a light-transmissive conductive material.

11. The display panel according to claim 10, wherein the first electrode plate is a light-transmissive electrode.

12. The display panel according to claim 10, wherein the first electrode plate includes a first sub-electrode plate and a second sub-electrode plate that are electrically connected. The first sub-electrode plate is a metal electrode, and the second sub-electrode plate is a light-transmissive electrode; In a direction perpendicular to the plane of the substrate, an edge of the positive projection of the first sub-electrode plate is located within the positive projection of the second sub-electrode plate.

13. The display panel according to claim 12, wherein In a direction perpendicular to the plane of the substrate, the positive projection of the second sub-electrode plate covers the positive projection of the first sub-electrode plate.

14. The display panel according to claim 12, wherein the second sub-electrode plate has a hollowed-out area, and in a direction perpendicular to the plane of the substrate, the hollowed-out area at least partially overlaps with the overlapping area between the first sub-electrode plate and the second electrode plate.

15. The display panel according to claim 12, wherein the second sub-electrode plate is located on a side of the first sub-electrode plate facing the substrate, and a surface of the second sub-electrode plate on a side facing away from the substrate contacts a surface of the first sub-electrode plate on a side facing the substrate.

16. A display device, characterized in that, including the display panel according to any one of claims 1 to 15.

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