Automated testing method, device, computer equipment and readable storage medium

Abstract

The present application provides an automated testing method, device, computer equipment and readable storage medium. The method includes: after receiving the start simulation instruction initiated by the user, the computer equipment executes the first connection function of the test script to trigger the hardware simulation accelerator to execute the first connection command to achieve the communication connection between the computer equipment and the hardware simulation accelerator; after the hardware simulation accelerator executes the first connection command, the computer equipment executes the configuration function of the test script to configure the function to be tested of the chip to be tested based on the configuration process corresponding to the configuration function. Since the test script will output the configuration instructions corresponding to each configuration process, and automatically perform the configuration of the next configuration process when the previous configuration process is completed, the above method reduces the manual intervention of the hardware simulation accelerator in the configuration process and improves the configuration efficiency.

Description

Technical Field

[0001] The present application relates to the field of hardware simulation technology, and in particular to an automated testing method, apparatus, computer equipment and readable storage medium. Background Art

[0002] With the rapid development of integrated circuit technology, the design scale of microprocessors has gradually increased, and the design complexity has increased day by day, which has put forward higher requirements for verification technology. Verification technology mainly includes software simulation verification, FPGA (Field Programmable Gate Array) prototype system verification and hardware simulation accelerator verification. Software simulation verification technology can verify the modules in the microprocessor, but it is difficult to meet the simulation speed requirements of large-scale verification at the system level. FPGA prototype verification can improve the simulation speed, but due to the capacity of FPGA, a microprocessor design needs to be divided into multiple FPGAs, which introduces a problem of logic division, and the technical difficulty and time cost are relatively large. At the same time, there are also problems such as I / O (Input / Output) bottleneck and inconvenient debugging.

[0003] Hardware simulation accelerator is the main means of system-level verification of microprocessors at present, which effectively makes up for the shortcomings of software simulation verification and FPGA prototype verification. Its advantages are as follows: it is convenient for users to build hardware models of chips in the early stage of design; it is convenient for users to debug chip software and design in the early stage of design; it can be reused many times; the built-in logic analyzer can be used to debug the circuit very conveniently; there are a variety of reusable standard bus models, such as PCI (Peripheral Component Interconnect, peripheral component interconnect standard), Ethernet, etc.

[0004] However, currently, the configuration of hardware simulation accelerators before testing needs to be manually performed by testers, which consumes a lot of manpower and greatly reduces the configuration efficiency. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide an automated testing method, apparatus, computer equipment and readable storage medium, which can reduce manual intervention and improve configuration efficiency.

[0006] The present invention is achieved in that:

[0007] In a first aspect, an embodiment of the present application provides an automated testing method, which is applied to a computer device, wherein the computer device is used to be physically connected to a hardware simulation accelerator, and the hardware simulation accelerator runs files related to a chip to be tested to test the function to be tested of the chip to be tested; the method comprises: after receiving a start simulation instruction initiated by a user, the computer device executes a first connection function of a test script to trigger the hardware simulation accelerator to execute a first connection command to achieve a communication connection between the computer device and the hardware simulation accelerator; after the hardware simulation accelerator executes the first connection command, the computer device executes a configuration function of the test script to configure the function to be tested of the chip to be tested based on a configuration process corresponding to the configuration function; wherein, when executing the configuration function of the test script, the test script outputs configuration instructions corresponding to each configuration process, and automatically performs configuration of the next configuration process when the previous configuration process is completed.

[0008] In an embodiment of the present application, after receiving the start simulation instruction initiated by the user, the computer device can automatically execute the first connection function of the test script to trigger the hardware simulation accelerator to execute the first connection command, thereby establishing a communication connection between the computer device and the hardware simulation accelerator. In this way, the interaction between the computer device and the hardware simulation accelerator can be realized, and it is convenient for the subsequent computer device to complete the configuration of the hardware simulation accelerator through the configuration function of the test script. In addition, since the test script outputs the configuration instructions corresponding to each configuration process, and automatically performs the configuration of the next configuration process when the previous configuration process is completed, the manual intervention of the hardware simulation accelerator in the configuration process is reduced by the above method, and the configuration efficiency is improved.

[0009] In combination with the technical solution provided in the first aspect above, in some possible implementations, the hardware simulation accelerator also runs a serial port model; the configuration function of executing the test script includes: the computer device outputs a first configuration instruction corresponding to a first configuration process to the serial port model through the test script, so that the serial port model inputs the first configuration instruction into the hardware simulation accelerator by force; the first configuration process is any one of the configuration processes; the computer device receives actual characters output by the serial port model through a display cache, and the actual characters are generated when the hardware simulation accelerator executes the first configuration instruction and captured by a debugging script language supported by the hardware simulation accelerator; the computer device compares the preset expected completion characters with the actual characters through the comparison instructions in the configuration function to determine whether the first configuration process is completed; when the computer device determines that the first configuration process is completed and the first configuration process is not the last configuration process, the computer device outputs a second configuration instruction corresponding to a second configuration process to the serial port model through the test script, and the second configuration process is the next configuration process of the first configuration process.

[0010] In the embodiment of the present application, by replacing the traditional serial port chip with a serial port model, the configuration difficulty of the hardware simulation accelerator in the hardware environment can be reduced. And the serial port model sends the actual characters output to the computer device through a display cache, which is convenient for the user to intuitively see the process of each configuration stage, and it is also convenient for the user to analyze the problem, which greatly improves the test efficiency in complex scenarios. In addition, the computer device can compare the preset expected completion characters with the actual characters output by the serial port model through the comparison instructions in the configuration function, and then determine whether to output the configuration instructions corresponding to the next configuration process to the serial port model according to the comparison results, so as to realize the automatic triggering of the next configuration process, and then realize the automation of the entire configuration process of the test script.

[0011] In combination with the technical solution provided in the first aspect above, in some possible implementations, the actual characters are recognized and successfully recognized by the serial port model before being output through the display buffer.

[0012] In the embodiment of the present application, the serial port model is also used to recognize characters before the actual characters are output. The serial port model will output the characters only if they can be recognized successfully. In this way, the accuracy and reliability of the serial port model in application can be guaranteed, and the problem of the serial port model still outputting characters when they are missing, which will cause errors in subsequent comparison, can be avoided.

[0013] In combination with the technical solution provided in the first aspect above, in some possible implementations, the configuration process includes uboot booting, operating system booting, driver loading of the function to be tested, and parameter configuration of the function to be tested.

[0014] In an embodiment of the present application, the configuration process may include uboot booting, operating system booting, driver loading of the function to be tested, and parameter configuration of the function to be tested, thereby realizing full-stage automated configuration.

[0015] In combination with the technical solution provided in the first aspect above, in some possible implementations, the computer device is also used to connect to other computer devices, and the network card connected to the hardware simulation accelerator is connected to the other computer devices via a network cable. After determining that the configuration process of the function to be tested of the chip to be tested has been completed, the method also includes: the computer device executes the second connection function of the test script to enable the computer device to automatically remotely log in to the hardware simulation accelerator, and test the function to be tested by running a test program.

[0016] In an embodiment of the present application, when the network card connected to the hardware simulation accelerator is connected to other computer devices via optical fiber, and the computer device connected to the other computing devices, after determining that the configuration process of the function to be tested has been completed, can automatically execute the second connection function of the test script, so that the computer device can automatically log in to the hardware simulation accelerator remotely, and at the same time test the function to be tested through the test program. In this way, manual intervention in the testing process of the function to be tested can be reduced, thereby realizing the full process automation from the configuration of the hardware simulation accelerator to the testing of the function to be tested.

[0017] In combination with the technical solution provided in the first aspect above, in some possible implementations, the test script is an expect script, and the computer device executes the second connection function of the test script, including: the computer device connects the SSH port of the computer device to the network configured by the hardware simulation accelerator through the spawn command in the expect script; wherein the address of the network is set in the spawn command.

[0018] In the embodiment of the present application, the spawn command in the expect script is modified and carries the address of the network, so as to connect the SSH port of the computer device to the network configured by the hardware simulation accelerator. Further, because the spawn command has the function of starting a new process, it can meet the requirements of simultaneously starting the test connection between multiple computer devices and the hardware simulation accelerator, and then multiple functions to be tested of the chip to be tested can be tested simultaneously.

[0019] In combination with the technical solution provided in the first aspect above, in some possible implementations, the computer device is also used to connect to the other computer device through non-password access.

[0020] In the embodiment of the present application, since the computer device can be connected to other computer devices through non-encrypted access, different computer devices can quickly access the hardware simulation accelerator and perform testing.

[0021] In a second aspect, an embodiment of the present application provides an automated testing device, which is applied to a computer device, wherein the computer device is used to be physically connected to a hardware simulation accelerator, and the hardware simulation accelerator runs files related to a chip to be tested to test the function to be tested of the chip to be tested; the device includes: a startup module, which is used to receive a startup simulation instruction initiated by a user; a first connection module, which is used to execute a first connection function of a test script after the startup module receives the startup simulation instruction initiated by the user, so as to trigger the hardware simulation accelerator to execute a first connection command, and realize the communication connection between the computer device and the hardware simulation accelerator; a configuration module, which is used to execute the configuration function of the test script after the hardware simulation accelerator executes the first connection command, so as to configure the function to be tested of the chip to be tested based on the configuration process corresponding to the configuration function; wherein, when executing the configuration function of the test script, the test script outputs the configuration instructions corresponding to each configuration process, and automatically performs the configuration of the next configuration process when the previous configuration process is completed.

[0022] In a third aspect, an embodiment of the present application provides a computer device, comprising: a processor and a memory, wherein the processor and the memory are connected; the memory is used to store programs; the processor is used to call the programs stored in the memory to execute the method provided in the above-mentioned first aspect embodiment and / or in combination with some possible implementation methods of the above-mentioned first aspect embodiment.

[0023] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, executes a method provided in the embodiment of the first aspect above and / or in combination with some possible implementations of the embodiment of the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A module block diagram of an automated testing system provided in an embodiment of the present application.

[0026] Figure 2 A module block diagram of a computer device provided in an embodiment of the present application.

[0027] Figure 3 A module block diagram of another automated testing system provided in an embodiment of the present application.

[0028] Figure 4 A flowchart of the steps of an automated testing method provided in an embodiment of the present application.

[0029] Figure 5 A flowchart of another step of automated testing provided in an embodiment of the present application.

[0030] Figure 6 A schematic diagram of performing a test using multiple computer devices is provided in an embodiment of the present application.

[0031] Figure 7 A module block diagram of an automated testing device provided in an embodiment of the present application.

[0032] Icons: 10 - automated test system; 100 - computer equipment; 110 - processor; 120 - memory; 200 - hardware simulation accelerator; 300 - automated test device; 310 - startup module; 320 - first connection module; 330 - configuration module. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0034] In order to facilitate the understanding of this application, the relevant technical terms are explained below:

[0035] Test scripts are computer-readable instructions that automatically execute a test process (or part of a test process). Test scripts can be created (recorded) or automatically generated using a test automation tool, or programmed in a programming language, or can be completed by combining the first three methods. In this application, the test script may include three processes, namely: connecting a computer device to a hardware simulation accelerator, configuring the function to be tested of the chip to be tested, and realizing automatic remote login of the computer device to the hardware simulation accelerator. This application will focus on how to implement a simulation test based on a hardware simulation accelerator based on a test script below.

[0036] The inventors of the present application have found in practice that in simulation tests based on hardware simulation accelerators, the tester needs to wait for the command response to complete before entering other commands each time he enters a command. This method wastes the tester's waiting time. And after the driver is loaded, if the tester is delayed due to other things, the hardware simulation accelerator will not be configured. To solve this technical problem, the embodiments of the present application provide an automated testing system, method and device.

[0037] For details, please refer to Figure 1 The embodiment of the present application provides an automated testing system 10 . The automated testing system 10 includes: a computer device 100 and a hardware simulation accelerator 200 .

[0038] The computer device 100 is physically connected to the hardware simulation accelerator 200 .

[0039] In the embodiment of the present application, the computer device 100 and the hardware simulation accelerator 200 are physically connected via optical fiber.

[0040] During the automated testing process of the automated testing system 10, the hardware simulation accelerator 200 runs files related to the chip to be tested, and can simulate the relevant functions of the chip to be tested. The computer device 100 is configured with a test script. After the computer device 100 establishes a communication connection with the hardware simulation accelerator 200, the computer device 100 is used to execute the configuration function of the test script, thereby enabling the hardware simulation accelerator 200 to automatically configure the function to be tested of the chip to be tested based on the configuration process corresponding to the configuration function.

[0041] See also Figure 2 , Figure 2 A schematic structural block diagram of a computer device 100 for applying an automated testing method and apparatus provided in an embodiment of the present application. In the embodiment of the present application, the computer device 100 may be a terminal or a server, and the terminal may be, but is not limited to, a PC (Personal Computer), a laptop, etc. The server may be, but is not limited to, a network server, a database server, a cloud server, or a server integration consisting of multiple sub-servers, etc. Of course, the above-listed devices are only used to facilitate the understanding of the embodiments of the present application, and should not be used as a limitation on the embodiments.

[0042] Structurally, the computer device 100 may include a processor 110 and a memory 120 .

[0043] The processor 110 is electrically connected to the memory 120 directly or indirectly to realize data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses or signal lines. The automated test device includes at least one software module stored in the memory 120 in the form of software or firmware or solidified in the operating system (OS) of the computer device 100. The processor 110 is used to execute the executable modules stored in the memory 120, for example, the software function modules and computer programs included in the automated test device, to realize the automated test method. The processor 110 can execute the computer program after receiving the execution instruction.

[0044] The processor 110 may be an integrated circuit chip with signal processing capability. The processor 110 may also be a general-purpose processor, for example, a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. In addition, the general-purpose processor may be a microprocessor or any conventional processor, etc.

[0045] The memory 120 may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), and an electric erasable programmable read-only memory (EEPROM). The memory 120 is used to store a program, and the processor 110 executes the program after receiving an execution instruction.

[0046] It should be noted that Figure 2 The structure shown is for illustration only. The computer device 100 provided in the embodiment of the present application may also have Figure 2 Fewer or more components, or with Figure 2 In addition, Figure 2 The components shown may be implemented by software, hardware or a combination thereof.

[0047] In the embodiment of the present application, the number of computer devices 100 may be one or more. When the number of computer devices 100 is more than one, the multiple computer devices 100 are communicatively connected with each other.

[0048] Optionally, when there are multiple computer devices 100, the multiple computer devices 100 may be connected in a non-encrypted access manner.

[0049] The hardware simulation accelerator 200 is described below. In the embodiment of the present application, the hardware simulation accelerator 200 runs files related to the chip to be tested.

[0050] Exemplarily, the entire verification environment is compiled and loaded into the hardware simulation accelerator 200, so that the hardware simulation accelerator 200 simulates the relevant functions of the chip to be tested. The verification environment includes the RTL (Register Transfer Level) code and testbench (test platform) code of the chip to be tested. The above loading is equivalent to allocating the calculation work of a large IC (Integrated Circuit) design to each unit in the hardware simulation accelerator 200.

[0051] The RTL code and testbench code of the chip under test mentioned above are files related to the chip under test.

[0052] See also Figure 3 , Figure 3 A schematic diagram of a possible hardware connection relationship before testing. Specifically, the hardware simulation accelerator 200 is physically connected to multiple computer devices 100 (computer device A, computer device B and computer device C) through optical fibers, and multiple computer devices 100 are connected through non-encrypted access. The hardware simulation accelerator 200 can support but is not limited to Ethernet interface, SATA (Serial Advanced Technology Attachment, serial hard disk) interface, USB (Universal Serial Bus, universal serial bus) interface, PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) interface, display interface.

[0053] The above interfaces can be divided into two categories. Among them, the first type of interface requires a motherboard when connecting to the test, such as USB interface and PCIE interface. The second type of interface does not require a motherboard when connecting to the test, such as Ethernet interface, SATA interface, and display interface.

[0054] For the first type of interface, during testing, the connection relationship may be: the first type of interface of the hardware simulation accelerator 200 is connected to one end of the optical fiber, and the other end of the optical fiber is connected to the speed bridge corresponding to the interface through a tpod (a hardware connector). The speed bridge is plugged into the motherboard for power supply, and the corresponding peripheral card is plugged into another slot on the motherboard.

[0055] It should be noted that for the test of high-speed peripherals, in the real system, the speed of high-speed peripherals is very high, such as the transmission rate of PCIE4.0 is 16GT / s (unit: gigatransfer / second), while when tested on the hardware emulation accelerator 200, the speed is very slow, and the speed on the real board is about 2000 times faster than that on the hardware emulation accelerator 200. Therefore, for the test of high-speed peripherals, the speed is reduced by the speed reduction bridge to match the speed of the hardware emulation accelerator 200.

[0056] For example, when the first type of interface is a USB interface, the USB interface is connected to one end of the optical fiber, and the other end of the optical fiber is connected to a speed reduction bridge corresponding to the USB interface through a tpod. The speed reduction bridge is plugged into the motherboard for power supply, and another slot on the motherboard is plugged into a corresponding peripheral card, such as a USB flash drive (short for USB flash drive) or a mouse.

[0057] When the first type of interface is a PCIE interface, the PCIE interface is connected to one end of the optical fiber, and the other end of the optical fiber is connected to the speed reduction bridge corresponding to the PCIE interface through a tpod. The speed reduction bridge is plugged into the motherboard for power supply, and at the same time, another slot on the motherboard is plugged into the corresponding peripheral card, such as SATA, SSD (Solid State Disk or Solid State Drive), NIO (Non-blocking IO, non-blocking input and output), and network card. Among them, the network card can be a gigabit network card or a 10G network card, and this application does not limit it. When the network card is a gigabit network card, the gigabit network card is connected to the computer device 100 via a gigabit network cable; when the network card is a 10G network card, the 10G network card is connected to the computer device 100 via a 10G network cable.

[0058] For the second type of interface, during testing, the connection relationship may be: the second type of interface of the hardware simulation accelerator 200 is connected to the corresponding speed reduction bridge of the interface through an optical fiber line, and a power supply box (chasis) is used to power the speed reduction bridge, and the speed reduction bridge is also connected to the computer device 100 through an optical fiber. At the same time, the speed reduction bridge is physically connected to the peripheral device.

[0059] Exemplarily, when the first type of interface is an Ethernet interface, the Ethernet interface of the hardware emulation accelerator 200 is connected to a speed reduction bridge corresponding to the Ethernet interface through an optical fiber line, and a power supply box is used to power the speed reduction bridge, and the speed reduction bridge is also connected to the computer device 100 through an optical fiber. At the same time, the speed reduction bridge is physically connected to the network cable. The network cable is also physically connected to the computer device 100. Among them, the network cable can be a gigabit network cable or a 10 gigabit network cable, which is not limited in this application.

[0060] When the first type of interface is a SATA interface, the SATA interface of the hardware emulation accelerator 200 is connected to a speed reduction bridge corresponding to the SATA interface through an optical fiber line, and a power supply box is used to power the speed reduction bridge, which is also connected to the computer device 100 through an optical fiber. At the same time, the speed reduction bridge is physically connected to the SATA or SSD.

[0061] In addition, when the first type of interface is a display interface, the display interface is directly connected to the PC through a network cable.

[0062] It should be noted that, regarding the connection method of each interface of the hardware simulation accelerator 200 during the simulation process, please refer to the prior art, and no further details will be given here.

[0063] The following is an explanation of the automated testing method provided in the embodiment of the present application. Figure 4 , Figure 4 The following is a flowchart of the steps of the automated testing method provided in the embodiment of the present application. The method can be applied to Figure 1 The automated testing system 10 shown in FIG. Figure 3 The connection relationship shown completes the construction of the hardware environment (which type of interface is required for testing, then the corresponding hardware connection relationship is established). It should be noted that the automated testing method provided in the embodiment of the present application is not based on Figure 4 The order shown below is limited, and the method includes: step S101-step S104.

[0064] Step S101: the computer device 100 receives a simulation start instruction initiated by a user.

[0065] When the user needs to test the function to be tested of the chip to be tested, the chip to be tested can be simulated by the hardware simulation accelerator 200. If the hardware simulation accelerator 200 is configured with files related to the chip to be tested, the hardware simulation accelerator 200 can simulate the relevant functions of the chip to be tested. Then, the user connects the corresponding interface according to the function to be tested. If the user needs to test the connection function of the USB interface of the chip to be tested, the USB interface is connected to one end of the optical fiber, and the other end of the optical fiber is connected to the speed reduction bridge corresponding to the USB interface through tpod. The speed reduction bridge is plugged into the motherboard for power supply, and another slot on the motherboard is plugged with a USB flash drive.

[0066] For example, when the user needs to test the network card function of the chip under test, the PCIE interface is connected to one end of the optical fiber, and the other end of the optical fiber is connected to the speed reduction bridge corresponding to the PCIE interface through the tpod. The speed reduction bridge is inserted into the motherboard for power supply, and the gigabit network card is inserted into another slot on the motherboard.

[0067] For example, when the user needs to test the SATA function of the chip under test, the PCIE interface is connected to one end of the optical fiber, and the other end of the optical fiber is connected to the speed reduction bridge corresponding to the PCIE interface through the tpod. The speed reduction bridge is plugged into the motherboard for power supply, and the other slot on the motherboard is plugged into the SATA.

[0068] After the user has built the above hardware environment, he can send a start simulation instruction to the computer device 100. For example, the user can click a button to start simulation on the test interface displayed by the computer device 100.

[0069] The above-mentioned users may be testers who perform automated testing.

[0070] Step S102: after receiving the start simulation instruction initiated by the user, the computer device 100 executes the first connection function of the test script to trigger the hardware simulation accelerator 200 to execute the first connection command.

[0071] When the computer device 100 receives the start simulation instruction initiated by the user, it executes the first connection function in the test script to trigger the hardware simulation accelerator 200 to execute the first connection command through the first connection function.

[0072] In a possible implementation, the test script may be an expect script. Of course, in other implementations, the test script may be written in other languages, as long as the script can realize automatic human-computer interaction, such as shell, python, ruby, etc.

[0073] Step S103 : the hardware emulation accelerator 200 executes the first connection command to achieve communication connection between the computer device 100 and the hardware emulation accelerator 200 .

[0074] The computer device 100 and the hardware emulation accelerator 200 can be communicatively connected through the first connection command of the hardware emulation accelerator 200 itself.

[0075] In the embodiment of the present application, the first connection command executed by the hardware emulation accelerator 200 may be its own XeClient command. Of course, in other embodiments, it may also be other connection commands supported by the hardware emulation accelerator 200 that can realize the above communication connection.

[0076] Step S104: after the hardware simulation accelerator 200 executes the first connection command, the computer device 100 executes the configuration function of the test script to configure the function to be tested of the chip to be tested based on the configuration process corresponding to the configuration function.

[0077] After the hardware emulation accelerator 200 executes the first connection command to realize the communication connection with the hardware emulation accelerator 200, the computer device 100 executes the configuration function of the test script, and then configures the function to be tested of the chip to be tested based on the configuration process corresponding to the configuration function. When executing the configuration function of the test script, the computer device 100 outputs the configuration instructions corresponding to each configuration process, and automatically performs the configuration of the next configuration process when the previous configuration process is completed.

[0078] Exemplarily, after the computer device 100 establishes a communication connection with the hardware simulation accelerator 200, the first configuration process in the configuration function of the test script is executed, that is, the computer device 100 outputs the configuration instructions corresponding to the first configuration process to the hardware simulation accelerator 200. The hardware simulation accelerator 200 is configured based on the first configuration process. When the computer device 100 determines that the first configuration process of the hardware simulation accelerator 200 is completed, the second configuration process in the configuration function of the test script is executed, that is, the computer device 100 outputs the instructions corresponding to the second configuration process to the hardware simulation accelerator 200. The hardware simulation accelerator 200 is configured based on the second configuration process. And so on, until the computer device 100 executes all configuration processes in the configuration function of the test script.

[0079] The above configuration process may specifically include uboot (universal boot loader, boot loader) booting, operating system (operating system, os) booting, driver loading of the function to be tested and parameter configuration of the function to be tested.

[0080] Among them, uboot booting is the first configuration process, operating system booting is the second configuration process, driver loading of the function to be tested is the third configuration process, and parameter configuration of the function to be tested is the fourth configuration process.

[0081] Exemplarily, when the function to be tested is a network card function, the third configuration process is loading the driver of the network card, and the fourth configuration process is configuring the IP (Internet Protocol) address.

[0082] When the function to be tested is the function of connecting the PCIE interface to SATA, the third configuration process is the installation of the SATA driver, and the fourth configuration process is to mount the SATA.

[0083] It can be seen that in the embodiment of the present application, when the configuration process includes uboot booting, operating system booting, driver loading of the function to be tested, and parameter configuration of the function to be tested, full-stage automated configuration can be achieved.

[0084] In summary, in the embodiment of the present application, after receiving the start simulation instruction initiated by the user, the computer device 100 can automatically execute the first connection function of the test script to trigger the hardware simulation accelerator to execute the first connection command, thereby establishing a communication connection between the computer device 100 and the hardware simulation accelerator 200. In this way, the interaction between the computer device 100 and the hardware simulation accelerator 200 can be achieved, thereby facilitating the subsequent computer device to complete the configuration of the hardware simulation accelerator 200 through the configuration function of the test script. In addition, since the test script will output the configuration instructions corresponding to each configuration process, and automatically perform the configuration of the next configuration process when the previous configuration process is completed, the above method reduces the manual intervention of the hardware simulation accelerator 200 in the configuration process, and improves the configuration efficiency.

[0085] In one embodiment, the hardware simulation accelerator 200 also runs a serial port model. The serial port model can be understood as a model abstracted based on the characteristics of the serial port chip itself. The serial port model has the following characteristics: first, it simulates the serial port chip (the functions of the two are completely equivalent); second, the input value and output value of the serial port model and the serial port chip are the same.

[0086] In the embodiment of the present application, the serial port model is configured to use the force mode of the hardware simulation accelerator 200 for input and the display cache (display) mode of the debugging script language supported by the hardware simulation accelerator 200 for output.

[0087] The debugging script language supported by the hardware simulation accelerator 200 may be State Description Language (SDL).

[0088] See also Figure 5 When the computer device 100 executes the configuration function of the test script, the interaction process with the hardware simulation accelerator 200 may specifically include: step S201-step S205.

[0089] Step S201: the computer device 100 outputs a first configuration instruction corresponding to a first configuration process to the serial port model through a test script, so that the serial port model inputs the first configuration instruction into the hardware simulation accelerator 200 by force; the first configuration process is any one of each configuration process.

[0090] Step S202: after receiving the first configuration instruction, the serial port model running in the hardware simulation accelerator 200 inputs the first configuration instruction into the hardware simulation accelerator 200 by force, so that the hardware simulation accelerator 200 executes the first configuration instruction for configuration.

[0091] Step S203: the serial port model run by the hardware emulation accelerator 200 captures the actual characters generated when executing the first configuration instruction through the debugging script language supported by the hardware emulation accelerator 200, and outputs the actual characters to the computer device through a display cache.

[0092] Step S204: the computer device 100 compares the preset expected completion characters with the actual characters through the comparison instructions in the configuration function to determine whether the first configuration process is completed.

[0093] It should be noted that, in the present embodiment, the expected completion characters corresponding to each configuration process are pre-set in the test script. After the computer device 100 receives the actual characters output by the serial port model run by the hardware simulation accelerator 200, the actual characters are compared with the expected completion characters corresponding to the current configuration process. If the current configuration process is the first configuration process, the computer device compares the actual characters with the expected completion characters corresponding to the first configuration process through the comparison instructions in the configuration function. If the actual characters are the same as the expected completion characters corresponding to the first configuration process, it is determined whether the first configuration process is the last configuration process. If the first configuration process is not the last configuration process, step S205 is executed. If the first configuration process is the last configuration process, the automated configuration of the hardware simulation accelerator 200 is completed.

[0094] If the actual character is different from the expected completed character corresponding to the first configuration process, it is determined that the first configuration process is not completed, and the hardware simulation accelerator 200 continues to wait for the actual character output next time, or the user is notified to switch to the manual configuration mode so that the user can perform manual configuration.

[0095] Step S205: when the computer device 100 determines that the first configuration process is completed, the computer device 100 outputs a second configuration instruction corresponding to the second configuration process to the serial port model through the test script, and the second configuration process is the next configuration process of the first configuration process.

[0096] When the computer device 100 determines that the first configuration process is completed and the first configuration process is not the last configuration process, the second configuration instruction corresponding to the second configuration process is automatically output to the serial port model through the test script, and the second configuration process is the next configuration process of the first configuration process. After the serial port model run by the hardware simulation accelerator 200 receives the second configuration instruction, the second configuration instruction is input into the hardware simulation accelerator 200 by force, so that the hardware simulation accelerator 200 executes the second configuration instruction for configuration. Then the serial port model run by the hardware simulation accelerator 200 captures the actual characters generated when executing the second configuration instruction through the debugging script language supported by the hardware simulation accelerator 200, and outputs the latest actual characters to the computer device 100 through the display cache method. The computer device 100 compares the latest actual characters with the expected completion characters corresponding to the second configuration process through the comparison instructions in the configuration function. If the latest actual characters are the same as the expected completion characters corresponding to the second configuration process, it is determined whether the second configuration process is the last configuration process. If the second configuration process is not the last configuration process, the third configuration instruction corresponding to the third configuration process is output to the serial port model through the test script, and the third configuration process is the next configuration process of the second configuration process, and so on. If the second configuration process is the last configuration process, the automatic configuration of the hardware simulation accelerator 200 is completed.

[0097] Exemplarily, when the function to be tested is a network card function, the above process specifically includes: the computer device 100 outputs the configuration instructions corresponding to the uboot boot to the serial port model through the test script. After the serial port model run by the hardware emulation accelerator 200 receives the configuration instruction, the configuration instruction is input into the hardware emulation accelerator 200 by force, so that the hardware emulation accelerator 200 performs uboot boot. Then, the serial port model run by the hardware emulation accelerator 200 captures the actual characters generated when executing the configuration instruction through the debugging script language supported by the hardware emulation accelerator 200, and outputs the actual characters to the computer device 100 by displaying the cache mode. The computer device 100 compares the expected completion characters set in advance with the actual characters through the comparison instructions in the configuration function to determine whether the uboot boot is completed. When the computer device 100 determines that the uboot boot is completed, the configuration instructions corresponding to the operating system boot are output to the serial port model through the test script. After the serial port model run by the hardware emulation accelerator 200 receives the configuration instruction, the configuration instruction is input into the hardware emulation accelerator 200 by force, so that the hardware emulation accelerator 200 performs the operating system boot. Then, the serial port model run by the hardware emulation accelerator 200 captures the actual characters generated when executing the configuration instruction through the debugging script language supported by the hardware emulation accelerator 200, and outputs the actual characters to the computer device 100 through the display cache mode. The computer device 100 compares the preset expected completion characters with the actual characters through the comparison instructions in the configuration function to determine whether the operating system boot is completed. When the computer device 100 determines that the operating system boot is completed, it outputs the configuration instructions corresponding to the network card driver loading to the serial port model through the test script. After the serial port model run by the hardware emulation accelerator 200 receives the configuration instruction, it inputs the configuration instruction into the hardware emulation accelerator 200 through the force mode, so that the hardware emulation accelerator 200 loads the network card driver. Then, the serial port model run by the hardware emulation accelerator 200 captures the actual characters generated when executing the configuration instruction through the debugging script language supported by the hardware emulation accelerator 200, and outputs the actual characters to the computer device 100 through the display cache mode. The computer device 100 compares the expected completion characters and the actual characters in the configuration function through the comparison instructions in the configuration function to determine whether the network card driver loading is completed. When the computer device 100 determines that the network card driver loading is completed, it outputs the configuration instructions corresponding to the configuration of the IP address to the serial port model through the test script. After the serial port model running the hardware simulation accelerator 200 receives the configuration instructions, it inputs the configuration instructions into the hardware simulation accelerator 200 through the force method, so that the hardware simulation accelerator 200 configures the IP address (wherein the IP address is configured to be in the same network segment as the connected computer device).Then, the serial port model run by the hardware emulation accelerator 200 captures the actual characters generated when executing the configuration instruction through the debugging script language supported by the hardware emulation accelerator 200, and outputs the actual characters to the computer device 100 through the display cache. The computer device 100 compares the preset expected completion characters with the actual characters through the comparison instructions in the configuration function to determine whether the configuration of the IP address is completed. When the configuration of the IP address is completed, the automatic configuration of the hardware emulation accelerator 200 when the function to be tested is the network card function is completed.

[0098] It can be seen that in the embodiment of the present application, by replacing the traditional serial port chip with a serial port model, the configuration difficulty of the hardware simulation accelerator 200 in the hardware environment can be reduced. And the serial port model sends the actual characters output to the computer device 100 by displaying the cache, which is convenient for the user to intuitively see the process of each configuration stage, and also convenient for the user to analyze the problem, which greatly improves the test efficiency in complex scenarios. In addition, the computer device 100 can compare the preset expected completion characters with the actual characters output by the serial port model through the comparison instructions in the configuration function, and then determine whether to output the configuration instructions corresponding to the next configuration process to the serial port model according to the comparison results, so as to realize the automatic triggering of the next configuration process, and then realize the automation of the entire configuration process of the test script.

[0099] Optionally, the actual characters are recognized and successfully recognized by the serial port model before being output through the display buffer.

[0100] That is, a function to prevent character loss can also be added to the serial port model. Take the debugging script language supported by the hardware simulation accelerator 200 as an example, SDL. After the serial port model captures the character, it uses the SDL load function in SDL to detect whether the character has been recognized by the SDL tool through the load function before the character is output. If recognized, it is output. Otherwise, the serial port model will automatically re-enter the previously input characters into SDL to ensure that the characters can be recognized after loading, so as to ensure that the input characters can be correctly output.

[0101] It can be seen that in the embodiment of the present application, the serial port model is also used to recognize characters before the actual characters are output. The serial port model will output the characters only if they can be recognized successfully. In this way, the accuracy and reliability of the serial port model in application can be guaranteed, and the problem of the serial port model still outputting the characters when they are missing, which will cause errors in subsequent comparison, can be avoided.

[0102] In addition, the hardware simulation accelerator 200 can also use a traditional serial port chip to implement the input of instructions and the output of actual characters, which is not limited in this application.

[0103] After completing the automatic configuration of the hardware simulation accelerator 200, the function to be tested of the chip to be tested can be tested.

[0104] In some embodiments, if it is determined that the previous configuration process is completed and the previous configuration process is the last process in the configuration process, the function to be tested can be automatically triggered to be tested, or it can be switched to manual triggering, and the user can manually test the function to be tested.

[0105] The following will take the case of automatically triggering a test on the function to be tested as an example to introduce the implementation method of automated testing.

[0106] In one embodiment, please continue to refer to Figure 3 The computer device 100 is also used to connect to other computer devices 100. The network card connected to the hardware simulation accelerator 200 is connected to other computer devices 100 through a network cable. After determining that the configuration process of the function to be tested of the chip to be tested has been completed, the method also includes: the computer device 100 executes the second connection function of the test script to realize the computer device 100 automatically remotely logs in to the hardware simulation accelerator 200, and tests the function to be tested by running the test program.

[0107] Specifically, after determining that the last configuration process of the function to be tested of the chip to be tested has been completed, the computer device 100 executes the second connection function of the test script, connects to the configured network through the SSH (Secure Shell) port of the computer device 100, then enters the hardware simulation accelerator 200 through the test script, and then runs the test program to test the function to be tested.

[0108] It can be seen that in the embodiment of the present application, when the network card connected to the hardware simulation accelerator 200 is connected to other computer devices 100 via optical fiber, and the computer device 100 connected to other computer devices 100 can automatically execute the second connection function of the test script after determining that the configuration process of the function to be tested has been completed, so that the computer device 100 can automatically log in to the hardware simulation accelerator remotely, and test the function to be tested through the test program. In this way, manual intervention in the testing process of the function to be tested can be reduced, thereby realizing the full process automation from the configuration of the hardware simulation accelerator 200 to the testing of the function to be tested.

[0109] In the embodiment of the present application, the test script may be an expect script, and the computer device 100 executes the second connection function of the test script, including: the computer device 100 connects the SSH port of the computer device 100 to the network configured by the hardware simulation accelerator 200 through the spawn command in the expect script. The spawn command is provided with the address of the network.

[0110] In the embodiment of the present application, the spawn command in the expect script is modified and carries the address of the network, so as to connect the SSH port of the computer device 100 to the network configured by the hardware simulation accelerator 200. Further, because the spawn command has the function of starting a new process, it can meet the requirements of simultaneously starting the test connection between multiple computer devices 100 and the hardware simulation accelerator 200, and then multiple functions to be tested of the chip to be tested can be tested simultaneously.

[0111] Take the network card test process as an example: when the network card driver has been successfully loaded and the IP address has been configured, the computer device 100 executes the second connection function of the test script. The configured network is connected through the SSH (Secure Shell) of the computer device 100, and the computer device 100 connects to the network through the spawn command in the expect script. The spawn command in the expect script can be spawn sh-c "ssh-t server1 telnet$IP_ADDR". Finally, enter the hardware simulation accelerator 200 through the test script, and then run the network card test program for testing. Among them, the network card test program can be a network performance test program.

[0112] Take the functional test process of connecting the PCIE interface to SATA as an example: when the SATA driver has been loaded successfully and mounted successfully, the next step is the same as the network card test process, and the configured network is connected through the SSH (Secure Shell) of the computer device 100. The computer device 100 connects to the network through the spawn command in the expect script. The spawn command in the expect script can be spawn sh-c "ssh-t server1 telnet$IP_ADDR". Finally, enter the hardware simulation accelerator 200 through the test script, and then run the SATA test program for testing. Among them, the SATA test program can be a disk performance test program.

[0113] In addition, it should be noted that when there are multiple computer devices 100, only one of the computer devices 100 needs to be connected to the configured network. Since the computer devices 100 are connected to each other, the test can be performed on multiple computer devices 100 at the same time. Of course, any computer device 100 can also be selected to perform the test of the function to be tested. Figure 6 As shown, after computer device A is connected to the configured network, computer device A can establish two test connections with the hardware simulation accelerator 200 to perform a network card test and a SATA test respectively. At this time, computer device B can also establish a test connection with the hardware simulation accelerator 200 to perform a USB test.

[0114] In one embodiment, the computer device 100 is also used to connect to other computer devices 100 through non-password access. For example, Figure 3 In the example, computer device A and computer device B can access each other without secrets, computer device A and computer device C can access each other without secrets, and computer device B and computer device C can access each other without secrets.

[0115] In the embodiment of the present application, since the computer device 100 can be connected to other computer devices 100 through non-encrypted access, different computer devices 100 can quickly access the hardware simulation accelerator 200 and perform testing.

[0116] See also Figure 7 Based on the same inventive concept, the embodiment of the present application further provides an automated testing device 300, which is applied to a computer device 100, wherein the computer device 100 is used to be physically connected to a hardware simulation accelerator 200, and the hardware simulation accelerator 200 runs files related to the chip to be tested to test the function to be tested of the chip to be tested; the automated testing device 300 includes:

[0117] The starting module 310 is used to receive a simulation starting instruction initiated by a user.

[0118] A first connection module 320 is used to execute a first connection function of a test script after the start module receives a start simulation instruction initiated by a user, so as to trigger the hardware simulation accelerator to execute a first connection command, thereby realizing a communication connection between the computer device and the hardware simulation accelerator;

[0119] The configuration module 330 is used to execute the configuration function of the test script after the hardware simulation accelerator executes the first connection command, so as to configure the function to be tested of the chip to be tested based on the configuration process corresponding to the configuration function; wherein, when executing the configuration function of the test script, the test script outputs the configuration instructions corresponding to each configuration process, and automatically performs the configuration of the next configuration process when the previous configuration process is completed.

[0120] Optionally, the hardware simulation accelerator also runs a serial port model; the configuration module 330 is specifically used to output a first configuration instruction corresponding to a first configuration process to the serial port model through the test script, so that the serial port model inputs the first configuration instruction into the hardware simulation accelerator by force; the first configuration process is any one of the configuration processes; receiving actual characters output by the serial port model through a display cache, the actual characters are characters generated when the hardware simulation accelerator executes the first configuration instruction and captured by a debugging script language supported by the hardware simulation accelerator; through the comparison instructions in the configuration function, the pre-set expected completion characters are compared with the actual characters to determine whether the first configuration process is completed; when it is determined that the first configuration process is completed and the first configuration process is not the last configuration process, outputting a second configuration instruction corresponding to the second configuration process to the serial port model through the test script, and the second configuration process is the next configuration process of the first configuration process.

[0121] Optionally, the configuration process in the configuration module 330 includes uboot booting, operating system booting, driver loading of the function to be tested, and parameter configuration of the function to be tested.

[0122] Optionally, the computer device is also used to connect to other computer devices, and the network card connected to the hardware simulation accelerator is connected to the other computer devices via a network cable. The automated testing device 300 further includes: a second connection module;

[0123] The second connection module is used to execute the second connection function of the test script after determining that the configuration process of the function to be tested of the chip to be tested has been completed, so as to realize the automatic remote login of the computer device to the hardware simulation accelerator and test the function to be tested by running the test program.

[0124] Optionally, the test script is an expect script. The second connection module is specifically used to connect the SSH port of the computer device to the network configured by the hardware simulation accelerator through a spawn command in the expect script; wherein the spawn command is provided with an address of the network.

[0125] It should be noted that, since technicians in the relevant field can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0126] Based on the same inventive concept, an embodiment of the present application further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed, the method provided in the above embodiment is executed.

[0127] The storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, a tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

[0128] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0129] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0130] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0131] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0132] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An automated testing method, characterized in that: Applied to a computer device, the computer device is used to be physically connected to a hardware simulation accelerator, the hardware simulation accelerator runs a file related to a chip to be tested to test a function to be tested of the chip to be tested; the method comprises: After receiving the start simulation instruction initiated by the user, the computer device executes the first connection function of the test script to trigger the hardware simulation accelerator to execute the first connection command to achieve the communication connection between the computer device and the hardware simulation accelerator; After the hardware simulation accelerator executes the first connection command, the computer device executes the configuration function of the test script to configure the function to be tested of the chip to be tested based on the configuration process corresponding to the configuration function; Among them, when executing the configuration function of the test script, the test script outputs the configuration instructions corresponding to each configuration process, and automatically performs the configuration of the next configuration process when the previous configuration process is completed, which includes the computer device outputting the configuration instructions corresponding to the first configuration process in the configuration function of the test script to the hardware simulation accelerator, and when the first configuration process is completed, the computer device outputs the configuration instructions corresponding to the second configuration process in the configuration function of the test script to the hardware simulation accelerator, until all configuration processes in the configuration function of the test script are executed.

2. The method according to claim 1, characterized in that The hardware simulation accelerator also runs a serial port model; the configuration function of executing the test script includes: The computer device outputs a first configuration instruction corresponding to a first configuration process to the serial port model through the test script, so that the serial port model inputs the first configuration instruction into the hardware simulation accelerator by force; the first configuration process is any one of the configuration processes; The computer device receives actual characters output by the serial port model in a display buffer manner, wherein the actual characters are characters generated when the hardware emulation accelerator executes the first configuration instruction and captured by a debugging script language supported by the hardware emulation accelerator; The computer device compares the preset expected completion character with the actual character through the comparison instruction in the configuration function to determine whether the first configuration process is completed; When the computer device determines that the first configuration process is completed and the first configuration process is not the last configuration process, the computer device outputs a second configuration instruction corresponding to a second configuration process to the serial port model through the test script, and the second configuration process is the next configuration process of the first configuration process.

3. The method according to claim 2, characterized in that The actual characters are recognized and successfully recognized by the serial port model before being outputted through the display buffer mode.

4. The method according to claim 1, characterized in that: The configuration process includes uboot booting, operating system booting, driver loading of the function to be tested, and parameter configuration of the function to be tested.

5. The method according to any one of claims 1 to 4, characterized in that The computer device is also used to connect to other computer devices, and the network card connected to the hardware simulation accelerator is connected to the other computer devices through a network cable. After determining that the configuration process of the function to be tested of the chip to be tested has been completed, the method further includes: The computer device executes the second connection function of the test script to enable the computer device to automatically remotely log in to the hardware simulation accelerator, and to test the function to be tested by running a test program.

6. The method according to claim 5, characterized in that The test script is an expect script, and the computer device executes the second connection function of the test script, including: The computer device connects the SSH port of the computer device to the network configured by the hardware simulation accelerator through the spawn command in the expect script; wherein the address of the network is set in the spawn command.

7. The method according to claim 5, characterized in that The computer device is also used to connect with the other computer devices through non-password access.

8. An automated testing device, characterized in that: Applied to a computer device, the computer device is used to be physically connected to a hardware simulation accelerator, the hardware simulation accelerator runs a file related to a chip to be tested to test a function to be tested of the chip to be tested; the device comprises: A startup module, used for receiving a startup simulation instruction initiated by a user; A first connection module, configured to execute a first connection function of a test script after the startup module receives a startup simulation instruction initiated by a user, so as to trigger the hardware simulation accelerator to execute a first connection command, thereby realizing a communication connection between the computer device and the hardware simulation accelerator; A configuration module is used to execute the configuration function of the test script after the hardware simulation accelerator executes the first connection command, so as to configure the function to be tested of the chip to be tested based on the configuration process corresponding to the configuration function; wherein, when executing the configuration function of the test script, the test script outputs the configuration instructions corresponding to each configuration process, and automatically performs the configuration of the next configuration process when the previous configuration process is completed, which includes the computer device outputting the configuration instructions corresponding to the first configuration process in the configuration function of the test script to the hardware simulation accelerator, and when the first configuration process is completed, the computer device outputs the configuration instructions corresponding to the second configuration process in the configuration function of the test script to the hardware simulation accelerator, until all configuration processes in the configuration function of the test script are executed.

9. A computer device, characterized in that: include: A processor and a memory, the processor and the memory being connected; The memory is used to store programs; The processor is configured to run a program stored in the memory to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a computer, the method according to any one of claims 1 to 7 is executed.

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