Simulation method and device for FPGA

Abstract

The present disclosure relates to a simulation method, device, electronic device and computer-readable medium for FPGA. The method includes: generating simulation code and simulation file based on the FPGA to be simulated; configuring write address, write data and read address for the data storage module; simulating the FPGA through front-door simulation based on the simulation code, the simulation file and the configured data storage module, and generating simulation results; and / or simulating the FPGA through back-door simulation based on the simulation code, the simulation file and the configured data storage module, and generating simulation results. The simulation method, device, electronic device and computer-readable medium for FPGA involved in the present application can simulate the FPGA more flexibly and more specifically, and the simulation results are more diverse and complete.

Description

Technical Field

[0001] The present disclosure relates to the field of FPGA simulation analysis, and more specifically, to a simulation method, device, electronic device and computer-readable medium for FPGA; and the field of computer information processing, and more specifically, to a message data parsing method, device, equipment, electronic device and computer-readable medium. Background Art

[0002] For FPGA simulation, Questasim is the most commonly used tool. The current simulation process is: use Tcl as stimulus to perform overall simulation verification. However, the Tcl stimulus method cannot simulate a single module, and the Tcl stimulus is relatively simple, and many situations cannot be simulated. In general, the use of Tcl as a stimulus method is not targeted, flexible, and has a small scope of application.

[0003] The main files needed for simulation verification by sending stimulus using Tcl are divided into three parts: simulation startup file, stimulus and code. The code is the code to be tested, the stimulus contains Tcl files, and the simulation startup file can start Questasim.

[0004] The overall simulation process is as follows Figure 1 As shown. Run . / runtest.lnx|grep Err in the simulation startup file directory. First open the questasim simulation software and run the tcl file to send the stimulus into the code. Then select the code to be simulated in questasim and add it to the waveform. After running for a while, you can see the waveform. The waveform interface is the user monitoring interface.

[0005] The method of using tcl to insert stimulus into the code cannot simulate a specific module. In addition, no additional signals can be added during the simulation. The stimulus inserted by tcl is also relatively simple, and multiple stimulus cannot be added at will.

[0006] Therefore, a new simulation method, device, electronic device and computer-readable medium for FPGA are needed.

[0007] The above information disclosed in the Background section is only for enhancement of understanding of the background of the present application and therefore it may contain information that does not constitute the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0008] In view of this, the present application provides a simulation method, device, electronic device and computer-readable medium for FPGA, which can simulate FPGA more flexibly and more specifically, and the simulation results are more diverse and complete.

[0009] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0010] According to one aspect of the present application, a simulation method for FPGA is proposed, the method comprising: generating simulation code and simulation file based on the FPGA to be simulated; configuring write address, write data and read address for the data storage module; simulating the FPGA by front-door simulation based on the simulation code, the simulation file and the configured data storage module, and generating simulation results; and / or simulating the FPGA by back-door simulation based on the simulation code, the simulation file and the configured data storage module, and generating simulation results.

[0011] In an exemplary embodiment of the present application, simulation code and simulation files are generated based on the FPGA to be simulated, including: generating the simulation code based on the tested code of the FPGA to be simulated; generating the simulation file based on a python file, a simulation run file, a systemverilog file, and a stimulus file.

[0012] In an exemplary embodiment of the present application, a write address, write data and a read address are configured for a data storage module, including: writing a write address, write data and a read address for the data storage module; configuring the data storage module so that the data storage module outputs data in the form of read data when the write address matches the read address.

[0013] In an exemplary embodiment of the present application, the FPGA is simulated by front-door simulation based on the simulation code, the simulation file, and the configured data storage module, and a simulation result is generated, including: the data storage module obtains a first write address and a second write address; matches the first write address and the second write address; and transmits successfully matched data back to the simulation code.

[0014] In an exemplary embodiment of the present application, the data storage module obtains a first write address and a second write address, including: writing the value of the register into the simulation code through the register configuration bus; the simulation code passes the value of the register into the data storage module to generate a first write address; passing at least one stimulus to the table entry function through the SystemVerilog file; the data storage module obtains the corresponding second write address by calling the table entry function.

[0015] In an exemplary embodiment of the present application, the FPGA is simulated by front-door simulation based on the simulation code, the simulation file, and the configured data storage module, and simulation results are generated, which also includes: inputting a read register instruction; opening a graphical interface; and viewing the simulation waveform based on the fmbus in the simulation code.

[0016] In an exemplary embodiment of the present application, the FPGA is simulated by backdoor simulation based on the simulation code, the simulation file, and the configured data storage module, and a simulation result is generated, including: the data storage module obtains the third write address and the fourth write address; the third write address and the fourth write address are matched; if the match is successful, the SystemVerilog function value is returned to the C function.

[0017] In an exemplary embodiment of the present application, the data storage module obtains a third write address and a fourth write address, including: a C function calls a simulation code based on a parameter module to perform a write operation on a register; a third write address is generated based on the write operation; at least one stimulus is passed to a table entry function through a SystemVerilog file; and the data storage module obtains a fourth write address corresponding to the table entry function by calling the table entry function.

[0018] In an exemplary embodiment of the present application, the FPGA is simulated by backdoor simulation based on the simulation code, the simulation file, and the configured data storage module, and simulation results are generated, which also includes: calling a C function to view the simulation waveform.

[0019] According to one aspect of the present application, a simulation device for FPGA is proposed, which includes: a data module, which is used to generate simulation code and simulation files based on the FPGA to be simulated; an address module, which is used to configure write addresses, write data and read addresses for data storage modules; a front-door simulation module, which is used to simulate the FPGA through front-door simulation based on the simulation code, the simulation file and the configured data storage module, and generate simulation results; and / or a back-door simulation module, which is used to simulate the FPGA through back-door simulation based on the simulation code, the simulation file and the configured data storage module, and generate simulation results.

[0020] According to one aspect of the present application, an electronic device is proposed, which includes: one or more processors; a storage device for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the method as described above.

[0021] According to one aspect of the present application, a computer-readable medium is provided, on which a computer program is stored. When the program is executed by a processor, the method described above is implemented.

[0022] According to the simulation method, device, electronic device and computer-readable medium for FPGA of the present application, by generating simulation code and simulation file based on the FPGA to be simulated; configuring write address, write data and read address for the data storage module; simulating the FPGA through front-door simulation based on the simulation code, the simulation file and the configured data storage module, and generating simulation results; and / or simulating the FPGA through back-door simulation based on the simulation code, the simulation file and the configured data storage module, and generating simulation results, the FPGA can be simulated more flexibly and more specifically, and the simulation results are more diverse and complete.

[0023] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the present application will become more apparent by describing in detail the exemplary embodiments thereof with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of the present application, and it is clear to a person skilled in the art that other accompanying drawings can be obtained from these accompanying drawings without creative effort.

[0025] Figure 1 It is a system block diagram of a simulation method for FPGA in the prior art.

[0026] Figure 2 The present invention is a flowchart of a simulation method for FPGA according to an exemplary embodiment.

[0027] Figure 3 The present invention is a working principle diagram of a data storage module in a simulation method for FPGA according to another exemplary embodiment.

[0028] Figure 4 The diagram is a schematic diagram of a mid-front door simulation of a simulation method for FPGA according to another exemplary embodiment.

[0029] Figure 5 The diagram is a schematic diagram of a middle-backdoor simulation of a simulation method for FPGA according to another exemplary embodiment.

[0030] Figure 6 The present invention is a block diagram of a simulation device for FPGA according to an exemplary embodiment.

[0031] Figure 7 It is a block diagram of an electronic device according to an exemplary embodiment.

[0032] Figure 8It is a block diagram of a computer-readable medium according to an exemplary embodiment. DETAILED DESCRIPTION

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0034] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0035] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0036] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0037] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the concepts of the present application. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more.

[0038] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present application, and therefore cannot be used to limit the scope of protection of the present application.

[0039] The technical abbreviations involved in this application are explained as follows:

[0040] tcl: A scripting language used to process strings.

[0041] makefile: stores commands. Executing make xxx can run the corresponding commands.

[0042] parameter: txt file, where the used parameters can be written. The C function will call it later.

[0043] entry_pkg: stores the messages sent from the platform to the fpga.

[0044] In view of various defects in the prior art, the present application proposes a simulation method for FPGA, which can perform overall simulation and single module simulation for a certain table item. At the same time, the simulation method in the present application can be used flexibly, for example, multiple stimuli can be added, simulation signals can be added at any time, etc. The technical content of the present application is described in detail below with the help of specific embodiments.

[0045] Figure 2 The flowchart of a simulation method for FPGA according to an exemplary embodiment is shown. The simulation method 20 for FPGA includes at least steps S202 to S208.

[0046] like Figure 2 As shown, in S202, simulation code and simulation files are generated based on the FPGA to be simulated. The simulation code can be generated based on the tested code of the FPGA to be simulated; the simulation file is generated based on the python file, the simulation run file, the systemverilog file, and the stimulus file. Furthermore, the simulation file includes the overall simulation file and the simulation files of each single module.

[0047] In one embodiment, the overall simulation is used as an example for explanation. The overall simulation file contains a python file, a simulation run file, a systemverilog file, and a stimulus file. The python file contains test stimulus and simulation environment automatic generation scripts, simulation IP core file generation scripts, and simulation output monitoring data and stimulus reference model data comparison scripts, etc. The simulation run file includes a C script compilation generation file, a list of table items and .v files used in the code, a makefile, etc. The systemverilog file is a file for the simulation environment (mainly a .sv file). The stimulus file can be written into the stimulus file.

[0048] In S204, the data storage module is configured with a write address, write data and a read address. The write address, write data and read address may be written to the data storage module; the data storage module is configured so that when the write address matches the read address, the data storage module outputs the data in the form of read data.

[0049] like Figure 3 As shown, write the write address, write data and read address to the storage module. When the write address matches the read address, the data is output in the form of read data.

[0050] In S206, the FPGA is simulated by front-door simulation based on the simulation code, the simulation file, and the configured data storage module, and a simulation result is generated.

[0051] In one embodiment, the register value is written into the simulation code through the register configuration bus; the simulation code transfers the register value to the data storage module to generate a first write address; at least one stimulus is transferred to the table entry function through the systemverilog file; the data storage module obtains the corresponding second write address by calling the table entry function. The data storage module obtains the first write address and the second write address; the first write address and the second write address are matched; and the matched data is returned to the simulation code.

[0052] In one embodiment, the method further includes: inputting a read register instruction; opening a graphical interface; and viewing a simulation waveform based on the fmbus in the simulation code.

[0053] In S208, the FPGA is simulated by backdoor simulation based on the simulation code, the simulation file, and the configured data storage module, and a simulation result is generated.

[0054] In one embodiment, the C function calls the simulation code based on the parameter file to perform a write operation on the register; generates a third write address based on the write operation; transmits at least one stimulus to the table entry function through the systemverilog file; the data storage module obtains the fourth write address corresponding to the table entry function by calling the table entry function. The data storage module obtains the third write address and the fourth write address; matches the third write address and the fourth write address; and returns the systemverilog function value to the C function if the match is successful.

[0055] In one embodiment, the method further includes: calling a C function to view a simulation waveform.

[0056] According to the simulation method for FPGA of the present application, by generating simulation code and simulation file based on the FPGA to be simulated; configuring write address, write data and read address for the data storage module; simulating the FPGA through front-door simulation based on the simulation code, the simulation file and the configured data storage module, and generating simulation results; and / or simulating the FPGA through back-door simulation based on the simulation code, the simulation file and the configured data storage module, and generating simulation results, the FPGA can be simulated more flexibly and more specifically, and the simulation results are more diverse and complete.

[0057] The simulation method for FPGA of the present application can perform overall simulation as well as single module simulation for a certain table item. At the same time, we need this simulation method to be more flexible, for example, multiple stimuli can be added, simulation signals can be added at any time, and so on.

[0058] The simulation method for FPGA of the present application adopts a new simulation method, which can make the simulation more flexible and meet the various needs of users. This method is divided into front-door simulation and back-door simulation. Front-door simulation is a simulation method that operates the register bus in the code to read and write the code, and the front-door simulation verification can be verified by waveform. Back-door simulation is a simulation method that does not pass through the bus of the code to read and write the register or table entry in the code, and the back-door simulation can view the result by calling the C function.

[0059] It should be clearly understood that the present application describes how to form and use specific examples, but the principles of the present application are not limited to any details of these examples. On the contrary, based on the teaching of the content disclosed in the present application, these principles can be applied to many other embodiments.

[0060] Figure 4 The diagram is a schematic diagram of a mid-front door simulation of a simulation method for FPGA according to another exemplary embodiment.

[0061] like Figure 4 As shown, for the simulation of the front door table, you can first run the compiled file of the C function in the directory of the simulation running file, write the value of the register through the register configuration bus, and get the first write address.

[0062] After the register value is written into the code, the code will call the data storage module and pass the register value into the data storage module.

[0063] Write stimulus in entry_pkg in the stimulus module. You can write multiple entries. Each entry function calls the function in systemverilog to pass the stimulus to each entry function. The data storage module will call the corresponding entry function to get the second write address of the data storage module.

[0064] In the data storage module, the first written address of the table entry function is matched with the second written address of the register. The matched data is transmitted back to the code in the form of output. If the match is unsuccessful, the read-back data is 0.

[0065] You can also add a command to read the register at the end of writing the register value, and then enter make post to open the graphical interface and compare it with the fmbus in the code to view the corresponding waveform.

[0066] Figure 5 The diagram is a schematic diagram of a middle-backdoor simulation of a simulation method for FPGA according to another exemplary embodiment.

[0067] like Figure 5 As shown, the backdoor simulation table below can first write the parameters in the parameter file, so that when the C function calls the parameter, the register in the code can be written to generate the third write address.

[0068] The stimulus is written in entry_pkg in the stimulus module and called by each table entry function in SystemVerilog. The data storage module calls the functions of each table entry in SystemVerilog and the C function.

[0069] Match the third address written into the register in the C function with the fourth address written into each table entry function. If the match is successful, return the function value in SystemVerilog to the C function. If the match is unsuccessful, the output data is 0.

[0070] You can also see the readback results by calling the C function.

[0071] Those skilled in the art will appreciate that all or part of the steps for implementing the above embodiments are implemented as a computer program executed by a CPU. When the computer program is executed by the CPU, the above functions defined by the above method provided in the present application are executed. The program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0072] In addition, it should be noted that the above figures are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present application, and are not intended to be limiting. It is easy to understand that the processes shown in the above figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.

[0073] The following is an embodiment of the device of the present application, which can be used to execute the embodiment of the method of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the method of the present application.

[0074] Figure 6 FIG. 1 is a block diagram of a simulation device for FPGA according to another exemplary embodiment. Figure 6 As shown, the simulation device 60 for FPGA includes: a data module 602 , an address module 604 , a front door simulation module 606 , and a back door simulation module 608 .

[0075] The data module 602 is used to generate simulation code and simulation files based on the FPGA to be simulated;

[0076] The address module 604 is used to configure the write address, write data and read address for the data storage module;

[0077] The front door simulation module 606 is used to simulate the FPGA through the front door simulation method based on the simulation code, the simulation file, and the configured data storage module, and generate simulation results; and / or

[0078] The backdoor simulation module 608 is used to simulate the FPGA through backdoor simulation based on the simulation code, the simulation file, and the configured data storage module, and generate simulation results.

[0079] According to the simulation device for FPGA of the present application, by generating simulation code and simulation file based on the FPGA to be simulated; configuring write address, write data and read address for the data storage module; simulating the FPGA through front-door simulation based on the simulation code, the simulation file and the configured data storage module, and generating simulation results; and / or simulating the FPGA through back-door simulation based on the simulation code, the simulation file and the configured data storage module, and generating simulation results, the FPGA can be simulated more flexibly and more specifically, and the simulation results are more diverse and complete.

[0080] Figure 7 It is a block diagram of an electronic device according to an exemplary embodiment.

[0081] Refer to the following Figure 7hereinafter describes an electronic device 700 according to this embodiment of the present application. Figure 7 The electronic device 700 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0082] like Figure 7 As shown, the electronic device 700 is in the form of a general computing device. The components of the electronic device 700 may include, but are not limited to: at least one processing unit 710, at least one storage unit 720, a bus 730 connecting different system components (including the storage unit 720 and the processing unit 710), a display unit 740, etc.

[0083] The storage unit stores a program code, which can be executed by the processing unit 710, so that the processing unit 710 performs the steps described in this specification according to various exemplary embodiments of the present application. For example, the processing unit 710 can perform the following steps: Figure 2 Follow the steps shown in .

[0084] The storage unit 720 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 7201 and / or a cache memory unit 7202 , and may further include a read-only memory unit (ROM) 7203 .

[0085] The storage unit 720 may also include a program / utility 7204 having a set (at least one) of program modules 7205, such program modules 7205 including but not limited to: an operating system, one or more application programs, other program modules and program data, each of which or some combination may include the implementation of a network environment.

[0086] Bus 730 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0087] The electronic device 700 may also communicate with one or more external devices 700' (e.g., keyboards, pointing devices, Bluetooth devices, etc.) to enable a user to communicate with the electronic device 700, and / or any device (e.g., routers, modems, etc.) that the electronic device 700 can communicate with one or more other computing devices. Such communication may be performed via an input / output (I / O) interface 750. In addition, the electronic device 700 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 760. The network adapter 760 may communicate with other modules of the electronic device 700 via a bus 730. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 700, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0088] Through the above description of the implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by combining software with necessary hardware. Figure 8 As shown, the technical solution according to the implementation mode of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes a number of instructions to enable a computing device (which can be a personal computer, a server, or a network device, etc.) to execute the above method according to the implementation mode of the present application.

[0089] The software product may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, a system, device or component of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0090] The computer readable storage medium may include a data signal propagated in a baseband or as part of a carrier wave, wherein a readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The readable storage medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by an instruction execution system, an apparatus, or a device or used in combination with it. The program code contained on the readable storage medium may be transmitted with any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the above.

[0091] Program code for performing the operations of the present application may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., using an Internet service provider to connect through the Internet).

[0092] The above-mentioned computer-readable medium carries one or more programs. When the above-mentioned one or more programs are executed by a device, the computer-readable medium realizes the following functions: generates simulation code and simulation file based on the FPGA to be simulated; configures write address, write data and read address for the data storage module; simulates the FPGA through front-door simulation based on the simulation code, the simulation file and the configured data storage module, and generates simulation results; and / or simulates the FPGA through back-door simulation based on the simulation code, the simulation file and the configured data storage module, and generates simulation results.

[0093] Those skilled in the art will appreciate that the above modules can be distributed in the device according to the description of the embodiment, or can be changed accordingly and only used in one or more devices different from the embodiment. The modules of the above embodiments can be combined into one module, or further divided into multiple sub-modules.

[0094] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the embodiment of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiment of the present application.

[0095] The exemplary embodiments of the present application are specifically shown and described above. It should be understood that the present application is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present application is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended claims.

Claims

1. A simulation method for FPGA, characterized in that: include: Generate simulation code and simulation files based on the FPGA to be simulated; Configure write address, write data and read address for the data storage module; Based on the simulation code, the simulation file, and the configured data storage module, the FPGA is simulated by front-door simulation, and a simulation result is generated, including: writing the register value into the simulation code through the register configuration bus; the simulation code transfers the register value into the data storage module to generate a first write address; at least one stimulus is transferred to the table entry function through the systemverilog file; the data storage module obtains the corresponding second write address by calling the table entry function; the first write address and the second write address are matched; and the matched data is returned to the simulation code; and / or Based on the simulation code, the simulation file, and the configured data storage module, the FPGA is simulated by backdoor simulation, and a simulation result is generated, including: a C function calls the simulation code based on a parameter file to perform a write operation on a register; a third write address is generated based on the write operation; at least one stimulus is passed to a table entry function through a systemverilog file; the data storage module obtains a fourth write address corresponding to the table entry function by calling the table entry function; the third write address and the fourth write address are matched; and the systemverilog function value is returned to the C function after the match is successful.

2. The method according to claim 1, characterized in that Generate simulation code and simulation files based on the FPGA to be simulated, including: Generate the simulation code based on the tested code of the FPGA to be simulated; The simulation file is generated based on the python file, the simulation run file, the systemverilog file, and the stimulus file.

3. The method according to claim 1, characterized in that Configure the write address, write data, and read address for the data storage module, including: Write the write address, write data and read address to the data storage module; The data storage module is configured so that when the write address matches the read address, the data storage module outputs the data in the form of read data.

4. The method according to claim 1, characterized in that Based on the simulation code, the simulation file, and the configured data storage module, the FPGA is simulated by a front-door simulation method, and a simulation result is generated, and the method further includes: Enter the read register instruction; Open the graphical interface; View the simulation waveform based on the fmbus in the simulation code.

5. The method according to claim 1, characterized in that Based on the simulation code, the simulation file, and the configured data storage module, the FPGA is simulated by backdoor simulation, and a simulation result is generated, which also includes: Call the C function to view the simulation waveform.

6. A simulation device for FPGA, characterized in that: include: A data module, used for generating simulation codes and simulation files based on the FPGA to be simulated; An address module, used to configure a write address, write data and a read address for the data storage module; A front-door simulation module is used to simulate the FPGA by means of front-door simulation based on the simulation code, the simulation file, and the configured data storage module, and generate simulation results, including: writing the register value into the simulation code through the register configuration bus; the simulation code transfers the register value into the data storage module to generate a first write address; at least one stimulus is transferred to the table entry function through the systemverilog file; the data storage module obtains the second write address corresponding to the table entry function by calling the table entry function; the first write address and the second write address are matched; and the matched data is returned to the simulation code; and / or The backdoor simulation module is used to simulate the FPGA by backdoor simulation based on the simulation code, the simulation file, and the configured data storage module, and generate simulation results, including: a C function calls the simulation code based on a parameter file to perform a write operation on a register; a third write address is generated based on the write operation; at least one stimulus is passed to the table entry function through a systemverilog file; the data storage module obtains a fourth write address corresponding to the table entry function by calling the table entry function; the third write address and the fourth write address are matched; and the systemverilog function value is returned to the C function after the match is successful.

Images