Semiconductor element and method for manufacturing the same

Abstract

This invention discloses a semiconductor device and its fabrication method. The method for fabricating the semiconductor device involves first forming a magnetic tunneling junction (MTJ) in an MRAM region on a substrate, then forming a first intermetallic dielectric layer around the MTJ, forming a patterned mask in a logic region on the substrate, performing a nitriding process to convert a portion of the first intermetallic dielectric layer into a nitrided layer on the MTJ, forming a first metal interconnect in the logic region, forming a stop layer on the first intermetallic dielectric layer, forming a second intermetallic dielectric layer on the stop layer, and finally forming a second metal interconnect in the second intermetallic dielectric layer and connecting it to the MTJ.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing magnetoresistive random access memory (MRAM) devices. Background Technology

[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a magnetic tunneling junction (MTJ) is formed in an MRAM region on a substrate. Then, a first intermetallic dielectric layer is formed around the MTJ. A patterned mask is formed in a logic region on the substrate. A nitriding process is performed to convert a portion of the first intermetallic dielectric layer into a nitrided layer on the MTJ. A first metal interconnect is formed in the logic region. A stop layer is formed on the first intermetallic dielectric layer. A second intermetallic dielectric layer is formed on the stop layer. Finally, a second metal interconnect is formed within the second intermetallic dielectric layer and connected to the MTJ.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a magnetic tunneling junction (MTJ) disposed on a substrate, a first intermetallic dielectric layer surrounding the MTJ, and a nitride layer disposed on the MTJ.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a magnetic tunneling junction (MTJ) disposed on a substrate, an upper electrode disposed on the MTJ, a first intermetallic dielectric layer surrounding the MTJ, a second intermetallic dielectric layer disposed on the first intermetallic dielectric layer, a metal interconnect disposed in the second intermetallic dielectric layer and connecting the MTJ, and a protrusion disposed next to the metal interconnect, wherein the bottom of the protrusion is higher than the top of the upper electrode.

[0007] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a first magnetic tunneling junction (MTJ) and a second MTJ disposed on a substrate, a masking layer disposed on the sidewalls of the first MTJ and the second MTJ, a dielectric layer surrounding the masking layer, a metal interconnect disposed on the first MTJ, the second MTJ and the dielectric layer, and an inter-metal dielectric layer surrounding the dielectric layer and the metal interconnect. Attached Figure Description

[0008] Figures 1 to 5 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention;

[0009] Figure 6 This is a schematic diagram of the structure of an MRAM cell according to an embodiment of the present invention;

[0010] Figures 7 to 10 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention.

[0011] Explanation of main component symbols

[0012] 12: Base

[0013] 14: MRAM region

[0014] 16: Logical Area

[0015] 18: Interlayer dielectric layer

[0016] 20: Metal interconnect structure

[0017] 22: Metal interconnect structure

[0018] 24: Intermetallic dielectric layer

[0019] 26: Metal interconnects

[0020] 28: Stop Layer

[0021] 30: Intermetallic dielectric layer

[0022] 32: Metal interconnects

[0023] 34: Barrier Layer

[0024] 36: Metal layer

[0025] 38: MTJ stacked structure

[0026] 42: Lower electrode

[0027] 44: Fixed layer

[0028] 46: Barrier Layer

[0029] 48: Free Layer

[0030] 50: Upper electrode

[0031] 52:MTJ

[0032] 54:MTJ

[0033] 56: Covering layer

[0034] 58: Intermetallic dielectric layer

[0035] 60: Nitriding process

[0036] 62: Nitride layer

[0037] 64: Patterned Mask

[0038] 66: Metal interconnects

[0039] 68: Stop Layer

[0040] 70: Intermetallic dielectric layer

[0041] 72: Metal interconnects

[0042] 74: Stop Layer

[0043] 76: Protrusion

[0044] 78: Trench conductor

[0045] 80: Contact hole conductor

[0046] 92: Dielectric layer

[0047] 94: Metal interconnects

[0048] 96: Conical part Detailed Implementation

[0049] Please refer to Figures 1 to 5, Figures 1 to 5 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 16 are preferably defined on the substrate 12.

[0050] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0051] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30 and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0052] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and the metal interconnect 32 in the MRAM region 14 of the metal interconnect structure 22 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 20 and 22 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer 28 and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 and 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 36 in the metal interconnect 26 preferably contains copper, the metal layer 36 in the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 24 and 30 preferably contain silicon oxide such as tetraethylorthosilicate (TEOS), and the stop layer 28 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0053] Next, a lower electrode 42, an MTJ stack structure 38, an upper electrode 50, and a patterned mask (not shown) are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 38 can be formed by first sequentially forming a pinned layer 44, a barrier layer 46, and a free layer 48 on the lower electrode 42. In this embodiment, the lower electrode 42 and the upper electrode 50 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 44 may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Furthermore, the fixing layer 44 can also be made of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer 46 can be made of an insulating material containing oxides, such as aluminum oxide (AlO). x The free layer 48 can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer 48 can be "freely" changed by an external magnetic field.

[0054] Subsequently, as Figure 2 As shown, a patterned mask is used as the mask to perform one or more etching processes to remove a portion of the upper electrode 50, a portion of the MTJ stack structure 38, a portion of the lower electrode 42, and a portion of the intermetallic dielectric layer 30 to form MTJs 52 and 54 in the MRAM region 14. It is worth noting that the etching process performed on the patterned upper electrode 50, MTJ stack structure 38, lower electrode 42, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. It should also be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, it is preferable to remove part of the metal interconnects 32 at the same time, so that the metal interconnects 32 form an inclined sidewall near the junction of MTJ 52 and 54.

[0055] Then, a masking layer 56 is formed on MTJs 52 and 54, covering the surface of the intermetallic dielectric layer 30. A photolithography and etching process is then performed to remove part of the masking layer 56 and part of the intermetallic dielectric layer 30 of the logic region 16, exposing the underlying stop layer 28. Finally, an intermetallic dielectric layer 58 is formed to cover each MTJ 52 and 54. In this embodiment, the masking layer 56 preferably comprises silicon nitride, but other dielectric materials may be selected according to the fabrication process requirements, such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide nitride. The intermetallic dielectric layer 58 preferably comprises an ultra-low dielectric constant dielectric layer, such as, but not limited to, porous dielectric materials such as, but not limited to, silicon carbide oxycarbonide (SiOC) or silicon carbide hydrogen oxycarbonide (SiOCH).

[0056] like Figure 3 As shown, a nitriding fabrication process 60 is then performed to form a nitriding layer 62 on MTJs 52 and 54. More specifically, the nitriding fabrication process 60 performed in this stage preferably first forms a patterned mask 64, such as a patterned photoresist covering the logic region 16, and then uses any nitrogen-based implantation method, such as but not limited to ion implantation or plasma-enhanced chemical vapor deposition (PECVD), to inject nitrogen and / or ammonia into a portion of the intermetallic dielectric layer 58 above MTJs 52 and 54 in the MRAM region 14, and converts the portion of the intermetallic dielectric layer 58 into a nitriding layer 62.

[0057] It is worth noting that, in this stage, the nitriding fabrication process 60 preferably converts part of the intermetallic dielectric layer 58, which is composed of an ultra-low dielectric constant dielectric layer, after implanting nitrogen atoms into it, into a nitriding layer 62 composed of silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH). This nitriding layer 62 prevents the formation of protrusions or bumps on the sidewalls of the metal interconnects due to the porous intermetallic dielectric layer being too soft when subsequently fabricating metal interconnects, such as those made of copper, using a dual damascene fabrication process. In detail, the nitriding layer 62 preferably contains a gradient nitrogen concentration, and the nitrogen concentration in the nitriding layer 62 preferably decreases towards MTJs 52 and 54. In other words, the nitriding layer 62 closer to MTJs 52 and 54 preferably contains a lower nitrogen concentration, while the nitriding layer 62 farther from MTJs 52 and 54 preferably contains a higher nitrogen concentration. It should also be noted that although the nitrided layer 62 formed in this embodiment is exemplified by having a gradient nitrogen concentration, it is not limited to this. According to other embodiments of the present invention, the concentration distribution of the injected nitrogen atoms can be adjusted during the nitriding process 60 so that the nitrogen atom concentration is evenly distributed throughout the entire nitrided layer 62 rather than decreasing towards MTJ52 and 54. This variation is also within the scope of the present invention.

[0058] Then as Figure 4 As shown, the patterned mask 64 is first removed, followed by a pattern transfer fabrication process. For example, a patterned mask (not shown) can be used to remove part of the intermetallic dielectric layer 58 and part of the stop layer 28 of the logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26. Then, the required metal material is filled into the contact holes, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization fabrication process is performed, for example, by chemical mechanical polishing to remove part of the metal material, part of the intermetallic dielectric layer 58, and part of the nitride layer 62 to form contact plugs or metal interconnects 66 that electrically connect the metal interconnects 26 within the contact holes. A stop layer 68 is then formed on the nitride layer 62, the intermetallic dielectric layer 58, and the metal interconnect 66. The stop layer 68 may contain silicon dioxide, silicon nitride, or silicon carbon nitride (SiCN), and preferably contains silicon carbon nitride, but is not limited thereto.

[0059] Subsequently, as Figure 5As shown, an intermetallic dielectric layer 70 is formed on the stop layer 68. One or more photolithography and etching processes are performed to remove portions of the intermetallic dielectric layer 70, the stop layer 68, and the nitride layer 62 in the MRAM region 14, and portions of the intermetallic dielectric layer 70 and the stop layer 68 in the logic region 16, forming contact holes (not shown). Next, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 72 in the MRAM region 14 and the logic region 16, connecting to the underlying MTJs 52 and 54 and the metal interconnects 66. Preferably, the metal interconnects 72 in the MRAM region 14 directly contact the underlying upper electrode 50, while the metal interconnects 72 in the logic region 16 contact the underlying metal interconnects 66. Then, another stop layer 74 is formed on the intermetallic dielectric layer 70, covering the metal interconnects 72.

[0060] In this embodiment, stop layer 68 and stop layer 74 may contain the same or different materials, both of which can be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, the metal interconnects 72 disposed within the intermetallic dielectric layer 70 can be embedded within the intermetallic dielectric layer 70 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 72 may further include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0061] Please refer to Figure 6 , Figure 6 This is a schematic diagram of an MRAM cell according to an embodiment of the present invention. For simplicity, the same reference numerals are preferably used for the same components disclosed in this embodiment and the previous embodiments. Figure 6As shown, the semiconductor device mainly includes MTJs 52 and 54 disposed on the substrate 12, an upper electrode 50 disposed on each MTJ 52 and 54, a cover layer 56 surrounding the upper electrode 50 and MTJs 52 and 54, an intermetallic dielectric layer 58 surrounding the MTJs 52 and 54, an intermetallic dielectric layer 70 disposed on the intermetallic dielectric layer 58, metal interconnects 72 disposed within the intermetallic dielectric layer 70 and connecting each MTJ 52 and 54, and protrusions 76 disposed beside each metal interconnect 72. In this embodiment, the metal interconnects 72 of the MRAM region 14 further include a trench conductor 78 and two contact hole conductors 80 respectively connecting MTJs 52 and 54, wherein protrusions 76 are respectively disposed on the sidewalls of each contact hole conductor 80.

[0062] It should be noted that, generally, if a nitride layer 62 is not formed above the upper electrode 50 as a buffer according to the aforementioned embodiment, the metal interconnects 72 formed when using the dual damascene fabrication process typically have protrusions 76 on both sides of the contact hole conductor 80 near the upper electrode 50. In detail, the protrusions may be approximately triangular or other irregular shapes. The protrusions 76 are preferably located on both sides of each contact hole conductor 80 and directly contact the intermetallic dielectric layer 58, but preferably do not contact the upper stop layer 68, the lower upper electrode 50, and / or the cover layer 56. The bottom of the protrusion 76 is preferably higher than the top of the upper electrode 50 and the top of the cover layer 56, and the top of the protrusion 76 is preferably lower than the top of the metal interconnect 66 in the logic region 16. Furthermore, since the protrusions 76 and the metal interconnects 72 are formed in the same fabrication process, such as the aforementioned dual damascene fabrication process, they preferably contain the same material, such as, but not limited to, copper.

[0063] Please refer to Figures 7 to 10 , Figures 7 to 10 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. For simplicity, the same reference numerals are preferably used for the same components disclosed in this embodiment as in the preceding embodiments. For example... Figure 7 As shown, first compare Figure 1 The embodiment provides a substrate 12, such as a substrate 12 made of a semiconductor material, wherein the semiconductor material may be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and preferably an MRAM region 14 and a logic region 16 are defined on the substrate 12.

[0064] The substrate 12 may contain active components such as metal-oxide-semiconductor (MOS) transistors, passive components, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor elements, wherein the MOS transistor may include a gate structure (such as a metal gate) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistor, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistor. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0065] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30 and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0066] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and the metal interconnect 32 in the MRAM region 14 of the metal interconnect structure 22 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 20 and 22 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer 28 and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 and 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 36 in the metal interconnect 26 preferably contains copper, the metal layer 36 in the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 24 and 30 preferably contain silicon oxide such as tetraethyl orthosilicate (TEOS), and the stop layer 28 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0067] Next, a lower electrode 42, an MTJ stack structure 38, an upper electrode 50, and a patterned mask (not shown) are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 38 can be formed by first sequentially forming a pinned layer 44, a barrier layer 46, and a free layer 48 on the lower electrode 42. In this embodiment, the lower electrode 42 and the upper electrode 50 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 44 may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Furthermore, the fixing layer 44 can also be made of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer 46 can be made of an insulating material containing oxides, such as aluminum oxide (AlO). x The free layer 48 can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer 48 can be "freely" changed by an external magnetic field.

[0068] Subsequently, a patterned mask is used as the mask to perform one or more etching processes to remove a portion of the upper electrode 50, a portion of the MTJ stack structure 38, a portion of the lower electrode 42, and a portion of the intermetallic dielectric layer 30 to form MTJs 52 and 54 in the MRAM region 14. It is worth noting that the etching process performed on the patterned upper electrode 50, MTJ stack structure 38, lower electrode 42, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of the ion beam etching process, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. Additionally, it should be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, it is preferable to also remove part of the metal interconnects 32, so that the metal interconnects 32 form sloping sidewalls near the junction of MTJs 52 and 54. Then, a masking layer 56 is formed on MTJs 52 and 54 and covers the surface of the intermetallic dielectric layer 30. In this embodiment, the masking layer 56 preferably contains silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide can be selected according to the fabrication process requirements.

[0069] like Figure 8 As shown, an atomic deposition process is then performed to form a dielectric layer 92 covering MTJs 52 and 54. A back-etch process is then performed to remove a portion of the dielectric layer 92, a portion of the masking layer 56, and a portion of the intermetallic dielectric layer 30 from the MRAM region 14 and logic region 16. The remaining dielectric layer 92 is only located in the MRAM region 14 and surrounds MTJs 52 and 54, or, from another angle, is located on the left side of MTJ 52, the right side of MTJ 54, and between the two MTJs 52 and 54. It should be noted that while this embodiment retains a portion of the intermetallic dielectric layer 30 in the MRAM region 14 and logic region 16 and does not expose the underlying stop layer 28 when removing a portion of the dielectric layer 92 using the back-etch process, it is not limited to this. According to other embodiments of the invention, all intermetallic dielectric layers 30 in the logic region 16 can be removed when removing the dielectric layer 92, exposing the underlying stop layer 28. This variation is also within the scope of this invention.

[0070] like Figure 9As shown, an intermetallic dielectric layer 58 is then formed in the MRAM region 14 and logic region 16, covering the dielectric layer. A planarization process, such as CMP, is then performed to remove part of the intermetallic dielectric layer 58, leaving the remaining intermetallic dielectric layer 58 with a planar surface. In this embodiment, the dielectric layer 92 preferably comprises silicon oxide, and as in the aforementioned embodiments, the intermetallic dielectric layer 58 preferably comprises an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).

[0071] Next, a pattern transfer fabrication process is performed. For example, a patterned mask can be used to remove part of the intermetallic dielectric layer 58, part of the dielectric layer 92, and part of the masking layer 56 in the MRAM region 14 to form contact holes (not shown) and expose the underlying upper electrode 50. Then, the contact holes are filled with the desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization fabrication process is performed, such as a chemical mechanical polishing process to remove part of the metal material to form contact plugs or metal interconnects 94 in the contact holes, while simultaneously electrically connecting MTJs 52 and 54.

[0072] It is worth noting that, since the dielectric layers 92 on the left and right sides of MTJ 52 and 54 have an arc-shaped profile when formed by atomic deposition, the metal interconnects 94 connected to them preferably form a tapered portion 96 at the location where they contact the dielectric layers 92. In this embodiment, although the bottom of the tapered portion 96 is located between the upper electrode 50 and the lower electrode 42, it is not limited thereto. According to other embodiments of the present invention, the position of the tapered portion 96 can be adjusted according to the manufacturing process requirements or the curvature of the sidewall of the dielectric layer 92 so that it is higher than the bottom of the upper electrode 50 or lower than the bottom of MTJ 52 and 54. These variations are all within the scope of the present invention.

[0073] A subsequent pattern transfer fabrication process is performed, for example, by using a patterned mask to remove part of the intermetallic dielectric layer 58, part of the intermetallic dielectric layer 30, and part of the stop layer 28 of the logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26. The contact holes are then filled with the desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization fabrication process is performed, for example, by chemical mechanical polishing to remove part of the metal material to form contact plugs or metal interconnects 66 electrically connecting the metal interconnects 26 within the contact holes. A stop layer 68 is then formed on the intermetal dielectric layer 58 and the metal interconnects 66 and 94. The stop layer 68 may contain silicon dioxide, silicon nitride, or silicon carbon nitride (SiCN), and preferably contains silicon carbon nitride, but is not limited to this.

[0074] Subsequently, as Figure 10 As shown, an intermetallic dielectric layer 70 is formed on the stop layer 68. One or more photolithography and etching processes are performed to remove portions of the intermetallic dielectric layer 70 and the stop layer 68 in the MRAM region 14 and logic region 16, forming contact holes (not shown). Next, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 72 in the MRAM region 14 and logic region 16, connecting to the underlying MTJs 52 and 54 and the metal interconnect 66. Preferably, the metal interconnect 72 in the MRAM region 14 directly contacts the underlying metal interconnect 94, while the metal interconnect 72 in the logic region 16 contacts the underlying metal interconnect 66. Then, another stop layer 74 is formed on the intermetallic dielectric layer 70, covering the metal interconnect 72. As... Figure 6 In this embodiment, the metal interconnect 72 of the MRAM region 14 further includes a trench conductor 78 and two contact hole conductors 80, which are respectively connected to the metal interconnect 94 below.

[0075] In this embodiment, stop layer 68 and stop layer 74 may contain the same or different materials, both of which can be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, the metal interconnects 72 disposed within the intermetallic dielectric layer 70 can be embedded within the intermetallic dielectric layer 70 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 72 may further include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0076] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: A magnetic tunneling junction (MTJ) is formed on the upper surface of the substrate; A first intermetallic dielectric layer is formed around the magnetic tunnel junction; A nitriding fabrication process is performed to form a nitriding layer on the magnetic tunneling junction, wherein in the cross-sectional structure of the semiconductor device, in the direction perpendicular to the upper surface of the substrate, there is no first intermetallic dielectric layer between the nitriding layer and the magnetic tunneling junction. as well as A stop layer is formed on the nitrided layer and in direct contact with the nitrided layer.

2. The method of claim 1, wherein the substrate comprises an MRAM region and a logic region, the method comprising: A patterned mask is formed in this logical region; The nitriding process converts a portion of the first intermetallic dielectric layer into the nitrided layer. A first metal interconnect is formed on the logic region; The stop layer is formed on the first intermetallic dielectric layer; A second intermetallic dielectric layer is formed on the stop layer; as well as A second metal interconnect is formed within the second metal inter-dielectric layer and connects to the magnetic tunnel junction.

3. The method of claim 2, wherein the top of the nitride layer is flush with the top of the first metal interconnect.

4. The method of claim 2, wherein the nitrided layer comprises a gradient nitrogen concentration.

5. The method of claim 1, wherein the nitrogen concentration of the nitride layer decreases toward the first intermetallic dielectric layer.

6. The method of claim 1, wherein the nitriding process comprises a plasma-assisted chemical vapor deposition process.

7. The method of claim 1, wherein the nitriding process comprises nitrogen or ammonia.

8. A semiconductor element, characterized in that, Include: A magnetic tunneling junction (MTJ) is located on the upper surface of the substrate. A first intermetallic dielectric layer surrounds the magnetic tunneling junction; A nitride layer is disposed on the magnetic tunnel junction; and A stop layer is disposed on the nitrided layer and in direct contact with the nitrided layer. In the cross-sectional structure of the semiconductor device, in the direction perpendicular to the upper surface of the substrate, there is no first intermetallic dielectric layer between the nitride layer and the magnetic tunneling junction.

9. The semiconductor device of claim 8, wherein the substrate includes an MRAM region and a logic region, and the semiconductor device comprises: The first metal interconnect is located in this logic region; The stop layer is located on the inner interconnect of the first metal; A second intermetallic dielectric layer is disposed on the stop layer; and The second metal interconnect is disposed within the second metal dielectric layer and connects to the magnetic tunnel junction, wherein the nitride layer surrounds the second metal interconnect.

10. The semiconductor device of claim 9, wherein the top of the nitride layer is flush with the top of the first metal interconnect.

11. The semiconductor device of claim 8, wherein the nitride layer comprises a gradient nitrogen concentration.

12. The semiconductor device of claim 8, wherein the nitrogen concentration of the nitride layer decreases toward the magnetic tunnel junction.

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