Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The method of fabricating the semiconductor device includes forming a first intermetal dielectric layer on a substrate and a metal interconnect in the first intermetal dielectric layer, forming a magnetic tunneling junction (MTJ) and an upper electrode on the metal interconnect, forming a spacer on the MTJ and the upper electrode, forming a second intermetal dielectric layer around the spacer, forming a capping layer on the upper electrode, the spacer and the second intermetal dielectric layer, and patterning the capping layer to form a protective cap on the upper electrode and the spacer.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing magnetoresistive random access memory (MRAM) devices. Background Technology

[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a first intermetallic dielectric layer is formed on a substrate and a first metal interconnect is formed within the first intermetallic dielectric layer. Then, a magnetic tunneling junction (MTJ) and an upper electrode are formed on the first metal interconnect. A spacer is formed next to the MTJ and the upper electrode. A second intermetallic dielectric layer is formed around the spacer. A masking layer is formed on the upper electrode, the spacer, and the second intermetallic dielectric layer. Finally, the masking layer is patterned to form a protective cover on the upper electrode and the spacer.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a magnetic tunneling junction (MTJ) disposed on a substrate, an upper electrode disposed on the MTJ, and a protective cap disposed on the upper electrode.

[0006] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a magnetic tunneling junction (MTJ) disposed on a substrate, an upper electrode disposed on the MTJ, a spacer wall disposed on the MTJ and next to the upper electrode, and a protective cover disposed on the upper electrode and the spacer wall. Attached Figure Description

[0007] Figures 1 to 6 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention;

[0008] Figures 7 to 10 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention.

[0009] Explanation of main component symbols

[0010] 12: Base

[0011] 14: MRAM region

[0012] 18: Interlayer dielectric layer

[0013] 20: Metal interconnect structure

[0014] 22: Metal interconnect structure

[0015] 24: Intermetallic dielectric layer

[0016] 26: Metal interconnects

[0017] 28: Stop Layer

[0018] 30: Intermetallic dielectric layer

[0019] 32: Metal interconnects

[0020] 34: Barrier Layer

[0021] 36: Metal layer

[0022] 38: MTJ stacked structure

[0023] 42: Lower electrode

[0024] 44: Fixed layer

[0025] 46: Barrier Layer

[0026] 48: Free Layer

[0027] 50: Upper electrode

[0028] 52:MTJ

[0029] 54: Spacer wall

[0030] 56: Metal dielectric layer

[0031] 58: Covering layer

[0032] 60: Patterned Mask

[0033] 62: Opening

[0034] 64: Protective cover

[0035] 66: Intermetallic dielectric layer

[0036] 68: Stop Layer

[0037] 70: Intermetallic dielectric layer

[0038] 72: Metal interconnects

[0039] 74: Stop Layer Detailed Implementation

[0040] Please refer to Figures 1 to 6 , Figures 1 to 6 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region (not shown) are preferably defined on the substrate 12.

[0041] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 18 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0042] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30 and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0043] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and the metal interconnect 32 in the MRAM region 14 of the metal interconnect structure 22 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 20 and 22 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer 28 and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 and 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 36 in the metal interconnect 26 preferably contains copper, the metal layer 36 in the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 24 and 30 preferably contain silicon oxide such as tetraethylorthosilicate (TEOS), and the stop layer 28 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0044] Next, a lower electrode 42, an MTJ stack structure 38, an upper electrode 50, and a patterned mask (not shown) are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 38 can be formed by first sequentially forming a pinned layer 44, a barrier layer 46, and a free layer 48 on the lower electrode 42. In this embodiment, the lower electrode 42 and the upper electrode 50 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer 44 may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Furthermore, the fixing layer 44 can also be made of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer 46 can be made of an insulating material containing oxides, such as aluminum oxide (AlO). x The free layer 48 can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer 48 can be "freely" changed by an external magnetic field.

[0045] Subsequently, as Figure 2As shown, using a patterned mask, such as a patterned photoresist, one or more etching processes are performed to remove a portion of the upper electrode 50, a portion of the MTJ stack structure 38, a portion of the lower electrode 42, and a portion of the intermetallic dielectric layer 30 to form multiple MTJs 52 on the metal interconnects 32. Although this embodiment uses three sets of MTJs 52 in the MRAM region 14 as an example, the number of MTJs 52 can be adjusted according to the fabrication process requirements and is not limited to this. It should be noted that the etching process performed on the patterned upper electrode 50, MTJ stack structure 38, lower electrode 42, and intermetallic dielectric layer 30 in this embodiment may include reactive ion etching (RIE) and / or ion beam etching (IBE). Due to the characteristics of ion beam etching, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnects 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. It should also be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, it is preferable to remove part of the metal interconnects 32 at the same time, so that the metal interconnects 32 form an inclined sidewall near the junction of MTJ 62.

[0046] A masking layer (not shown) is then formed on the MTJ 52 and covers the surface of the intermetallic dielectric layer 30. A portion of the masking layer is then removed by etch-back to form spacer walls 54 on the sidewalls of each MTJ 52. In this embodiment, the spacer walls 54 preferably comprise silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide can be selected depending on the fabrication process requirements.

[0047] Then as Figure 3 As shown, an intermetallic dielectric layer 56 is first formed around the spacer wall 54 on each MTJ 52. Then, a masking layer 58 is formed on the upper electrode 50, the spacer wall 54, and the intermetallic dielectric layer 56. Preferably, the masking layer 58 has undulations according to the underlying components. For example, the top of the masking layer 58 above the intermetallic dielectric layer 56 is slightly lower than the top of the masking layer 58 above the upper electrode 50. In this embodiment, the intermetallic dielectric layer 56 preferably includes an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH). The masking layer 58 preferably includes a conductive material or, more specifically, a metal or metal nitride, such as, but not limited to, tantalum or titanium nitride.

[0048] like Figure 4As shown, a patterned mask 60, such as a patterned photoresist, is then formed on the cover layer 58, wherein the patterned photoresist includes a plurality of openings 62 exposing a portion of the surface of the cover layer 58. Next, the patterned mask 60 is used to remove a portion of the cover layer 58 to form a protective cap 64 directly above each MTJ 52 or the upper electrode 50. In this embodiment, although the sidewalls of each protective cap 64 are preferably flush with the outer sidewall of the lower gap wall 54, this is not a limitation. According to other embodiments of the present invention, the sidewalls of each protective cap 64 may optionally not be flush with the outer sidewall of the lower gap wall 54; for example, the protective cap 64 may simultaneously cover both the gap wall 54 and the intermetallic dielectric layer 56. This variation is also within the scope of the present invention.

[0049] Subsequently, as Figure 5 As shown, the patterned mask 60 is first removed, followed by a wet cleaning process to remove some residue from the surface and surrounding area of ​​the protective cover 64. Then, another intermetallic dielectric layer 66 is formed to completely cover the protective cover 64. A planarization process, such as chemical mechanical polishing, is then performed to remove part of the intermetallic dielectric layer 66, leaving a flat surface on the remaining layer while the top of the intermetallic dielectric layer 66 remains higher than the top of the protective cover 64. Like the intermetallic dielectric layer 56, the intermetallic dielectric layer 66 may contain an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, for example, but not limited to silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).

[0050] Then as Figure 6 As shown, a stop layer 68 is first formed on the inter-metal dielectric layer 66, and an inter-metal dielectric layer 70 is formed on the stop layer 68. One or more photolithography and etching processes are then performed to remove portions of the inter-metal dielectric layer 70, the stop layer 68, and the inter-metal dielectric layer 66, forming contact holes (not shown) to expose the protective caps 64. Next, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 72 connecting to the underlying MTJ 52. Preferably, the metal interconnects 72 directly contact the underlying protective caps 64. Subsequently, another stop layer 74 is formed on the inter-metal dielectric layer 70 to cover the metal interconnects 72.

[0051] In this embodiment, stop layer 68 and stop layer 74 may contain the same or different materials, both of which can be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, the metal interconnects 72 disposed within the intermetallic dielectric layer 70 can be embedded within the intermetallic dielectric layer 70 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 72 may further include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0052] Please refer to Figures 7 to 10 , Figures 7 to 10 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. For simplicity, the same reference numerals are preferably used for the same components disclosed in this embodiment as in the preceding embodiments. For example... Figure 7 As shown, the aforementioned steps are performed first. Figures 1 to 2 The fabrication process involves forming MTJ 52 on the substrate 12 and forming spacer walls 54 on the sidewalls of each MTJ 52, and then directly forming a cover layer 58 on the upper electrode 50, the spacer walls 54, and the intermetallic dielectric layer 30. It should be noted that, since this embodiment does not first form another intermetallic dielectric layer surrounding the sidewalls of the spacer walls 54 before forming the cover layer 58, the formed cover layer 58 covers and contacts the top of the spacer walls 54, the sidewalls of the spacer walls 54, and the top of the intermetallic dielectric layer 30, in addition to covering the top of the upper electrode 50. As in the aforementioned embodiments, the cover layer 58 preferably comprises a conductive material or more specifically a metal or metal nitride, such as, but not limited to, tantalum or titanium nitride.

[0053] Then as Figure 8As shown, a single etching process removes part of the masking layer 58 to form a protective cover 64 on the gap walls 54 on both sides of each MTJ 52 or the upper electrode 50. Compared to the protective cover 64 in the previous embodiment, which is located on the top of the upper electrode 50 and the gap wall 54 but not on the sidewall surface of the gap wall 54, the protective cover 64 in this embodiment, although not located on the top of the upper electrode 50, preferably covers and contacts the top of the gap wall 54, the sidewall of the gap wall 54, the top of the intermetallic dielectric layer 30, and even part of the inclined sidewall close to the top of the upper electrode 50. It should be noted that although the top of the protective cover 64 in this embodiment is not located directly above the upper electrode 50, it is not limited thereto. According to other embodiments of the present invention, the portion of the masking layer 58 directly above the upper electrode 50 can be retained during the etching process so that the subsequently formed protective cover 64, in addition to being located on the top of the gap wall 54, the sidewall of the gap wall 54, and the top of the intermetallic dielectric layer 30, also contacts the top of the upper electrode 50. This variation is also within the scope of the present invention. Furthermore, according to another embodiment of the present invention, the protective cover 64 may be provided only on the top and side walls of the gap wall 54, but not on the top of the upper electrode 50 or the inclined side wall near the top of the upper electrode 50. That is, the protective cover 64 only contacts the gap wall 54 but does not contact any part of the upper electrode 50. This variation is also within the scope of the present invention.

[0054] It should also be noted that, during the process of forming the protective cover 64 from the masking layer 58 in the aforementioned embodiment, part of the top of the masking layer 58 is covered by the patterned mask 60. Therefore, after the formation of the protective cover 64, the protective cover 64 on the top of the upper electrode 50 and the protective cover 64 on the top of the gap wall 54 preferably have the same thickness. In this embodiment, since the masking layer 58 is directly formed into the protective cover 64 by back etching without using any patterned mask, the thickness of the protective cover 64 on the top of the gap wall 54 is preferably slightly lower than the thickness of the protective cover 64 on the sidewall of the gap wall 54.

[0055] Subsequently, as Figure 9 As shown, another intermetallic dielectric layer 66 is formed to completely cover the protective cap 64 and the intermetallic dielectric layer 30, and a planarization process is performed, such as chemical mechanical polishing, to remove part of the intermetallic dielectric layer 66, so that the remaining intermetallic dielectric layer 66 has a flat surface, but the top of the intermetallic dielectric layer 66 is still higher than the top of the protective cap 64. Like the intermetallic dielectric layer 56, the intermetallic dielectric layer 66 may contain an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).

[0056] Then as Figure 10As shown, a stop layer 68 is first formed on the inter-metal dielectric layer 66, and an inter-metal dielectric layer 70 is formed on the stop layer 68. One or more photolithography and etching processes are then performed to remove portions of the inter-metal dielectric layer 70, the stop layer 68, and the inter-metal dielectric layer 66, forming contact holes (not shown) to expose the protective caps 64. Next, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 72 connecting to the underlying MTJ 52. Preferably, the metal interconnects 72 directly contact the upper electrode 50 located below. Subsequently, another stop layer 74 is formed on the inter-metal dielectric layer 70 to cover the metal interconnects 72.

[0057] As in the aforementioned embodiments, stop layer 68 and stop layer 74 may comprise the same or different materials, both of which may be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, the metal interconnects 72 disposed within the intermetallic dielectric layer 70 may be embedded within the intermetallic dielectric layer 70 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 72 may further comprise a barrier layer and a metal layer, wherein the barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0058] In summary, the main feature of this invention is that after forming the gap wall on the sidewall of the MTJ, a protective cap made of metal or metal nitride is additionally formed on the MTJ or the upper electrode directly above the MTJ for protection. The protective cap can be as follows: Figure 6 In general, the embodiment is only located at the top of the upper electrode and the top of the gap wall, or as... Figure 10 In general, the protective cap is located on the top and sidewalls of the spacer wall, but not on the top of the upper electrode. Forming a protective cap above the MTJ and the spacer wall using the above method can prevent excessive etching of the spacer wall and erosion of the MTJ body during the subsequent formation of metal interconnects using a dual damascene fabrication process, thus avoiding component failure.

[0059] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: A magnetic tunneling junction (MTJ) and an upper electrode are formed on the substrate; A spacer wall is formed next to the magnetic tunnel junction and the upper electrode; and A protective cover is formed on the magnetic tunnel junction, the upper electrode, and the gap wall, wherein the upper electrode includes a top, sidewalls located on both sides of the top, and an inclined wall located between the top and the sidewalls. The protective cover includes a conductive material and directly contacts the inclined wall of the upper electrode, but is not disposed on the top of the upper electrode.

2. The method of claim 1, further comprising: A first intermetallic dielectric layer is formed on the substrate and a first metal interconnect is formed within the first intermetallic dielectric layer; The magnetic tunnel junction and the upper electrode are formed on the first metal interconnect. The gap wall is formed next to the magnetic tunnel junction and the upper electrode; A second intermetallic dielectric layer is formed around the gap wall; A masking layer is formed on the upper electrode, the gap wall, and the second intermetallic dielectric layer; The cover layer is patterned to form the protective cover on the upper electrode and the gap wall; A third intermetallic dielectric layer is formed on the protective cover; as well as A second metal interconnect is formed within the third metal inter-metal dielectric layer and the second metal inter-metal dielectric layer, and connects to the magnetic tunnel junction.

3. The method of claim 2, wherein the protective cover covers the sidewall of the gap wall.

4. The method of claim 2, wherein the bottom of the protective cover is lower than the top of the upper electrode.

5. The method of claim 1, further comprising: A first intermetallic dielectric layer is formed on the substrate and a first metal interconnect is formed within the first intermetallic dielectric layer; The magnetic tunnel junction and the upper electrode are formed on the first metal interconnect. The gap wall is formed next to the magnetic tunnel junction; A masking layer is formed on the magnetic tunnel junction, the spacer wall, and the first intermetallic dielectric layer; Remove the covering layer to form a protective cover on the gap wall; A second intermetallic dielectric layer is formed around the gap wall; A third intermetallic dielectric layer is formed on the protective cover; as well as A second metal interconnect is formed within the third metal inter-metal dielectric layer and the second metal inter-metal dielectric layer, and connects to the magnetic tunnel junction.

6. The method of claim 5, further comprising forming the protective cover on the top and sidewalls of the gap wall.

7. The method of claim 1, wherein the bottom of the gap wall is lower than the bottom of the magnetic tunnel junction.

8. The method of claim 1, wherein the protective cover comprises metal.

9. A semiconductor element, characterized in that, Include: A magnetic tunneling junction (MTJ) is located on a substrate. The upper electrode is disposed on the magnetic tunnel junction; A protective cover is disposed on the upper electrode, wherein the upper electrode includes a top, side walls located on both sides of the top, and an inclined wall located between the top and the side walls. The protective cover includes a conductive material and directly contacts the inclined wall of the upper electrode, but is not disposed on the top of the upper electrode. as well as A spacer wall is provided next to the magnetic tunnel junction and the upper electrode, wherein the protective cover is provided on the upper electrode and the spacer wall.

10. The semiconductor element of claim 9, further comprising: A first intermetallic dielectric layer surrounds the gap wall; A stop layer is disposed on the first intermetallic dielectric layer; A second intermetallic dielectric layer is disposed on the stop layer; and Metal interconnects are disposed within the second intermetallic dielectric layer, the stop layer, and the first intermetallic dielectric layer and connected to the upper electrode.

11. The semiconductor element of claim 9, wherein the protective cap covers the sidewall of the gap wall.

12. The semiconductor element of claim 9, wherein the bottom of the protective cover is lower than the top of the upper electrode.

13. A semiconductor element, characterized in that, Include: A magnetic tunneling junction (MTJ) is located on a substrate. The upper electrode is disposed on the magnetic tunnel junction; A spacer wall is provided next to the magnetic tunnel junction and the upper electrode; as well as A protective cover is disposed on the upper electrode and the gap wall, wherein the upper electrode includes a top, side walls located on both sides of the top, and an inclined wall located between the top and the side walls. The protective cover is made of conductive material and directly contacts the inclined wall of the upper electrode, but is not disposed on the top of the upper electrode.

14. The semiconductor device of claim 13, further comprising: A first intermetallic dielectric layer surrounds the gap wall; A stop layer is disposed on the first intermetallic dielectric layer; A second intermetallic dielectric layer is disposed on the stop layer; and Metal interconnects are disposed within the second intermetallic dielectric layer, the stop layer, and the first intermetallic dielectric layer and connected to the upper electrode.

15. The semiconductor element of claim 13, wherein the protective cover is disposed on the top and sidewalls of the gap wall.

16. The semiconductor device of claim 15, wherein the bottom of the spacer wall is lower than the bottom of the magnetic tunnel junction.

17. The semiconductor device of claim 13, wherein the protective cover comprises metal.

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