Method for manufacturing an image display device and image display device

Abstract

The present invention provides a method for manufacturing an image display device and an image display device. The method for manufacturing an image display device according to an embodiment includes: a step of preparing a first substrate including a circuit having circuit elements formed on a light-transmissive substrate and a first insulating film covering the circuit; a step of forming a layer containing graphene on the first insulating film; a step of forming a semiconductor layer including a light-emitting layer on the layer containing the graphene; a step of etching the semiconductor layer to form a light-emitting element; a step of forming a second insulating film covering the layer containing the graphene, the light-emitting element, and the first insulating film; a step of forming a through hole penetrating the first insulating film and the second insulating film; and a step of electrically connecting the light-emitting element and the circuit element via the through hole on a light-emitting surface of the light-emitting element facing the first insulating film side.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing an image display device and an image display device. Background Art

[0002] There is a demand for a thin image display device with high brightness, wide viewing angles, high contrast, and low power consumption. In order to meet the above market demands, display devices using self-emitting elements are being developed.

[0003] As self-emitting elements, display devices using fine light-emitting elements, i.e., micro LEDs, are expected to emerge. As a method for manufacturing a display device using micro LEDs, a method of sequentially transferring individually formed micro LEDs to a driving circuit has been introduced. However, when the number of elements of micro LEDs increases for high image quality such as full high definition, 4K, 8K, etc., in the process of individually forming a large number of micro LEDs and sequentially transferring them to a substrate on which a driving circuit or the like is formed, the transfer process requires a large amount of time. In addition, connection problems between the micro LEDs and the driving circuit or the like may occur, resulting in a problem of reduced yield.

[0004] There is known a technique in which a semiconductor layer including a light-emitting layer is grown on a Si substrate, and after forming an electrode on the semiconductor layer, it is bonded to a circuit substrate on which a driving circuit is formed (for example, Patent Document 1).

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2002-141492

[0008] Non-Patent Documents

[0009] Non-Patent Document 1: H. Kim, J. Ohta, K. Ueno, A. Kobayashi, M. Morita, Y. Tokumoto & H. Fujioka, "Fabrication of full-color GaN-based light-emitting diodes on nearly lattice-matched flexible metal foils", Scientific Reports, 7: 2112, May 18, 2017

[0010] Non-Patent Document 2: J. W. Shon, J. ohta, K. Ueno, A. Kobayashi & H. Fujioka, "Fabrication of full-color InGaN-based light-emitting diodes by pulsed sputtering on amorphous substrates", Scientific Reports, 4: 5325, June 23, 2014 Summary of the Invention

[0011] Technical Problem to be Solved by the Invention

[0012] One embodiment of the present invention provides a method for manufacturing an image display device that shortens the transfer process of light-emitting elements and improves the yield.

[0013] Technical solution for solving technical problems

[0014] The method for manufacturing an image display device according to one embodiment of the present invention includes: a step of preparing a first substrate, the first substrate including: a circuit having circuit elements formed on a light-transmissive substrate, and a first insulating film covering the circuit; a step of forming a layer containing graphene on the first insulating film; a step of forming a semiconductor layer including a light-emitting layer on the layer containing graphene; a step of etching the semiconductor layer to form a light-emitting element; a step of forming a second insulating film covering the layer containing graphene, the light-emitting element, and the first insulating film; a step of forming a through hole penetrating the first insulating film and the second insulating film; and a step of electrically connecting the light-emitting element and the circuit element via the through hole on a light-emitting surface of the light-emitting element facing the first insulating film side.

[0015] An image display device according to one embodiment of the present invention includes: a light-transmissive substrate having a first surface, circuit elements provided on the first surface, a first wiring layer provided on the circuit elements and electrically connected to the circuit elements, a first insulating film covering the circuit elements and the first wiring layer on the first surface, a first portion containing graphene provided on the first insulating film, a light-emitting element provided on the first portion, a second insulating film covering at least a portion of the light-emitting element, the first portion, and the first insulating film, a second wiring layer provided on the second insulating film and electrically connected to a light-emitting surface of the light-emitting element facing the first insulating film side, and a first through hole penetrating the first insulating film and the second insulating film and electrically connecting the first wiring layer and the second wiring layer.

[0016] An image display device according to one embodiment of the present invention includes: a flexible substrate having a first surface, circuit elements provided on the first surface, a first wiring layer provided on the circuit elements and electrically connected to the circuit elements, a first insulating film covering the circuit elements and the first wiring layer on the first surface, a first portion containing graphene provided on the first insulating film, a light-emitting element provided on the first portion, a second insulating film covering at least a portion of the light-emitting element, the first portion, and the first insulating film, a second wiring layer provided on the second insulating film and electrically connected to a light-emitting surface of the light-emitting element facing the first insulating film side, and a first through hole penetrating the first insulating film and the second insulating film and electrically connecting the first wiring layer and the second wiring layer.

[0017] An image display device according to an embodiment of the present invention includes: a light-transmissive substrate having a first surface, a plurality of transistors provided on the first surface, a first wiring layer provided on the plurality of transistors and electrically connected to the plurality of transistors, a first insulating film covering the plurality of transistors and the first wiring layer on the first surface, a portion containing graphene provided on the first insulating film, a first semiconductor layer of a first conductivity type provided on the portion, a light-emitting layer provided on the first semiconductor layer, a second semiconductor layer of a second conductivity type different from the first conductivity type provided on the light-emitting layer, a second insulating film covering the portion, the first insulating film, the light-emitting layer, and the first semiconductor layer and covering at least a part of the second semiconductor layer, a second wiring layer connected to a light-transmissive electrode disposed on a plurality of light-emitting surfaces of the second semiconductor layer exposed from the second insulating film corresponding to the plurality of transistors, and a plurality of through holes penetrating the first insulating film and the second insulating film and electrically connecting a wiring of the first wiring layer and a wiring of the second wiring layer respectively.

[0018] Effects of the Invention

[0019] According to an embodiment of the present invention, it is possible to provide a method for manufacturing an image display device that can shorten the transfer process of light-emitting elements and improve the yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 FIG. is a schematic cross-sectional view illustrating a part of the image display device according to the first embodiment.

[0021] Figure 2A FIG. is a schematic cross-sectional view illustrating a part of a modified example of the image display device according to the first embodiment.

[0022] Figure 2B FIG. is a schematic cross-sectional view illustrating a part of a modified example of the image display device according to the first embodiment.

[0023] Figure 3 FIG. is a schematic block diagram illustrating the image display device according to the first embodiment.

[0024] Figure 4 FIG. is a schematic top view illustrating a part of the image display device according to the first embodiment.

[0025] Figure 5A FIG. is a schematic cross-sectional view illustrating the manufacturing method of the image display device according to the first embodiment.

[0026] Figure 5B FIG. is a schematic cross-sectional view illustrating the manufacturing method of the image display device according to the first embodiment.

[0027] Figure 6AIt is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0028] Figure 6B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0029] Figure 7A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0030] Figure 7B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0031] Figure 8A It is a schematic cross-sectional view illustrating a method of manufacturing a modified example of the image display device according to the first embodiment.

[0032] Figure 8B It is a schematic cross-sectional view illustrating a method of manufacturing a modified example of the image display device according to the first embodiment.

[0033] Figure 9A It is a schematic cross-sectional view illustrating a method of manufacturing a modified example of the image display device according to the first embodiment.

[0034] Figure 9B It is a schematic cross-sectional view illustrating a method of manufacturing a modified example of the image display device according to the first embodiment.

[0035] Figure 10 It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0036] Figure 11A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0037] Figure 11B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0038] Figure 11C It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0039] Figure 11D It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the first embodiment.

[0040] Figure 12 It is a schematic cross-sectional view illustrating a part of an image display device according to the second embodiment.

[0041] Figure 13 It is a schematic block diagram illustrating an image display device according to the second embodiment.

[0042] Figure 14A It is a schematic cross-sectional view illustrating a manufacturing method of an image display device according to a second embodiment.

[0043] Figure 14B It is a schematic cross-sectional view illustrating a manufacturing method of an image display device according to a second embodiment.

[0044] Figure 15A It is a schematic cross-sectional view illustrating a manufacturing method of an image display device according to a second embodiment.

[0045] Figure 15B It is a schematic cross-sectional view illustrating a manufacturing method of an image display device according to a second embodiment.

[0046] Figure 16 It is a schematic cross-sectional view illustrating a part of an image display device according to a third embodiment.

[0047] Figure 17A It is a schematic cross-sectional view illustrating a manufacturing method of an image display device according to a third embodiment.

[0048] Figure 17B It is a schematic cross-sectional view illustrating a manufacturing method of an image display device according to a third embodiment.

[0049] Figure 18 It is a schematic cross-sectional view illustrating a part of an image display device according to a fourth embodiment.

[0050] Figure 19A It is a schematic cross-sectional view illustrating a manufacturing method of an image display device according to a fourth embodiment.

[0051] Figure 19B It is a schematic cross-sectional view illustrating a manufacturing method of an image display device according to a fourth embodiment.

[0052] Figure 19C It is a schematic cross-sectional view illustrating a manufacturing method of an image display device according to a fourth embodiment.

[0053] Figure 20A It is a schematic cross-sectional view illustrating a manufacturing method of an image display device according to a fourth embodiment.

[0054] Figure 20B It is a schematic cross-sectional view illustrating a manufacturing method of an image display device according to a fourth embodiment.

[0055] Figure 21A It is a schematic cross-sectional view illustrating a manufacturing method of an image display device according to a fourth embodiment.

[0056] Figure 21BIt is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a fourth embodiment.

[0057] Figure 22A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a fourth embodiment.

[0058] Figure 22B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a fourth embodiment.

[0059] Figure 23 It is a schematic cross-sectional view illustrating a part of an image display device according to a modified example of the fourth embodiment.

[0060] Figure 24A It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a modified example of the fourth embodiment.

[0061] Figure 24B It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to a modified example of the fourth embodiment.

[0062] Figure 25 It is a graph illustrating the characteristics of a pixel LED element.

[0063] Figure 26 It is a block diagram illustrating an image display device according to a fifth embodiment.

[0064] Figure 27 It is a block diagram illustrating an image display device according to a modified example of the fifth embodiment.

[0065] Figure 28 It is a perspective view schematically illustrating an image display device according to the first to fourth embodiments and the above-described modified examples. Detailed Embodiments

[0066] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0067] It should be noted that the drawings are schematic or conceptual drawings, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as the actual situation. In addition, even when showing the same part, the mutual dimensions and ratios may sometimes be shown differently depending on the drawings.

[0068] It should be noted that in the present application specification and each drawing, for the main components that are the same as those of the components related to the already shown drawings, the same reference numerals are used, and the detailed description is appropriately omitted.

[0069] (First Embodiment)

[0070] Figure 1A schematic cross-sectional view of a part of an image display device according to an exemplary embodiment.

[0071] Figure 1 Schematically shows the structure of sub-pixel 20-1 of the image display device according to the present embodiment. A pixel constituting an image displayed on the image display device is composed of a plurality of sub-pixels. In Figure 1 In addition to sub-pixel 20-1, a part of the structure of sub-pixel 20-2 is also shown.

[0072] Hereinafter, the description will sometimes be made using a three-dimensional coordinate system of XYZ. Sub-pixels 20-1 and 20-2 are arranged on a two-dimensional plane. The two-dimensional plane on which sub-pixels 20-1 and 20-2 are arranged is the XY plane. Sub-pixels 20-1 and 20-2 are arranged along the X-axis direction and the Y-axis direction. Figure 1 Represents the vector cross-section of line A-A' of Figure 4 described later, and becomes a cross-sectional view in which the cross-sections of a plurality of planes perpendicular to the XY plane are connected together. In other drawings, as Figure 1 shown, in the cross-sectional views of a plurality of planes perpendicular to the XY plane, the X-axis and the Y-axis are not shown, and the Z-axis perpendicular to the XY plane is shown. That is, in the above-mentioned drawings, the plane perpendicular to the Z-axis is used as the XY plane.

[0073] Sub-pixels 20-1 and 20-2 each have light-emitting surfaces 153S1 and 153S2 that are substantially parallel to the XY plane. Light-emitting surfaces 153S1 and 153S2 mainly emit light in the positive direction of the Z-axis that is substantially orthogonal to the XY plane.

[0074] As Figure 1 shown, sub-pixel 20-1 of the image display device according to the present embodiment includes: a substrate 102, a transistor (circuit element) 103, a first wiring layer (first wiring layer) 110, a first interlayer insulating film (first insulating film) 112, a graphene sheet 140-1, a light-emitting element 150-1, a second interlayer insulating film (second insulating film) 156, a plurality of through holes 161d, 161k, 161k-1, and a second wiring layer (second wiring layer) 160.

[0075] In the present embodiment, the image display device has sub-pixel 20-2. For example, sub-pixel 20-2 is arranged adjacent to sub-pixel 20-1. Sub-pixel 20-2 includes: a substrate 102, a first wiring layer 110, a first interlayer insulating film 112, a second interlayer insulating film 156, a through hole 161k, and a second wiring layer 160, and the above-mentioned layers are shared with sub-pixel 20-1. In Figure 1 In it, the transistor for sub-pixel 20-2 is not shown, and a transistor for driving the light-emitting element 150-2 is additionally provided.

[0076] In this embodiment, the substrate 102 on which the circuit element including the transistor 103 is formed is a light-transmissive substrate, such as a glass substrate. The substrate 102 has a first surface 102a, and the first surface 102a is a surface substantially parallel to the XY plane. The transistor 103 is a thin film transistor (TFT) and is formed on the first surface 102a. The light-emitting elements 150-1 and 150-2 are driven by the TFTs formed on the glass substrate. The process of forming circuit elements including TFTs on a large glass substrate has been established for manufacturing liquid crystal panels, organic EL panels, etc., and has the advantage of being able to utilize existing equipment.

[0077] The sub-pixels 20-1 and 20-2 also include color filters 180. The color filters (wavelength conversion components) 180 are provided on the surface resin layer 170 via a transparent thin film adhesive layer 188. The surface resin layer 170 is provided on the interlayer insulating film 156 and the wiring layer 160.

[0078] The structure of the sub-pixels 20-1 and 20-2 will be described in detail.

[0079] The transistor 103 is formed on the TFT lower layer film 106 formed on the first surface 102a of the substrate 102. The TFT lower layer film 106 is provided for the purpose of ensuring flatness when forming the transistor 103 and protecting the TFT channel 104 of the transistor 103 from contamination during heat treatment. The TFT lower layer film 106 is, for example, SiO 2 etc.

[0080] On the substrate 102, in addition to the transistor 103 for driving the light-emitting element 150-1, transistors for driving the light-emitting element 150-2, other transistors, capacitors, and other circuit elements are also formed, and a circuit 101 is formed by wirings and the like. For example, the transistor 103 corresponds to the driving transistor 26 described later Figure 3 as shown.

[0081] Hereinafter, it is assumed that the circuit 101 includes: a TFT channel 104, an insulating layer 105, an insulating film 108, vias 111s and 111d, and a wiring layer 110. Sometimes, including the substrate 102, the TFT lower layer film 106, the circuit 101, and other structural main components such as the interlayer insulating film 112, it is called a circuit board 100.

[0082] The transistor 103 is a p-channel TFT in this example. The transistor 103 includes a TFT channel 104 and a gate 107. The TFT is preferably formed by a Low Temperature Poly Silicon (LTPS) process. The TFT channel 104 is a region of polycrystalline Si formed on the substrate 102. The region formed as amorphous Si is annealed by laser irradiation to be polycrystallized and activated. The TFT formed by the LTPS process has a sufficiently high mobility.

[0083] The TFT channel 104 includes regions 104s, 104i, and 104d. The regions 104s, 104i, and 104d are all provided on the TFT lower layer film 106. The region 104i is provided between the regions 104s and 104d. The regions 104s and 104d are doped with p-type impurities such as boron ions (B + ), boron fluoride ions (BF 2 + ), etc., and are ohmically connected to the vias 111s and 111d.

[0084] The gate 107 is provided on the TFT channel 104 via the insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 from the gate 107 and from other adjacent circuit elements. When a potential lower than that of the region 104s is applied to the gate 107, a channel is formed in the region 104i, and the current flowing between the regions 104s and 104d can be controlled.

[0085] The insulating layer 105 is, for example, SiO 2 . Depending on the covered region, the insulating layer 105 may also be a multilayer insulating layer containing SiO 2 , Si 3 N 4 , etc.

[0086] The gate 107 is, for example, polycrystalline Si. The polycrystalline Si film of the gate 107 can be manufactured by an ordinary CVD (Chemical Vapor Deposition) process.

[0087] In this example, the gate 107 and the insulating layer 105 are covered by the insulating film 108. The insulating film 108 is, for example, SiO 2 , Si 3 N 4 , etc. The insulating film 108 serves as a planarization film for forming the wiring layer 110. The insulating film 108 is, for example, a multilayer insulating film containing SiO 2 , Si 3 N 4 , etc.

[0088] Through holes 111s and 111d are formed to penetrate the insulating film 108. A first wiring layer (first wiring layer) 110 is formed on the insulating film 108. The first wiring layer 110 includes a plurality of wirings having different potentials, including wirings 110s, 110d, and 110k. In Figure 1 In the wiring layers of the subsequent cross-sectional views, in order to label the marks, the marks of the wirings are indicated at positions beside one of the wirings included in the wiring layer.

[0089] The through hole 111s is provided between the wiring 110s and the region 104s and electrically connects them. The through hole 111d is provided between the wiring 110d and the region 104d and electrically connects them.

[0090] In this example, the wiring 110s electrically connects the source region of the transistor 103, that is, the region 104s, to the Figure 3 power supply line 3 shown later. As will be described later, the wiring 110d is electrically connected to the p-type semiconductor layer 153-1 on the light emitting surface 153S1 side of the light emitting element 150-1 via the through hole 161d, the wiring 160a-1, and the light transmissive electrode 159a1.

[0091] In this example, the wiring 110k is connected to the ground line 4 shown later via the through hole 161k, the wiring 160k, and the light transmissive electrode 159k. The wiring 110k is not limited to the ground line 4 and may be connected to the power supply line 3 or other potentials, or may not be connected to any potential. Figure 3 The wiring (second part) 110k is provided below the light emitting elements 150-1 and 150-2 and serves as a light reflecting plate for reflecting the light emitted downward by the light emitting elements 150-1 and 150-2. The outer periphery of the wiring 110k is set so as to include the entire outer periphery of the light emitting elements 150-1 and 150-2 when the light emitting elements 150-1 and 150-2 are projected onto the wiring 110k in the XY top view. By appropriately selecting the material of the wiring 110k, the scattered light of the light emitting elements 150-1 and 150-2 downward can be reflected toward the light emitting surfaces 153S1 and 153S2, improving the light emitting efficiency.

[0092] The wiring (second part) 110k is provided below the light emitting elements 150-1 and 150-2 and serves as a light reflecting plate for reflecting the light emitted downward by the light emitting elements 150-1 and 150-2. The outer periphery of the wiring 110k is set so as to include the entire outer periphery of the light emitting elements 150-1 and 150-2 when the light emitting elements 150-1 and 150-2 are projected onto the wiring 110k in the XY top view. By appropriately selecting the material of the wiring 110k, the scattered light of the light emitting elements 150-1 and 150-2 downward can be reflected toward the light emitting surfaces 153S1 and 153S2, improving the light emitting efficiency.

[0093] Since the wiring 110k reflects the downward-scattered light of the light-emitting element 150-1 toward the light-emitting surface 153S1 side, the emitted light of the light-emitting element 150-1 can be prevented from reaching the transistor 103. Since the wiring 110k also reflects the downward-scattered light of the light-emitting element 150-2 toward the light-emitting surface 153S2 side, the emitted light of the light-emitting element 150-2 can be prevented from reaching the transistor that drives the light-emitting element 150-2. The wiring 110k blocks the downward-scattered light of the light-emitting elements 150-1 and 150-2, thereby suppressing the scattered light from reaching the circuit elements including the transistor 103 and preventing malfunction of the circuit elements.

[0094] The wiring layer 110 and the vias 111s, 111d are formed of, for example, Al, an alloy of Al, a laminated film of Al and Ti, or the like. For example, on a laminated film of Al and Ti, Al is laminated on a thin film of Ti, and Ti is further laminated on Al.

[0095] A first interlayer insulating film 112 is provided on the insulating film 108 and the wiring layer 110. The interlayer insulating film (first insulating film) 112 is, for example, an organic insulating film such as PSG (Phosphorus Silicon Glass) or BPSG (Boron Phosphorus Silicon Glass). The interlayer insulating film 112 insulates between circuit elements in the circuit 101 formed on the circuit board 100 and provides a flat surface for disposing the graphene sheets 140-1 and 140-2. The interlayer insulating film 112 also serves as a protective film for protecting the surface of the circuit board 100.

[0096] The graphene sheets 140-1 and 140-2 are disposed above the wiring 110k via the interlayer insulating film 112. The light-emitting element 150-1 is disposed on the graphene sheet (the first part containing graphene) 140-1, and the light-emitting element 150-2 is disposed on the graphene sheet 140-2. The outer periphery of the graphene sheet 140-1 substantially coincides with the outer periphery of the light-emitting element 150-1. The outer periphery of the graphene sheet 140-2 substantially coincides with the outer periphery of the light-emitting element 150-2.

[0097] The light-emitting element 150-1 includes an n-type semiconductor layer (first semiconductor layer) 151-1, a light-emitting layer 152-1, and a p-type semiconductor layer (second semiconductor layer) 153-1. The n-type semiconductor layer 151-1, the light-emitting layer 152-1, and the p-type semiconductor layer 153-1 are laminated in sequence from the side of the interlayer insulating film 112 toward the light-emitting surface 153S1. The lower part of the n-type semiconductor layer 151-1 has a stepped portion 151a-1. The stepped portion 151a-1 is provided so as to protrude toward the light-emitting element 150-2. The stepped portion 151a-1 is provided to connect the n-type semiconductor layer 151-1 to the through hole 161k-1.

[0098] The light-emitting element 150-2 includes an n-type semiconductor layer 151-2, a light-emitting layer 152-2, and a p-type semiconductor layer 153-2. The n-type semiconductor layer 151-2, the light-emitting layer 152-2, and the p-type semiconductor layer 153-2 are laminated in sequence from the side of the interlayer insulating film 112 toward the light-emitting surface 153S2. The lower part of the n-type semiconductor layer 151-2 has a stepped portion 151a-2. The stepped portion 151a-2 is provided so as to protrude toward the light-emitting element 150-1. The stepped portion 151a-2 is provided to connect the n-type semiconductor layer 151-2 to the through hole 161k-2.

[0099] The area of the light-emitting element in the XY plan view is set according to the emission colors of the red, green, and blue sub-pixels. The areas of the light-emitting elements 150-1 and 150-2 in the XY plan view are appropriately set according to the visual sensitivity, the conversion efficiency of the color conversion portion 182 of the color filter 180, etc. In this example, the areas of the two light-emitting elements 150-1 and 150-2 in the XY plan view are different. Since the light-emitting elements 150-1 and 150-2 are placed on the wiring 110k having a surface substantially parallel to the XY plane, the area in the XY plan view refers to the area of the region surrounded by the outer peripheries of the light-emitting elements 150-1 and 150-2 projected on the XY plane. Hereinafter, the area in the XY plan view will be simply referred to as the area. In this example, the area of the light-emitting element 150-1 is smaller than the area of the light-emitting element 150-2.

[0100] It should be noted that, in this example, the light-emitting elements 150-1 and 150-2 respectively have stepped portions 151a-1 and 151a-2. Since the stepped portions 151a-1 and 151a-2 are formed by processing the n-type semiconductor layers 151-1 and 151-2, they do not directly contribute to light emission. Therefore, when referring to the areas of the light-emitting elements 150-1 and 150-2, it means the areas of the light-emitting layers 152-1 and 152-2 in the XY plan view.

[0101] The light-emitting elements 150-1 and 150-2, for example, have a substantially square or rectangular shape in the XY top view, but the corners may also be rounded. The light-emitting element 150 may also have an elliptical shape or a circular shape in the XY top view, for example. By appropriately selecting the shape, configuration, etc. of the light-emitting element in the top view, the degree of freedom in design is improved.

[0102] The light-emitting elements 150-1 and 150-2 are, for example, suitably made of a gallium nitride-based compound semiconductor including In X Al Y Ga 1-X-Y N (0≦X, 0≦Y, X + Y < 1), etc. for the light-emitting layer. Hereinafter, the above-mentioned gallium nitride-based compound semiconductor may sometimes be simply referred to as gallium nitride (GaN). The light-emitting elements 150-1 and 150-2 of one embodiment of the present invention are so-called light-emitting diodes, and the wavelength of the light emitted by the light-emitting elements 150-1 and 150-2 is, for example, about 467 nm ± 20 nm. The wavelength of the light emitted by the light-emitting elements 150-1 and 150-2 may also be blue-violet light of about 410 nm ± 20 nm. The wavelength of the light emitted by the light-emitting elements 150-1 and 150-2 is not limited to the above values and may be an appropriate value.

[0103] The second interlayer insulating film 156 covers the first interlayer insulating film 112, the graphene sheets 140-1 and 140-2, and the light-emitting elements 150-1 and 150-2. The interlayer insulating film 156 is formed of, for example, an organic insulating material or the like. By covering the light-emitting elements 150-1 and 150-2, the graphene sheets 140-1 and 140-2, etc., the interlayer insulating film 156 protects the above-mentioned light-emitting elements, graphene sheets, etc. from the influence of the surrounding environment such as dust and humidity. By covering the light-emitting element 150, the graphene sheets 140-1 and 140-2, etc., the interlayer insulating film 156 has a function of insulating the above-mentioned light-emitting elements, graphene sheets, etc. from other conductive objects. The surface of the interlayer insulating film 156 only needs to have flatness such that a wiring layer 160 can be formed on the interlayer insulating film 156.

[0104] The organic insulating material used for the interlayer insulating film 156 is preferably a white resin. The white resin interlayer insulating film 156 reflects the lateral emitted light of the light-emitting elements 150-1 and 150-2 and the backward light generated at the interface of the color filter 180 or the like, and can actually improve the light-emitting efficiency of the light-emitting elements 150-1 and 150-2.

[0105] The white resin is formed by dispersing scattering particles having a Mie scattering effect in a transparent resin such as a silicon-based resin like SOG (Spin On Glass) or a novolak-type phenolic resin. The particles are colorless or white and have a diameter ranging from about 1 / 10 to several times the wavelength of the light emitted by the light-emitting elements 150-1 and 150-2. Particles having a diameter of about 1 / 2 of the wavelength of light are suitable as the scattering particles. For example, as the above-mentioned scattering particles, TiO 2 , Al 2 SO 3 , ZnO can be cited. Alternatively, the white resin can also be formed by utilizing a large number of fine pores dispersed in the transparent resin. In the interlayer insulating film 156, instead of SOG or the like, for example, a SiO 2 film formed by ALD (Atomic-layer-deposition) or CVD can be used to whiten it.

[0106] The second interlayer insulating film 256 can also be a black resin. By making the interlayer insulating film 256 a black resin, scattering of light within the sub-pixels 20-1 and 20-1 can be suppressed, and stray light can be more effectively suppressed. An image display device with suppressed stray light can display a clearer image.

[0107] The through hole 161k-1 is provided so as to penetrate the second interlayer insulating film 156. One end of the through hole 161k-1 is connected to the step portion 151a-1. The through hole 161k-1 is provided so as to penetrate the second interlayer insulating film 156. One end of the through hole 161k-2 is connected to the step portion 151a-2.

[0108] The through hole (second through hole) 161k is provided so as to penetrate the interlayer insulating films 112 and 156. One end of the through hole 161k is connected to the wiring 110k.

[0109] The through hole (first through hole) 161d is provided so as to penetrate the interlayer insulating films 112 and 156. One end of the through hole 161d is connected to the wiring 110d.

[0110] The wiring layer 160 is provided on the interlayer insulating film 156. The wiring layer 160 includes wirings 160a-1 and 160k. The wiring 160a-1 is connected to the other end of the through hole 161d.

[0111] The transparent electrode 159a1 is provided over the wiring 160a-1. The transparent electrode 159a1 is provided over the light-emitting surface 153S1 of the light-emitting element 150-1. The transparent electrode 159a1 is provided between the wiring 160a-1 and the light-emitting surface 153S1, and electrically connects the wiring 160a-1 and the p-type semiconductor layer 153-1. Accordingly, the anode electrode of the light-emitting element 150-1, i.e., the p-type semiconductor layer 153-1, is electrically connected to the drain electrode of the transistor 103, i.e., the channel region 104d, via the transparent electrode 159a1, the wiring 160a-1, the through hole 161d, and the wiring 110d.

[0112] The transparent electrode 159a2 is provided over the light-emitting surface 153S2 of the light-emitting element 150-2. Similar to the case of the light-emitting element 150-1, the light-emitting surface 153S2 is electrically connected to the transistor that drives the light-emitting element 150-2 via the transparent electrode 159a2, the wiring included in the wiring layer 160, and the through holes that penetrate the interlayer insulating films 112 and 156. Both the light-emitting surfaces 153S1 and 153S2 are roughened.

[0113] The wiring 160k is connected to the other ends of the through holes 161k, 161k-1, and 161k-2. The transparent electrode 159k is provided over the wiring 160k. The wiring 160k and the transparent electrode 159k are connected to the Figure 3 ground wire 4 shown later. Accordingly, the n-type semiconductor layers 151-1 and 151-2 are connected to the ground wire 4 via the through holes 161k-1, 161k-2, the wiring 160k, and the transparent electrode 159k. Further, in this example, the wiring 110k is connected to the ground wire 4 together with the n-type semiconductor layers 151-1 and 151-2.

[0114] The source electrode of the transistor 103, i.e., the region 104s of the TFT channel 104, is electrically connected to the Figure 3 power supply line 3 shown later.

[0115] The surface resin layer 170 covers the second interlayer insulating film 156, the second wiring layer 160, and the transparent electrodes 159a1, 159a2, and 159k. The surface resin layer 170 is a transparent resin that protects the second interlayer insulating film 156, the wiring layer 160, and the transparent electrodes 159a1, 159a2, and 159k, and provides a flat surface for bonding the color filter 180.

[0116] The color filter 180 includes a light-shielding portion 181 and a color conversion portion 182. The color conversion portion 182 is disposed directly above the light-emitting surfaces 153S1 and 153S2 of the light-emitting elements 150-1 and 150-2 according to the shapes of the light-emitting surfaces 153S and 153S2. In the color filter 180, the portion other than the color conversion portion 182 is the light-shielding portion 181. The light-shielding portion 181 is a so-called black matrix, which reduces blurring caused by color mixing of light emitted from adjacent color conversion portions 182 and can display a clear image.

[0117] The color conversion portion 182 is one or two layers. Figure 1 Indicates the portion of two layers. Whether the color conversion portion 182 is one layer or two layers depends on the color of the light emitted from the sub-pixels 20-1 and 20-2, that is, the wavelength. When the emission colors of the sub-pixels 20-1 and 20-2 are red or green, the color conversion portion 182 is preferably two layers, namely the color conversion layer 183 and the light filter layer 184 described later. When the emission color of the sub-pixels 20-1 and 20-2 is blue, it is preferably one layer.

[0118] When the color conversion portion 182 is two layers, the first layer closer to the light-emitting elements 150-1 and 150-2 is the color conversion layer 183, and the second layer is the light filter layer 184. That is, the light filter layer 184 is laminated on the color conversion layer 183.

[0119] The color conversion layer 183 is a layer that converts the wavelength of the light emitted from the light-emitting elements 150-1 and 150-2 into a desired wavelength. For example, when the sub-pixel emits red light, the color conversion layer 183 converts the light with a wavelength of 467nm ± 20nm, which is the wavelength of the light-emitting element 150-1, into light with a wavelength of about 630nm ± 20nm. When the sub-pixel emits green light, the color conversion layer 183 converts the light with a wavelength of 467nm ± 20nm, which is the wavelength of the light-emitting element, into light with a wavelength of about 532nm ± 20nm.

[0120] The light filter layer 184 blocks the wavelength component of blue light that remains without being color-converted by the color conversion layer 183.

[0121] When the color of the light emitted from the sub-pixel is blue, the light-emitting element of this sub-pixel can output light via the color conversion layer 183 or directly output light without passing through the color conversion layer 183. When the wavelength of the light emitted from the light-emitting element is about 467nm ± 20nm, the light-emitting element of this sub-pixel can also output light without passing through the color conversion layer 183. When the wavelength of the light emitted from the light-emitting element is 410nm ± 20nm, in order to convert the wavelength of the output light into about 467nm ± 20nm, it is preferable to provide one layer of the color conversion layer 183.

[0122] Even in the case of a blue sub-pixel, the sub-pixel may include a filter layer 184. By providing the filter layer 184 in the blue sub-pixel, minute reflection of external light generated on the surface of the light-emitting element of the sub-pixel can be suppressed.

[0123] (Variation Example)

[0124] Modifications of the sub-pixel structure will be described.

[0125] Figure 2A and Figure 2B This is a schematic cross-sectional view illustrating a part of a modification example of the image display device according to the present embodiment.

[0126] exist Figure 2A In, for Figure 1 The light emitting element 150-1 is shown as one of the two light emitting elements 150-1 and 150-2. The structures including the two light emitting elements 150-1 and 150-2 are the same. Regarding this modification, the structure including the light emitting element 150-1 will be described below. Figure 2B In the description, the structure of the light emitting element 150a-1 including one of the two light emitting elements is also described.

[0127] exist Figure 2A In the subsequent cross-sectional views of the sub-pixels, the surface resin layer 170 and the color filter 180 are not shown in order to avoid complication. In the subsequent drawings, unless otherwise specified, the surface resin layer 170 and the color filter 180 are provided on the second interlayer insulating film 156, 256 and the second wiring layer 160. For other embodiments and their modified examples described later, the surface resin layer 170 and the color filter 180 are also not shown in the drawings.

[0128] exist Figure 2A In the sub-pixel 20a-1, the connection method between the light emitting element 150-1 and the wiring 160a1-1 is different from that in the first embodiment. The same reference numerals are used for the same structural main components, and detailed descriptions are appropriately omitted.

[0129] like Figure 2A As shown, the sub-pixel 20a-1 includes a wiring 160a1-1. The wiring 160a1-1 extends to the light-emitting surface 153S1 of the light-emitting element 150-1, and is electrically connected to the surface of the p-type semiconductor layer 153-1 including the light-emitting surface 153S1 at one end of the wiring 160a1-1. The light-emitting surface 153S1 and the surface including the light-emitting surface 153S1 are surfaces on the same plane.

[0130] The light-emitting surface 153S1 is the same as in the above-described embodiment, and preferably, roughening is performed as described in this example. When the light-emitting element 150-1 has a roughened light-emitting surface 153S1, the light extraction efficiency can be improved.

[0131] In Figure 2B sub-pixel 20b-1, the difference from the case of the first embodiment is that the light-emitting element 150a-1 includes a p-type semiconductor layer 153a-1 that is not roughened. In sub-pixel 20b-1, the connection method of the light-emitting element 150a-1 to the wiring 160a2-1 is different from the case of the first embodiment. Sub-pixel 20b-1 of this modification includes a second interlayer insulating film (second insulating film) 256 that is different from the case of the first embodiment.

[0132] As Figure 2B shown, in sub-pixel 20b-1, the second interlayer insulating film 256 is a resin having light transmittance, preferably a transparent resin. As the transparent resin material, a silicon-based resin such as SOG or a novolak-type phenolic resin can be used. The light-emitting element 150a-1 emits light from the light-emitting surface 153S1 through the transparent interlayer insulating film 256. The light-emitting surface 153S1 is connected to the wiring 160a2-1 of the second wiring layer 160 through a contact hole.

[0133] In sub-pixel 20b-1 of this modification, since the light-emitting element 150a-1 emits light from the light-emitting surface 153S1 through the interlayer insulating film 256, the process of forming an opening in the interlayer insulating film 256 and the process of roughening the light-emitting surface 153S1 can be omitted.

[0134] In this embodiment, any one of the structures of the sub-pixels 20-1, 20a-1, and 20b-1 shown above may be included.

[0135] Figure 3 is a schematic block diagram illustrating the image display device of this embodiment.

[0136] As Figure 3 shown, the image display device 1 of this embodiment has a display area 2. Sub-pixels 20 are arranged in the display area 2. The sub-pixels 20 are arranged in a grid pattern, for example. For example, n sub-pixels 20 are arranged along the X-axis and m sub-pixels 20 are arranged along the Y-axis.

[0137] Pixel 10 includes a plurality of sub-pixels 20 that emit light of different colors. Sub-pixel 20R emits red light. Sub-pixel 20G emits green light. Sub-pixel 20B emits blue light. By emitting light with desired brightness from the three sub-pixels 20R, 20G, and 20B, the emission color and brightness of one pixel 10 can be determined.

[0138] One pixel 10 includes three sub-pixels 20R, 20G, and 20B. The sub-pixels 20R, 20G, and 20B are arranged linearly on the X-axis as shown in the example of Figure 3 For the example shown. Each pixel 10 can arrange sub-pixels of the same color in the same column, or as shown in this example, sub-pixels of different colors are arranged in each column.

[0139] The image display device 1 also has a power supply line 3 and a ground line 4. The power supply line 3 and the ground line 4 are wired in a grid pattern along the arrangement of the sub-pixels 20. The power supply line 3 and the ground line 4 are electrically connected to each sub-pixel 20, and power is supplied to each sub-pixel 20 from a DC power supply connected between the power supply terminal 3a and the GND terminal 4a. The power supply terminal 3a and the GND terminal 4a are respectively provided at the ends of the power supply line 3 and the ground line 4 and are connected to a DC power supply circuit provided outside the display area 2. The power supply terminal 3a supplies a positive voltage with reference to the GND terminal 4a.

[0140] The image display device 1 also has a scanning line 6 and a signal line 8. The scanning line 6 is wired in a direction parallel to the X-axis. That is, the scanning line 6 is wired along the arrangement of the sub-pixels 20 in the row direction. The signal line 8 is wired in a direction parallel to the Y-axis. That is, the signal line 8 is wired along the arrangement of the sub-pixels 20 in the column direction.

[0141] The image display device 1 also has a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 in each column via the scanning line 6 and supplies a selection signal to each sub-pixel 20.

[0142] The signal voltage output circuit 7 is provided along the X-axis direction of the outer edge of the display area 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 in each row via the signal line 8 and supplies a signal voltage to each sub-pixel 20.

[0143] The sub-pixel 20 includes: a light-emitting element 22, a selection transistor 24, a driving transistor 26, and a capacitor 28. In Figure 3 Sometimes, the selection transistor 24 is denoted as T1, the driving transistor 26 is denoted as T2, and the capacitor 28 is denoted as Cm.

[0144] The light-emitting element 22 is connected in series with the driving transistor 26. In the present embodiment, the driving transistor 26 is a p-channel TFT, and an anode electrode connected to the p-type semiconductor layer of the light-emitting element 22 is connected to the main electrode, i.e., the drain electrode, of the driving transistor 26. The series circuit of the light-emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 corresponds to Figure 1transistor 103, the light-emitting element 22 corresponds to Figure 1 light-emitting elements 150, 150a. According to the voltage applied between the gate and source of the driving transistor 26, the current flowing through the light-emitting element 22 is determined, and the light-emitting element 22 emits light with a brightness corresponding to the flowing current.

[0145] The selection transistor 24 is connected between the gate electrode of the driving transistor 26 and the signal line 8 via the main electrode. The gate electrode of the selection transistor 24 is connected to the scanning line 6. A capacitor 28 is connected between the gate electrode of the driving transistor 26 and the power supply line 3.

[0146] The row selection circuit 5 selects one row from the arrangement of the sub-pixels 20 in m rows and supplies a selection signal to the scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having a required analog voltage value to each of the sub-pixels 20 in the selected row. A signal voltage is applied between the gate and source of the driving transistor 26 of the sub-pixels 20 in the selected row. The signal voltage is held by the capacitor 28. The driving transistor 26 causes a current corresponding to the signal voltage to flow through the light-emitting element 22. The light-emitting element 22 emits light with a brightness corresponding to the current flowing through the light-emitting element 22.

[0147] The row selection circuit 5 sequentially switches the selected rows and supplies the selection signal. That is, the row selection circuit 5 scans the rows in which the sub-pixels 20 are arranged. A current corresponding to the signal voltage flows through the light-emitting elements 22 of the sequentially scanned sub-pixels 20 and emits light. Each pixel 10 emits light with a light-emitting color and brightness determined by the light-emitting color and brightness emitted by the sub-pixels 20 of each of the RGB colors, and an image is displayed in the display area 2.

[0148] Figure 4 is a schematic top view showing a part of the image display device according to the present embodiment.

[0149] In the present embodiment, as described in Figure 1 , the light-emitting element 150-1 (in Figure 3 is the light-emitting element 22) and the driving transistor 103 (in Figure 3 is the driving transistor 26) are laminated in the Z-axis direction. The anode electrode of the light-emitting element 150-1 is electrically connected to the drain electrode of the transistor 103 through the via hole 161d. In addition, the cathode electrode of the light-emitting element 150-1 is connected to the Figure 3 ground wire 4 shown in, through the via hole 161k-1. The same applies to the light-emitting element 150-2, and the anode electrode and the cathode electrode are electrically connected to a predetermined circuit through the via holes. Figure 4 The above three-dimensional structure is decomposed into two top views and schematically shown.

[0150] Figure 4The upper part schematically shows a top view of the first layer, and the lower part schematically shows a top view of the second layer. In Figure 4 , the first layer is denoted as "I", and the second layer is denoted as "II". The first layer is the layer on which the light-emitting elements 150-1 and 150-2 are formed. That is, the first layer represents the main components closer to the positive side of the Z-axis than the first interlayer insulating film 112 in Figure 1 . Figure 4 The main components shown are the layers from the graphene sheets 140-1 and 140-2 to the second wiring layer 160. In Figure 4 , the second interlayer insulating film 156 is not shown.

[0151] The second layer represents the main components closer to the positive side of the Z-axis than the TFT lower layer film 106 in Figure 1 . Figure 4 The main components shown are the layers from the transistor 103 to the first interlayer insulating film 112. In Figure 4 , the substrate 102, the insulating layer 105, the insulating film 108, and the first interlayer insulating film 112 are not shown.

[0152] Figure 1 The cross-sectional view of Figure 4 is the vector cross-section of the AA' line indicated by a one-dot chain line for each of the first layer and the second layer in

[0153] In the present embodiment, the wiring 160k of the first layer is provided to extend along the Y-axis direction between the light-emitting elements 150-1 and 150-2. The wiring 110s of the second layer extends in the positive direction of the Y-axis at substantially the same X coordinate as the wiring 160k. The wiring 110s avoids the wiring 110k, bends in the X-axis direction, extends in the X-axis direction along the outer periphery of the wiring 110k, and then bends again in the Y-axis direction. After bending in the Y-axis direction, the wiring 110s extends in the positive direction of the Y-axis along the outer periphery of the wiring 110k.

[0154] The AA' line crosses the wiring 160k, the light-transmissive electrode 159k, and the wiring 110s on the negative side of the Y-axis direction closer than the light-emitting elements 150-1 and 150-2 and the wiring 110k. That is, in Figure 1 , on the A side of the AA' line, at the positions where the wiring 160k, the light-transmissive electrode 159k, and the wiring 110s should be shown, since the drawing is complicated, the wiring 160k and the light-transmissive electrode 159k are not shown in the illustrated B area. The same applies to other embodiments described below.

[0155] As Figure 4 shown, the light-emitting elements 150-1 and 150-2 are provided above the wiring 110k. The wiring 110k and Figure 1The through-hole 161k shown is connected in the second layer. The through-hole 161k and the wiring 160k are connected at the via-hole 162k.

[0156] Figure 1 One end of the through-hole 161k-1 shown is connected to the stepped portion 151a-1 of the light-emitting element 150-1. The other end of the through-hole 161k-1 is connected to the wiring 160k at the via-hole 162k-1. Figure 1 One end of the through-hole 161k-2 shown is connected to the stepped portion 151a-2 of the light-emitting element 150-2. The other end of the through-hole 161k-2 is connected to the wiring 160k at the via-hole 162k-2. The light-transmissive electrode 159k is provided over the wiring 160k, and the wiring 160k and the light-transmissive electrode 159k are connected to the ground wire 4.

[0157] The light-emitting element 150-1 has an opening 158-1 provided in the Figure 1 interlayer insulating film 156 shown. In this example, the through-hole 161d is separated from the light-emitting element 150-1 in the negative X-axis direction and is provided adjacent thereto. The through-hole 161d is Figure 4 schematically shown by a double-dashed line in. In the first layer, the through-hole 161d is connected to the wiring 160a-1 through the contact hole 162d1. The light-transmissive electrode 159a1 is provided over the light-emitting element 150-1 and the wiring 160a-1 exposed from the opening 158-1, and electrically connects the light-emitting element 150-1 and the through-hole 161d. In the second layer, the through-hole 161d is connected to the wiring 110d through the contact hole 162d2.

[0158] The wiring 110d passes through the Figure 1 contact hole 111c1 opened in the insulating film 108 shown, and is Figure 1 connected to the through-hole 111d shown, and is connected to the drain electrode provided in the TFT channel 104 of the transistor 103.

[0159] In this way, through the through-hole 161d penetrating the two interlayer insulating films 112 and 156, the light-emitting element 150-1 formed in the first layer is electrically connected to the wiring 110d formed in a layer different from the first layer, i.e., the second layer, and the light-emitting element 150-1 can be electrically connected to the transistor 103. Similarly, the interlayer connection between the light-emitting element 150-2 and the transistor driving the light-emitting element 150-2 is also performed through a through-hole provided by penetrating two interlayer insulating films.

[0160] Using Figure 4 , the arrangement of the wiring 110k and the light-emitting elements 150-1 and 150-2 when the downward-scattered light of the light-emitting elements 150-1 and 150-2 is reflected toward the light-emitting surfaces 153S1 and 153S2 with respect to the wiring 110k will be described.

[0161] The wiring 110k is square with a length L1 in the X-axis direction and a length W1 in the Y-axis direction in the XY top view. On the other hand, the light-emitting element 150-1 has a square bottom surface with a length L21 in the X-axis direction and a length W2 in the Y-axis direction in the XY top view. The light-emitting element 150-2 has a square bottom surface with a length L22 in the X-axis direction and a length W2 in the Y-axis direction in the XY top view.

[0162] The lengths of each part are set such that L1 > L21, L1 > L22, and W1 > W2. That is, the area of the wiring 110k is set to be larger than the sum of the areas of the light-emitting elements 150-1 and 150-2. The wiring 110k is provided directly below the light-emitting elements 150-1 and 150-2, and the outer periphery of the wiring 110k includes the entire outer peripheries of the light-emitting elements 150-1 and 150-2. As long as the outer periphery of the wiring 110k includes the entire outer peripheries of the light-emitting elements 150-1 and 150-2, it is sufficient. The shape of the wiring 110k can be an appropriate arbitrary shape according to the design on the circuit board 100, etc., and is not limited to the case of being square.

[0163] The light-emitting elements 150-1 and 150-2 emit light upward, and there is downward light emission, reflected light, scattered light, etc. at the interface between the interlayer insulating film 112 and the surface resin layer 170. The wiring layer 110 includes the wiring 110k. Since the wiring layer 110 is formed of a conductor such as metal, the wiring 110k has a light reflectivity corresponding to the material. Therefore, the scattered light from the light-emitting elements 150-1 and 150-2 downward is reflected upward by the wiring 110k. As a result, the proportion of the light emitted from the light-emitting elements 150-1 and 150-2 that is distributed toward the light-emitting surfaces 153S1 and 153S2 increases, and the actual luminous efficiency of the light-emitting elements 150-1 and 150-2 is improved. In addition, by providing the wiring 110k in this way, it is possible to suppress light from reaching below the light-emitting elements 150-1 and 150-2. Therefore, even when circuit elements are arranged near directly below the light-emitting elements 150-1 and 150-2, the influence of light on the circuit elements can be reduced.

[0164] As described above, the wiring 110k is not limited to being connected to the ground wire 4, and can also be connected to other potentials such as the potential of the power supply line 3 according to the circuit structure and circuit design.

[0165] A method for manufacturing the image display device 1 of the present embodiment will be described.

[0166] Figures 5A - 7B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device of the present embodiment.

[0167] As Figure 5AAs shown, in the manufacturing method of the image display device 1 of the present embodiment, a circuit board 1100 is prepared. The circuit board (first substrate) 1100 includes a circuit 101 described in Figure 1 etc. The circuit 101 includes a first wiring layer 110, and the wiring layer 110 includes wirings 110s, 110d, and 110k. In the circuit board 1100, a first interlayer insulating film 112 is provided to cover the wiring layer 110.

[0168] As Figure 5B shown, a graphene layer 1140 is formed on the interlayer insulating film (first insulating film) 112. The graphene layer 1140 is a layer containing graphene, and is preferably formed by laminating single-layer graphene layers. The graphene layer 1140 cut into an appropriate size and shape is adhered to the interlayer insulating film 112 with an adhesive, for example. In this case, the graphene layer 1140 is preferably cut into a size sufficiently larger than the area of the light-emitting elements 150-1 and 150-2 formed on the graphene layer 1140 and adhered to the interlayer insulating film 112. In order to form the light-emitting elements 150-1 and 150-2 on the graphene layer 1140, for example, the outer periphery of the graphene layer 1140 is set to a size sufficient to include the outer periphery of the wiring 110k.

[0169] As Figure 6A shown, a semiconductor layer 1150 is formed over the graphene layer 1140 cut into an appropriate size and shape and attached to the interlayer insulating film 112. The semiconductor layer 1150 is formed in the order of an n-type semiconductor layer 1151, a light-emitting layer 1152, and a p-type semiconductor layer 1153 from the graphene layer 1140 side in the positive direction of the Z axis. In the initial stage of the growth of the semiconductor layer 1150, crystal defects are likely to occur due to lattice mismatch, and a crystal mainly composed of GaN generally exhibits n-type semiconductor characteristics. Therefore, by growing from the n-type semiconductor layer 1151 on the graphene layer 1140, the yield can be improved.

[0170] The formation of the semiconductor layer 1150 can use physical vapor growth methods such as evaporation, ion beam deposition, molecular beam epitaxy (MBE), sputtering, etc., and preferably use the low-temperature sputtering method. It should be noted that in the low-temperature sputtering method, when assisted by light or plasma during film formation, a lower temperature can be achieved, so it is preferred. In epitaxial growth by MOCVD, sometimes it exceeds 1000 °C. In contrast, in the low-temperature sputtering method, it is known that at a low temperature of about 400 °C to about 700 °C, a GaN crystal including a light-emitting layer can be epitaxially grown on the graphene layer 1140 (refer to Non-Patent Documents 1, 2, etc.). The above low-temperature sputtering method is consistent with forming the semiconductor layer 1150 on a circuit board having a TFT formed by the LTPS process. By using an appropriate film formation technique, a GaN semiconductor layer 1150 is grown on the graphene layer 1140, whereby a single-crystallized semiconductor layer 1150 including the light-emitting layer 1152 is formed on the graphene layer 1140. The graphene layer 1140 is cut into an appropriate size and shape and attached, so in the position where the graphene layer 1140 does not exist, as Figure 6A shown by the dashed line, a deposit 1160 including GaN that is not single-crystallized is formed.

[0171] In this embodiment, by using the graphene layer 1140 as a seed crystal, the crystal growth of GaN is promoted. It should be noted that a conductive buffer layer can also be provided on the graphene layer 1140, and on this buffer layer, the semiconductor layer is grown by the above sputtering method or the like. The buffer layer can be any material as long as it promotes the crystal growth of GaN, regardless of the type. For example, as the buffer layer, a metal layer containing single crystals such as Hf and Cu can also be used.

[0172] As Figure 6B shown, the semiconductor layer 1150 is formed into a desired shape by RIE (Reactive Ion Etching), etc., to form the light-emitting elements 150-1 and 150-2. At this time, Figure 6A the graphene layer 1140 shown is over-etched and formed into graphene sheets 140-1 and 140-2 having an outer peripheral shape corresponding to the outer peripheral shape of the light-emitting elements 150-1 and 150-2. In this example, the area of the light-emitting element 150-1 in the XY top view is set smaller than the area of the light-emitting element 150-2 in the XY top view.

[0173] After that, a second interlayer insulating film (second insulating film) 156 covering the first interlayer insulating film 112, the graphene sheets 140-1 and 140-2, and the light-emitting elements 150-1 and 150-2 is formed.

[0174] As Figure 7AAs shown, via holes 162k-1 and 162k-2 penetrate through the second interlayer insulating film 156 and are formed. Via holes 162d and 162k penetrate through the interlayer insulating films 112 and 156 and are formed. When forming the via holes 162k, 162k-1, 162k-2, and 162d, openings 158-1 and 158-2 are formed in the interlayer insulating film 156 to expose the light emitting surfaces 153S1 and 153S2. The formation of the openings 158-1 and 158-2 can be performed before or after the formation of the via holes 162k, 162k-1, 162k-2, and 162d. The exposed light emitting surfaces 153S1 and 153S2 are roughened.

[0175] As Figure 7B shown, conductive material is filled into the via holes 162d, 162k, 162k-1, and 162k-2 as Figure 7A shown. Thereafter, or simultaneously with the filling of the via holes and the like, the second wiring layer 160 is formed. A transparent electrode 159a1 is formed over the light emitting surface 153S1 and the wiring 160a-1 to electrically connect the p-type semiconductor layer 153-1 and the wiring 160a-1. At the same time, a transparent electrode 159a2 is formed over the light emitting surface 153S2, and the transparent electrode 159a2 is electrically connected to an electrode of another driving transistor different from the transistor 103. A transparent electrode 159k is also formed on the wiring 160k.

[0176] It should be noted that, as described above, the interlayer insulating film 156 can cover the light emitting elements 150-1, 150-2, etc. for insulation. The flatness of the interlayer insulating film 156 can be such that the second wiring layer 160 can be formed on the interlayer insulating film 156, and planarization may not be performed when forming the interlayer insulating film 156. In the case where the interlayer insulating film 156 is not planarized, in addition to being able to reduce the processes for planarization, there is also an advantage that the thickness of the interlayer insulating film 156 can be reduced at positions other than the positions where the light emitting elements 150-1 and 150-2 are formed. The depth of the via holes 162k, 162k-1, 162k-2, and 162d can be reduced at positions where the thickness of the interlayer insulating film 156 is thin. By forming the via holes shallower, it is possible to ensure a sufficient opening diameter throughout the depth of the via holes, so it is easy to ensure electrical connection by the through holes. Therefore, it is possible to suppress the reduction in yield due to electrical characteristic problems.

[0177] Figure 8A and Figure 8B are schematic cross-sectional views illustrating a manufacturing method of a modified example of the image display device according to the present embodiment.

[0178] Figure 8A and Figure 8BShows the manufacturing process for forming Figure 2A the sub-pixels shown. In this modification, before forming the openings 158-1 and 158-2, the processes are the same as those in the above-described other embodiments. Therefore, hereinafter, as the manufacturing process of this modification, the case where the processes of Figure 7A after and Figure 8A and Figure 8B are performed will be described.

[0179] As Figure 8A shown, after forming the openings 158-1 and 158-2 to expose the light-emitting surfaces 153S1 and 153S2 of the p-type semiconductor layers 153-1 and 153-2, the light-emitting surfaces 153S1 and 153S2 are roughened respectively. Conductive material is filled into the Figure 7A shown via holes 162k-1 and 162k-2 to form via holes 161k-1 and 161k-2 respectively. Conductive material is filled into the Figure 7A shown via holes 162d and 162k to form via holes 161d and 161k respectively.

[0180] As Figure 8B shown, a wiring layer 160 including respective wirings 160a1-1, 160a1-2, and 160k is formed on the interlayer insulating film 156. The wiring 160a1-1 is connected to the surface including the exposed light-emitting surface 153S1. The wiring 160a1-2 is connected to the surface including the exposed light-emitting surface 153S2.

[0181] In this way, the sub-pixels 20a-1 and 20a-2 of the modification are formed.

[0182] Figure 9A and Figure 9B are schematic cross-sectional views illustrating a manufacturing method of a modification of the image display device according to the present embodiment.

[0183] Figure 9A and Figure 9B Shows the manufacturing process for forming Figure 2B the sub-pixels shown. In this modification, before forming the light-emitting element, the processes are the same as those in the above-described other embodiments. Therefore, hereinafter, as the manufacturing process of this modification, the case where the processes of Figure 6A after and Figure 9A and Figure 9B are performed will be described. In the case of other embodiments, the interlayer insulating film 156 is formed of an opaque insulating material such as white resin. In contrast, in this modification, as described above, the interlayer insulating film 256 is formed of a light-transmissive insulating material.

[0184] As Figure 9A shown, Figure 6AThe semiconductor layer 1150 shown is shaped into a desired shape by RIE or the like to form light-emitting elements 150a-1 and 150a-2. At this time, due to over-etching of the semiconductor layer 1150, Figure 6A The graphene layer 1140 shown is shaped into graphene sheets 140-1 and 140-2 having outer peripheries corresponding to the outer peripheral shapes of the light-emitting elements 150a-1 and 150a-2. Thereafter, a second interlayer insulating film 256 is formed to cover the first interlayer insulating film 112, the graphene sheets 140-1 and 140-2, and the light-emitting elements 150a-1 and 150a-2. The interlayer insulating film 256 is an insulating resin having light-transmitting properties, and is preferably a transparent resin.

[0185] Contact holes 162a-1 and 162a-2 are formed in the second interlayer insulating film 256. Through holes 162k-1 and 162k-2 are formed to penetrate the interlayer insulating film 256. Through holes 162d and 162k are formed to penetrate the interlayer insulating films 112 and 156. For example, the contact holes and through holes are formed by RIE or the like.

[0186] As Figure 9B shown, conductive materials are filled into the Figure 9A shown contact holes 162a-1 and 162a-2 and through holes 162d, 162k, 162k-1, and 162k-2. Thereafter, a second wiring layer 160 is formed, and wirings 160a2-1, 160a2-2, and 160k are formed. One end of the wiring 160a2-1 is connected to the p-type semiconductor layer 153a-1, and the other end is connected to the wiring 110d via a via hole 161d. One end of the wiring 160a2-2 is connected to the p-type semiconductor layer 153a-2, and the other end is connected to a wiring for other driving transistors via a via hole. The second wiring layer 160 may also be formed while filling the conductive materials into the through holes 162d and 162k.

[0187] In this way, sub-pixels 20b-1 and 20b-2 of the modified example are formed.

[0188] A part of the circuit other than the sub-pixels 20-1 and 20-2 is formed in the circuit board 1100. For example, Figure 3 the row selection circuit 5 shown is formed in the circuit board 1100 together with driving transistors, selection transistors, and the like. That is, the row selection circuit 5 may sometimes be assembled simultaneously by the above manufacturing process. On the other hand, the signal voltage output circuit 7 is preferably assembled in a semiconductor device manufactured by a manufacturing process that can be highly integrated by fine processing. The signal voltage output circuit 7 is mounted on another substrate together with a CPU and other main circuit components, and is interconnected with the wiring of the circuit board 1100, for example, before or after assembling a color filter described later.

[0189] For example, the circuit board 1100 includes a light-transmissive substrate 102 formed of a glass substrate having a circuit 101. The substrate 102 is substantially square. A circuit 101 for one or more image display devices is formed on the circuit board 1100. In the case of a larger screen size or the like, the circuit 101 for constituting one image display device may be divided into a plurality of circuit boards 1100 and formed, and the divided circuits may be combined to constitute one image display device.

[0190] The circuit board 1100 includes a single substrate 102, and a plurality of circuits 101 are arranged in a lattice pattern on the single substrate 102, for example. The circuit 101 includes all sub-pixels 20 and the like required for one image display device 1. A gap of the width of a dicing groove is provided between the adjacent circuits 101. No circuit elements or the like are arranged at the ends and near the ends of the circuit 101.

[0191] Figure 10 It is a schematic cross-sectional view illustrating a method of manufacturing an image display device according to the present embodiment.

[0192] In Figure 10 , to avoid complication, the structures inside the circuit board 100, Figure 1 such as the interlayer insulating film 112, through holes 161d, 161k, 161k-1, 161k-2, and the wiring layer 160 shown, are not illustrated. In addition, Figure 10 a part of a color conversion member such as a color filter 180 is shown. In Figure 10 , a structure including graphene sheets 140-1, 140-2, light-emitting elements 150-1, 150-2, an interlayer insulating film 156, a surface resin layer 170, and through holes not illustrated is referred to as a light-emitting circuit portion 172. In addition, a structure having a light-emitting circuit portion 172 provided on the circuit board 100 is referred to as a structure 1192.

[0193] As Figure 10 shown, the color filter (wavelength conversion member) 180 is bonded to the structure 1192 on one side. The other side of the color filter 180 is bonded to the glass substrate 186. A transparent thin film adhesive layer 188 is provided on one side of the color filter 180, and it is bonded to the surface of the light-emitting circuit portion 172 side of the structure 1192 via the transparent thin film adhesive layer 188.

[0194] In this example, the color filter 180 has color conversion portions arranged in the positive direction of the X-axis in the order of red, green, and blue. For red, a red color conversion layer 183R is provided on the first layer. For green, a green color conversion layer 183G is provided on the first layer. For blue, a blue color conversion layer 183B is provided on the first layer. In any case, a filter layer 184 is provided on the second layer, but the frequency characteristics of the filter layer 184 can of course be changed for each color of the color conversion portion. For blue, a single-layer color conversion layer 183B can also be provided. A light-shielding portion 181 is provided between the respective color conversion portions.

[0195] Align the positions of the color conversion layers 183R, 183G, and 183B of each color with the position of the light-emitting element 150, and attach the color filter 180 to the structure 1192.

[0196] Figures 11A - 11D It is a schematic cross-sectional view showing a modification of the manufacturing method of the image display device according to the present embodiment.

[0197] Figures 11A - 11D It shows a method of forming a color filter by inkjet.

[0198] As Figure 11A shown, prepare a structure 1192 with a light-emitting circuit portion 172 attached to a circuit board 1100.

[0199] As Figure 11B shown, form a light-shielding portion 181 on the structure 1192. The light-shielding portion 181 is formed, for example, by screen printing, photolithography, or the like.

[0200] As Figure 11C shown, a phosphor corresponding to the emission color is ejected from an inkjet nozzle to form a color conversion layer 183. The phosphor is colored in the region where the light-shielding portion 181 is not formed. The phosphor can use a fluorescent coating material, which, for example, uses a common phosphor material, a perovskite phosphor material, or a quantum dot phosphor material. In the case of using a perovskite phosphor material or a quantum dot phosphor material, each emission color can be achieved, the monochromaticity is increased, and the color reproducibility can be improved, so it is preferred. After drawing with the inkjet nozzle, a drying process is performed at an appropriate temperature and time. When coloring, the thickness of the coating film is set to be thinner than the thickness of the light-shielding portion 181.

[0201] As described above, for the sub-pixel that emits blue light, when the color conversion portion is not formed, the phosphor is not ejected. In addition, for the sub-pixel that emits blue light, when forming the blue color conversion layer, in the case where the color conversion portion can be a single layer, it is preferred that the coating film thickness of the blue phosphor is about the same as the thickness of the light-shielding portion 181a.

[0202] AsFigure 11D As shown, the coating for the light filtering layer 184 is ejected from an inkjet nozzle. The coating is applied so as to overlap with the coating film of the phosphor 183a. The total thickness of the coating films of the phosphor and the coating is about the same as the thickness of the light shielding portion 181.

[0203] The effects of the image display device 1 according to the present embodiment will be described.

[0204] In the manufacturing method of the image display device 1 according to the present embodiment, circuit elements such as the transistors 103 that drive the light emitting elements 150-1 and 150-2 are formed in advance on the circuit substrate 1100, and the graphene layer 1140 is formed on the interlayer insulating film 112 of the circuit substrate 1100. Further, the semiconductor layer 1150 is grown on the graphene layer 1140. By shaping the semiconductor layer 1150 on which crystal growth has been performed together with the graphene layer 1140 into a desired shape, the light emitting elements 150-1 and 150-2 can be formed on the graphene sheets 140-1 and 140-2, respectively. Therefore, compared with the case where the light emitting elements that have been singulated are transferred onto the circuit substrate 1100 one by one, the process of transferring the light emitting elements 150-1 and 150-2 can be shortened.

[0205] For example, in an image display device with 4K picture quality, the number of sub-pixels exceeds 24 million, and in the case of an image display device with 8K picture quality, the number of sub-pixels exceeds 99 million. Mounting such a large number of light emitting elements on the circuit substrate one by one requires a lot of time, and it is difficult to realize an image display device formed by micro LEDs at a realistic cost. In addition, mounting a large number of light emitting elements individually will reduce the yield due to connection problems during mounting, etc., and inevitably increase the cost.

[0206] In contrast, in the manufacturing method of the image display device 1 according to the present embodiment, since the semiconductor layer 1150 is grown as a whole on the graphene layer 1140 formed on the circuit substrate 1100 and then the light emitting elements 150-1 and 150-2 are formed, the transfer process of the light emitting elements can be reduced.

[0207] Since the semiconductor layer 1150 grows on the graphene layer 1140 with a uniform crystal structure, by making the graphene layer 1140 of an appropriate size and shape, the light emitting elements can be arranged in self-alignment. Therefore, it is not necessary to align the light emitting elements on the circuit substrate 1100, and it is also easy to miniaturize the light emitting elements 150-1 and 150-2, which is suitable for high-definition displays.

[0208] After directly forming the light emitting elements on the circuit substrate by etching or the like, the light emitting elements are electrically connected to the circuit elements in the circuit substrate 1100 by forming through holes, so a uniform connection structure can be realized and a reduction in yield can be suppressed.

[0209] In the present embodiment, for example, the TFT formed on the glass substrate can be used as the circuit board 1100, so that existing flat panel manufacturing processes and equipment can be utilized.

[0210] In the image display device 1 of the present embodiment, the first wiring layer 110 includes a wiring 110k. The wiring 110k is pre-formed at positions on the circuit board 1100 where the light-emitting elements 150-1 and 150-2 are formed. Therefore, the light scattered downward from the light-emitting elements 150-1 and 150-2 is reflected by the wiring 110k and distributed toward the light-emitting surfaces 153S1 and 153S2. As a result, the luminous efficiency of the light-emitting elements 150-1 and 150-2 is actually improved.

[0211] Since the wiring 110k blocks the light scattered downward from the light-emitting elements 150-1 and 150-2, it is possible to suppress the irradiation of light to the circuit elements located below and near the light-emitting elements 150-1 and 150-2, and prevent malfunction of the circuit elements.

[0212] (Second Embodiment)

[0213] Figure 12 It is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.

[0214] Figure 12 It shows the Figure 4 director cross-section at the position corresponding to the AA' line.

[0215] In the present embodiment, the difference from the above-described other embodiments is that one light-emitting element 250 is provided on one wiring 210a. In addition, in the present embodiment, the difference from the above-described other embodiments is the structure of the light-emitting element 250 and the structure of the transistor 203 that drives the light-emitting element. For the main components having the same structure as in the above-described other embodiments, the same reference numerals are used, and detailed descriptions are appropriately omitted.

[0216] As Figure 12 shown, in the sub-pixel 220 of the image display device of the present embodiment, the first wiring layer 110 includes a wiring 210a. The wiring (second part) 210a is provided below the light-emitting element 250 via the interlayer insulating film 112. The outer periphery of the wiring 210a is set to include the outer periphery of the light-emitting element 250 when the light-emitting element 250 is projected onto the wiring 210a.

[0217] A graphene sheet 140 is provided above the wiring 210a. The light-emitting element 250 is provided on the graphene sheet 140.

[0218] In the present embodiment, the light-emitting element 250 is laminated in the order of the p-type semiconductor layer 253, the light-emitting layer 252, and the n-type semiconductor layer 251 from the side of the first interlayer insulating film 112 toward the light-emitting surface 251S side. In the present embodiment, the n-type semiconductor layer 251 is the light-emitting surface 251S.

[0219] The light-emitting surface 251S is the surface of the n-type semiconductor layer 251 that faces the surface in contact with the light-emitting layer 252. The light-emitting surface 251S is roughened.

[0220] The light-emitting element 250 may be made of the same materials as in the case of the other embodiments described above. The light-emitting element 250 emits, for example, blue light of about 467 nm ± 20 nm or blue-violet light having a wavelength of 410 nm ± 20 nm.

[0221] The second interlayer insulating film (second insulating film) 156 covers the first interlayer insulating film 112, the graphene sheet 140, and the light-emitting element 250. The second interlayer insulating film 156 has an opening 258. The opening 258 is formed over the light-emitting element 250, and the interlayer insulating film 156 is not provided over the light-emitting surface 251S.

[0222] The transistor 203 is an n-channel TFT in this example. The transistor 203 includes a TFT channel 204 and a gate 107. The TFT channel 204 is a region of polycrystalline Si formed on the first surface 102a of the substrate 102, and is annealed by laser irradiation to crystallize and activate a region formed as amorphous Si. The TFT channel 204 includes regions 204s, 204i, and 204d. The regions 204s, 204i, and 204d are all provided on the TFT lower layer film 106. The region 204i is provided between the regions 204s and 204d. The regions 204s and 204d are doped with n-type impurities such as phosphorus (P) and are ohmically connected to the through holes 111s and 111d.

[0223] The gate 107 is provided over the TFT channel 204 with an insulating layer 105 interposed therebetween. When a potential higher than that of the region 204s is applied to the gate 107, a channel is formed in the region 204i to control the current flowing between the regions 204s and 204d.

[0224] The structure of the upper portion of the transistor 203 and the wiring layer 110 is the same as in the case of the other embodiments described above.

[0225] A through hole 261a1 is formed through the interlayer insulating film 156. One end of the through hole 261a1 is connected to the step portion 253a.

[0226] A through hole 261a is formed through the interlayer insulating films 112 and 156. One end of the through hole 261a is connected to the wiring 210a.

[0227] The second wiring layer 160 includes wirings 260a and 260k. The other ends of vias 261a1 and 261a are connected to the wiring 260a. The wiring 260a is electrically connected to, for example, the power supply line 3 described later. Figure 13 The wiring 210a is electrically connected to the power supply line 3 via the via 261a and the wiring 260a.

[0228] One end of the via 161d is connected to the wiring 110d, and the other end of the via 161d is connected to the wiring 260k. One end of the wiring 260k is connected to the surface of the n-type semiconductor layer 251 having the light emitting surface 251S. Therefore, the n-type semiconductor layer 251 is electrically connected to the region 204d corresponding to the drain electrode of the transistor 203 via the wiring 260k, the via 161d, and the wiring 110d.

[0229] The source electrode of the transistor 203, that is, the region 204s, is connected to the wiring 110s via the via 111s. The wiring 110s is connected to, for example, the ground line 4 described later. Figure 13

[0230] Figure 13 It is a schematic block diagram illustrating the image display device of the present embodiment.

[0231] As Figure 13 shown, the image display device 201 of the present embodiment includes a display area 2, a row selection circuit 205, and a signal voltage output circuit 207. Similar to the cases of the other above-described embodiments, on the display area 2, for example, the sub-pixels 220 are arranged in a lattice pattern in the XY plane.

[0232] Similar to the cases of the other above-described embodiments, the pixel 10 includes a plurality of sub-pixels 220 that emit different colors of light. The sub-pixel 220R emits red light. The sub-pixel 220G emits green light. The sub-pixel 220B emits blue light. The three sub-pixels 220R, 220G, and 220B emit light with a desired brightness, thereby determining the emission color and brightness of one pixel 10.

[0233] One pixel 10 is formed by three sub-pixels 220R, 220G, and 220B. The sub-pixels 220R, 220G, and 220B are arranged linearly on the X-axis as in this example. Each pixel 10 may arrange the sub-pixels of the same color in the same column, or may arrange sub-pixels of different colors in each column as in this example.

[0234] The sub-pixel 220 includes: a light emitting element 222, a selection transistor 224, a driving transistor 226, and a capacitor 228. In Figure 13 , the selection transistor 224 is sometimes denoted as T1, the driving transistor 226 is denoted as T2, and the capacitor 228 is denoted as Cm.

[0235] In the present embodiment, the light-emitting element 222 is provided on the power supply line 3 side, and the driving transistor 226 connected in series with the light-emitting element 222 is provided on the ground line 4 side. That is, the driving transistor 226 is connected closer to the low potential side than the light-emitting element 222. The driving transistor 226 is an n-channel transistor.

[0236] A selection transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. A capacitor 228 is connected between the gate electrode of the driving transistor 226 and the ground line 4.

[0237] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage having a polarity different from that of the above-described other embodiments to the signal line 208 in order to drive the n-channel transistor, i.e., the driving transistor 226.

[0238] In the present embodiment, since the driving transistor 226 is of n-channel polarity, the polarity of the signal voltage and the like are different from those of the above-described other embodiments. That is, the row selection circuit 205 supplies a selection signal to the scanning line 206 to sequentially select one row from the arrangement of the sub-pixels 220 in the m-th row. The signal voltage output circuit 207 supplies a signal voltage having a required analog voltage value to each of the sub-pixels 220 in the selected row. A current corresponding to the signal voltage flows from the driving transistor 226 of the sub-pixel 220 in the selected row to the light-emitting element 222. The light-emitting element 222 emits light with a brightness corresponding to the flowing current.

[0239] A method for manufacturing the image display device according to the present embodiment will be described.

[0240] Figures 14A - 15B FIG. is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the present embodiment.

[0241] In the present embodiment, before forming the graphene layer 1140 on the circuit substrate 1100, it is the same as in the above-described other embodiments. Hereinafter, the description will start from the process after the process shown in Figure 5B the following description.

[0242] As Figure 14A shown, a semiconductor layer 1150 is formed over the graphene layer 1140. In the present embodiment, the semiconductor layer 1150 is formed in the order of a p-type semiconductor layer 1153, a light-emitting layer 1152, and an n-type semiconductor layer 1151 from the graphene layer 1140 side in the positive direction of the Z axis.

[0243] The formation of the semiconductor layer 1150 is the same as in other embodiments. Physical vapor growth methods such as evaporation, ion beam deposition, MBE, and sputtering can be used, and low-temperature sputtering is preferably used. By growing the semiconductor layer 1150 of GaN on the graphene layer 1140, even starting from the p-type semiconductor layer 1153, a single-crystallized semiconductor layer 1150 including the light-emitting layer 1152 can be stably formed on the graphene layer 1140 (see Non-Patent Documents 1, 2, etc.).

[0244] As Figure 14B shown, the semiconductor layer 1150 is formed into a required shape by RIE or the like to form the light-emitting element 250. Then, the first interlayer insulating film 112, the graphene sheet 140, and the light-emitting element 250 are covered to form the second interlayer insulating film 156.

[0245] As Figure 15A shown, the via hole 262a1 penetrates through the second interlayer insulating film 156 to be formed. The via holes 262a and 162d penetrate through the interlayer insulating films 112 and 256 to be formed. When forming the via holes 262a1, 262a, and 162d, an opening 258 is formed in the interlayer insulating film 156 to expose the light-emitting surface 251S. The exposed light-emitting surface 251S is roughened. The formation of the opening 258 can be before or after the formation of the via holes 262a1, 262a, and 162d.

[0246] As Figure 15B shown, a conductive material is filled into the via holes 262a1, 262a, and 162d shown in Figure 15A to form the through holes 261a1, 261a, and 161d. Then, or simultaneously with filling the conductive material into the via holes 262a1, 262a, and 162d, the second wiring layer 160 is formed. In this example, one end of the wiring 260k is connected to the surface including the light-emitting surface 251S.

[0247] Thereafter, a color filter is formed in the same manner as in other embodiments.

[0248] In this way, the image display device 201 of this embodiment can be manufactured.

[0249] The effects of the image display device 201 of this embodiment will be described.

[0250] In this embodiment, in addition to the effects in the above other embodiments, the following effects are also provided. That is, in this embodiment, since the semiconductor layer 1150 is grown on the graphene layer 1140, stable growth can be achieved even in the p-type semiconductor layer. Therefore, the yield of the image display device can be improved.

[0251] (Third Embodiment)

[0252] In the image display device of the present embodiment, instead of a glass substrate, circuit elements such as transistors are formed on a flexible substrate. In other aspects, it is the same as in the above-described other embodiments. For the same structural main components, the same reference numerals are used, and detailed descriptions are appropriately omitted.

[0253] Figure 16 FIG. is a schematic cross-sectional view illustrating a part of the image display device of the present embodiment.

[0254] Figure 16 Indicates the equivalent to Figure 4 The vector cross-section at the position of the AA' line shown.

[0255] As Figure 16 shown, the image display device of the present embodiment has sub-pixels 320-1 and 320-2. The sub-pixels 320-1 and 320-2 include a common substrate 402. The substrate 402 includes a first surface 402a. Circuit elements such as transistors 103 are provided on the first surface 402a. In the sub-pixels 320-1 and 320-2, an upper structure including circuit elements is formed on the first surface 402a.

[0256] The substrate 402 has flexibility. The substrate 402 is formed of, for example, a polyimide resin or the like. The interlayer insulating films 112 and 156 and the wiring layers 110 and 160 are preferably formed of a material having a certain degree of elasticity according to the flexibility of the substrate 402. It should be noted that the wiring layer 110 having the longest wiring length has the highest risk of breakage during bending. Therefore, it is desirable to adjust various film thicknesses, materials, and film qualities so that the neutral plane including a plurality of protective films added to the front and back surfaces as needed is located at the position of the wiring layer 110.

[0257] In this example, the transistors 103 and the light-emitting elements 150-1 and 150-2 formed on the substrate 402 are the same as in the first embodiment, and for example, the Figure 3 applicable circuit structure. The structures of other embodiments can also be easily applied Figure 3 circuit structure.

[0258] A manufacturing method of the image display device of the present embodiment will be described.

[0259] Figures 17A - 17B FIG. is a schematic cross-sectional view illustrating a manufacturing method of the image display device of the present embodiment.

[0260] As Figure 17AAs shown, in this embodiment, a circuit board 3100 different from that in the above other embodiments is prepared. The circuit board 3100 includes two layers of substrates 102 and 402. The substrate 402 is provided on the first surface 102a of the substrate 102 and is formed by, for example, coating a polyimide material and firing. An inorganic film such as SiNx may also be provided between the two layers of substrates 102 and 402. The TFT lower layer film 106, the circuit 101, and the interlayer insulating film 112 are provided on the first surface 402a of the substrate 402. The first surface 402a of the substrate 402 is the surface facing the surface where the substrate 102 is provided.

[0261] In the above circuit board 3100, for example, by applying Figures 5A - 11D the processes described in, the upper structures of the sub-pixels 320-1 and 320-2 are formed.

[0262] As Figure 17B shown, the substrate 102 is removed from the structure in which the upper structures such as color filters are formed to form a new circuit board 3100a. The removal of the substrate 102 can be performed, for example, by laser lift-off. The removal of the substrate 102 is not limited to the above time point and can also be performed at other appropriate time points. For example, the substrate 102 can also be removed after wafer bonding or before color filter formation. By removing the substrate 102 at an earlier time point, problems such as cracks and notches in the manufacturing process can be reduced.

[0263] The effects of the image display device according to this embodiment will be described.

[0264] Since the substrate 402 is flexible, the image display device can be bent, and can be attached to a curved surface and used for wearable terminals, etc. without any discomfort.

[0265] (Fourth Embodiment)

[0266] In this embodiment, an image display device with higher luminous efficiency is realized by forming a plurality of light-emitting surfaces equivalent to a plurality of light-emitting elements in a single semiconductor layer including a light-emitting layer. In the following description, the same reference numerals are used for the main components having the same structure as those in the above other embodiments, and the detailed description is appropriately omitted.

[0267] Figure 18 is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.

[0268] As Figure 18As shown, the image display device has a sub-pixel group 420. The sub-pixel group 420 includes: transistors (multiple transistors) 103-1, 103-2, a first wiring layer (first wiring layer) 410, an interlayer insulating film (first insulating film) 112, a plug 416k, a graphene sheet (graphene-containing portion) 440, a semiconductor layer 450, an interlayer insulating film (second insulating film) 456, and vias (multiple vias) 461d1, 461d2.

[0269] In the present embodiment, by turning on the p-channel transistors 103-1, 103-2, holes are injected into the semiconductor layer 450 via the wiring layer 460, and electrons are injected into the semiconductor layer 450 via the plug 416k, thereby causing the light-emitting layer 452 to emit light. The driving circuit is, for example, applicable Figure 3 to the circuit structure shown. It is also possible to use the above-described other embodiments, interchange the n-type semiconductor layer and the p-type semiconductor layer of the semiconductor layer up and down, and form a structure in which the semiconductor layer is driven by an n-channel transistor. In this case, the driving circuit is, for example, applicable Figure 13 to the circuit structure.

[0270] The semiconductor layer 450 includes two light-emitting surfaces 453S1, 453S2, and the sub-pixel group 420 actually includes two sub-pixels. In the present embodiment, as in the case of the above-described other embodiments, by actually arranging the sub-pixel group 420 including two sub-pixels in a lattice pattern, a display area is formed.

[0271] The transistors 103-1, 103-2 are respectively formed in the TFT channels 104-1, 104-2. In this example, the TFT channels 104-1, 104-2 include regions doped with p-type, and a channel region is included between the above regions.

[0272] An insulating layer 105 is formed on the TFT channels 104-1, 104-2, and gates 107-1, 107-2 are respectively formed via the insulating layer 105. The gates 107-1, 107-2 are the gates of the transistors 103-1, 103-2. In this example, the transistors 103-1, 103-2 are p-channel TFTs.

[0273] An insulating film 108 is covered on the two transistors 103-1, 103-2. A wiring layer 410 is formed on the insulating film 108.

[0274] Vias 111s1, 111d1 are provided between the p-type doped region of the transistor 103-1 and the wiring layer 410. Vias 111s2, 111d2 are provided between the p-type doped region of the transistor 103-2 and the wiring layer 410.

[0275] The wiring layer 410 includes wirings 410k, 410s1, 410s2, 410d1, and 410d2. The wiring 410k is connected to the plug 416k via the connection portion 415k. The wiring 410k is connected to, for example, Figure 3 the ground wire 4 shown.

[0276] The wiring 410s1 is electrically connected to the region corresponding to the source electrode of the transistor 103-1 via the through hole 111s1. The wiring 410s2 is electrically connected to the region corresponding to the source electrode of the transistor 103-2 via the through hole 111s2. The wirings 410s1 and 410s2 are connected to, for example, Figure 3 the power supply line 3 shown.

[0277] The wiring 410d1 is connected to the region corresponding to the drain electrode of the transistor 103-1 via the through hole 111d1. The wiring 410d2 is connected to the region corresponding to the drain electrode of the transistor 103-2 via the through hole 111d2.

[0278] The interlayer insulating film 112 covers the transistors 103-1 and 103-2 and the wiring layer 410. The plug 416k is formed on the interlayer insulating film 112.

[0279] The planarization film 414 is formed on the interlayer insulating film 112. The planarization film 414 is also provided on the side surface of the plug 416k. The plug 416k is buried in the planarization film 414, and the planarization film 414 and the plug 416k have surfaces in the same plane in the XY plan view. The above-mentioned surface is the surface on the side opposite to the surface on the interlayer insulating film 112 side.

[0280] The graphene sheet 440 is provided on the plug 416k. The outer periphery of the graphene sheet 440 substantially coincides with the outer periphery of the semiconductor layer 450. The outer periphery of the plug 416k is set to include the outer peripheries of the plug 416k and the graphene sheet 440 when the graphene sheet 440 and the semiconductor layer 450 are projected onto the plug 416k. Therefore, the plug 416k serves as a light reflecting plate that reflects the scattered light emitted downward from the semiconductor layer 450 toward the light emitting surfaces 453S1 and 453S2.

[0281] The semiconductor layer 450 is disposed on the graphene sheet 440. The semiconductor layer 450 includes an n-type semiconductor layer (first semiconductor layer) 451, a light-emitting layer 452, and a p-type semiconductor layer (second semiconductor layer) 453. The semiconductor layer 450 is laminated in the order of the n-type semiconductor layer 451, the light-emitting layer 452, and the p-type semiconductor layer 453 from the side of the graphene sheet 440 toward the light-emitting surfaces 453S1 and 453S2. The n-type semiconductor layer 451 is disposed on the graphene sheet 440. Since the graphene sheet 440 is very thin, the resistance in the thickness direction is very low. Therefore, the n-type semiconductor layer 451 is electrically connected to the plug 416k via the graphene sheet 440.

[0282] The interlayer insulating film 456 covers the planarization film 414 and the plug 416k. The interlayer insulating film 456 covers a part of the semiconductor layer 450. Preferably, the interlayer insulating film 456 covers the surface of the p-type semiconductor layer 453 except for not covering the light-emitting surfaces (exposed surfaces) 453S1 and 453S2 of the semiconductor layer 450. The interlayer insulating film 456 covers the side surface of the semiconductor layer 450. The interlayer insulating film 456 is, for example, a white resin or the like, and may also be a black resin.

[0283] Openings 458-1 and 458-2 are formed in the portion of the semiconductor layer 450 not covered by the interlayer insulating film 456. The openings 458-1 and 458-2 are formed at positions corresponding to the light-emitting surfaces 453S1 and 453S2. The light-emitting surfaces 453S1 and 453S2 are formed at positions spaced apart on the p-type semiconductor layer 453. The light-emitting surface 453S1 is disposed on the p-type semiconductor layer 453 at a position closer to the transistor 103-1. The light-emitting surface 453S2 is disposed on the p-type semiconductor layer 453 at a position closer to the transistor 103-2.

[0284] The openings 458-1 and 458-2 are, for example, square or rectangular in the XY plan view. It is not limited to a square, and may also be a polygon such as a circle, an ellipse, or a hexagon. The light-emitting surfaces 453S1 and 453S2 are also square, rectangular, other polygons, circular, etc. in the XY plan view. The shapes of the light-emitting surfaces 453S1 and 453S2 may be similar to the shapes of the openings 458-1 and 458-2, or may be different shapes.

[0285] The wiring layer 460 is disposed on the interlayer insulating film 456. The wiring layer 460 includes wirings 460a1 and 460a2.

[0286] Through holes 461d1 and 461d2 are provided penetrating through the interlayer insulating films 112 and 456 and the planarization film 414. The through hole 461d1 is provided between the wiring 410d1 and the wiring 460a1. One end of the through hole 461d1 is connected to the wiring 410d1, and the other end of the through hole 461d1 is connected to the wiring 460a1. The through hole 461d2 is provided between the wiring 410d2 and the wiring 460a2. One end of the through hole 461d2 is connected to the wiring 410d2, and the other end of the through hole 461d2 is connected to the wiring 460a2.

[0287] The light-transmissive electrode 459a1 is provided over the wiring 460a1, and electrically connects the wiring 460a1 and the light-transmissive electrode 459a1. The light-transmissive electrode 459a1 extends in the opening 458-1. The light-transmissive electrode 459a1 is provided over the entire light-emitting surface 453S1 exposed from the opening 458-1, and is electrically connected to the p-type semiconductor layer 453 via the light-emitting surface 453S1.

[0288] The light-transmissive electrode 459a2 is provided over the wiring 460a2, and electrically connects the wiring 460a2 and the light-transmissive electrode 459a2. The light-transmissive electrode 459a2 extends in the opening 458-2. The light-transmissive electrode 459a2 is provided over the entire light-emitting surface 453S2 exposed from the opening 458-2, and is electrically connected to the p-type semiconductor layer 453 via the light-emitting surface 453S2.

[0289] As described above, the light-transmissive electrodes 459a1 and 459a2 are respectively connected to the light-emitting surfaces 453S1 and 453S2 exposed from the openings 458-1 and 458-2. When the transistor 103-1 is turned on, holes are injected into the light-transmissive electrode 459a1 via the wiring 460a1, the through hole 461d1, and the wiring 410d1. When the transistor 103-2 is turned on, holes are injected into the light-transmissive electrode 459a2 via the wiring 460a2, the through hole 461d2, and the wiring 410d2. On the other hand, electrons are injected into the n-type semiconductor layer 451 via the wiring 410k connected to the ground wire 4, the connection portion 415k, the plug 416k, and the graphene sheet 440.

[0290] The transistors 103-1 and 103-2 are driving transistors of adjacent sub-pixels and are driven in sequence. Therefore, holes injected from either one of the two transistors 103-1 and 103-2 are injected into the light-emitting layer 452, and electrons injected from the plug 416k are injected into the light-emitting layer 452, causing the light-emitting layer 452 to emit light. When the transistor 103-1 is turned on, the light-emitting surface 453S1 emits light, and when the transistor 103-2 is turned on, the light-emitting surface 453S2 emits light. In this way, since the resistance of the p-type semiconductor layer 453 suppresses the drift current flowing in the direction parallel to the XY plane in the semiconductor layer 450, the light emission of the light-emitting layer 452 is localized.

[0291] A method for manufacturing the image display device according to this embodiment will be described.

[0292] Figures 19A - 22B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the embodiment.

[0293] In Figures 19A - 20B it shows the process of forming the plug 416k on the circuit board 4100.

[0294] In Figures 21A - 22B it shows the process of forming the semiconductor layer 450 etc. on the circuit board 4100 on which the plug 416k is formed, and forming the sub-pixel group 420.

[0295] As Figure 19A shown, the circuit board 4100 is prepared. The circuit board 4100 includes the same circuit 101, substrate 102, TFT lower layer film 106, and first interlayer insulating film 112 as described in Figure 1 etc. The circuit 101 includes transistors 103-1, 103-2, etc., and is formed on the TFT lower layer film 106 formed on the substrate 102. The circuit 101 is covered by the first interlayer insulating film 112. The contact hole h is formed in the interlayer insulating film 112. The position where the contact hole h is formed is the position where the wiring 410k is provided. The contact hole h is formed to a depth at which the surface of the wiring 410k is exposed.

[0296] As Figure 19B shown, the metal layer 4416 is formed over the entire surface of the interlayer insulating film 112. While forming the metal layer 4416, the contact hole h is filled with the same conductive material as the metal layer 4416. The connection portion 415k is formed in the contact hole h filled with the material of the metal layer 4416. Therefore, the connection portion 415k electrically connects the wiring 410k and the metal layer 4416.

[0297] As Figure 19C shown, the plug 416k is formed on the connection portion 415k by photolithography and dry etching. It is also possible to directly form the plug on the wiring 410k without forming the connection portion 415k.

[0298] As Figure 20A shown, the planarization film 4414 is coated to cover the interlayer insulating film 112 and the plug 416k, and then fired. The planarization film 4414 is formed thicker than the thickness of the plug 416k. Therefore, the planarization film 4414 also covers the side surface of the plug 416k. After that, the surface of the planarization film 4414 is polished. The polishing of the planarization film 4414 can be performed, for example, by CMP (Chemical Mechanical Polishing).

[0299] As Figure 20B shown, by polishing, the surface of the plug 416k is exposed, and the planarization film 414 is formed. Thus, the plug 416k and the connection portion 415k are formed.

[0300] In addition, as Figure 21A shown, a graphene layer 4440 is formed on the plug 416k and the planarization film 414 of the circuit board 4100. The graphene layer 4440 is pre-cut and shaped to form an appropriate outer periphery. The outer periphery of the graphene layer 4440 is set so that Figure 21B the semiconductor layer 4450 shown grows within a sufficient area in the XY plan view. In this example, the outer periphery of the graphene layer 4440 is set to include the outer periphery of the plug 416k.

[0301] As Figure 21B shown, the semiconductor layer 4450 is formed on the graphene layer 4440. The formation of the semiconductor layer 4450 is preferably performed by pulsed sputtering. The semiconductor layer 4450 starts growing from the n-type semiconductor layer 4451 and grows in the order of the light-emitting layer 4452 and the p-type semiconductor layer 4453. The semiconductor layer 4450 is formed on the graphene layer 4440, and a non-single-crystallized deposit 4160 is formed at a position other than on the graphene layer 4440.

[0302] As Figure 22A shown, Figure 21B the semiconductor layer 4450 shown is shaped into a semiconductor layer 450 having a desired shape by RIE or the like. At this time, in the XY plan view, the outer periphery of the semiconductor layer 450 when the semiconductor layer 450 is projected onto the plug 416k is formed to be included within the outer periphery of the plug 416k.

[0303] Figure 21B The graphene layer 4440 shown is shaped by over-etching the semiconductor layer 450 to have an outer periphery substantially the same as that of the semiconductor layer 450, and a graphene sheet 440 is formed.

[0304] As Figure 22B shown, a second interlayer insulating film 456 covering the side surfaces of the planarization film 414, the plug 416k, the graphene sheet 440, and the semiconductor layer 450 is formed. Through holes 461d1 and 461d2 are formed through the interlayer insulating films 112 and 456 and the planarization film 414. In addition, a wiring layer 460 is formed, and wirings 460a1, 460a2, etc. are formed.

[0305] Thereafter, openings 458-1 and 458-2 are formed between the wirings 460a1 and 460a2. The light-emitting surfaces 453S1 and 453S2 of the p-type semiconductor layer exposed through the openings 458-1 and 458-2 are roughened respectively. Thereafter, the translucent electrodes 459a1 and 459a2 are formed.

[0306] In this way, a sub-pixel group 420 having a semiconductor layer 450 sharing two light-emitting surfaces 453S1 and 453S2 is formed.

[0307] In the present embodiment, two light-emitting surfaces 453S1 and 453S2 are provided in one semiconductor layer 450. The number of light-emitting surfaces is not limited to two, and three or more light-emitting surfaces may be provided in one semiconductor layer 450. As an example, one row or two rows of sub-pixels may be realized by a single semiconductor layer 450. Thus, as described later, the recombination current that is not helpful for light emission can be reduced for each light-emitting surface, and the effect of realizing a finer light-emitting element is increased.

[0308] (Modification example)

[0309] Figure 23 FIG. is a schematic cross-sectional view showing a part of an image display device according to a modification example of the present embodiment.

[0310] In the present modification example, the difference from the case of the fourth embodiment described above is that two p-type semiconductor layers 4453a1 and 4453a2 are provided on the light-emitting layer 452. Other aspects are the same as those in the case of the fourth embodiment, and the same reference numerals are used for the same main components of the structure, and the detailed description is appropriately omitted.

[0311] As Figure 23 shown, the image display device of the present modification example has a sub-pixel group 420a. The sub-pixel group 420a includes a semiconductor layer 450a. The semiconductor layer 450a includes an n-type semiconductor layer 451, a light-emitting layer 452, and p-type semiconductor layers 4453a1 and 4453a2. The semiconductor layer 450a is provided with the n-type semiconductor layer 451 on the plug 416k via the graphene sheet 440. The light-emitting layer 452 is laminated on the n-type semiconductor layer 451. Two different p-type semiconductor layers 4453a1 and 4453a2 are laminated on the light-emitting layer 452 respectively.

[0312] In this example, the p-type semiconductor layers 4453a1 and 4453a2 are arranged at intervals in the X-axis direction on the light-emitting layer 452. An interlayer insulating film 456 is provided between the p-type semiconductor layers 4453a1 and 4453a2, and the p-type semiconductor layers 4453a1 and 4453a2 are separated by the interlayer insulating film 456.

[0313] The p-type semiconductor layers 4453a1 and 4453a2 have substantially the same shape in the XY plan view, and the shape is substantially square or rectangular, and may also be other polygonal shapes, circular shapes, etc.

[0314] The p-type semiconductor layers 4453a1 and 4453a2 respectively have light-emitting surfaces 4453S1 and 4453S2. The light-emitting surfaces 4453S1 and 4453S2 are the surfaces of the p-type semiconductor layers 4453a1 and 4453a2 respectively exposed through the openings 458-1 and 458-2.

[0315] The shapes of the light-emitting surfaces 4453S1 and 4453S2 in the XY plan view are the same as the shapes of the light-emitting surfaces in the case of the fourth embodiment, have substantially the same shape, and have a shape such as substantially square. The shapes of the light-emitting surfaces 4453S1 and 4453S2 are not limited to the square shape described in this embodiment, and may also be polygonal shapes such as circular, elliptical or hexagonal. The shapes of the light-emitting surfaces 4453S1 and 4453S2 may be similar to the shapes of the openings 458-1 and 458-2, or may be different shapes.

[0316] Light-transmissive electrodes 459a1 and 459a2 are respectively provided on the light-emitting surfaces 4453S1 and 4453S2. The light-transmissive electrodes 459a1 and 459a2 are also respectively provided on the wirings 460a1 and 460a2. The light-transmissive electrode 459a1 is provided between the wiring 460a1 and the light-emitting surface 4453S1, and electrically connects the wiring 460a1 and the light-emitting surface 4453S1. The light-transmissive electrode 459a2 is provided between the wiring 460a2 and the light-emitting surface 4453S2, and electrically connects the wiring 460a2 and the light-emitting surface 4453S2.

[0317] The manufacturing method of this modification will be described.

[0318] Figure 24A and Figure 24B is a schematic cross-sectional view illustrating the manufacturing method of the image display device of this modification.

[0319] In this modification, before forming the graphene layer 4440 on the circuit board 4100 formed with the plug 416k, the same processes as those described in Figures 19A - 21B in the case of the fourth embodiment are applied. Hereinafter, as the manufacturing process of this modification, the processes after the process shown in Figure 21B will be described.

[0320] As Figure 24A shown, in this modification, in Figure 21BIn this case, the semiconductor layer 4450 grown on the graphene layer 4440 is etched to form the semiconductor layer 450a. In the process of forming the semiconductor layer 450a, after the n-type semiconductor layer 451 and the light-emitting layer 452 are formed, further etching is performed to form two p-type semiconductor layers 4453a1 and 4453a2.

[0321] The p-type semiconductor layers 4453a1 and 4453a2 can also be formed by deep etching. For example, the etching for forming the p-type semiconductor layers 4453a1 and 4453a2 can also be performed to a depth reaching inside the light-emitting layer 452 or inside the n-type semiconductor layer 451. In this way, in the case of performing deep etching on the p-type semiconductor layer, it is desirable that the etching position of the p-type semiconductor layer 4453 is separated from the outer periphery of the light-emitting surfaces 4453S1 and 4453S2 of the p-type semiconductor layer by 1 μm or more. By separating the etching position from the outer periphery of the light-emitting surfaces 4453S1 and 4453S2, the recombination current can be suppressed.

[0322] Figure 21B The shown graphene layer 4440 is formed into an outer periphery corresponding to the outer periphery of the semiconductor layer 450a by over-etching the semiconductor layer 450a.

[0323] As Figure 24B shown, an interlayer insulating film 456 covering the planarization film 414 and the semiconductor layer 450a is formed, and then through-holes 461d1 and 461d2 are formed. In addition, a wiring layer 460 is formed, and wirings 460a1, 460a2, etc. are formed.

[0324] Openings 458-1 and 458-2 are respectively formed in the interlayer insulating film 456. The light-emitting surfaces 4453S1 and 4453S2 of the p-type semiconductor layer exposed through the openings 458-1 and 458-2 are respectively roughened. Then, light-transmissive electrodes 459a1 and 459a2 are formed.

[0325] In this way, a sub-pixel group 420a having two light-emitting surfaces 4453S1 and 4453S2 is formed.

[0326] In the case of this modification example, it is the same as the case of the fourth embodiment. The number of light-emitting surfaces is not limited to two, and three or more light-emitting surfaces can also be provided on one semiconductor layer 450a.

[0327] The effects of the image display device according to this embodiment will be described.

[0328] Figure 25 is a graph illustrating the characteristics of the pixel LED element.

[0329] Figure 25The vertical axis represents the luminous efficiency [%]. The horizontal axis represents the current density of the current flowing through the pixel LED element by a relative value.

[0330] As Figure 25 shown, in the region where the relative value of the current density is less than 1.0, the luminous efficiency of the pixel LED element is substantially constant or monotonically increasing. In the region where the relative value of the current density is greater than 1.0, the luminous efficiency monotonically decreases. That is, for the pixel LED element, there is an appropriate current density that maximizes the luminous efficiency.

[0331] It is expected to achieve an efficient image display device by suppressing the current density to an extent where sufficient brightness can be obtained from the light-emitting element. However, Figure 25 it is shown that at low current densities, as the current density decreases, the luminous efficiency tends to decrease.

[0332] For example, as described in the above first embodiment, the light-emitting elements 150-1 and 150-2 are formed by individually separating the entire layer of the semiconductor layer 1150 including the light-emitting layers 152-1 and 152-2 by using etching or the like. At this time, the bonding surfaces of the light-emitting layers 152-1 and 152-2 with the p-type semiconductor layers 153-1 and 153-2 are exposed at the ends. Similarly, the bonding surfaces of the light-emitting layers 152-1 and 152-2 with the n-type semiconductor layers 151-1 and 151-2 are exposed at the ends.

[0333] In the presence of the above ends, electrons and holes recombine at the ends. On the other hand, the above recombination does not contribute to light emission. The recombination generated at the ends has little relation to the current flowing through the light-emitting element. It can be considered that the recombination is generated according to the length of the bonding surface that contributes to light emission at the ends.

[0334] When two light-emitting elements having the same size of a cubic shape emit light, since the ends are formed on all four sides of each light-emitting element, recombination can occur at a total of eight ends.

[0335] In contrast, in the present embodiment, the number of ends of the semiconductor layers 450 and 450a having two light-emitting surfaces is four. In the region between the openings 458-1 and 458-2, the injection of electrons and holes is reduced and hardly contributes to light emission, so the number of ends that contribute to light emission can be considered to be six. Thus, in the present embodiment, the number of ends of the semiconductor layer is actually reduced, thereby reducing the recombination current that does not contribute to light emission, and by reducing the recombination current, the driving current can be reduced.

[0336] In cases where the distance between sub-pixels is shortened for high definition or the like, or where the current density is relatively high, in the sub-pixel group 420 of the fourth embodiment, the distance between the light-emitting surfaces 453S1 and 453S2 is shortened. In this case, when the p-type semiconductor layer 453 is shared, a part of the electrons injected toward the adjacent light-emitting surface side is shunted, and the light-emitting surface on the side that is not driven may emit faint light. In the modified example, since the p-type semiconductor layers 4453a1 and 4453a2 are separated for each of the light-emitting surfaces 4453S1 and 4453S2, it is possible to reduce the generation of faint light on the light-emitting surface on the side that is not driven.

[0337] In the present embodiment, the semiconductor layer including the light-emitting layer is laminated in the order of an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer from the first interlayer insulating film 112 side, and the exposed surface of the p-type semiconductor layer is roughened, which is preferable from the viewpoint of improving the light-emitting efficiency. Similar to the cases of the above-described other embodiments, the lamination order of the n-type semiconductor layer and the p-type semiconductor layer may be replaced with the order of a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer.

[0338] In all of the above-described embodiments and modified examples, the lamination order of the light-emitting elements can be changed according to the above-described appropriate manufacturing process and applied. For example, for the light-emitting element of the first embodiment, it can be laminated in the order of a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer from the first interlayer insulating film 112 side toward the light-emitting surface side. Similarly, for the light-emitting element of the second embodiment, it can be laminated in the order of an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer from the first interlayer insulating film 112 side toward the light-emitting surface side.

[0339] In addition, in the above-described embodiments and modified examples, the above-described structures can be appropriately combined and applied. For example, in the first to third embodiments, the plug used in the fourth embodiment can be applied to the connection between the lower semiconductor layer and the external circuit. Similarly, in the fourth embodiment, instead of the connection by the plug, the lower semiconductor layer can be connected to the external circuit using a via hole.

[0340] (Fifth Embodiment)

[0341] The above-described image display device, as an image display module having an appropriate number of pixels, can be, for example, a computer monitor, a television, a portable terminal such as a smartphone, or a car navigation system.

[0342] Figure 26 It is a block diagram illustrating the image display device of the present embodiment.

[0343] Figure 26 It shows the main part of the structure of a computer monitor.

[0344] As Figure 26 shown, the image display device 501 has an image display module 502. The image display module 502 is, for example, an image display device having the structure in the case of the above-described first embodiment. The image display module 502 includes: a display area 2 in which sub-pixels 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7. The image display device 501 may also have the structure in any of the second to fourth embodiments and the modification examples.

[0345] The image display device 501 further has a controller 570. The controller 570 inputs control signals separated and generated by an interface circuit (not shown), and controls the driving and driving order of each sub-pixel for the row selection circuit 5 and the signal voltage output circuit 7.

[0346] (Modification example)

[0347] Figure 27 is a block diagram illustrating the image display device of this modification example.

[0348] Figure 27 shows the structure of a high-definition thin TV.

[0349] As Figure 27 shown, the image display device 601 has an image display module 602. The image display module 602 is, for example, the image display device 1 having the structure in the case of the above-described first embodiment. The image display device 601 has a controller 670 and a frame memory 680. The controller 670 controls the driving order of each sub-pixel in the display area 2 based on the control signals supplied by the bus 640. The frame memory 680 stores display data for one frame amount for processing such as smooth moving image reproduction.

[0350] The image display device 601 has an I / O circuit 610. The I / O circuit 610 provides an interface circuit for connecting to external terminals, devices, etc. The I / O circuit 610 includes, for example, a USB interface for connecting an external hard disk device, an audio interface, etc.

[0351] The image display device 601 has a receiving unit 620 and a signal processing unit 630. The receiving unit 620 is connected to an antenna 622, and separates and generates a required signal from the radio waves received by the antenna 622. The signal processing unit 630 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signal separated and generated by the receiving unit 620 is separated and generated into image data, audio data, etc. by the signal processing unit 630.

[0352] By making the receiving unit 620 and the signal processing unit 630 high-frequency communication modules such as those for transmitting / receiving in a mobile phone, WiFi, and GPS receivers, etc., it can also be formed into other image display devices. For example, an image display device having an image display module with an appropriate screen size and resolution can be a portable information terminal such as a smart phone or a car navigation system.

[0353] In the case of this embodiment, the image display module is not limited to the structure of the image display device in the case of the first embodiment, and can also be a modified example or the case of other embodiments.

[0354] Figure 28 It is a perspective view schematically illustrating the image display devices of the first to fourth embodiments and the above-described modified examples.

[0355] As Figure 28 shown, in the image display devices of the first to fourth embodiments as described above, a light-emitting circuit portion 172 having a large number of sub-pixels is provided on the circuit board 100. A color filter 180 is provided on the light-emitting circuit portion 172. It should be noted that in the fifth embodiment, the structure including the circuit board 100, the light-emitting circuit portion 172, and the color filter 180 is the image display module 502, 602, which is assembled into the image display devices 501, 601.

[0356] According to the embodiments described above, it is possible to realize a manufacturing method of an image display device that shortens the transfer process of light-emitting elements and improves the yield rate, and an image display device.

[0357] Above, several embodiments of the present invention have been described. However, the above embodiments are mentioned as examples and are not intended to limit the scope of the invention. The above new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. The above embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention described in the technical solution and its equivalents. In addition, the respective embodiments can be implemented in combination with each other.

[0358] Description of Reference Numerals

[0359] 1, 201, 501, 601 Image display device; 2 Display area; 3 Power supply line; 4 Ground line; 5, 205 Row selection circuit; 6, 206 Scanning line; 7, 207 Signal voltage output circuit; 8, 208 Signal line; 10 Pixel; 20-1, 20-2, 20a-1, 20a-2, 20b-1, 20b-2 Sub-pixel; 22, 222 Light-emitting element; 24, 224 Selection transistor; 26, 226 Driving transistor; 28, 228 Capacitor; 100 Circuit board; 101 Circuit; 102, 402 Substrate; 103-1, 103-2, 203 Transistor; 104, 104-1, 104-2, 204 TFT channel; 105 Insulating layer; 107, 107-1, 107-2 Gate; 108 Insulating film; 110 First wiring layer; 110k, 210a Wiring; 112 First interlayer insulating film; 114, 414 Planarization film; 140, 140-1, 140-2, 440 Graphene sheet; 150-1, 150-2, 150a-1, 250 Light-emitting element; 156, 256, 456 Second interlayer insulating film; 159a1, 159a2, 159k, 459a1, 459a2 Transparent electrode; 160 Second wiring layer; 160a-1, 160k, 260a, 260k Wiring; 161d, 161k, 161k-1, 161k-2, 261a, 261a1, 461d1, 461d2 Through hole; 180 Color filter; 416k Plug; 420, 420a Sub-pixel group; 450, 450a Semiconductor layer; 410 First wiring layer; 410k Wiring; 1100, 3100, 3100a, 4100 Circuit board; 1140, 4440 Graphene layer; 1150 Semiconductor layer; 1192 Structure.

Claims

1. A manufacturing method of an image display device, characterized in that, it has: a process of preparing a first substrate, the first substrate including: a circuit including circuit elements formed on a light-transmissive substrate, and a first insulating film covering the circuit; a process of forming a layer containing graphene on the first insulating film; a process of forming a semiconductor layer including a light-emitting layer on the layer containing the graphene; a process of etching the semiconductor layer to form a light-emitting element; a process of forming a second insulating film covering the layer containing the graphene, the light-emitting element, and the first insulating film; a process of forming a through hole penetrating the first insulating film and the second insulating film; a process of electrically connecting the light-emitting element and the circuit element via the through hole on a light-emitting surface of the light-emitting element facing the first insulating film side, further includes a second substrate having flexibility and disposed between the light-transmissive substrate and the circuit element, and also has a process of removing the light-transmissive substrate after the process of growing the semiconductor layer.

2. The manufacturing method of the image display device according to claim 1, characterized in that, in the process of growing the semiconductor layer, the semiconductor layer is grown by a sputtering method.

3. The manufacturing method of the image display device according to claim 1, characterized in that, the light-transmissive substrate includes a glass substrate.

4. The manufacturing method of the image display device according to claim 1, characterized in that, it also has a process of exposing the light-emitting surface.

5. The manufacturing method of the image display device according to claim 4, characterized in that, it also has a process of forming a light-transmissive electrode on the exposed light-emitting surface.

6. The manufacturing method of the image display device according to claim 1, characterized in that, the semiconductor layer includes a gallium nitride-based compound semiconductor.

7. The manufacturing method of the image display device according to claim 1, characterized in that, it also has a process of forming a wavelength conversion component on the light-emitting element.

8. An image display device, characterized in that, it has: a light-transmissive substrate having a first surface; circuit elements disposed on the first surface; a first wiring layer disposed on the circuit elements and electrically connected to the circuit elements; a first insulating film covering the circuit elements and the first wiring layer on the first surface; a first part disposed on the first insulating film and containing graphene; a light-emitting element disposed on the first part; a second insulating film covering at least a part of the light-emitting element, the first part, and the first insulating film; a second wiring layer disposed on the second insulating film and electrically connected to a light-emitting surface of the light-emitting element facing the first insulating film side; a first through hole penetrating the first insulating film and the second insulating film and electrically connecting the first wiring layer and the second wiring layer, and also has a plug disposed between the first part and the first wiring layer, the light-emitting element is disposed on the plug, and an outer periphery of the plug includes an outer periphery of the light-emitting element projected on the plug in a top view.

9. The image display device according to claim 8, wherein, the light-transmissive substrate includes a glass substrate.

10. The image display device according to claim 8, wherein, the first wiring layer includes a second portion having light reflectivity, the light-emitting element is disposed on the second portion, the outer periphery of the second portion includes, in a plan view, the outer periphery of the light-emitting element projected on the second portion.

11. The image display device according to claim 10, wherein, it further has a second through hole provided to penetrate the first insulating film and the second insulating film, the second through hole electrically connects the second portion and the second wiring layer.

12. The image display device according to claim 8, wherein, the second insulating film has an opening for exposing the light-emitting surface, it further has a light-transmissive electrode disposed on the light-emitting surface.

13. The image display device according to claim 12, wherein, the light-emitting surface exposed from the opening includes a rough surface.

14. The image display device according to claim 8, wherein, the light-emitting element includes: a first semiconductor layer of a first conductivity type, a first light-emitting layer disposed on the first semiconductor layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type and disposed on the first light-emitting layer. Laminated in order of the first semiconductor layer, the first light-emitting layer, and the second semiconductor layer from the first insulating film side to the light-emitting surface side, the first conductivity type is n-type and the second conductivity type is p-type.

15. The image display device according to claim 8, wherein, the light-emitting element includes a gallium nitride-based compound semiconductor.

16. The image display device according to claim 8, wherein, a wavelength conversion member is further provided on the light-emitting element.

17. An image display device, wherein, it has: a substrate having a first surface and being flexible; a circuit element disposed on the first surface; a first wiring layer disposed on the circuit element and electrically connected to the circuit element; a first insulating film covering the circuit element and the first wiring layer on the first surface; a first portion disposed on the first insulating film and containing graphene; a light-emitting element disposed on the first portion; a second insulating film covering at least a part of the light-emitting element, the first portion, and the first insulating film; a second wiring layer disposed on the second insulating film and electrically connected to the light-emitting surface of the light-emitting element facing the first insulating film side; a first through hole penetrating the first insulating film and the second insulating film and electrically connecting the first wiring layer and the second wiring layer, it further has a plug disposed between the first portion and the first wiring layer, the light-emitting element is disposed on the plug, the outer periphery of the plug includes, in a plan view, the outer periphery of the light-emitting element projected on the plug.

18. An image display device, wherein, it has: a light-transmissive substrate having a first surface; A plurality of transistors, which are disposed on the first surface; A first wiring layer, which is disposed on the plurality of transistors and is electrically connected to the plurality of transistors; A first insulating film, which covers the plurality of transistors and the first wiring layer on the first surface; A portion, which is disposed on the first insulating film and contains graphene; A first semiconductor layer of a first conductivity type, which is disposed on the portion; A light-emitting layer, which is disposed on the first semiconductor layer; A second semiconductor layer of a second conductivity type, which is disposed on the light-emitting layer and is different from the first conductivity type; A second insulating film, which covers the portion, the first insulating film, the light-emitting layer, and the first semiconductor layer, and covers at least a part of the second semiconductor layer; A second wiring layer, which is connected to a light-transmissive electrode disposed on a plurality of light-emitting surfaces of the second semiconductor layer and exposed from the second insulating film corresponding to the plurality of transistors; A plurality of through holes, which penetrate the first insulating film and the second insulating film and electrically connect the wiring of the first wiring layer and the wiring of the second wiring layer respectively; Further comprising a plug disposed between the portion and the first wiring layer; The first semiconductor layer and the light-emitting layer are disposed on the plug; The outer periphery of the plug includes, in a plan view, the outer peripheries of the first semiconductor layer and the light-emitting layer projected on the plug.

19. The image display device according to claim 18, characterized in that, the second semiconductor layer is separated by the second insulating film.

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