Cyclic redundancy check calculation circuit, communication unit and method thereof

Abstract

A cyclic redundancy check, CRC, computation circuit, the CRC computation circuit comprising: an input for receiving an input stream having an input bit sequence comprising two or more bits at a time, the two or more bits aligned with rows of a CRC generator matrix stored in a look-up table, LUT; and a set of two or more parallel processors configured to perform a CRC computation of the input bit sequence, wherein the look-up table, LUT, comprises a plurality of addresses, wherein at least one of the addresses is configured to store two or more rows of the CRC generator matrix, and the set of parallel processors is configured to: combine LUT data with the input stream by masking the two or more rows of the CRC generator matrix stored in the LUT using the two or more bits of the aligned input stream; and combine the generated two or more intermediate parity bit sequences into a single parity bit sequence.

Description

Technical Field

[0001] This invention relates to Cyclic Redundancy Check (CRC) circuits, communication units, and methods for calculating CRC. The scope of this invention is applicable to, but not limited to, channel coding in current and future generations of communication standards. Background Technology

[0002] Cyclic Redundancy Check (CRC) is known to be used to detect whether any errors have been introduced into the sequence of information bits as the sequence of information bits is passed from the source to the destination.

[0003] Source-side CRC calculation

[0004] At the source end, the sequence of information bits A is a = [a0, a...]. l ,a2,...,a A-1 Perform a CRC calculation to generate a sequence p = [p0, p1, p2, ..., p1] of L parity bits. L-1 ].

[0005] According to the CRC generator polynomial, a sequence of parity bits p is generated as a function of A information bits of a. The CRC generator polynomial is usually specified in the communication standards being implemented, such as the L=6-bit CRC generator polynomial of the 3GPP New Radio [1]: g CRC6 (D)=[D 6 +D 5 +1]. It is worth noting that communication standards typically specify constraints governing the generation of CRC, but not how it can be implemented. More specifically, communication standards typically only specify that the computation be performed in a systemic manner, such that the polynomial a0D A+L-1 +a1D A+L-2 +…+a A-1 D L +p0D L-1 +p1D L-2 +…+p L-2 D 1 +p L-1 When divided by the CRC generator polynomial, a remainder equal to "0" is produced in GF(2).

[0006] A sequence p of L parity bits is typically appended to the end of a sequence a of A information bits to produce a CRC encoded sequence of B = A + L bits.

[0007] b = [b0, b l ,b2,...,b B-1 ],in

[0008] b k =a k For k = 0, 1, 2, ..., A-1 and

[0009] b k = p k-A for k = A, A+1, A+2,..., A+L-1.

[0010] Some communication standards specify that a sequence of A information bits a can be appended to the end of a sequence of L ones-valued bits to generate an extended information bit sequence comprising L+A bits before the CRC computation:

[0011] a' = [a'0, a' l , a'2,..., a' L+A-1 ] where

[0012] a' k = 1 for k = 0, 1, 2,..., L-1 and

[0013] a' k = a k-L for k = L, L+1, L+2,..., L+A-1.

[0014] In these cases, a sequence of L parity bits p can be computed as a function of all L+A bits of the extended information bit sequence a' instead of as a function of the A bits of the information bit sequence a. The sequence of L parity bits can be appended to the end of the sequence of A information bits a to produce a CRC-encoded sequence:

[0015] B = A+L bits b = [b0, b l , b2,..., b B-1 ] as above.

[0016] In some cases, the bits of the CRC-encoded sequence b can be scrambled, interleaved, and / or channel-encoded at the source.

[0017] Sink CRC computation

[0018] At the sink, a CRC computation can be performed to detect errors in a sequence of B = A+L recovered CRC-encoded bits , if any, which would differ from the CRC-encoded bit sequence b obtained in the source. Here, the sequence of B = A+L recovered CRC-encoded bits may represent a sequence of L recovered parity bits appended to the end of a sequence of A recovered information bits , which would differ from the parity bit sequence p and the information bit sequence a obtained in the source if there are errors.

[0019] Errors can be detected by performing a CRC computation to obtain a sequence of L computed parity bits as a function of the A recovered information bits of ​ If the computed parity bit sequence is different from the recovered parity bit sequence then an error has been detected. Alternatively, the error can be detected by performing a CRC computation as a function of all B = A + L recovered CRC-encoded bits of to obtain a sequence of L computed parity bits In this case, the computed parity bit sequence becomes a syndrome of the CRC (as understood). If this syndrome is not equal to a sequence of L zero-valued bits, then an error has been detected. Note that the standard typically does not specify how to use the CRC to detect errors, allowing the implementer to choose the method described here or another method.

[0020] In the case where the source obtains the extended information bit sequence a' by appending the sequence a of A information bits to the end of a sequence of L one-valued bits, the same extension operation is performed in the sink. More specifically, the sequence a of A recovered information bits is appended to the end of a sequence of L one-valued bits to generate an extended recovered information bit sequence comprising L + A bits:

[0021] where

[0022] for k = 0, 1, 2,... L - 1 and

[0023] for k = L, L + 1, L + 2,... L + A - 1.

[0024] In these cases, the sequence of L computed parity bits may be computed as a function of all L + A bits of the extended recovered information bit sequence rather than as a function of the A bits of the recovered information bit sequence Alternatively, the sequence of B recovered CRC-encoded bits may be appended to the end of a sequence of L one-valued bits to generate an extended recovered CRC-encoded bit sequence comprising L + B bits:

[0025] where

[0026] for k = 0, 1, 2,... L - 1 and

[0027] for k = L, L + 1, L + 2,... L + B - 1.

[0028] ​In these cases, the sequence of L calculated check bits CRC encoded bit sequence that can be used as an extended recovery The function is calculated for all L+B bits, rather than as the recovered CRC encoded bit sequence. The function calculation for the B digits.

[0029] If the source performs scrambling, interleaving, and / or channel coding on the bits of the CRC encoded sequence b, inverse descrambling, deinterleaving, and / or channel decoding operations can be performed in the destination to obtain the recovered CRC encoded bit sequence. If scrambling the CRC-encoded sequence b in the source only affects the bits provided by the parity bit sequence p, the destination can scramble the calculated parity bit sequence after the CRC calculation. Instead of applying inverse scrambling to the recovered CRC encoded bit sequence before CRC calculation, this method uses inverse scrambling. Apply the inverse scrambling operation.

[0030] CRC calculation using shift registers

[0031] Now for reference Figure 1 The L=6-bit CRC generator polynomial g of the source circuit is shown. CRC6 (D)=[D 6 +D 5 The known shift register implementation 100 of +1]. The CRC generator polynomial can be interpreted as a linear feedback shift register 101, such as Figure 1 For the L=6-bit CRC generator polynomial g of [1] CRC6 (D)=[D 6 +D 5 The example illustrated by +1].

[0032] This shift register can be used to compute a sequence s = [s0, s1, s2, ..., sk] with K input bits. K-1 The sequence of L parity bits corresponding to 103 is p = [p0, p1, p2, ..., p1]. L-1 ]102, the sequence of these K input bits can be formed by the information bit sequence a, the extended information bit sequence a', and the recovered information bit sequence. Recovered CRC encoded bit sequence Recovered extended information bit sequence Or the recovered extended CRC encoded bit sequence supply. Figure 1 At position 104, the sequence of A = 12 information bits is shown:

[0033] a = [0 1 1 0 0 1 1 1 0 1 1 0] can be converted to a sequence of L = 6 parity bits:

[0034] p = [1 0 0 1 0 1], where K = A and s = a. These parity bits can be appended to the end of the sequence a of information bits to obtain a sequence of B = 18 CRC encoded bits:

[0035] b = [0 1 1 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1].

[0036] Note that some applications can employ the inverse of the CRC generator polynomial, which can be obtained by subtracting each exponent from L. For example, the L = 6-bit CRC generator polynomial g CRC6 (D) = [D 6 + D 5 + 1] = [D 6 + D 5 + D 0 ] is the inverse of g invCRC6 (D) = [D L-6 + D L-5 + D L-0 ] = [D 6 + D + 1].

[0037] The inverse generator polynomial can be represented by the inverse linear feedback shift register 201, as Figure 2 illustrated for the L = 6-bit inverse CRC generator polynomial g invCRC6 (D) = [D 6 + D + 1].

[0038] Referring now to Figure 2 , a known shift register implementation 200 of the L = 6-bit inverse CRC generator polynomial g invCRC6 (D) = [D 6 + D + 1] of the source circuit is shown.

[0039] Figure 2 The same sequence of A = 12 information bits is shown at 204:

[0040] a = [0 1 1 0 0 1 1 1 0 1 1 0] from Figure 1 can be converted to a sequence of L = 6 parity bits:

[0041] p = [1 0 0 1 1 1], where K = A and s = a.

[0042] Note that these parity bits are different from those of Figure 1 because the inverse generator polynomial ginvCRC6 (D) = [D 6 + D + 1] is different from the generator polynomial g CRC6 (D) = [D 6 + D 5 + 1].

[0043] CRC computation using generator matrix

[0044] The generator matrix can be used to perform a CRC computation on a sequence of K input bits s = [s0, s1, s2,..., s K-1 K-1] which can be provided by a sequence of information bits a, a sequence of extended information bits a', a sequence of recovered information bits Recovering a sequence of CRC encoded bits Recovering a sequence of extended information bits or a sequence of recovered extended CRC encoded bits More specifically, a sequence of L parity bits p = [p0, p1, p2,..., p L-1 K-1] can be generated as a function of the input bit sequence s according to p = sG, where G is a K x L generator matrix for the CRC, with the matrix multiplication being performed in GF(2). The Kth row of the generator matrix G is obtained as the parity bit sequence that results when computing the CRC for a sequence of K input bits, with the Kth bit set to 1 and all other bits set to 0. For example, in the case of a L = 6-bit CRC generator polynomial g CRC6 (D) = [D 6 + D 5 + 1] for computing the CRC for a sequence of K = 12 input bits, the generator matrix is given by:

[0045]

[0046] Note that from the above example sequence of A = 12 information bits a = [0 1 1 0 0 1 1 1 0 1 1 0], the 2nd, 3rd, 6th, 7th, 8th, 10th and 11th bits are set to 1. In this case, a sequence of L = 6 parity bits p = [1 0 0 1 0 1] can be obtained as the "XOR" of the 2nd, 3rd, 6th, 7th, 8th, 10th and 11th rows of this generator matrix.

[0047] Note that when the generator matrix is applied to a sequence of recovered CRC encoded bits to obtain a syndrome At this time, the generator matrix appears as a parity check matrix. In the example sequence b = [0 1 1 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1] of B = 18 CRC encoded bits from above, the 2nd, 3rd, 6th, 7th, 8th, 10th, 11th, 13th, 16th, and 18th bits are set to 1. As can be expected, the parity check matrix H = G The "XOR" of the 2nd, 3rd, 6th, 7th, 8th, 10th, 11th, 13th, 16th, and 18th rows of the generator matrix for K = 18 input bits, given by

[0048]

[0049] It can be observed that the last K rows in the generator matrix G corresponding to a particular number of K' input bits are equal to the generator matrix G corresponding to K input bits, where K < K'. For example, the last 12 rows of the generator matrix G for K = 18 above are equal to the generator matrix G for K = 12 above.

[0050] In the case where the bits of the CRC encoded sequence b are interleaved in the source, the sink can apply a corresponding de-interleaving operation to obtain a recovered CRC encoded bit sequence The CRC computation is then performed using the generator matrix G. Alternatively, the rows of the generator matrix G can be correspondingly interleaved and used to compute the CRC based on the interleaved version of the recovered CRC encoded bit sequence For example, this enables early termination of polar decoding [2] during blind decoding in the Physical Downlink Control Channel (PDCCH) of 3GPP New Radio [1].

[0051] In summary, it is known that a CRC computation can be equivalently described in a number of ways, including a generator polynomial, such as: g CRC6 (D) = [D 6 + D 5 + 1]; a linear feedback shift register, such as 101; or a generator matrix G, such as the examples above.

[0052] Parallel processing can be used to implement a CRC computation with low latency. Here, a set of two or more parallel processors can operate under the direction of a controller to process two or more bits at a time and compute corresponding CRC bits within a set of registers. In some known implementations, the processors can perform a multiplication of a bit with a binary representation of a generator polynomial [3]. However, multiplication is a relatively complex operation compared to, for example, an "XOR" operation, and there is a need for improved CRC methods, for example, when using parallel processing. SUMMARY

[0053] The present invention provides a method for low latency CRC computation using processing. In particular, the present invention details memory mapping and introduces a look-up table (LUT) that eliminates the need for a permutation network between memory and processor. Particular embodiments of the present invention are set forth in the dependent claims. These and other aspects of the present invention will become evident to those skilled in the art upon reading the following description of the embodiments described below in conjunction with the accompanying figures.

[0054] In a first aspect of the present invention, a cyclic redundancy check, CRC, computation circuit includes an input for receiving an input stream having an input bit sequence that includes two or more bits of the input stream at a time, the two or more bits aligned with rows of a CRC generator matrix stored in a look-up table, LUT, and a set of two or more parallel processors configured to perform a CRC computation of the input bit sequence. The LUT is operably coupled to the set of two or more parallel processors and includes a plurality of addresses, wherein at least one of the plurality of addresses is configured to store two or more rows of the CRC generator matrix. At least one of the set of two or more parallel processors is configured to: first combine LUT data with the input stream by masking the two or more rows of the CRC generator matrix stored in the LUT using the two or more bits of the aligned input stream, thereby generating two or more intermediate parity bit sequences; and second combine the two or more intermediate parity bit sequences into a single parity bit sequence. In this way, and because the input stream is aligned with the rows of the CRC generator matrix, the single parity bit sequence can be obtained without complex routing that would be required to enable any input bit to be combined with any row of the CRC generator matrix.

[0055] In an optional example, the two or more rows of the CRC generator matrix stored in the LUT can be aligned by zero padding the input bit sequence. In this way, the zero padding repositions the bits within the input bit sequence so that they are aligned with the corresponding rows of the CRC generator matrix.

[0056] In an optional example, the alignment with the two or more rows of the CRC generator matrix stored in the LUT includes one of: at least one of the set of two or more parallel processors receiving the input stream having zero padding that provides a multiple of P of the input bit sequence length; wherein the input bit sequence has a first length and at least one of the set of two or more parallel processors zero pads the input bit sequence to increase the bit sequence first length to a multiple of the number P of the set of two or more parallel processors, where P is the number of two or more parallel processors. In this way, the bits of the input bit sequence can be evenly distributed among the P parallel processors, thereby allowing all parallel processors to operate in the same manner and no processor to require special independent control.

[0057] In an optional example, the number of rows in the CRC generator matrix stored in the LUT can be equal to or greater than the maximum supported input bit sequence length (K). max Divide by P. In this way, a single LUT can be used to enable CRC processing for any supported input bit sequence length, avoiding the need for different CRC processing mechanisms for different input bit sequence lengths.

[0058] In an optional example, the CRC calculation circuitry may include a controller operatively coupled to and configured to control a group of two or more parallel processors and a LUT. In this way, the controller can coordinate the operation of the parallel processors and read rows of the CRC generator matrix from the LUT.

[0059] In an optional example, generating two or more intermediate parity bit sequences may include performing a first combination of data multiples of [K / P], where K is the length of the input bit sequence and P is the number of two or more parallel processors. In this way, the number of steps required to process K bits of the input sequence is divided by the number of parallel processors, thereby minimizing the number of processing steps and maximizing processing efficiency.

[0060] In an optional example, a second combination of two or more intermediate parity bit sequences can be performed a multiple of [log2(P)] times to generate a single parity bit sequence, where P is the number of two or more parallel processors. In this way, the number of steps required to process K bits of the input sequence is reduced to the logarithm of the number of parallel processors, thereby minimizing the number of processing steps and maximizing processing efficiency.

[0061] In an optional example, at least L bits in at least one row of the generator matrix (G) can be padded with zero-value bits to increase the bit sequence to a second length (L'). In this way, the length can be adjusted to a length that is more convenient for storage in conventional memory architectures such as 32-bit RAM.

[0062] In an optional example, zero padding can be applied at the beginning of the input bit sequence. In this way, zero padding does not contribute to the CRC parity bit sequence because of the property that zero-value bits at the beginning of the input bit sequence do not contribute to the CRC parity bit sequence.

[0063] In an optional example, combining the LUT data with the input stream can first include using data stored in the LUT with an index (K). maxdata of two or more rows of the CRC generator matrix of / P1-GK / P+c) are combined with an aligned set of two or more input bits provided by the input stream having index c, where K is the length of the input bit sequence, P is the number of two or more processors; and c is a counter value ranging from 0 to [K / P] - 1. In this way, the correct row of the CRC generator matrix can be read from the LUT and combined with the input stream of bits only under the operation of a simple controller, which is based on the counter.

[0064] In an optional example, the CRC computation circuit can be configured as a CRC decoder, wherein the two or more parallel processors can be further configured to: apply an inverse processing operation of a predefined CRC generator polynomial, which encodes the input bit sequence to produce a data set; compute a CRC syndrome from the data set; and determine whether the CRC syndrome contains any 1-valued bits indicating a CRC error. In this way, the information bits can be processed in a reversed order, which can be more convenient in some applications.

[0065] In an optional example, the LUT can be configured to use a generator matrix G generated from an inverse CRC generator polynomial. In this way, most of the CRC computation work can be pre-computed, leaving only simple operations to be performed at runtime in order to complete the CRC computation process.

[0066] In an optional example, the order of the rows in the generator matrix G can be reversed to obtain an inverse generator matrix G'. In this way, the information bits can be processed in their natural order, which can be more convenient in some applications.

[0067] In an optional example, zero padding can be applied at the end of the input bit sequence. In this way, the convention of applying zero padding at the end of the bit sequence is preserved, which contrasts with a computation using a non-inverse generator matrix, in which zero padding is inconveniently applied instead at the beginning of the input bit sequence.

[0068] In a second aspect of the invention, a communication unit comprising a CRC computation circuit according to the first aspect of the invention is described.

[0069] In a third aspect of the invention, a method for Cyclic Redundancy Check (CRC) includes: receiving an input stream having an input bit sequence comprising two or more bits of the input stream at a time, the two or more bits being aligned with rows of a CRC generator matrix stored in a lookup table (LUT); and performing a CRC calculation of the input bit sequence by a group of two or more parallel processors. The method includes storing two or more rows of the CRC generator matrix in at least one of a plurality of addresses of the lookup table (LUT); and firstly combining LUT data with the input stream by masking two or more rows of the CRC generator matrix stored in the LUT using the aligned input stream to generate two or more intermediate parity bit sequences; and secondly combining the two or more intermediate parity bit sequences into a single parity bit sequence. Attached Figure Description

[0070] Further details, aspects, and embodiments of the invention will be described by way of example only with reference to the accompanying drawings. In the drawings, similar reference numerals are used to identify similar or functionally similar elements. Elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0071] Figure 1 The L=6-bit CRC generator polynomial g of the source circuit is shown. CRC6 (D)=[D 6 +D 5 The document describes a known shift register implementation of [+1] and provides an example of how a sequence of A = 12 information bits, a = [0 1 1 0 0 1 1 1 0 1 1 0], can be converted into a sequence of L = 6 parity bits, p = [1 0 0 1 0 1], where K = A and s = a.

[0072] Figure 2 The L=6-bit inverse CRC generator polynomial g of the source circuit is shown. invCRC6 (D)=[D 6 The document describes a known shift register implementation of [+D+1] and provides an example of how a sequence of A = 12 information bits, a = [0 1 1 0 0 1 1 1 0 1 1 0], can be converted into a sequence of L = 6 parity bits, p = [1 0 0 1 1 1], where K = A and s = a.

[0073] Figure 3 An example embodiment of the invention is shown for the case where P=4.

[0074] Figure 4 The polynomial g corresponding to the L=6-bit CRC generator is shown in an example embodiment of the present invention. CRC6 (D)=[D 6 +D5 the storage of the generator matrix G of the L = 6-bit CRC generator polynomial g max (D) = [D + D + 1] in a LUT, where: L' = 8, K = 18 and P = 4. Figure 4 An example is also provided of how a sequence a = [1 1 0 1 1 0 0 1 1] of A = 9 information bits can be converted into a sequence p = [0 0 0 1 0 1] of L = 6 parity check bits, where: K = A and s = a.

[0075] Figure 5 A flowchart showing the operation of the controller in an example embodiment of the invention is shown.

[0076] Figure 6 A L = 6-bit inverse CRC generator polynomial g invCRC6 (D) = [D + D + 1] is shown. 6 A shift register implementation of the L = 6-bit CRC generator polynomial g CRC6 (D) = [D + D + 1] is shown. 6 A shift register implementation of the L = 6-bit CRC generator polynomial g 5 (D) = [D + D + 1] is shown. Figure 6 An example is also provided of how a sequence b = [0 1 1 0 0 1 1 1 0 1 1 0 1 0 0 1 1 1] of B = 18 CRC encoded bits can be converted into a sequence of L = 6 parity check bits, where K = B, s = b and

[0077] Figure 7 A L = 6-bit inverse CRC generator polynomial g invCRC6 (D) = [D + D + 1] is shown. 6 The storage of the inverse generator matrix G' of the L = 6-bit CRC generator polynomial g max (D) = [D + D + 1] in a LUT, where: L' = 8, K = 18 and P = 4. Figure 7 An example is also provided of how a sequence b = [1 1 0 1 1 0 0 1 1 0 0 0 1 0 1] of B = 15 CRC encoded bits can be converted into a sequence of L = 6 parity check bits, where K = B, s = b and

[0078] Figure 8 A typical computing system that can be employed in an electronic device or wireless communication unit to perform a CRC computation in accordance with some example embodiments of the invention is shown.

[0079] Figure 9 A flowchart showing the operation of the controller in an example embodiment of the invention is shown, the controller operating based on the inverse generator matrix G'. DETAILED DESCRIPTION

[0080] Parallel processing of CRC computation using generator matrix according to first aspect

[0081] Reference is now made to Figure 3 , which shows an example cyclic redundancy check, CRC, computation circuit 300 for the case where P = 4. The first aspect of the present invention aims to address the challenge of efficiently performing an L-bit CRC computation on a consecutive sequence of input bits using a set of P parallel processors 301. Here, the number of parallel processors takes a fixed value P, which can be chosen at design time to be any value greater than or equal to “2”. In contrast, the number of bits K e [1, K max ] in the consecutive input bit sequence s can vary at run time, where the maximum input bit sequence length K max may be specified in the standard being implemented. As Figure 3 shown for the example where P = 4, the parallel processors 301 are aided by look-up tables (LUTs) 302, input streams 303, register banks 304, and controllers 305. In other examples, the number of parallel processors 301 can vary.

[0082] In steps of the CRC computation process, multiple of the P processors 301 (and in some examples, each of the P processors 301) are capable of computing an “and” 307 of a set of L’ bits with a mask bit, and then computing an “exclusive or” 308 of the resulting set of L’ bits with another set of L’ bits, where L’ > L can be chosen to be a value that facilitates implementation, such as, for example, 8, 16, or 32 bits. Multiple of the processors are also capable of optionally performing neither of these “and” 307 and “exclusive or” 308 operations during some steps. In some examples, each step can correspond to at least one clock cycle in a hardware implementation. In some examples, each processor can be a processing unit in a single instruction multiple data (SIMD) processor. Note that instead of using the “and” 307 operation, the masking operation can be implemented by using clock or power gating to disable the passing of a set of L’ bits when the mask bit is set to zero. Thereafter, the use of two or more bits of the input stream 303 to mask two or more aligned rows of the CRC generator matrix stored in the LUT 302 and to generate two or more intermediate parity bit sequences therefrom includes such clock or power gating techniques that disable the passing of several sets of bits.

[0083] Some examples of the present invention exploit the observation that in a generator matrix G corresponding to K max input bits, the last K rows are equal to a generator matrix G corresponding to K max input bits, where K < K Figure 3The continuous CRC calculation process is completed with the help of the same LUT 302, which can be implemented in read-only memory (ROM) or random access memory (RAM). Here, in a dedicated hardware embodiment of the invention, a specially configured ROM can be used to store the LUT, while in an embodiment using a general-purpose processor, RAM can be used to store the LUT 302. More specifically, the LUT 302 can store input bits K corresponding to the maximum supported number. max The generator matrix G of K max Each line.

[0084] Now for reference Figure 4 In an exemplary embodiment of the present invention, a polynomial g corresponding to the L=6-bit CRC generator is shown. CRC6 (D)=[D 6 +D 5 Storage of the generator matrix G 400 in the LUT, where L' = 8, K + 1] . max =18 and P=4. Figure 4 It also provides an example of how a sequence a = [1 1 0 1 1 0 0 1 1] with A = 9 information bits can be converted into a sequence p = [0 0 0 1 0 1] with L = 6 parity bits, where K = A and s = a.

[0085] As shown in the figure, in some examples, the L bits in each row of the generator matrix G stored in the LUT can optionally be padded with zero-value bits 401 to increase its length to L' bits. For example, if the rows of the generator matrix G consist of L = 24 bits, they can be padded with 8 zero-value bits to increase their length to L' = 32 bits and allow them to be stored in 32-bit RAM. In some examples, the padding bits can be added to the beginning of each row of the generator matrix G, while in other examples they can be added to the end of each row. Instead of applying padding to each row of the generator matrix G stored in the LUT, it is envisioned that in an alternative arrangement, padding can be added to the rows at some point during subsequent processing after the rows have been read from the LUT.

[0086] K of the generator matrix G max Each row is stored in several groups of P rows 402 within LUT 302. In K max If the generator matrix G is not divisible by P, a set of additional modulo (-K) elements can be added to the top of the generator matrix G. max P) rows of 403 are added to expand the number of rows to a multiple of P. These additional rows can contain any arbitrary bit values. [K] from the (expanded) generator matrix maxEach of the [K / P] consecutive groups of P rows (and their padding bits) 402 can be concatenated and stored in consecutive addresses of the LUT 302, where the first group of P rows can be indexed by address 0. Here, [x] is the smallest integer greater than or equal to x.

[0087] In an alternative arrangement, the bits of each (padded) row of the generator matrix G can be reversed before they are concatenated. In an alternative arrangement, the number [K max The [K / P] consecutive groups of P rows 402 can be stored in other addresses within the LUT 302. Figure 4 An example is shown for the case where L' = 8, K max = 18 and P = 4, corresponding to the L = 6-bit CRC generator polynomial g CRC6 (D) = [D 6 + D 5 + 1] in the LUT 302.

[0088] Reference is also made to Figure 3 , Figure 3 The input stream 303 is used to provide a sequence of consecutive input bits s. The bits of the input sequence s are provided by the input stream 303 in a manner that aligns with the arrangement of rows of the generator matrix G in the LUT 302. As will be detailed below, this alignment avoids the need for complex routing between the input stream 303, the LUT 302 and the processor 301. More specifically, the alignment is achieved by arranging the K bits of the input bit sequence s into groups of P bits 404 as they are provided by the input stream 303. In the case where K is not divisible by P, the alignment can be achieved by prepending a group of mod(-K, P) zero-valued padding bits 405 to the input bit sequence s in order to extend its length to a multiple of P. The [K / P] consecutive groups of P bits 404 from the (extended) input bit sequence can be provided by the input stream 303 in consecutive steps of the CRC computation process. Note that in some arrangements, the [K / P] consecutive groups of P bits from the (extended) input bit sequence provided by the input stream can be read from consecutive addresses of a RAM having a capacity of at least [K max / P] addresses.

[0089] The CRC computation process for a K-bit sequence of input bits s is completed under the direction of the controller 305 using two sets of steps as shown in the flowchart of Figure 3 Figure 5 An intermediate sequence 406 of a set of P L-parity bits can be computed during the first set of [K / P] steps. The P intermediate parity bit sequences 406 can then be combined into a single sequence p = [p0, pi, p2,..., p L-1 ​]102.

[0090] Reference is now made to Figure 5 , to the foregoing discussion of Figure 3 and Figure 4 , the flowchart 500 illustrates the operation of the controller according to an example embodiment of the present application. During a first set of [K / P] steps, the P intermediate parity bit sequences 406 are accumulated in the register set 304 of the Figure 3 . This register set 304 comprises P registers, each of which can store L' bits. A counter c 306 within the controller 305 is initialized 501 to a value of 0 at the beginning of the first step in the set of [K / P] steps 511, and this counter c 306 is incremented 502 at the beginning of each of the successive steps thereafter. In each of the steps, a set of P rows 402 of the generator matrix G is read 503 from the address ([K max / P]-[K / P]+c) of the LUT 302. At the same time, a set of P bits 404 having the index c from the (extended) input bit sequence is provided 504 by the input stream 303.

[0091] In each of the first set of [K / P] steps, each of the P rows of the generator matrix G provided by the LUT 302 is masked 505 by a corresponding one of the P input bits provided by the input stream 303. More specifically, each of the P processors 301 performs a corresponding one of these P masking operations by performing an "and" 307 of each of the L' bits in the corresponding row of the generator matrix G with the corresponding input bit. Due to the alignment between the arrangement of the P input bits in the input stream 303 and the P rows of the generator matrix G in the LUT 302, this masking can advantageously be performed without requiring complex routing between the input stream 303, the LUT 302 and the processors 301.

[0092] Note that in the first step of the [K / P] steps, in this example and when c=0, the set of P input bits 404 provided by the input stream 303 will include mod(-K,P) leading zero value padding bits 405 in the case that K is not a multiple of P. As noted above, these zero value padding bits serve to achieve alignment and to mask a corresponding mod(-K,P) rows from the set of P rows 402 of the generator matrix G read from the LUT 302. In this case, these mod(-K,P) masked rows will precede the last K rows of the generator matrix G, thereby advantageously ensuring that only the last K rows of the generator matrix G will have the opportunity to influence the P intermediate parity bit sequences 406. As noted above, the K maxThe last K rows of the matrix equal the generator matrix G corresponding to the K input bits. In this way, even if K is not a multiple of P, the same LUT 302 storing the generator matrix G corresponding to K max input bits can advantageously be reused for all values of K.

[0093] During a first step 506 of the first set of [K / P] steps, when c = 0, the P masked rows of the generator matrix G obtained during this step are written 507 to the register set 304 in order to initialize the P intermediate parity bit sequences 406. In a number of subsequent steps, when 0 < c < [K / P], the P intermediate parity bit sequences 406 are read 508 from the register set 304 and provided to the P processors 301 where they are XORed 308 509 with the P masked rows of the generator matrix G obtained in this step. The result is then written back 510 to the register set 304 in order to accumulate the P intermediate parity bit sequences 406. Note that the action of the counter c 306 is to read [K / P] addresses in the LUT 302 in ascending order, in line with the natural order in which the input stream 303 provides the groups of P input bits 404. However, in other arrangements, the input stream 303 can provide the groups of P input bits 404 in any order and the addresses of the LUT can be read in a corresponding order. Figure 4 An example is provided of how a sequence a = [1 1 0 1 1 0 0 1 1] of A = 9 information bits 303 can be converted into a set of P = 4 intermediate parity bit sequences 406.

[0094] During a second set of [log2(P)] steps 514, the register set 304 is used to combine the P intermediate parity bit sequences 406 into a single desired parity bit sequence 102. The counter c 306 is initialized 512 to a value of 0 at the beginning of the first step of the set of [log2(P)] steps, and this counter c 306 is incremented 513 at the beginning of successive steps thereafter. In a number of steps when 0 < c < [log2(P)], a group of P / 2 c intermediate parity bit sequences is read 515 from the first P / 2 c registers of the set of P registers 304. The group of P / 2 c intermediate parity bit sequences is then split into two subsets, each subset comprising P / 2 c+1 intermediate parity bit sequences. Each intermediate parity bit sequence in the first subset of P / 2 c+1 intermediate parity bit sequences is then XORed 308 516 with a corresponding intermediate parity bit sequence from the second subset of P / 2 c+1 intermediate parity bit sequences. The resulting group of P / 2c+1 The P intermediate parity check bit sequences that are "XORed" 308 are then written 517 into the first of the set of P registers 304 in the set of P registers 304 c+1 .

[0095] Upon completion of the last of the second set of [log2(P)] steps, the P intermediate parity check bit sequences will be combined into a single desired parity check bit sequence, which is stored in the first register in the set of P registers 304. The parity check bit sequence p = [p0, pi, p2,..., pL-1] of L bits can then be extracted 518 from the L' bits in the register by removing the zero-valued padding bits. Note that in the method described herein, the P intermediate parity check bit sequences are successively combined into the first of the P registers in the set of registers 304. L-1 ] of L bits. Note that in the method described herein, the P intermediate parity check bit sequences are successively combined into the first of the P registers in the set of registers 304.

[0096] In an alternative arrangement, the P intermediate parity check bit sequences can be successively combined into any of the P registers in the set of registers 304. For example and returning reference to Figure 4 , an example is provided of how a set of P = 4 intermediate parity check bit sequences 406 can be combined into a sequence of L = 6 parity check bits p = [0 0 0 1 0 1] 102, where K = A and s = a.

[0097] The parity check sub-computation using the inverse generator matrix in the first aspect of the invention and its associated parallel processing

[0098] Reference is now made to Figure 6 , which shows a shift register implementation 600 of the L = 6 bit inverse CRC generator polynomial g invCRC6 (D) = [D 6 + D + 1] for computing the parity check sub-code of a CRC encoded bit sequence generated using the L = 6 bit CRC generator polynomial g CRC6 (D) = [D 6 + D 5 + 1]. Figure 6 An example is also provided of how a sequence of B = 18 CRC encoded bits b = [0 1 1 00 1 1 1 0 1 1 0 1 0 0 1 1 1] can be transformed into a sequence of L = 6 parity check bits , where K = B, s = b and

[0099] In the sink, the parity check sub-code of the recovered CRC encoded bit sequence can be performed using the inverse of the CRC generator polynomial The CRC calculation can be performed even if a regular CRC generator polynomial was used in the source. More specifically, the shift register representation of the inverse CRC generator polynomial can be used as a sequence. The function is used to calculate the sequence of L check bits by using all B = A + L recovered CRC encoded bits. However, when using the shift register representation of the inverse CRC generator polynomial to calculate the checksum... When this happens, the sequence must be processed in reverse order. The B digits. If the checksum An error has been detected if the sequence is not equal to L zero-valued bits. This is in Figure 6 The sequence is shown as L parity bits 102, where the inverse CRC generator polynomial g invCRC6 (D)=[D 6 +D+1] is used for calculation Figure 1 The error-free B=18-bit CRC encoded sequence b has an L=6-bit checksum. Where: K = B, 102 and s = reverse(b) is obtained by reversing the order of the bits in b 103. Note the checksum. Including L = 6 zero-value bits, confirming that b is error-free.

[0100] Alternatively, a K×L generator matrix G of the inverse CRC generator polynomial can be used to perform the sequence of B recovered CRC encoded bits. L-bit checksum The CRC calculation is performed, where K = B. Here, the order of the rows in the generator matrix G can be reversed to obtain the inverse generator matrix G'. This advantageously allows sequences to be processed in forward order rather than reverse order. The units digit of B. More specifically, the checksum can be calculated as: In the example sequence b = [0 1 1 0 0 1 1 1 0 1 1 0 1 1 0 1 0 0 1 0 1] from the above B = 18 CRC encoded bits, bits 2, 3, 6, 7, 8, 10, 11, 13, 16, and 18 are set to 1. As expected, L = 6 bits of checksum. g can be used as the inverse CRC generator polynomial for K=18 invCRC6 (D)=[D 6 The inverse generator matrix of K×L[+D+1] is obtained by XORing rows 2, 3, 6, 7, 8, 10, 11, 13, 16, and 18, which is given by the following formula:

[0101]

[0102] It can be observed that in the inverse generator matrix G' corresponding to a certain number K' of input bits, the first K rows are equal to the inverse generator matrix G' corresponding to K input bits, where K < K'. For example, the first 12 rows of the generator matrix G' for K = 18 above are equal to the inverse generator matrix G' for K = 12. This is in contrast to a regular generator matrix G corresponding to a certain number K' of input bits, where it is the last K rows that are equal to the generator matrix G corresponding to K input bits, where K < K'.

[0103] In some examples of the application, this property of the inverse generator matrix G' can be exploited to adapt the scheme of Figure 3 so that the recovered CRC encoded bit sequence does not require the prepending of zero-valued padding bits 405 when used as the input bit sequence s. This advantageously allows the CRC encoded bit sequence to be stored in a more convenient format. If the CRC check is successful, the CRC encoded bit sequence Figure 3 can be output directly. Figure 3 As mentioned above, max the LUT 302 stores K max rows of the inverse generator matrix G' for K max input bits. However, when K max cannot be divided evenly by the number P of parallel processors, instead of prepending a set of mod(-K invCRC6 ,P) arbitrary rows 403 to the top of the generator matrix, these additional rows 703 are appended to the bottom of the inverse generator matrix G' as shown in Figure 7 .

[0104] Reference is now made to Figure 7 , which illustrates the storage in a LUT of the inverse generator matrix G' 700 corresponding to the inverse CRC generator polynomial g 6 (D) = [D max + D + 1] for L' = 8, K max = 18 and P = 4, according to an example embodiment of the application. Figure 7 An example is also provided of how a sequence b = [1 1 0 1 1 0 0 1 1 0 0 0 1 0 1] of B = 15 CRC encoded bits can be converted to a sequence of L = 6 syndrome bits, where K = B, s = b and

[0105] As mentioned above,As shown, when K is not divisible by the number P of parallel processors, instead of prepending a set of mod(-K, P) zero-valued padding bits 405 to the beginning of the input bit sequence s, these additional padding bits 705 are appended to the end of the input bit sequence s. As mentioned above, the multiple consecutive sets of P rows 702 of the (extended) generator matrix are stored in consecutive addresses of the LUT 302, where the first set of P rows can be indexed by address 0, respectively. Likewise, in the consecutive steps of the CRC computation, the input stream 303 provides multiple consecutive sets of P bits 704 of the (extended) input bit sequence.

[0106] Figure 7 shows the storage of the inverse generator matrix G' corresponding to the L = 6-bit inverse CRC generator polynomial g max (D) = [D invCRC6 + D + 1] for the case of L' = 8, K 6 = 18 and P = 4. As mentioned above, the counter c 306 is initialized to the 0 value at the beginning of the first step of a set of [K / P] steps, and this counter c 306 is incremented at the beginning of multiple (e.g., each) consecutive steps thereafter. However, instead of reading a set of P rows 402 of the generator matrix from address ([K max / P] - [K / P] + c) of the LUT 302 in each step, a set of P rows 702 of the inverse generator matrix G' is read from address c. At the same time, a set of P bits 704 having index c from the (extended) input bit sequence is provided by the input stream 303, as mentioned above. Apart from these differences, Figure 7 the operation of the scheme of

[0107] More specifically, the operation proceeds as shown in the flowchart of Figure 9 , with the difference that only the computation 903 of the address for reading a set of P rows 402 of the generator matrix from the LUT. Figure 5

[0108] Thus, Figure 7 An example is provided of how a sequence a = [1 1 0 1 1 0 0 1 1 0 0 0 1 01] of B = 15 CRC encoding bits 303 can be transformed into a set of P = 4 intermediate parity bit sequences 706 (which are then combined into a sequence of L = 6 parity bits ) with K = B, s = b and

[0109] Figure 9 A flowchart is shown of the operation of a controller in an example embodiment of the present invention, which operates based on an inverse generator matrix G'.

[0110] Application​

[0111] Referring now to the drawing in which is shown a typical computing system 800 that can be used to implement CRC calculations in accordance with some example embodiments of the present application. Figure 8 The computing system 800 can represent, for example, a desktop, laptop or notebook computer, handheld computing device (PDA, cell phone, palmtop, etc.), mainframe, server, client, or any other type of special or general purpose computing device as can be desirable or appropriate for a given application or environment. The computing system 800 can include at least one processor, such as processor 804. Processor 804 can be implemented using a general or special purpose processing engine such as, for example, a microprocessor, microcontroller or other control logic. In this example, processor 804 is connected to a bus 802 or other communication medium. In some examples, the computing system 800 can be a non-transitory, tangible computer program product including executable code stored therein for implementing CRC calculations.

[0112] The computing system 800 can also include a main memory 808, such as random access memory (RAM) or other dynamic memory, for storing information and instructions to be executed by processor 804. Main memory 808 can also be used for storing temporary variables or other intermediate information during execution of instructions to be executed by processor 804. The computing system 800 can likewise include a read only memory (ROM) or other static storage device coupled to bus 802 for storing static information and instructions for processor 804.

[0113] The computing system 800 can further include an information storage system 810, which can include, for example, a media drive 812 and a removable storage interface 820. The media drive 812 can include a drive or mechanism to support fixed or removable storage media, such as a hard disk drive, a floppy disk drive, a magnetic tape drive, an optical disk drive, a Compact Disk (CD) or Digital Video Drive (DVD) read or write drive (R or RW), or other removable or fixed media drive. Storage media 818, of which the removable storage interface 820 can be part, can include, for example, a hard disk, floppy disk, magnetic tape, optical disk, CD or DVD, or other fixed or removable medium employed in connection with the media drive 812. As these examples illustrate, the storage media 818 can include a computer-readable storage medium having stored therein particular computer software or data.

[0114] In an alternative embodiment, the information storage system 810 may include other similar components for allowing computer programs or other instructions or data to be loaded into the computing system 800. Such components may include, for example, removable storage units 822 and interfaces 820, such as program cartridges and cartridge interfaces, removable memory (e.g., flash memory or other removable memory modules) and memory slots, as well as other removable storage units 822 and interfaces 820 that allow software and data to be transferred from the removable storage unit 818 to the computing system 800.

[0115] The computing system 800 may also include a communication interface 824. The communication interface 824 can be used to allow software and data to be transferred between the computing system 800 and external devices. Examples of the communication interface 824 may include a modem, a network interface (such as Ethernet or other NIC cards), a communication port (such as a Universal Serial Bus (USB) port), a PCMCIA slot, and cards. The software and data transferred via the communication interface 824 are in the form of signals, which may be electronic, electromagnetic, or optical signals, or other signals that can be received by the communication interface 824. These signals are provided to the communication interface 824 via a channel 828. The channel 828 can carry signals and can be implemented using wireless media, wires or cables, optical fibers, or other communication media. Some examples of channels include telephone lines, cellular telephone links, RF links, network interfaces, local area networks (LANs) or wide area networks (WANs), and other communication channels.

[0116] In this document, the terms "computer program product," "computer-readable medium," etc., are generally used to refer to media such as, for example, memory 808, storage device 818, or storage unit 822. These and other forms of computer-readable media may store at least one instruction for use by processor 804 to cause the processor to perform specified operations. Such instructions, generally referred to as "computer program code" (which may be grouped as a computer program or other groupings), when executed, enable computing system 800 to perform the functions of embodiments of the present invention. Note that code may directly cause the processor to perform specified operations, be compiled to perform specified operations, and / or be combined with other software, hardware, and / or firmware elements (e.g., libraries for performing standard functions) to perform specified operations.

[0117] In embodiments using software implementation elements, the software may be stored on a computer-readable medium and loaded into the computing system 800 using, for example, a removable storage drive 822, a drive 812, or a communication interface 824. Control logic (in this example, software instructions or computer program code) causes the processor 804 to perform the functions of the invention as described herein when executed by the processor 804.

[0118] Now for reference Figure 9 In the second aspect of the invention and with reference toFigure 3 and Figure 4 The preceding discussion, but without the need for parallel processing, is illustrated in flowchart 900. Figure 7 The operation of the controller according to an exemplary embodiment of the present invention. During the first set of [K / P] steps, P intermediate parity bit sequences 706 are... Figure 3 The increment is accumulated in register group 304. Register group 304 includes P registers, each of which can store L' bits. Counter c 306 within controller 305 is initialized to a value of "0" at the beginning of the first step in a set of [K / P] steps 911, and counter c 306 is incremented at the beginning of subsequent consecutive steps 902. In multiple (e.g., each) steps, a set of P rows 702 of generator matrix G is read from address (c) of LUT 302 903. Simultaneously, a set of P bits 704 with index c is provided 904 from the (extended) input bit sequence by input stream 303.

[0119] In each of the first group of [K / P] steps, each of the P rows of the generator matrix G provided by LUT 302 is masked 905 by a corresponding one of the P input bits provided by input stream 303. More specifically, each of the P processors 301 performs one of these P masking operations by performing an AND operation 307 on each of the L' bits in the corresponding row of the generator matrix G with the corresponding input bit. Due to the alignment between the arrangement of the P input bits in input stream 303 and the P rows of the generator matrix G in LUT 302, the masking can be advantageously performed without the need for complex routing between input stream 303, LUT 302, and processors 301.

[0120] Note that in the first step of the [K / P] steps, in this example and when c = 0, the set of P input bits 704 provided by input stream 303 will include mod(-K,P) leading zero-value padding bits 705 if K is not a multiple of P. As described above, these zero-value padding bits are used to achieve alignment and to mask the corresponding mod(-K,P) rows of the set of P rows 702 of the generator matrix G read from LUT 302. In this case, these mod(-K,P) masked rows will precede the last K rows of the generator matrix G, thereby advantageously ensuring that only the last K rows of the generator matrix G will have the opportunity to affect the P intermediate parity bit sequence 706. As described above, the K in the generator matrix G stored in LUT 302 max The last K rows of each row are equal to the generator matrix G corresponding to the K input bits. In this way, even if K is not a multiple of P, the data corresponding to K input bits is stored. maxThe same LUT 302 of generator matrices G of input bits of one can also advantageously be reused for all values of K.

[0121] During a first step 906 of the first set of [K / P] steps, when c = 0, the P masked rows of the generator matrix G obtained during this step are written 907 to the register set 304 in order to initialize the P intermediate parity bit sequences 706. In a number of subsequent steps, when 0 < c < [K / P], the P intermediate parity bit sequences 706 are read 908 from the register set 304 and provided to the P processors 301 where they are "XORed" 308 909 with the P masked rows of the generator matrix G obtained in this step. The result is then written back 910 to the register set 304 in order to accumulate the P intermediate parity bit sequences 706. Note that the action of the counter c 306 is to read [K / P] addresses in the LUT 302 in ascending order, in line with the natural order in which the input stream 303 provides the groups of P input bits 704. However, in other arrangements, the input stream 303 can provide the groups of P input bits 704 in any order and the addresses of the LUT can be read in a corresponding order. Figure 7 An example is provided of how the sequence a = [1 1 0 1 1 0 0 1 1 0 0 0 1 0 1] 303 of B = 15 CRC encoding bits can be transformed into a set of P = 4 intermediate parity bit sequences 706.

[0122] During a second set of [log2(P)] steps 914, the register set 304 is used to combine the P intermediate parity bit sequences 706 into a single desired parity bit sequence 102. The counter c 306 is initialized 912 to a value of 0 at the beginning of the first step of the set of [log2(P)] steps, and this counter c 306 is incremented 913 at the beginning of successive steps thereafter. In a number of steps when 0 < c < [log2(P)], a group of P / 2 c intermediate parity bit sequences is read 915 from the first P / 2 c registers of the set 304 of P registers. The group of P / 2 c intermediate parity bit sequences is then split into two subsets, each subset comprising P / 2 c+1 intermediate parity bit sequences. Each intermediate parity bit sequence in the first subset of P / 2 c+1 intermediate parity bit sequences is then "XORed" 308 916 with a corresponding intermediate parity bit sequence from the second subset of P / 2 c+1 intermediate parity bit sequences. The resulting group of P / 2 c+1The P intermediate parity bit sequences are then written 917 into the first of the set of P registers 304 c+1 of the P registers.

[0123] Upon completion of the last of the second set of [log2(P)] steps, the P intermediate parity bit sequences will be combined into a single desired parity bit sequence, which is stored in the first of the set of P registers 304. The parity bit sequence p = [p0, pi, p2,..., pL-1] of L bits can then be extracted 918 from the L' bits of the register by removing the zero-valued padding bits. Note that in the method described here, the P intermediate parity bit sequences are successively combined into the first of the P registers of the register set 304. L-1 ] of L bits. Note that in the method described here, the P intermediate parity bit sequences are successively combined into the first of the P registers of the register set 304.

[0124] In alternative arrangements, the P intermediate parity bit sequences can be successively combined into any of the P registers of the register set 304. For example and returning reference to Figure 7 , an example is provided of how a set of P = 4 intermediate parity bit sequences 706 can be combined into a sequence of L = 6 check subbits with K = B, s = b and

[0125] In the foregoing specification, the application has been described with reference to specific examples of embodiments of the application. It is evident, however, that various modifications and changes can be made thereto without departing from the scope of the application as set forth in the claims that follow. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

[0126] Connections as discussed herein can be any type of connection suitable to communicate signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied otherwise by context, connections can be direct or indirect and can be physical, wireless or any combination thereof. Connections can be illustrated as a single connection or a plurality of connections by virtue of being divided into different connections illustrating different physical couplings, different physical mediums, different physical nodes, different physical devices, different physical locations etc. It will be appreciated that a multitude of individual connections can be substituted for a single connection have the same or similar function. Connections illustrated as single inverted arcs can be replaced with a plurality of arcs and vice versa. Connections illustrated as direct physical connections can be replaced with some form of indirect electrical or magnetic coupling. Similarly, connections illustrated as indirect physical connections can be replaced with a direct physical connection. It will also be appreciated that like reference numerals can refer to like parts throughout the specification and figures.

[0127] Those skilled in the art will realize that the architectural framework described herein is merely an example and that many other architectures can be implemented which achieve the same functionality.

[0128] Any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, a first component described herein can be "associated with" a second component even though the first component is not physically present with the second component, with the

[0129] Moreover, those skilled in the art will appreciate that the boundaries between the aforementioned operations merely illustrative. The multiple operations can be combined into a single operation, a single operation can be distributed in additional operations and operations can be executed at least partially overlapping in time. Moreover, alternative embodiments can include a number of instances of the particular operations, and the order of the operations can be changed.

[0130] The present application is described herein with reference to integrated circuit devices including, for example, microprocessors configured to perform the functions of a CRC calculation. However, it will be appreciated that the present application is not limited to such integrated circuit devices, and can equally apply to integrated circuit devices including any alternative type of operational functionality. Examples of such integrated circuit devices including alternative types of operational functionality can include, by way of example only, application specific integrated circuit (ASIC) devices, field programmable gate array (FPGA) devices or the like integrated with other components. Moreover, because the illustrated embodiments of the present application can be implemented using electronic components and circuits known to those skilled in the art, no further details as to the application of the electronic components and circuits are given in order not to obscure the basic concepts underlying the present application and in order to avoid unnecessary diversion from the teaching of the present application. Alternatively, the circuit and / or component examples can be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.

[0131] Furthermore, for example, an example or a part thereof can be implemented as a physical circuitry or a soft or code representation of the logic representation translatable into a physical circuitry, such as in any appropriate type of hardware description language.

[0132] Moreover, the present application is not limited to physical devices or units implemented in non-programmable hardware, but can also apply to programmable devices or units capable of performing the desired CRC calculations by operating in accordance with suitable program code, such as small computers, personal computers, notebooks, personal digital assistants, electronic games, automobiles and other embedded systems, mobile phones and various other wireless devices, which are generally referred to herein as "computer systems".

[0133] However, other modifications, changes and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

[0134] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. Further, as used herein, the term "and / or" comprises at least one of the elements or steps listed before and / or after this term. Furthermore, as used herein, the terms "one" or "a" are defined as at least one, rather than one. Moreover, the use of introductory phrases such as "one or more" and "at least one" in the claims should not be construed as implying that there is only one of the element or step present in the claims. Rather, the use of such phrases is intended to denote that there are either one or more elements or steps present in the claims. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.

[0135] References

[0136] [1] "3rd Generation Partnership Project; Technical Specification Group Radio Access Network; NR; Multiplexing and channel coding (Release 15)", 3GPP TS 38.212 V15.2.0, June 2018.

[0137] [2] Nokia, Alcatel-Lucent Shanghai Bell, "Rl-1703497 Details of CRC distribution of polar design", 3GPP TSG-RAN WG1 Meeting #88, Athens, Greece, February 2017.

[0138] [3] Intel, "Fast CRC Computation for Generic Polynomials Using PCLMULQDQ Instruction", December 2009.

Claims

1. A cyclic redundancy check (CRC) computation circuit, comprising: an input for receiving an input stream having an input bit sequence comprising two or more bits of the input stream at a time, the two or more bits aligned with rows of a CRC generator matrix stored in a lookup table (LUT); a set of two or more parallel processors configured to perform a CRC computation of the input bit sequence; wherein the LUT is operably coupled to the set of two or more parallel processors and comprises a plurality of addresses, wherein at least one of the plurality of addresses is configured to store two or more rows of the CRC generator matrix; and the set of two or more parallel processors is configured to: combine LUT data with the input stream by masking the two or more rows of the CRC generator matrix stored in the LUT using the two or more bits of the aligned input stream, thereby generating two or more intermediate parity bit sequences; and combine the two or more intermediate parity bit sequences into a single parity bit sequence.

2. The CRC calculation circuit of claim 1, wherein, the two or more rows of the CRC generator matrix stored in the LUT are aligned by zero padding the input bit sequence.

3. The CRC calculation circuit of claim 2, wherein, aligning with the two or more rows of the CRC generator matrix stored in the LUT comprises one of: At least one of the set of two or more parallel processors receiving the input stream with zero padding provides P an input bit sequence length that is a multiple of the number of input bits in the input stream, wherein P is the number of two or more parallel processors. wherein the input bit sequence has a first length and at least one of the set of two or more parallel processors zero-pads the input bit sequence to increase the first length of the bit sequence to a multiple of the number of the set of two or more parallel processors P .

4. The CRC calculation circuit of claim 1, wherein, The number of rows in the CRC generator matrix stored in the LUT is equal to or exceeds the maximum supported input bit sequence length (Nmax) divided by K max ) minus one P wherein P is the number of two or more parallel processors.

5. The CRC computation circuit of claim 1, further comprising a controller operably coupled and configured to control the set of two or more parallel processors and the LUT.

6. The CRC calculation circuit of claim 1, wherein, Generating the two or more intermediate parity bit sequences comprises performing a combination of data a number of times ceil(K / P), wherein, K is a length of the input bit sequence, and wherein, P is a number of the two or more parallel processors, and wherein ceil(K / P) represents a minimum integer greater than or equal to K / P.

7. The CRC calculation circuit of claim 1, wherein, The combination of the two or more intermediate parity bit sequences is performed a number of times equal to ceil(log2(P)) to generate a single parity bit sequence, wherein P P is the number of the two or more parallel processors, and wherein ceil(log2(P)) represents the smallest integer greater than or equal to log2(P).

8. The CRC calculation circuit of claim 1, wherein, L bits in at least one of the rows of the generator matrix (G) are padded with zero-valued bits to increase a bit sequence to a second length (L’).

9. The CRC calculation circuit of claim 1, wherein, zero padding is applied at a beginning of the input bit sequence.

10. The CRC calculation circuit of claim 9, wherein, combining the LUT data with the input stream comprises combining data from the two or more rows of the CRC generator matrix having indices ceil(K max / P) - c of the input bit sequence with data from the two or more rows of the CRC generator matrix having indices ceil(K c / P) - c of the input bit sequence with data from the two or more rows of the CRC generator matrix having indices ceil(K K / P) - c of the input bit sequence with data from the two or more rows of the CRC generator matrix having indices ceil(K K / P) - c of the input bit sequence with data from the two or more rows of the CRC generator matrix having indices ceil(K max / P) - c of the input bit sequence with data from the two or more rows of the CRC generator matrix having indices ceil(K P / P) - c of the input bit sequence with data from the two or more rows of the CRC generator matrix having indices ceil(K c / P) - c of the input bit sequence with data from the two or more rows of the CRC generator matrix having indices ceil(K max / P) - c of the input bit sequence with data from the two or more rows of the CRC generator matrix having indices ceil(K max / P) - c of the input bit sequence with data from the two or more rows of the CRC generator matrix having indices ceil(K 11. The CRC calculation circuit of claim 1, when the CRC calculation circuit is configured as a CRC decoder, wherein, the set of two or more parallel processors is further configured to: apply an inverse processing operation of a predefined CRC generator polynomial, the inverse processing operation encoding the input bit sequence to produce a data set; compute a CRC syndrome from the data set; and determine whether the CRC syndrome contains any 1-valued bits indicative of a CRC error.

12. The CRC calculation circuit of claim 11, wherein, the LUT is configured to use a generator matrix G generated from an inverse CRC generator polynomial.

13. The CRC calculation circuit of claim 12, wherein, an order of the rows in generator matrix G is reversed to obtain an inverse generator matrix G’.

14. The CRC calculation circuit of claim 11, wherein, applying zero padding at the end of the input bit sequence, and wherein combining the LUT data with the input stream comprises combining the data from the two or more rows (702) of the CRC generator matrix having indices c with an aligned set of two or more input bits (704) provided by the input stream, wherein, K is the length of the input bit sequence, P is the number of the two or more parallel processors, and c is a counter value ranging from 0 to ceil(K / P)-1, and wherein ceil(K / P) denotes the smallest integer greater than or equal to K / P.

15. A communication unit comprising a cyclic redundancy check (CRC) decoder circuit, the CRC decoder circuit comprising: an input for receiving an input stream having an input bit sequence comprising two or more bits of the input stream at a time, the two or more bits aligned with rows of a CRC generator matrix stored in a lookup table (LUT); a set of two or more parallel processors configured to perform a CRC computation of the input bit sequence; wherein the LUT is operably coupled to the set of two or more parallel processors and comprises a plurality of addresses, wherein at least one of the plurality of addresses is configured to store two or more rows of the CRC generator matrix; and the set of two or more parallel processors is configured to: combine LUT data with the input stream by masking the two or more rows of the CRC generator matrix stored in the LUT using the two or more bits of the aligned input stream, thereby generating two or more intermediate parity bit sequences; and combine the two or more intermediate parity bit sequences into a single parity bit sequence. wherein the set of two or more parallel processors is configured to: combine LUT data with the input stream by using two or more bit masks of the aligned input stream to mask the two or more rows of the CRC generator matrix stored in the LUT to generate two or more intermediate parity bit sequences; and combine the two or more intermediate parity bit sequences into a single parity bit sequence.

16. A method for cyclic redundancy check (CRC), comprising: receiving an input stream having an input bit sequence comprising two or more bits of the input stream at a time, the two or more bits aligned with rows of a CRC generator matrix stored in a lookup table (LUT); performing a CRC computation of the input bit sequence by a set of two or more parallel processors; storing two or more rows of a CRC generator matrix in at least one of a plurality of addresses of the LUT; and combine LUT data with the input stream by using two or more bit masks of the aligned input stream to mask the two or more rows of the CRC generator matrix stored in the LUT to generate two or more intermediate parity bit sequences; and combine the two or more intermediate parity bit sequences into a single parity bit sequence.

17. The method for cyclic redundancy check (CRC) of claim 16, wherein, The two or more rows of the CRC generator matrix stored in the LUT are aligned by zero padding the input bit sequence.

18. The method for a cyclic redundancy check (CRC) of claim 17, wherein, The aligning with the two or more rows of the CRC generator matrix stored in the LUT comprises one of: At least one of the set of two or more parallel processors receiving the input stream with zero padding provides P an input bit sequence length that is a multiple of P where N is the number of two or more parallel processors. wherein the input bit sequence is zero-padded by at least one of the set of two or more parallel processors to increase the bit sequence first length to a multiple of the number of the set of two or more parallel processors P .

19. The method for a cyclic redundancy check (CRC) of claim 16, wherein, The number of rows in the CRC generator matrix stored in the LUT is equal to or exceeds the maximum supported input bit sequence length divided by K max ) minus one P wherein P is the number of two or more parallel processors.

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