Feedback convergence method and device for optimizing incentive constraint files

Abstract

The present invention discloses a feedback convergence method and device for optimizing stimulus constraint files, which are applied to chip verification test. After the verification environment is built on the verification platform, the method includes: no constraint restrictions are imposed on the stimulus generator, but stimulus is randomly generated; in the functional test, the first stimulus combination in the case of test error is recorded and saved; according to the received input information, the second stimulus combination that needs to be set with constraint restrictions is screened out from the first stimulus combination, and the second stimulus combination is merged into a stimulus set; the input information is tested and analyzed by the test analyst and then input into the verification platform; the constraint of the stimulus generator is modified according to the stimulus set. The device and method can solve the problems of insufficient verification reliability or large test workload in the existing chip functional test in the prior art.

Description

Technical Field

[0001] The invention relates to chip testing technology, and in particular to a feedback convergence method and device for optimizing a stimulus constraint file. Background Art

[0002] In the current chip function verification, complex module verification is often encountered. This complexity is not reflected in the module scale or the complexity of the internal logic, but in the difficulty of constructing the previous module excitation. When the constraints of the excitation become complex to a certain extent, it is a test for the construction of the verification environment and the completeness of the verification.

[0003] Chip verifiers who perform module verification need to build a verification environment based on the good design specifications provided by the architects and the register transfer level (RTL) code of the module provided by the designers, use abstract language to build a reference model, simulate and generate stimuli, and check whether the functions of the current module meet expectations. As the complexity of the design increases, the workload and difficulty of functional verification increase by orders of magnitude. Verification engineers build complex reference models and stimulus generators with complex constraints on the verification environment, send stimuli to the reference model and RTL code module, and check the functions of the corresponding chip specifications by comparing the output results of the reference model and the RTL code module.

[0004] At present, in most cases, when functional verification encounters complex constraints, there are generally two solutions:

[0005] (1) When the verification personnel read the design specification of the module, they found that the incentive constraints of this module were complex and needed to carefully study the functional specifications and constantly confirm the incentive constraints with the person who formulated the design specifications and the designer of the previous module. Only then could they build the verification environment to construct incentives that met the constraints.

[0006] This process may last for several days or even weeks. During the simulation verification process, the excitations are randomly combined under constraints, which often leads to situations that were not considered when constructing the excitations. At this time, it is necessary to confirm with the person who sets the specifications whether constraints are needed in this case.

[0007] In modules with complex constraints, executing this solution often requires repeated reconfirmation of whether new stimulus combinations require constraints during the functional verification process. This is a challenge to the stability of the verification environment and there is also a risk that uncovered stimulus combinations will cause module functional errors.

[0008] (2) In this scheme, when the verification personnel read the design specification of the module, they found that the incentive constraints of this module were complex and the module had many internal functions. Generally, the internal design of the module would be divided into blocks according to functional relevance. During verification, the internal functional modules were split out and verified separately as sub-modules. When splitting the modules, the functional relevance was considered. The incentive constraints between different sub-modules were not considered. The incentives were randomly given to test whether the functions of some modules were met.

[0009] This solution is suitable for modules with many functions and clear internal divisions. It is difficult to deal with when the incentive constraints are harsh only because the functional logic is mutually constrained, and the functional divisions are unclear or not divided. In addition, this solution requires the construction of multiple sub-module environments, which reduces the complexity of incentive constraints, but the tasks of building the environment increase sharply, resulting in a longer time for verifying functions. The advantage of this solution is that all incentive coverage of each sub-module is verified separately to ensure coverage of boundary cases. The disadvantage is that the verification environment needs to be constructed multiple times, which increases the workload and is not suitable for modules with all complex constraints. Summary of the invention

[0010] The technical problem to be solved by the embodiments of the present invention is how to solve the problem of insufficient verification reliability or large testing workload in the existing chip function test in the prior art.

[0011] In order to solve the above-mentioned technical problems, an embodiment of the present invention provides a feedback convergence method for optimizing a stimulus constraint file, which is applied to a chip verification test. After the verification environment is built on a verification platform, the method further includes: randomly generating stimuli without imposing constraints on the stimulus generator; in functional testing, recording and saving a first stimulus combination in the event of a test error; based on received input information, screening out a second stimulus combination that requires constraint settings from the first stimulus combination, and merging the second stimulus combination into a stimulus set; the input information is tested and analyzed by a test analyst and then input into the verification platform; and modifying the constraints of the stimulus generator according to the stimulus set.

[0012] The above feedback convergence method for optimizing the stimulus constraint file, wherein, after modifying the constraints of the stimulus generator according to the stimulus set, further comprises: in the subsequent verification simulation process, the stimulus generator does not send the second stimulus combination in the stimulus set.

[0013] The above-mentioned feedback convergence method for optimizing the excitation constraint file, wherein the first excitation combination includes the excitation combination of different interfaces and the combination of different data fields of the same interface bus signal; the combination of different data fields includes: the combination of different excitation signals, the combination of values ​​of each field under the excitation being a bus signal, and the combination of signal values ​​under the excitation being a mixed signal type.

[0014] The above-mentioned feedback convergence method for optimizing the stimulus constraint file, wherein, after recording and saving the first stimulus combination in the case of a test error, it also includes: generating an error information coverage report, and displaying the information of the first stimulus combination through a visual interface, and providing an option to determine whether constraints are required.

[0015] In the above feedback convergence method for optimizing the stimulus constraint file, the input information is the selection input of the option for determining whether a constraint is required by the test analyst on the visual interface.

[0016] In order to solve the above-mentioned technical problems, an embodiment of the present invention also provides a feedback convergence device for optimizing stimulus constraint files, which is applied to chip verification tests. After the verification environment is built on the verification platform, it includes: a setting unit, which is used to randomly generate stimuli without imposing constraints on the stimulus generator; a recording unit, which is used to record and save the first stimulus combination in the event of a test error in the functional test; a processing unit, which is used to screen out the second stimulus combination that needs to set constraints from the first stimulus combination based on the received input information, and merge the second stimulus combination into a stimulus set; the input information is input into the verification platform after being tested and analyzed by the test analyst; and a control unit, which is used to modify the constraints of the stimulus generator according to the stimulus set.

[0017] In the above-mentioned feedback convergence device for optimizing the stimulus constraint file, the control unit is further used to control the stimulus generator not to send the second stimulus combination in the stimulus set during the subsequent verification simulation process.

[0018] The above-mentioned feedback convergence device for optimizing the excitation constraint file, wherein the first excitation combination includes the excitation combination of different interfaces and the combination of different data fields of the same interface bus signal; the combination of different data fields includes: a combination of different excitation signals, a combination of field values ​​under the excitation being a bus signal, and a combination of signal values ​​under the excitation being a mixed signal type.

[0019] The above-mentioned feedback convergence device for optimizing the stimulus constraint file also includes: a generation unit, which is used to generate an error information coverage report, and display the information of the first stimulus combination through a visual interface, and provide an option to determine whether constraints are required.

[0020] In the above-mentioned feedback convergence device for optimizing the stimulus constraint file, the input information is the selection input of the option for judging whether constraints are needed by the test analyst on the visual interface.

[0021] The present invention aims at the problems in the prior art. First, the stimulus generator is not constrained, but the stimulus is randomly generated, so as to reduce the difficulty of constructing the stimulus generator for modules with complex stimuli, and reduce the untested abnormalities that may be caused by unconsidered constraints. At the same time, by screening out the second stimulus combination that needs to be set with constraints for the first stimulus combination in the case of test errors, the constraints on the stimulus are changed from the existing manual confirmation to manual confirmation assisted by machine screening, which reduces the risk of stimulus errors or too small a range of stimulus, and improves the reliability of verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic diagram of a flow chart of Embodiment 1 of the present invention;

[0023] Figure 2 is a schematic diagram of different excitation signal combinations in Example 1 of the present invention;

[0024] Figure 3 It is a schematic diagram of the value combination of each field when the stimulus is a bus signal in Embodiment 1 of the present invention;

[0025] Figure 4 It is a schematic diagram of signal value combinations when the excitation is a mixed signal type in Example 1 of the present invention. DETAILED DESCRIPTION

[0026] At present, in most cases, when functional verification encounters complex constraints, there are generally two solutions:

[0027] (1) When the verification personnel read the design specification of the module, they find that the stimulus constraints of this module are complex and need to carefully study the functional specifications and constantly confirm the stimulus constraints with the person who formulated the design specifications and the designer of the previous module. Only then can the verification environment be built to construct the stimulus that meets the constraints. This process may last for several days or even weeks. During the simulation verification process, the stimulus is often randomly combined under the constraints, resulting in situations that were not considered when constructing the stimulus. At this time, it is necessary to confirm with the person who formulated the specifications whether constraints are required in this case. In a module with complex constraints, executing with this solution often requires repeated reconfirmation of whether new stimulus combinations require constraints during the functional verification process. This is a challenge to the stability of the verification environment, and there is also a risk that module functions may fail due to uncovered stimulus combinations.

[0028] (2) In this scheme, when the verification personnel read the design specification of the module, they found that the incentive constraints of this module were complex and the module had many internal functions. Generally, the internal design of the module would be divided into blocks according to functional relevance. During verification, the internal functional modules were split out and verified separately as sub-modules. When splitting the modules, the functional relevance was considered. The incentive constraints between different sub-modules were not considered. The incentives were randomly given to test whether the functions of some modules were satisfied. This scheme is suitable for modules with many functions and clear internal blocks. If the incentive constraints are harsh only because the functional logic is mutually constrained, and the functional blocks are unclear or not divided, it will be difficult to deal with. In addition, this scheme requires the construction of multiple sub-module environments, which reduces the complexity of the incentive constraints, but the tasks of setting up the environment increase sharply, resulting in a longer time for verifying the function. The advantage of this scheme is that all incentive coverage of each sub-module is verified separately to ensure the coverage of boundary cases. The disadvantage is that the verification environment needs to be constructed multiple times, which increases the workload and is not suitable for all modules with complex constraints.

[0029] The present invention aims at the problems in the prior art. First, the stimulus generator is not constrained, but the stimulus is randomly generated, so as to reduce the difficulty of constructing the stimulus generator for modules with complex stimuli, and reduce the untested abnormalities that may be caused by unconsidered constraints. At the same time, by screening out the second stimulus combination that needs to be set with constraints for the first stimulus combination in the case of test errors, the constraints on the stimulus are changed from the existing manual confirmation to manual confirmation assisted by machine screening, which reduces the risk of stimulus errors or too small a range of stimulus, and improves the reliability of verification.

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] Example 1

[0032] A feedback convergence method for optimizing a stimulus constraint file according to an embodiment of the present invention can be applied to chip verification testing. Figure 1 As shown, compared with the verification test of the prior art, the embodiment of the present invention further includes the following steps after the verification platform completes the construction of the verification environment (i.e., understanding the functions according to the design specifications, building a suitable verification environment, establishing a correct reference model, checker, and basic stimulus generator):

[0033] Step S101, without any restriction on the stimulus generator, randomly generating stimulus;

[0034] Stimulus refers to the input signal of the module under test simulated in module-level verification. In the verification platform, the stimulus is sent to the module under test and the reference model at the same time. Generally speaking, the stimulus of the current module is the output signal of the previous module. This embodiment does not impose any constraints on the stimulus generator, but randomly generates stimulus and sends it to the module under test and the reference model.

[0035] Step S102, recording and saving the first stimulus combination in the case of a test error;

[0036] By running different test cases to cover each line of code and perform functional testing under different conditions, a wide range of regression testing is completed. All stimulus combination information in the event of a test error is recorded as the first stimulus combination.

[0037] The first stimulus combination recorded as error information mainly records the stimulus combination generated by random stimulus during functional testing. The stimulus combination here not only includes the stimulus of different interfaces, but also includes the combination of different data fields under the same interface bus signal. This embodiment uses tools such as collecting coverage and testing whether the function code is covered, etc., to summarize and report a group of signal combinations. Specifically, error information may include three situations, as described below:

[0038] (1) Figure 2 As shown in the figure, there are different combinations of excitation signals. Taking excitation a, b, c, d, and e as an example, after the test, in the error information collection report, the excitation combinations that cause module errors are listed as shown in Table 1 below.

[0039] a b c d e 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1

[0040] Table 1

[0041] (2) Figure 3 As shown in the figure, the stimulus is the value combination of each field under the bus signal. Taking signal A as an example, the 32-bit bus is divided into five fields: a, b, c, d, and e. After the test, in the error information collection report, the stimulus combination that causes the module error is listed in the error information collection report as shown in Table 2 below.

[0042] A_a[7:0] A_b[7:0] A_c[7:0] A_d[3:0] A_e[3:0] 8’b10111111 8’b10101010 8’b10101010 4’b1111 4’b1111 8’b11100000 8’b10101010 8’b10101010 4’b1111 4’b0000 8’b11111111 8’b10101010 8’b10101010 4’b0000 4’b1111

[0043] Table 2

[0044] (3) Figure 4 As shown in the figure, it is a signal value combination when the stimulus is a mixed signal type. Take bus signal A and single-bit signals a, b, c as an example, where the width of bus signal A is 8 bits. After the test, all signal value combinations that cause errors in the module are listed in the error information collection report as shown in Table 3 below.

[0045] a b c A_d[3:0] A_e[3:0] 0 1 1 4’b1111 4’b1111 1 1 0 4’b1111 4’b0000 1 1 1 4’b0000 4’b1111

[0046] Table 3

[0047] Afterwards, the verification platform will collect and save the first stimulus combinations of the error information. According to the stimulus combination situation, the first stimulus combinations that cause the functional test to fail will be screened out and summarized and saved in the form of a database.

[0048] Step S103, generating an error information coverage report and displaying an option of whether it is a constraint;

[0049] After completing the functional test, the platform generates a report on error information coverage, and can display the relevant information of the first stimulus combination stored in step S102 through a visual interface, and provide an option to determine whether it is a constraint (e.g., whether it is a constraint? Y / N). Through step S103, this embodiment transforms the combination of collected input stimuli based on the tool for collecting coverage, and then collects the erroneous combinations, summarizes them in the form of a report, and feeds them back to the verification personnel, designers, and specification function developers, who judge whether the erroneous stimulus combination needs to be constrained.

[0050] Step S104, selecting a second incentive combination that needs to be set with constraints from the first incentive combination according to the received input information;

[0051] In the test practice, the verification personnel, designers, specification developers and other related personnel will discuss the generated error information coverage report to confirm whether each stimulus combination information that causes errors is because the constraints cannot appear, but the random stimulus is covered, thus causing the test failure. If it is confirmed that the test failure is not caused by the lack of constraints, then the verification personnel will follow up to further analyze the cause; if the test fails because the constraints are required but not set, then the option "Is it constrained? Y" will be selected in the above visual interface.

[0052] At this time, the platform screens out the second incentive combination that needs to be constrained from the first incentive combination based on the input information received from the above-mentioned verifier, and the second incentive combination that is confirmed to need constraints will be included in a new data set.

[0053] Step S105: modifying the constraints of the stimulus generator according to the stimulus set.

[0054] According to the stimulus data set generated in step S104, the constraints of the stimulus generator are modified. In this way, after the evaluation and screening of the erroneous stimulus combination, the constraints that need to be added after evaluation are imported into the stimulus constraint database. In this way, in the subsequent verification simulation process, the newly generated stimulus will be restricted by this constraint database, and the stimulus generator will not send the second stimulus combination in the stimulus set.

[0055] The following description is made by taking the different excitation signal combinations in Table 1 as an example:

[0056] a b c d e Is it constrained? 0 1 1 1 1 Y

[0057] The error combination is shown in the table above. The data is imported into the database of stimulus constraints to generate code, and the following code is constrained: (a!=0)&&(b!=1)&&(c!=1)&&(d!=1)&&(e!=1). The generated stimulus is controlled by the constraint conditions, and this stimulus signal combination will not appear.

[0058] A feedback convergence method for optimizing a stimulus constraint file according to an embodiment of the present invention is applicable not only to module verification of complex stimuli in the early stage of functional verification, but also to checking the rationality of stimuli in the later stage of verification. If you want to check the constraints of the stimuli at the end of verification to ensure that there are no missing combinations due to too many stimuli constraints, you can use this solution to collect simulated stimulus combination information and evaluate uncovered stimulus combinations to verify the rationality of the stimuli constraints.

[0059] Example 2

[0060] In order to solve the problems in the prior art, the present embodiment also discloses a feedback convergence device for optimizing the stimulus constraint file, which is applied to chip verification testing. After the verification platform completes the construction of the verification environment, it includes: a setting unit, which is used to randomly generate stimuli without imposing constraints on the stimulus generator; a recording unit, which is used to record and save the first stimulus combination in the case of a test error in the functional test; a processing unit, which is used to screen out the second stimulus combination that needs to set constraints from the first stimulus combination according to the received input information, and merge the second stimulus combination into a stimulus set; the input information is input into the verification platform after being tested and analyzed by the test analyst; and a control unit is used to modify the constraints of the stimulus generator according to the stimulus set.

[0061] In a specific implementation, the control unit is further configured to control the stimulus generator not to send the second stimulus combination in the stimulus set during a subsequent verification simulation process.

[0062] In a specific implementation, the first excitation combination includes an excitation combination of different interfaces and a combination of different data fields of the same interface bus signal; the combination of different data fields includes: a combination of different excitation signals, a combination of field values ​​under the excitation being a bus signal, and a combination of signal values ​​under the excitation being a mixed signal type.

[0063] In a specific implementation, the feedback convergence device for optimizing the stimulus constraint file further includes: a generation unit for generating an error information coverage report, displaying the information of the first stimulus combination through a visual interface, and providing an option for determining whether constraints are required.

[0064] In a specific implementation, the input information is the selection input of the option for determining whether a constraint is required by the test analyst on the visual interface.

[0065] Those skilled in the art can understand that the feedback convergence device for optimizing the incentive constraint file in the second embodiment and the feedback convergence method for optimizing the incentive constraint file in the first embodiment are based on the same inventive concept, so the contents of the relevant embodiments can be referred to the corresponding contents in the previous text and will not be repeated here.

[0066] A person skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, which can include: ROM, RAM, disk or CD, etc.

[0067] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A feedback convergence method for optimizing a stimulus constraint file, applied to chip verification testing, after the verification environment is built on the verification platform, is characterized in that: Also includes: No constraints are imposed on the stimulus generator, and the stimulus is generated randomly; In the functional test, the first stimulus combination in the case of a test error is recorded and saved, wherein the first stimulus combination includes a stimulus combination of different interfaces and a combination of different data fields of a bus signal of the same interface; the combination of different data fields includes: a combination of different stimulus signals, a combination of values ​​of each field under the stimulus being a bus signal, and a combination of signal values ​​under the stimulus being a mixed signal type; According to the received input information, a second stimulus combination that needs to be set with constraints is selected from the first stimulus combination, and the second stimulus combination is merged into a stimulus set; the input information is tested and analyzed by a test analyst and then input into a verification platform; Constraints of the stimulus generator are modified according to the set of stimuli.

2. The feedback convergence method for optimizing the incentive constraint file according to claim 1, characterized in that: After modifying the constraint of the stimulus generator according to the stimulus set, the method further includes: in a subsequent verification simulation process, the stimulus generator does not send a second stimulus combination in the stimulus set.

3. The feedback convergence method for optimizing the incentive constraint file according to claim 1, characterized in that: After recording and saving the first stimulus combination in the case of a test error, the method further includes: An error information coverage report is generated, and the information of the first stimulus combination is displayed through a visual interface, and an option for determining whether constraints are required is provided.

4. The feedback convergence method for optimizing the incentive constraint file according to claim 3, characterized in that: The input information is the selection input of the test analyst on the visual interface for determining whether a constraint is required.

5. A feedback convergence device for optimizing stimulus constraint files, applied to chip verification testing, after the verification environment is built on the verification platform, characterized in that: include: A setting unit is used for randomly generating excitation without placing any constraints on the excitation generator; A recording unit is used to record and save a first stimulus combination in a test error situation in a functional test, wherein the first stimulus combination includes a stimulus combination of different interfaces and a combination of different data fields of a bus signal of the same interface; the combination of different data fields includes: a combination of different stimulus signals, a combination of values ​​of each field under the stimulus being a bus signal, and a combination of signal values ​​under the stimulus being a mixed signal type; A processing unit, configured to screen out a second stimulus combination that needs to be set with constraints from the first stimulus combination according to the received input information, and merge the second stimulus combination into a stimulus set; the input information is input into the verification platform after being tested and analyzed by the test analyst; A control unit is used to modify the constraints of the stimulus generator according to the stimulus set.

6. The feedback convergence device for optimizing the incentive constraint file according to claim 5, characterized in that: The first stimulus combination includes a stimulus combination of different interfaces and a combination of different data fields of a same interface bus signal; The combination of different data fields includes: a combination of different excitation signals, a combination of values ​​of each field when the excitation is a bus signal, and a combination of signal values ​​when the excitation is a mixed signal type.

7. The feedback convergence device for optimizing the incentive constraint file according to claim 5, characterized in that: Also includes: A generating unit is used to generate an error information coverage report, and display the information of the first stimulus combination through a visual interface, and provide an option to determine whether constraints are required.

8. The feedback convergence device for optimizing the incentive constraint file according to claim 7, characterized in that: The input information is the selection input of the test analyst on the visual interface for determining whether a constraint is required.

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