Variable frequency display device

Abstract

A display device is provided. The display device includes a pixel connected to each of a first scan line, a second scan line, and a data line, a scan driver supplying a first scan signal to the first scan line and a second scan signal to the second scan line, a controller dividing one frame period into an active period and a blanking period and generating a count signal in which a duration of the blanking period is counted and a power control signal, a data driver supplying a data signal to the data line, and a power supply controlling a source driving voltage supplied to the data driver according to the duration of the blanking period based on the power control signal. When the count signal reaches a reference value, the controller supplies a start signal for outputting the first scan signal to the scan driver.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0126345, filed on September 28, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates generally to display devices, and more specifically to a display device capable of changing the driving frequency or frame rate. Background Technology

[0003] A display device may include pixel units containing multiple pixels and drivers for driving the pixels. The drivers display images in the pixel units using image signals applied from an external graphics processor.

[0004] The graphics processor generates image signals by rendering raw data, and the rendering time used to generate the image signal corresponding to a frame can vary depending on the type or characteristics of the image. The driver can adjust the frame rate based on the rendering time.

[0005] However, the number of times the light-emitting element is turned off per unit time (e.g., the number of times it is turned off) changes with the frame rate, and this change can be identified as a change in the brightness of the image and / or flickering. Summary of the Invention

[0006] Embodiments of this disclosure provide a display device that can insert an emit-off period for supplying a reference voltage to a driving transistor of a pixel into a blanking period, and can control the source driving voltage supplied to a data driver based on the duration of the blanking period.

[0007] Embodiments of this disclosure provide a display device that can insert an emitter shutdown period for supplying a reference voltage to a driving transistor of a pixel into a blanking period, and can control the source driving voltage and / or the reference voltage based on the duration of the blanking period.

[0008] It will be understood that the inventive concept is not limited to the embodiments set forth herein, and various extensions of the inventive concept may be made without departing from the spirit and scope of this disclosure.

[0009] Embodiments of this disclosure provide a display device comprising: pixels connected to a first scan line, a second scan line, and a data line; a scan driver supplying a first scan signal to the first scan line and a second scan signal to the second scan line; a controller dividing a frame period into an active period and a blanking period based on an externally provided control signal, and generating a count signal and a power control signal for counting the duration of the blanking period; a data driver supplying a data signal to the data line; and a power supply controlling a source drive voltage supplied to the data driver based on the power control signal according to the duration of the blanking period. When the count signal reaches a reference value, the controller can supply a start signal for outputting the first scan signal to the scan driver.

[0010] The reference value could be the duration of the first blanking period corresponding to the maximum frame rate sent to the display device.

[0011] When the frame rate detected based on the control signal is slower than the maximum frame rate, the blanking period can continuously include a first blanking period and a second blanking period. The scan driver can supply the first scan signal to the first scan line based on the start signal during a first period included in the second blanking period.

[0012] The second blanking period may include a continuous first period and a second period. A first-level source drive voltage may be supplied during the first blanking period and the first period, and when the supply of the first scan signal in the first period ends, the source drive voltage may change from the first level to a second level that is higher than the first level.

[0013] The power supply can gradually reduce the source drive voltage from the second level during the second time period, and the duration of the second blanking period can be less than or equal to the duration of the first blanking period.

[0014] The source drive voltage supplied during the effective period immediately following the second blanking period can be the same as the source drive voltage at the end of the second blanking period.

[0015] When the duration of the second blanking period is an integer multiple of the duration of the first blanking period, the source drive voltage supplied in the effective period immediately following the second blanking period can have a first level.

[0016] A pixel may include: a light-emitting element; a first transistor connected between a first driving power supply and the light-emitting element, and including a gate electrode connected to a first node; a second transistor connected between a data line and the first node, and including a gate electrode connected to a second scan line; a third transistor supplying a reference voltage to a second node in response to a first scan signal provided to its gate electrode, the first transistor and the light-emitting element being connected at the second node; and a storage capacitor connected between the first node and the light-emitting element.

[0017] The power supply can also control the reference voltage based on the power control signal.

[0018] The reference voltage of the third level can be supplied during the first blanking period and the first time period, and when the supply of the first scan signal in the first time period ends, the reference voltage can be changed from the third level to a fourth level that is lower than the third level.

[0019] The power supply can gradually increase the reference voltage from the fourth level during the second period, and the duration of the second blanking period can be less than or equal to the duration of the first blanking period.

[0020] The reference voltage supplied during the effective period immediately following the second blanking period can be the same as the reference voltage at the end of the second blanking period.

[0021] When the duration of the second blanking period is an integer multiple of the duration of the first blanking period, the reference voltage supplied during the effective period immediately following the second blanking period may have a third level.

[0022] The effective time period can include the scanning period, during which data signals are written to pixels by turning on the second and third transistors.

[0023] The controller may include: a frame rate detector that detects the frame rate based on a frame rate variable signal and generates a counting signal; a voltage controller that controls the source drive voltage and the reference voltage of the source electrode of the drive transistor supplied to the pixel in response to the counting signal; and a scan controller that outputs a start signal in response to the counting signal.

[0024] Embodiments of this disclosure provide a display device comprising: a pixel connected to a first scan line, a second scan line, and a data line, and including a first transistor that generates a driving current for emitting light; a scan driver that supplies a first scan signal to the first scan line and a second scan signal to the second scan line; a controller that divides a frame period into an active period and a blanking period based on an externally supplied control signal, and generates a count signal and a power control signal therein for counting the duration of the blanking period; a data driver that supplies a data signal to the data line; and a power supply that controls a reference voltage supplied to the source electrode of the first transistor based on the power control signal according to the duration of the blanking period. When the count signal reaches a reference value, the scan driver can output the first scan signal during the blanking period.

[0025] The reference value can be the duration of the first blanking period corresponding to the maximum frame rate set in the display device.

[0026] When the frame rate detected based on the control signal is slower than the maximum frame rate, the blanking period may include a continuous first blanking period and a second blanking period, and the scan driver may supply the first scan signal to the first scan line during the first period included in the second blanking period.

[0027] The second blanking period may include a continuous first period and a second period. A first level reference voltage may be supplied during the first blanking period and the first period, and when the supply of the first scan signal in the first period ends, the reference voltage may change from the first level to a second level that is lower than the first level.

[0028] The power supply can gradually increase the reference voltage from the second level during the second time period, and the reference voltage supplied during the effective time period immediately following the second blanking period can be the same as the reference voltage at the end of the second blanking period.

[0029] In the display device according to this embodiment of the present disclosure, since a transmit shutdown period is additionally inserted during the blanking period based on the change in frame rate without frame delay, brightness flicker caused by the change in drive frequency (frame rate) can be controlled.

[0030] Furthermore, to compensate for the brightness degradation caused by the increased number of times the light-emitting element is turned off and the insertion of emission-off periods during the blanking period, the voltage difference between the source drive voltage and the reference voltage can be controlled (e.g., increased) according to the duration of the blanking period. Therefore, the gate-source voltage of the first transistor increases during the active period (or display period) to increase the brightness of the light-emitting element, and the average brightness at any frame rate can be similar to the average brightness at the maximum frame rate.

[0031] Therefore, since brightness control for a frame is performed in real time through the counting of blanking periods, the insertion of transmit shutdown periods, source drive voltage control, and / or reference voltage control, even under any frame rate variation, the average brightness in variable frequency drive can be stabilized and image quality can be controlled.

[0032] Embodiments of this disclosure provide a display device comprising: a plurality of pixels, each connected to a power line, a data line, and a scan line; a controller configured to divide each of a plurality of variable frequency frame periods into a corresponding active period and a corresponding blanking period, determine the duration of at least one of the corresponding active period and the corresponding blanking period, and provide a scan control output, a data control output, and a power control output based on the determined duration; a scan driver connected to the scan control output and configured to supply a scan signal to the scan line; a data driver connected to the data control output and configured to supply a data signal to the data line; and a power supply configured to change at least one variable supply voltage for at least one of the data driver and the scan driver based on the power control output.

[0033] The variable supply voltage may include at least one variable gate level voltage connected to a scan driver, which controls at least one of the gate on-level and gate off-level of a scan signal based on a determined duration. The variable supply voltage may include at least one variable output connected to the scan driver, which controls the timing of scan signals supplied to scan lines during a corresponding blanking period based on a determined duration. The variable supply voltage may include at least one variable output connected to the scan driver, which individually controls the timing of first and second scan signals supplied to first and second scan lines of the same pixel during a corresponding blanking period based on a determined duration. The variable supply voltage may include at least one variable source drive voltage connected to a data driver and at least one of a plurality of pixels, which controls a data signal based on a determined duration. The variable supply voltage may include at least one variable reference voltage connected to the source electrodes of the plurality of pixels and the driving transistors based on a determined duration.

[0034] However, the effects of the embodiments are not limited to those described herein, and various extensions can be made in alternative embodiments without departing from the spirit and scope of this disclosure. Attached Figure Description

[0035] Figure 1 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0036] Figure 2It is a signal timing diagram used to drive a display device based on an image signal supplied from an external source.

[0037] Figure 3 Is included Figure 1 The circuit diagram of the pixels in the display device.

[0038] Figure 4 yes Figure 3 The signal timing diagram for the operation of pixels.

[0039] Figure 5 This is a timing diagram of the signal causing the brightness change of the image due to the frame rate.

[0040] Figure 6 yes Figure 1 The signal timing diagram of the display device operating at maximum frame rate.

[0041] Figure 7 yes Figure 1 The signal timing diagram for the operation of the display device.

[0042] Figure 8 yes Figure 1 The signal timing diagram for the operation of the display device.

[0043] Figure 9 yes Figure 1 The signal timing diagram for the operation of the display device.

[0044] Figure 10 Is included Figure 1 A block diagram of a portion of the data driver in a display device.

[0045] Figure 11 yes Figure 1 The signal timing diagram for the operation of the display device.

[0046] Figure 12 yes Figure 1 A block diagram of a portion of a display device.

[0047] Figure 13 yes Figure 1 A block diagram of the controller for the display device.

[0048] Figure 14 yes Figure 13 Block diagram of the control signal generator.

[0049] Figure 15A yes Figure 1 The signal timing diagram for the operation of the display device.

[0050] Figure 15B yes Figure 1 The signal timing diagram for the operation of the display device.

[0051] Figure 16 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0052] Figure 17 Is included Figure 16 The circuit diagram of the pixels in the display device. Detailed Implementation

[0053] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same or identical reference numerals may be used for the same or identical components in the drawings, and substantially repetitive descriptions of the same or identical components may be omitted.

[0054] Figure 1 A display device according to an embodiment of the present disclosure is shown.

[0055] Reference Figure 1 The display device 1000 may include pixel units 100, scan drivers 200, data drivers 300, power supplies 400, and controllers 500. Each of the drivers and controllers may be implemented as one or more circuits. Optionally, one or more of the drivers and controllers may be combined in an integrated circuit.

[0056] Display device 1000 can be a flat panel display device, a flexible display device, a curved display device, a foldable display device, a bendable display device, and / or a stretchable display device. Furthermore, display device 1000 can be applied to transparent display devices, head-mounted display devices, wearable display devices, etc. Additionally, display device 1000 can be applied to various electronic devices (such as smartphones, tablets, smart tablets, TVs, or monitors).

[0057] The display device 1000 can be implemented as a self-emissive display device including multiple self-emissive elements. For example, the display device 1000 can be an organic light-emitting diode display including organic light-emitting elements, a display device including inorganic light-emitting elements, or a display device including light-emitting elements made of a combination of inorganic and organic materials. However, this is exemplary, and the display device 1000 can also be implemented as a liquid crystal display device, a plasma display device, a quantum dot display device, etc.

[0058] In an embodiment, the display device 1000 can be driven during a period divided into an effective time period for displaying an image (e.g., a display time period) and a blanking time period with a duration that changes with the frame rate (e.g., frame frequency). The duration of the blanking time period can be adjusted to control the difference between the timing of frame information supplied from an external host system (e.g., a graphics processor, application processor, etc.) and the timing of the image frames output by the display device 1000.

[0059] In an embodiment, the display device 1000 may further include a sensing circuit (e.g., Figure 16 In the data driver 300 (600), the sensing circuit is used to calculate the characteristics from pixel PX and generate its compensation value. For example, at least some components or functions of the sensing circuit can be integrated into the data driver 300.

[0060] The pixel unit 100 includes a pixel PX connected to a data line DL, a first scan line SL1, and a second scan line SL2.

[0061] The pixel PX can be supplied with the voltage of the first driving power supply VDD, the voltage of the second driving power supply VSS, and the reference voltage or initialization voltage Vint.

[0062] exist Figure 1 In the diagram, the first scan line SL1 and the second scan line SL2 are shown connected to pixel PX, but this disclosure is not limited thereto. For example, corresponding to the circuit structure of pixel PX, one or more of the control line, scan line, and sensing line may be additionally formed in pixel unit 100.

[0063] In an embodiment, the transistor included in the pixel PX may be an N-type oxide thin-film transistor. For example, the oxide thin-film transistor may be a low-temperature polycrystalline oxide (LTPO) thin-film transistor. However, this is merely an example, and the transistor is not limited thereto. For example, the active pattern or semiconductor layer included in the transistor may include inorganic semiconductors (e.g., amorphous silicon or polycrystalline silicon) or organic semiconductors. Furthermore, at least one of the transistors included in the display device 1000 may be replaced by a P-type transistor.

[0064] The controller 500 can generate a data control signal DCS, a scan control signal SCS, and a power control signal PCS in response to a control signal CTL supplied from an external source. The data control signal DCS generated by the controller 500 can be supplied to the data driver 300, the scan control signal SCS can be supplied to the scan driver 200, and the power control signal PCS can be supplied to the power supply 400.

[0065] In addition, the controller 500 can supply image data DAT to the data driver 300, in which the externally supplied image signal RGB is rearranged.

[0066] The Data Control System (DCS) can include a source start signal and a data clock signal. The source start signal controls the starting point for image data sampling. The data clock signal is used to control the sampling operation.

[0067] The scan control signal SCS can include a start signal and a scan clock signal. The start signal controls the timing of the scan signals. The scan clock signal can be used as the shift start signal.

[0068] The power control signal PCS can control the voltage levels and / or supply timing of the reference voltage Vint and the source drive voltage AVDD. The power control signal PCS can also control the voltage level and / or supply timing of the first drive power supply VDD and the second drive power supply VSS. Furthermore, the power control signal PCS can control the voltage levels of the gate on-state voltage and / or gate off-state voltage that determine the gate on-state and / or gate off-state of the scan signal.

[0069] In this embodiment, the controller 500 can divide a frame period into an active period and a blanking period based on the control signal CTL. The controller 500 can count the elapsed time of the blanking period and generate a counting signal. The controller 500 can generate a power control signal PCS based on the counting signal.

[0070] In addition, the controller 500 can supply a start signal to the scan driver 200 based on the counting signal, and the start signal is used to supply the output of the first scan signal to the first scan line SL1.

[0071] The scan driver 200 can receive a scan control signal SCS from the controller 500. The scan driver 200, supplied with the scan control signal SCS, can supply a first scan signal to the first scan line SL1 and a second scan signal to the second scan line SL2.

[0072] For example, scan driver 200 can sequentially supply a first scan signal to a first scan line SL1. The first scan signal can be set to a gate on-state voltage (e.g., a logic high level) such that transistors included in pixel PX can be turned on. The first scan signal can be used to sense or extract the drive current flowing through pixel PX (e.g., the current flowing through the drive transistor) or to apply a reference voltage Vint to pixel PX.

[0073] Similarly, the scan driver 200 can supply a second scan signal to the second scan line SL2. The second scan signal can be used to apply a data signal DS to pixel PX.

[0074] The timing and waveforms of the first and second scan signals can be set differently depending on the effective time period, the sensing time period, and the blanking time period.

[0075] although Figure 1The diagram illustrates a scan driver 200 that outputs both a first scan signal and a second scan signal, but this disclosure is not limited thereto. For example, the scan driver 200 may include a first scan driver for supplying a first scan signal to the pixel unit 100 and a second scan driver for supplying a second scan signal to the pixel unit 100 (see [link to documentation]). Figure 12 In other words, the first scan driver and the second scan driver can be implemented independently.

[0076] The data driver 300 can receive a data control signal DCS from the controller 500. The data driver 300 can supply a data signal DS (e.g., a data voltage) to the pixel unit 100 during each valid time period in a pixel PX within a frame period. The data signal can be a data voltage (such as a voltage corresponding to image data DAT) used to display a valid image.

[0077] As described above, in this embodiment, the data driver 300 may include the functionality of a sensing circuit. For example, current or voltage extracted from the pixel PX during a sensing period can be supplied to the data driver 300 via a data line DL. The sensing circuit included in the data driver 300 calculates characteristics (e.g., mobility characteristics, threshold voltage characteristics, degradation characteristics, etc.) of the light-emitting elements and / or driving transistors included in the pixel PX based on the extracted current and / or voltage. That is, Figure 16 The SSL function of the sensing line can be performed via the DL data line.

[0078] Image data DAT and / or data signals can be controlled, compensated, or altered based on computational characteristics.

[0079] Power supply 400 can supply a reference voltage Vint to pixel PX via predetermined power lines based on power control signal PCS. In an embodiment, the power lines can be commonly connected to all pixel PXs. For example, the power lines can be superimposed with pixel units 100 that will be patterned in the display panel. Alternatively, the power lines can be connected to each of the pixel PXs in predetermined pixel row units, pixel column units, or pixel block units. Power supply 400 can supply a first driving power supply VDD and a second driving power supply VSS to pixel unit 100 as driving power for pixel PX.

[0080] Furthermore, power supply 400 can supply a source drive voltage AVDD to data driver 300. The source drive voltage AVDD can be supplied to data driver 300 to generate gamma voltages (e.g., grayscale voltages). Gamma voltages are voltages corresponding to data signals and are analog voltages. Data driver 300 can divide the source drive voltage AVDD to generate multiple gamma voltages.

[0081] Figure 2An example of a display device driven by an image signal supplied from an external source is shown.

[0082] Reference Figure 1 and Figure 2 The RGB image signal supplied from an external source can be a signal rendered by a graphics processor or similar device. The frame rate of the RGB image signal can be changed based on the rendering time of the graphics processor.

[0083] In the following description, frame rate refers to the frame frequency (such as the number of frames transmitted per second, measured in frames per second). The faster the frame rate, the shorter the duration of a frame and the shorter the uncompensated blanking period, while the slower the frame rate, the longer the duration of a frame and the longer the uncompensated blanking period.

[0084] In this embodiment, the frame rate of the display device 1000 can also be changed when the frame rate of the image signal RGB changes according to the rendering time of the graphics processor.

[0085] The image signal RGB can be processed by the controller 500 and then delayed by one frame to be output as a data signal DS or a data voltage. In an embodiment, the data signal DS can be output based on a data enable signal DE supplied from the controller 500.

[0086] The frame rate of the display device 1000 can be the same as the frame rate of a frame (e.g., the immediately preceding frame) of the image signal RGB received from the outside, which is delayed by one (1) frame. For example, the frame rate of frame Fa of the data signal DS "A" output to the display device 1000 can be the same as the frame rate of frame F2 of the image signal RGB "B" received. The frame rate of frame Fb of the data signal DS "B" output to the display device 1000 can be the same as the frame rate of frame F3 of the image signal RGB "C" received.

[0087] A frame of the display device 1000 may include a valid period and a blanking period for the output data signal DS. In each of frames Fa, Fb, Fc, and Fd, the durations of the valid periods APa, APb, APc, and APd for the output data signals DS “A”, “B”, “C”, and “D” may be the same, but are not limited to this. In an embodiment, each of the valid periods APa, APb, APc, and APd may include a scan period in which the data signal DS is written to pixel PX.

[0088] The durations of blanking periods BPa, BPb, BPc, and BPd can be controlled, compensated, or changed based on the difference between the frame rate and / or duration of each of frames Fa, Fb, Fc, and Fd and the frame rate and / or duration of each corresponding effective time period APa, APb, APc, and APd.

[0089] exist Figure 2 In the example shown, since the frame rate of frame Fa of the output data signal DS “A” is slower (i.e., longer in duration) than the frame rate of frame Fb of the output data signal DS “B”, the duration of blanking period BPa can be longer than the duration of blanking period BPb.

[0090] Thus, even if the frame rate or duration of the frames changes irregularly, since the duration of the blanking periods BPa, BPb, BPc and BPd of each of the frames Fa, Fb, Fc and Fd is controlled, image tearing caused by the difference between the frame generation of the graphics processor and the frame output of the display device 1000 and / or input lag in which a portion of the input frame disappears can be minimized.

[0091] However, due to the variation in the blanking period based on frame rate changes, brightness variations or flickering can be identified (see...). Figure 5 Therefore, the driving method used to control image quality can be applied to, for example... Figure 3 The pixel structure shown can be applied to, and can be used in, including Figure 4 Pixel-driven Figure 2 In the driving process, it can be called a free synchronization driver or a G synchronization driver.

[0092] Figure 3 It shows that it includes Figure 1 A circuit diagram of an example pixel in a display device. Figure 4 It shows Figure 3 A timing diagram showing examples of pixel operations.

[0093] exist Figure 3 and Figure 4 For better understanding and ease of description, a pixel PXij is shown positioned at the i-th horizontal line and connected to the j-th data line DLj. In the following text, the i-th first scan line SL1_i connected to pixel PXij can be described as the first scan line SL1_i, and the i-th second scan line SL2_i can be described as the second scan line SL2_i.

[0094] Reference Figure 3 and Figure 4 Pixel PXij may include a light-emitting element LD, a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0095] The first electrode (anode or cathode electrode) of the light-emitting element LD can be connected to the second node N2, and the second electrode (cathode or anode electrode) of the light-emitting element LD can be connected to the second driving power supply VSS. The light-emitting element LD can generate light of a predetermined brightness in response to the amount of current supplied from the first transistor T1 (e.g., the driving transistor).

[0096] In one embodiment, the light-emitting element LD can be an organic light-emitting diode including an organic light-emitting layer. In another embodiment, the light-emitting element LD can be an inorganic light-emitting element made of inorganic materials. In yet another embodiment, the light-emitting element LD can be a light-emitting element made of a composite of inorganic and organic materials. Optionally, the light-emitting element LD can have a form in which multiple inorganic light-emitting elements are connected in parallel and / or in series between the second driving power supply VSS and the second node N2.

[0097] In an embodiment, pixel PXij may further include a parasitic capacitor Cld for the light-emitting element LD. The voltage difference based on the drive current generated from the first transistor T1 can be stored in the parasitic capacitor Cld. Therefore, pixel PXij can emit light with relatively stable brightness during a frame.

[0098] The first electrode of the first transistor T1 can be connected to the first driving power supply VDD, and the second electrode of the first transistor T1 can be connected to the first electrode of the light-emitting element LD. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of current flowing in the light-emitting element LD in response to the voltage of the first node N1.

[0099] The first electrode of the second transistor T2 can be connected to the data line DLj, and the second electrode of the second transistor T2 can be connected to the first node N1. The gate electrode of the second transistor T2 can be connected to the second scan line SL2_i. When the second scan signal (e.g., the gate on level of the second scan signal) is supplied to the second scan line SL2_i, the second transistor T2 can be turned on to transmit the voltage of the data signal DSj from the data line DLj to the first node N1.

[0100] The third transistor T3 can be connected between the power line PL and the second electrode (e.g., the second node N2) of the first transistor T1. The gate electrode of the third transistor T3 can be connected to the first scan line SL1_i. When the first scan signal (e.g., the gate on level of the first scan signal) is supplied to the first scan line SL1_i, the third transistor T3 can be turned on to electrically connect the power line PL to the second node N2 (e.g., the second electrode of the first transistor T1 and the first electrode of the light-emitting element LD).

[0101] In this embodiment, when the third transistor T3 is turned on, a reference voltage Vint can be supplied to the second node N2 via the power line PL. The reference voltage Vint can be used to set or initialize the voltage of the second electrode (e.g., the source electrode) of the first transistor T1 to a predetermined value. Therefore, the reliability of the drive current generated from the first transistor T1 can be maximized.

[0102] Furthermore, the reference voltage Vint can be set to be less than or equal to the voltage of the second driving power supply VSS. Therefore, when the reference voltage Vint is supplied to the second node N2, the light-emitting element LD does not emit light (emission off). The reference voltage Vint can initialize the voltage stored in the parasitic capacitor Cld of the light-emitting element LD. When the data signal is supplied to the pixel PXij after the voltage stored in the parasitic capacitor Cld is initialized, the light-emitting element LD can emit light with a brightness corresponding to the data signal. In particular, it can maximize the color reproducibility of low grayscale emission.

[0103] In another embodiment, when the third transistor T3 is turned on, the current generated by the first transistor T1 can be supplied to the sensing circuit of the data driver 300 or the sensing circuit of the controller 500 through the sensing line (not shown).

[0104] A storage capacitor Cst can be connected between the first node N1 and the second node N2. The storage capacitor Cst can store the voltage corresponding to the voltage difference between the first node N1 and the second node N2.

[0105] In embodiments of this disclosure, the circuit structure of pixel PXij is not limited to... Figure 3 The circuit structure. For example, the light-emitting element LD can be disposed between the first driving power supply VDD and the first electrode of the first transistor T1. Furthermore, in Figure 3 In this diagram, transistors T1 to T3 are shown as NMOS, but this disclosure is not limited thereto. For example, at least one of transistors T1 to T3 may be formed as PMOS.

[0106] like Figure 4 As shown, the driving for each pixel PXij can be performed in the active time period AP and the blanking time period BP. The active time period AP can include the scan time period SP.

[0107] In an embodiment, when the display device 1000 is driven at a drive frequency slower than the maximum frame rate set in the display device 1000, the blanking period BP may include the transmit off period OFP.

[0108] The transmit off period (OFP) can be performed during the blanking period (BP). During the transmit off period (OFP), the first scan signal is supplied to the first scan line SL1_i, enabling the third transistor T3 to conduct. Therefore, the reference voltage Vint can be supplied to the second node N2.

[0109] In this case, the second scan signal is not supplied to the second scan line SL2_i (e.g., the second scan signal has a gate cutoff level), and the second transistor T2 is turned off.

[0110] When the reference voltage Vint is supplied to the second node N2, the light emission of the light-emitting element LD can be temporarily turned off. Therefore, the brightness of pixel PXij can be temporarily reduced. In this case, a current path can be formed through the first transistor T1 and the third transistor T3. In this embodiment, the reference voltage Vint can be less than or equal to the voltage of the second driving power supply VSS.

[0111] When the emitter off period (OFP) has elapsed, the current generated by the first transistor T1 is supplied to the light-emitting element LD, allowing the LD to emit light again. In this embodiment, the emitter off period (OFP) is a horizontal period or a shorter period, and the brightness after the emitter off period (OFP) can be similar to the brightness before the emitter off period (OFP).

[0112] Additionally, the transmit shutdown period OFP can be performed sequentially, pixel by pixel. However, this is just an example, and the transmit shutdown period OFP can be performed simultaneously for a predetermined number of pixel rows.

[0113] Subsequently, the data signal DSj is supplied to the pixel PXij during the effective period AP, and the light-emitting element LD can emit light with a brightness corresponding to the data signal DSj.

[0114] In this embodiment, the first scan signal and the second scan signal can be supplied to the first scan line SL1_i and the second scan line SL2_i respectively during the scan period SP of the effective time period AP. Furthermore, the data signal DSj can be supplied to the data line DLj during the scan period SP. Therefore, the second transistor T2 can be turned on to supply the voltage of the data signal DSj to the first node N1, and the third transistor T3 can be turned on to supply the reference voltage Vint to the second node N2.

[0115] Therefore, the voltage corresponding to the difference between the voltage of the data signal DSj and the reference voltage Vint can be stored in the storage capacitor Cst.

[0116] Since the reference voltage Vint is supplied to the second node N2 even during the scan period SP, the light emission of the light-emitting element LD can be temporarily turned off. In this case, a current path can be formed through the first transistor T1 and the third transistor T3. Therefore, the brightness of pixel PXij can be temporarily reduced.

[0117] In an embodiment, the scanning period SP can be performed sequentially in units of pixel rows, or it can be performed simultaneously for predetermined pixel rows.

[0118] After the scan period SP, the second transistor T2 and the third transistor T3 can be turned off. The light-emitting element LD can emit light with a brightness corresponding to the voltage stored in the storage capacitor Cst. During the effective period AP following the scan period SP, the effective image that will be substantially displayed in the corresponding frame can be displayed.

[0119] Figure 5 An example of how the brightness of an image changes according to the frame rate is shown.

[0120] Reference Figure 1 , Figure 2 , Figure 4 and Figure 5 For the same grayscale value, the brightness of a display device that displays an image using a variable frame rate driving method can change according to the change in frame rate.

[0121] During the scanning period SP of the effective period AP, the image can be displayed in black for a very short time because the light-emitting element LD does not emit light. Therefore, as Figure 5 As shown, the period in which the brightness decreases occurs, corresponding to this scanning period SP.

[0122] Figure 5 This illustrates the variation in brightness based on the frame rate during the same time period in a conventional frame rate-driven method. For example, at a frame rate of 120Hz, the scan period SP can be repeated 4 times during the same time period, at a frame rate of 90Hz, the scan period SP can be repeated 3 times during the same time period, and at a frame rate of 60Hz, the scan period SP can be repeated 2 times during the same time period.

[0123] As mentioned above, as the number of repetitions of the scan period SP increases, the average brightness for the same grayscale value decreases. That is, as... Figure 5 As shown, for the same grayscale value, the average brightness of a 120Hz frame rate drive can be lower than that of a 90Hz frame rate drive. Similarly, for the same grayscale value, the average brightness of a 90Hz frame rate drive can be lower than that of a 60Hz frame rate drive.

[0124] To control or minimize brightness deviation caused by the difference in frequency and / or duration between the scan period SP and the previous scan period, the display device 1000 and its driving method according to this embodiment of the present disclosure may insert an additional emit-off period OFP into the blanking period BP for driving at a frame rate lower than the maximum frame rate set in the display device 1000 (see, for example, the following). Figure 4 and Figure 7(etc.). In terms of brightness, since the scan period SP has a brightness degradation characteristic that is essentially equivalent to that of the transmit off period OFP, the scan period SP can also be substantially understood as a transmit off period OFP. Therefore, for various frame rates, the number of transmit off periods OFP included in the same time (e.g., the sum of the number of scan period SPs and the number of transmit off periods OFPs) can be similar to each other.

[0125] Figure 6 It shows Figure 1 An example of how a display device operates at its maximum frame rate. For example... Figure 6 As shown, each frame period may include an active period AP and a blanking period BP (i.e., the first blanking period BP1). Each active period AP may include a scan period SP and a display period DP.

[0126] Reference Figure 1 , Figure 3 and Figure 6 Under the driving condition of maximum frame rate (MFR), frames including the effective time period (AP) and the first blanking time period (BP1) can be repeated. In an embodiment, for example, Figure 6 This can be understood as a schematic illustration of the drive for a single pixel or a row of pixels.

[0127] The first blanking period BP1 can correspond to the maximum frame rate (MFR) set in the display device 1000. The maximum frame rate (MFR) can be determined by a protocol between the display device 1000 and an external graphics processor. For example, the maximum frame rate (MFR) can be set to 120Hz.

[0128] Furthermore, the first blanking period BP1 may correspond to the maximum frame rate MFR, and the blanking period of the display device 1000 may not be shorter than the first blanking period BP1.

[0129] Embodiments of this disclosure provide a display device 1000 having: a plurality of pixels PX, each connected to a power line (e.g., a line supplying VDD, VSS, and / or Vint), a data line DL, and scan lines SL1 and / or SL2; a controller 500 configured to divide each of a plurality of variable frequency frame periods into a corresponding active time period AP and a corresponding blanking time period BP, determine the duration of at least one of the corresponding time periods, and provide a scan control output (i.e., scan control signal) SCS, a data control output (i.e., data control signal) DCS, and a power control output (i.e., power control signal) PCS based on the determined duration; and scan drivers 200 or 220 and 240 (see Figure 12A scan driver 300, connected to a scan control output SCS and configured to supply scan signals to scan lines SL1 and / or SL2; a data driver 300, connected to a data control output DCS and configured to supply data signals to data lines DL; and a power supply 400, configured to change at least one variable supply voltage for at least one of the data driver 300 and the scan driver 200 based on a power control output PCS. In an embodiment, the effective time period AP may include a scan time period SP and a display time period DP.

[0130] The controller 500 can count the duration of the first blanking period BP1 to generate a counting signal. The controller 500 can detect the duration of the first blanking period BP1 by counting the number of clock cycles supplied during the first blanking period BP1.

[0131] In an embodiment, when the count value included in the counting signal reaches a reference value, the controller 500 can supply a start signal for outputting a first scan signal to the scan driver 200. Here, the reference value can be the duration of the first blanking period BP1. Therefore, when the display device 1000 is driven at the maximum frame rate MFR and when the blanking period (e.g., the first blanking period BP1) ends, a scan period SP can be executed. During the scan period SP, the parameters related to the reference value can be executed. Figure 3 and Figure 4 The operation described is the same as the operation of SP during the scan period.

[0132] The data signal DSj can be written to pixel PXij through the operation of the scan period SP, and the light-emitting element LD can be temporarily turned off. At the maximum frame rate MFR, one frame can include one scan period SP.

[0133] When the display device 1000 is driven at the maximum frame rate (MFR), both the source drive voltage AVDD and the reference voltage Vint can have predetermined voltage levels. For example, the source drive voltage AVDD can have... Figure 7 The first level V1 shown can have the reference voltage Vint. Figure 7 The third level V3 is shown in the diagram.

[0134] Figure 7 It shows Figure 1 An example of the operation of a display device.

[0135] Reference Figure 1 , Figure 3 , Figure 6 and Figure 7 The display device 1000 can display an image at a first frame rate FR1 that is slower than the maximum frame rate MFR.

[0136] Figure 7This shows the supply to a pixel (e.g., Figure 3 An example of the signal of pixel PXij in the following. Figure 7 In the above, the supply to a single pixel can be primarily described (e.g., Figure 3 The signal of pixel PXij (or the pixel in the first pixel row). Such as Figure 7 The signal source can be driven sequentially in predetermined pixel row units, or it can be driven simultaneously in all pixel rows or some pixel rows.

[0137] In this embodiment, the controller 500 can detect the first frame rate FR1 by counting the duration of the blanking period BP. The slower the frame rate, the longer the blanking period BP can be. The blanking period following the first blanking period BP1 can be defined as the second blanking period BP2.

[0138] In this embodiment, the first frame rate FR1 can correspond to half of the maximum frame rate MFR. Therefore, the blanking period BR is approximately twice the length of the first blanking period BP1, and the duration of the first blanking period BP1 and the duration of the second blanking period BP2 can be substantially the same. For example, the maximum frame rate MFR can be 120Hz, while the first frame rate FR1 can be 60Hz.

[0139] As described above, when the count value included in the counting signal reaches the reference value during the blanking period BP, the transmit off period OFP can be activated. That is, as... Figure 7 As shown, the transmit shutdown period OFP can be included in the second blanking period BP2. For example, the count value can correspond to the duration of the first blanking period BP1. Therefore, the transmit shutdown period OFP can be activated immediately after the end of the first blanking period BP1.

[0140] In the first time period P1 (e.g., the transmit shutdown period OFP) included in the second blanking period BP2, operations can be performed with... Figure 3 and Figure 4 The same operation as described in the transmit shutdown period OFP. The second blanking period BP2 may include the second period P2 after the first period P1 and the end of the transmit shutdown period OFP.

[0141] During the emitter-off period (OFP), the third transistor T3 is turned on, allowing the reference voltage Vint to be supplied to the second node N2, and the light-emitting element LD can be temporarily turned off. In the second period (P2) following the first period (P1), the light-emitting element LD can resume emitting light based on the current generated during the emitter-off period (OFP).

[0142] Subsequently, in the third time period P3 corresponding to the scan time period SP of the effective time period AP, the second transistor T2 and the third transistor T3 are turned on, allowing the reference voltage Vint to be supplied to the second node N2, and the light-emitting element LD can be temporarily turned off again. After the third time period P3, the light-emitting element LD can emit light with a brightness corresponding to the data signal supplied to the third time period P3.

[0143] For example, according to such Figure 7 The drive shown, the transmit shutdown period OFP is additionally inserted in Figure 5 In a 60Hz drive, the number of times the light-emitting element (LD) is turned off increases in real time, and the average brightness in a 60Hz drive can decrease. Therefore, under the same grayscale conditions, the average brightness of a 120Hz drive and a 60Hz drive can be similar.

[0144] Thus, the transmit off period (OFP) is additionally inserted into the blanking period (BP) without frame delay based on frame rate variations lower than the maximum frame rate (MFR), making it possible to control brightness fluctuations caused by variable drive frequency (frame rate).

[0145] A source drive voltage AVDD with a first level V1 can be supplied during the first blanking period BP1 and the first period P1. A reference voltage Vint with a third level V3 can be supplied during the first blanking period BP1 and the first period P1.

[0146] In this embodiment, when the supply of the first scan signal terminates in the first time period P1, the power supply 400 can switch (raise) the source drive voltage AVDD from the first level V1 to the second level V2. Thereafter, the power supply 400 can gradually decrease the source drive voltage AVDD from the second level V2 back to the first level V1 during the second time period P2. However, the source drive voltage AVDD is not lower than the first level V1. For example, the voltage difference between the first level V1 and the second level V2 can be approximately 0.1V.

[0147] In this embodiment, when the supply of the second scan signal terminates in the first time period P1, the power supply 400 can transition (e.g., decrease) the reference voltage Vint from the third level V3 to the fourth level V4. Thereafter, the power supply 400 can gradually increase the reference voltage Vint from the fourth level V4 back to the third level V3 during the second time period P2. However, the reference voltage Vint does not need to exceed the third level V3. For example, the voltage difference between the third level V3 and the fourth level V4 can be approximately 0.1V.

[0148] When the blanking period BP ends, the period in which the reference voltage Vint increases and the period in which the source drive voltage AVDD decreases can be terminated. When the first frame rate FR1 is a divisor of the maximum frame rate MFR, the duration of the second blanking period BP2 can be an integer multiple of the duration of the first blanking period BP1. In an embodiment, when the duration of the second blanking period BP2 is an integer multiple of the duration of the first blanking period BP1, the source drive voltage AVDD supplied to the effective period AP immediately after the second blanking period BP2 can be a first level V1, and the reference voltage Vint can be a third level V3.

[0149] Therefore, as Figure 7 As shown, when the duration of the second blanking period BP2 is substantially the same as the duration of the first blanking period BP1, the source drive voltage AVDD and the reference voltage Vint supplied from the third period P3 can be the first level V1 and the third level V3, respectively. Even during the later restart of the first blanking period BP1, the corresponding voltage levels can be maintained.

[0150] Since neither the first nor the second scan signal is supplied during the second time period P2, both the second transistor T2 and the third transistor T3 can be turned off. Therefore, changes in the reference voltage Vint and the source drive voltage AVDD do not affect the brightness of pixel PXij during the blanking period BP (specifically, the second time period P2) or the blanking period BP.

[0151] You can refer to Figure 8 Describe in detail the reasons for changing the reference voltage Vint and the source drive voltage AVDD.

[0152] Figure 8 It shows Figure 1 Another example of the operation of a display device.

[0153] Reference Figure 1 , Figure 3 , Figure 6 and Figure 8 The display device 1000 can display images at a second frame rate FR2, which is slower than the maximum frame rate MFR.

[0154] The controller 500 can detect the second frame rate FR2 by counting the duration of the blanking period BP. In an embodiment, the second frame rate FR2 can be a value between the maximum frame rate MFR and the first frame rate FR1. For example, the second frame rate FR2 can be 90Hz.

[0155] As described above, the transmit shutdown period OFP can be activated in the first period P1 immediately following the end of the first blanking period BP1.

[0156] Furthermore, since the second frame rate FR2 is faster than the first frame rate FR1, the duration of the second blanking period BP2 can be reduced. Therefore, the interval between the first period P1 (which can be the emitter-off period OFP) and the third period P3 (which can be the scan period SP) can be narrowed. In other words, the emitter-off interval of the light-emitting element LD can be reduced.

[0157] As described above, when displaying an image at the second frame rate FR2, the interval between the first time period P1 and the third time period P3 (e.g., the second time period P2) narrows, and the average brightness is lower than the average brightness of the drive at the maximum frame rate MFR. To prevent this brightness degradation, when the first time period P1 ends, the source drive voltage AVDD can be increased to the second level V2, while the reference voltage Vint can be decreased to the fourth level V4. Here, the rate of change of the source drive voltage AVDD can be the same as that of the reference voltage. Figure 7 The rates of change of the described source drive voltage AVDD are essentially the same, and the rate of change of the reference voltage Vint can be the same as that of the reference voltage. Figure 7 The rates of change of the reference voltage Vint described are basically the same.

[0158] During the second time period P2, the source drive voltage AVDD can be changed at a predetermined rate. During the second time period P2, the reference voltage Vint can also be changed at a predetermined rate. The voltage level at the end of the second time period P2 can be supplied to the effective time period AP.

[0159] For example, the source drive voltage AVDD supplied during the effective period AP can be the fifth level V5, while the reference voltage Vint can be the sixth level V6. The fifth level V5 can be the voltage between the second level V2 and the first level V1, while the sixth level V6 can be the voltage between the third level V3 and the fourth level V4.

[0160] The source drive voltage AVDD is a voltage that can be used to generate a gamma voltage corresponding to a data signal with grayscale values. For example, the maximum gamma voltage, which is the largest among gamma voltages, can be determined by the source drive voltage AVDD. The gamma voltage can be determined by the voltage value between the maximum gamma voltage and the minimum gamma voltage. For example, the gamma voltage can be determined based on a predetermined gamma curve (e.g., the 2.2 gamma curve, etc.), and the shape of the gamma curve, which represents the relationship between grayscale values ​​and gamma voltages, can be changed according to the magnitude of the source drive voltage AVDD.

[0161] Therefore, as the source drive voltage AVDD increases, the data signal (e.g., gamma voltage) for the same grayscale value can increase. For example, the voltage level of the first grayscale data signal generated by the source drive voltage AVDD of the fifth level V5 can be greater than the voltage level of the first grayscale data signal generated by the source drive voltage AVDD of the first level V1.

[0162] By turning on the second transistor T2, the data signal can be supplied to the first node N1 of pixel PXij (e.g., the gate electrode of the first transistor T1).

[0163] By turning on the third transistor T3, the reference voltage Vint can be supplied to the second node N2 of pixel PXij (e.g., the source electrode of the first transistor T1).

[0164] The difference between the voltage of the data signal DSj supplied during the scan period SP and the reference voltage Vint can determine the gate-source voltage of the first transistor T1. However, under the same input grayscale value (e.g., input image data), the gate-source voltage of the first transistor T1 determined based on the reference voltage Vint of the sixth level V6 and the source drive voltage AVDD of the fifth level V5 in the drive at the second frame rate FR2 can be larger than the gate-source voltage of the first transistor T1 determined in the drive at the first frame rate FR1 or the maximum frame rate MFR.

[0165] When the gate-source voltage of the first transistor T1 increases, the driving current can increase, thereby increasing the brightness of the light-emitting element LD. Therefore, for the same grayscale value, the brightness of the light-emitting element LD in the second display period DP2 can be higher than the brightness of the light-emitting element LD in the first display period DP1.

[0166] As described above, to compensate for the brightness degradation caused by the narrowing interval between the transmit off period (OFP) and the scan period (SP) (such as driving at the second frame rate FR2), the voltage difference between the source drive voltage AVDD and the reference voltage Vint can be increased during the second display period DP2. Therefore, the gate-source voltage of the first transistor T1 in the second display period DP2 can be increased to increase the brightness of the light-emitting element LD, and the average brightness at the second frame rate FR2 can be similar to the average brightness at the maximum frame rate MFR. Thus, brightness fluctuations (or flickering) according to the variable drive frequency (frame rate) can be further reduced.

[0167] Subsequently, when the effective period AP ends, the source drive voltage AVDD and the reference voltage Vint can be supplied again at the first level V1 and the third level V3, respectively.

[0168] In addition, the magnitudes of the source drive voltage AVDD and the reference voltage Vint supplied during the effective period AP after the second blanking period BP2 can be changed according to the duration of the second blanking period BP2.

[0169] When the blanking period BP ends and the active period AP begins, the counting of the blanking period BP is terminated by a signal indicating the start of the active period AP, and the scanning period SP can be performed.

[0170] Figure 9 It shows Figure 1 Another example of the operation of a display device.

[0171] Reference Figure 1 , Figure 3 , Figure 6 , Figure 7 and Figure 9 The display device 1000 can display images at a third frame rate FR3, which is slower than the maximum frame rate MFR.

[0172] The third frame rate (FR3) is slower than the first frame rate (FR1). For example, when the maximum frame rate (MFR) is 120Hz, Figure 9 The third frame rate FR3 can be 40Hz, which is 1 / 3 of the maximum frame rate MFR. Optionally, the duration of the blanking period BP can be three times the duration of the first blanking period BP1.

[0173] In this embodiment, the transmit shutdown period OFP can be activated whenever the value of the counting signal reaches a reference value (e.g., the duration of the first blanking period BP1). Furthermore, during the blanking period BP, whenever the transmit shutdown period OFP ends, the source drive voltage AVDD and the reference voltage Vint can transition to the second level V2 and the fourth level V4, respectively.

[0174] Due to the insertion of the Off-Phase (OFP) during the transmit shutdown period (e.g., the output of the first scan signal) and as such Figure 9 The source drive voltage AVDD and the reference voltage Vint are varied in the manner shown, so that even with any frame rate variation at or below the maximum frame rate MFR, brightness control for the corresponding frame can be performed in real time. Therefore, brightness can be stably maintained in variable frequency drive, and image quality can be controlled.

[0175] Figure 10 It shows that it includes Figure 1 A block diagram of an example of a data drive in a display device.

[0176] Reference Figure 1 and Figure 10 The data driver 300 may include a gamma voltage generator 320.

[0177] The gamma voltage generator 320 can generate a gamma voltage GV corresponding to a grayscale value based on a gamma control signal CON supplied from the controller 500. In an embodiment, the gamma voltage generator 320 may include a gamma tap generator 322 and a voltage divider 324. However, this is an example, and at least some of the components of the gamma voltage generator 320 may be configured as separate circuitry or ICs external to the data driver 300.

[0178] The gamma tap generator 322 can determine the magnitudes of the first gamma tap voltage VGMA1 to the ninth gamma tap voltage VGMA9 based on the gamma control signal CON. For example, the first gamma tap voltage VGMA1 can be a gamma voltage (or the voltage of a data signal) corresponding to a white grayscale value, while the ninth gamma tap voltage VGMA9 can be a gamma voltage (or the voltage of a data signal) corresponding to a black grayscale value. However, this is just an example, and the number of gamma tap voltages VGMA1 to VGMA9 is not limited to this.

[0179] Voltage distributor 324 can generate gamma voltages GV (e.g., voltages corresponding to data signals) corresponding to all grayscale values ​​of display device 1000 based on first gamma tap voltages VGMA1 to ninth gamma tap voltages VGMA9. For example, gamma voltage GV may include voltage values ​​corresponding to each of 256 grayscale values ​​(e.g., GV0 to GV255).

[0180] In an embodiment, voltage divider 324 may include a series of resistors that divide the first gamma tap voltage VGMA1 to the ninth gamma tap voltage VGMA9. For example, the gamma voltage GV may be determined based on the first gamma tap voltage VGMA1 to the ninth gamma tap voltage VGMA9 and a predetermined gamma curve (e.g., 2.2 gamma curve, etc.).

[0181] The first gamma tap voltage VGMA1 to the ninth gamma tap voltage VGMA9 can be selected from the voltages between the source drive voltage AVDD and the ground voltage GND. Therefore, when the source drive voltage AVDD changes, the first gamma tap voltage VGMA1 to the ninth gamma tap voltage VGMA9 and the gamma voltage GV can be adjusted. For example, when the source drive voltage AVDD increases, at least some of the gamma voltages GV can increase.

[0182] Therefore, the gate-source voltage of the first transistor (e.g., the driving transistor) of a pixel can be controlled by adjusting the source drive voltage AVDD.

[0183] In this embodiment, at least some of the components of the gamma voltage generator 320 may be included in the power supply 400. For example, the gamma tap generator 322 may be included in the power supply 400.

[0184] Figure 11 It shows Figure 1 Another example of the operation of a display device.

[0185] exist Figure 11 In, it is used for reference. Figure 8 The same reference numerals are used for the constituent elements described, and redundant descriptions of these constituent elements may be omitted.

[0186] Reference Figure 1 , Figure 3 , Figure 4 and Figure 11 The power supply 400 can adjust the gate level voltage for the scan driver 200 based on the duration of the blanking period BP (such as determining the high voltage VGH and / or low voltage VGL for the gate on-level and / or gate off-level of the first scan signal SL1 and the second scan signal SL2, respectively).

[0187] Figure 11 It is shown that both the high voltage VGH and the low voltage VGL are controlled, but this disclosure is not limited thereto, and in an alternative embodiment only one of the high voltage VGH and the low voltage VGL can be controlled.

[0188] High voltage VGH and low voltage VGL can affect the effective gate voltages of the second transistor T2 and the third transistor T3. Even when the second transistor T2 and the third transistor T3, acting as switching transistors, are operating in the saturation region, the voltage levels supplied to the first node N1 and the second node N2 can be changed according to the gate voltage level. For example, when the high voltage VGH of the second scan signal increases, the gate-source voltage of the second transistor T2 increases, and the voltage supplied to the first node N1 can be changed accordingly.

[0189] In the embodiment, the variations in high voltage VGH and low voltage VGL can be similar to those in the reference embodiment. Figure 7 and Figure 8The variations in the source drive voltage AVDD and the reference voltage Vint described are similar in form, but not limited to them. Therefore, in response to the same grayscale value, the gate-source voltage supplied to the first transistor T1 during the scan period SP is adjusted according to the duration of the blanking period BP, and brightness fluctuations according to the variable drive frequency or frame rate can be controlled. In alternative embodiments, it will be understood that the duration can be the duration of the blanking period BP, or optionally the duration of the effective period AP relative to the variable frequency frame period.

[0190] Figure 12 It shows Figure 1 A block diagram of an example of a display device. In this embodiment, the power supply 400 includes connections to... Figure 1 The scan driver 200 has two additional voltage outputs, which supply a high voltage VGH and a low voltage VGL to the scan driver 200, respectively. (Repeated descriptions can be omitted.)

[0191] Reference Figure 1 , Figure 3 , Figure 4 and Figure 12 The controller 500 can control the power supply 400 and the scan driver 200. The scan driver 200 may include a first scan driver 220 and a second scan driver 240.

[0192] The controller 500 can generate a clock signal CLK and a first start signal STV1 and supply them to the first scan driver 220, and can generate a clock signal CLK and a second start signal STV2 and supply them to the second scan driver 240. The clock signal CLK, the first start signal STV1, and the second start signal STV2 can be included in the scan control signal SCS. The clock signal CLK supplied to the first scan driver 220 and the second scan driver 240 can be the same, or at least some of them can be different.

[0193] The first scan driver 220 can sequentially supply a first scan signal, in which a first start signal STV1 is shifted, to the first scan lines SL1_1 to SL1_n based on a clock signal CLK. The gate on-level and gate off-level of the first scan signal can be determined based on the high voltage VGH and low voltage VGL supplied from the power supply 400 to the scan driver 200, respectively.

[0194] In one embodiment, the controller 500 may output a first start signal STV1 based on a count signal used to count the duration of the blanking period BP. Therefore, a first scan signal can be inserted during the emitter off period (OFP) of the pixel PX, which is supplied during the blanking period BP.

[0195] The second scan driver 240 can sequentially supply a second scan signal, in which the second start signal STV2 is shifted, to the second scan lines SL2_1 to SL2_n based on the clock signal CLK. The gate on-level and gate off-level of the second scan signal can be determined based on the high voltage VGH and low voltage VGL supplied from the power supply 400, respectively.

[0196] The controller 500 can generate a power control signal PCS and supply the power control signal PCS to the power supply 400.

[0197] The power supply 400 can generate a power control signal PCS based on a counting signal used to count the time of the blanking period BP.

[0198] In this embodiment, the power supply 400 can output a reference signal based on the power control signal PCS. Figures 6 to 9 The source drive voltage AVDD and / or reference voltage Vint are described, but are not limited to these.

[0199] In another embodiment, the power supply 400 can be generated based on the power control signal PCS as shown in the reference. Figure 11 The high voltage VGH and low voltage VGL are described and supplied to the first scan driver 220 and the second scan driver 240.

[0200] In embodiments of this disclosure, the variable supply voltage from power supply 400 may include at least one variable gate level voltage VGH and / or VGL connected to scan drivers 200, 220, and / or 240, wherein the at least one variable gate level voltage VGH and / or VGL controls at least one of the gate on-level and gate off-level of the scan signal based on the duration of a determined effective period AP and / or blanking period BP, BP1, or BP2. The variable supply voltage may include at least one variable output connected to scan drivers 200, 220, and / or 240, wherein the at least one variable output controls the timing of the scan signals to scan lines SL1 and / or SL2 in the corresponding blanking period BP, BP1, or BP2 based on a determined duration. The variable supply voltage may include at least one variable output connected to scan drivers 200, 220, and / or 240, wherein the at least one variable output individually controls the timing of the first scan signal and the second scan signal to the first scan line SL1 and the second scan line SL2 of the same pixel PX in the corresponding blanking period BP, BP1, or BP2 based on a determined duration. The variable supply voltage may include at least one variable source drive voltage VDD, VSS, and / or Vint connected to at least one of the data driver 300 and the plurality of pixels PX, wherein the at least one variable source drive voltage VDD, VSS, and / or Vint controls the data signal based on a determined duration. The variable supply voltage may include at least one variable reference voltage connected to the source electrode of the plurality of pixels PX and the driving transistor T1 based on a determined duration.

[0201] Figure 13 It shows Figure 1 A block diagram of an example controller for a display device.

[0202] Figure 13 Only some of the components of the controller 500 that are relevant to this disclosure are shown.

[0203] Reference Figure 1 , Figure 2 and Figure 13 The controller 500 may include a receiver 520, a frame memory 540, an image data generator 560, and a control signal generator 580.

[0204] The controller 500 can control the voltage level of the source drive voltage AVDD and / or the voltage level of the reference voltage Vint output from the power supply 400, as well as the supply timing of the first start signal STV1 supplied to the first scan driver 220, based on the duration of the blanking period BP.

[0205] Receiver 520 can receive image signals RGB, control signals CTL, and frame rate variable signals Fsync from the outside.

[0206] The variable frame rate signal Fsync is a signal indicating that the frame rate of the image signal RGB and control signal CTL provided from the external graphics processor to the display device 1000 can be changed for each frame. The frame rate of the image signal RGB and control signal CTL can be changed according to the rendering speed of the graphics processor.

[0207] Receiver 520 can recover the control signal CTL into the data enable signal DE. Furthermore, receiver 520 can also recover the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the master clock signal MCLK based on the control signal CTL.

[0208] The frame memory 540 can delay the image signal RGB' output from the receiver 520 by one frame to output a delayed image signal RGB.

[0209] Image data generator 560 can convert delayed image signal "RGB" into image data "DAT". The image data "DAT" can be provided to data driver 300.

[0210] The control signal generator 580 can receive the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, the data enable signal DE, the master clock signal MCLK, and the frame rate variable signal Fsync, and can output the data control signal DCS, the first start signal STV1, the second start signal STV2, the power control signal PCS, and the clock signal CLK to the scan driver 200 and / or the power supply 400.

[0211] Figure 14 It shows Figure 13 A block diagram of an example control signal generator.

[0212] Reference Figure 1 , Figure 4 , Figure 6 , Figure 7 , Figure 8 , Figure 13 and Figure 14 The control signal generator 580 may include a frame rate detector 582, a voltage controller 584, and a scan controller 586.

[0213] The frame rate detector 582 can detect the frame rate based on the frame rate variable signal Fsync and can generate a counting signal CNT. In an embodiment, the frame rate detector 582 can distinguish between the active period AP and the blanking period BP of the data enable signal DE, and can count the time of the blanking period BP (such as pulses of the clock signal MCLK or CLK).

[0214] For example, the frame rate detector 582 can generate a count signal CNT that includes information about the duration of the blanking period BP by counting the pulses of the master clock signal MCLK during the blanking period BP. The count signal CNT can be provided to the voltage controller 584 and the scan controller 586.

[0215] In one embodiment, the control signal generator 580 can compare the count signal CNT with a reference value corresponding to the maximum frame rate MFR. The reference value may correspond to the duration of the first blanking period BP1.

[0216] When the value of the count signal CNT reaches the reference value, the scan controller 586 can supply the first start signal STV1 for outputting the first scan signal to the scan driver 200 (e.g., the first scan driver 220). Therefore, the transmit off period OFP in which the first scan signal is supplied to the pixel PX can be inserted within the blanking period BP of a frame rate smaller than the maximum frame rate MFR.

[0217] In this embodiment, a reference value can be set for each integer multiple of the first blanking period BP1. Therefore, when the duration of the blanking period BP is extended, a transmit shutdown period OFP can be inserted every integer multiple of the first blanking period BP1.

[0218] In addition, when the blanking period BP ends, the scan controller 586 can supply the first start signal STV1 to the scan driver.

[0219] The voltage controller 584 can control the source drive voltage AVDD and the reference voltage Vint in response to the counting signal CNT. Furthermore, the voltage controller 584 can control the voltage level of the high voltage VGH and / or the voltage level of the low voltage VGL in response to the counting signal CNT.

[0220] The first power control signal PCS1 can be provided to power supply 400 to control the source drive voltage AVDD. For example... Figure 8 As shown, the source drive voltage AVDD can have a first level V1 during the first blanking period BP1 and the first period P1, and can decrease from a second level V2 to a fifth level V5 during the second period P2. The fifth level V5 of the source drive voltage AVDD at the end of the second blanking period BP2 can be maintained during the subsequent active period AP.

[0221] The second power control signal PCS2 can be provided to power supply 400 to control the reference voltage Vint. For example... Figure 8As shown, the reference voltage Vint can have a third level V3 during the first blanking period BP1 and the first period P1, and can increase from a fourth level V4 to a sixth level V6 during the second period P2. The sixth level V6 of the reference voltage Vint at the end of the second blanking period BP2 can be maintained during the subsequent active period AP.

[0222] Figure 15A and Figure 15B It shows Figure 1 Other examples of the operation of the display device.

[0223] exist Figure 15A and Figure 15B In, it is used for reference. Figure 7 The same reference numerals are used for the constituent elements described, and redundant descriptions of these constituent elements may be omitted.

[0224] Reference Figure 15A and Figure 15B The display device 1000 can display an image at a first frame rate FR1 that is slower than the maximum frame rate MFR.

[0225] In an embodiment, such as Figure 15A As shown, the source drive voltage AVDD can be adjusted during the second time period P2 of the second blanking period BP2. The duration of the second time period P2 can be inversely proportional to the frame rate.

[0226] The source drive voltage AVDD at the end of the second time period P2 can be applied during the subsequent effective time period AP. Therefore, the voltage level of the data signal can be changed, and the gate-source voltage of the first transistor (e.g., the drive transistor) of the pixel can be controlled by adjusting the source drive voltage AVDD.

[0227] In an embodiment, such as Figure 15B As shown, the reference voltage Vint can be adjusted during the second time period P2 of the second blanking time period BP2. The reference voltage Vint at the end of the second time period P2 can be applied during the subsequent active time period AP. Therefore, the gate-source voltage of the first transistor (e.g., the driving transistor) of the pixel can be controlled by adjusting the reference voltage Vint.

[0228] Figure 16 A block diagram of a display device according to an embodiment of the present disclosure is shown.

[0229] exist Figure 16 In, it is used for reference. Figure 1 The same reference numerals are used for the constituent components described, and redundant descriptions of these components may be omitted. Furthermore, in addition to the sensing circuit 600 supplied with the reference voltage Vint and the wiring, Figure 16The display device 1001 may have the same as Figure 1 The display device 1000 has a basically the same or similar structure.

[0230] Reference Figure 16 The display device 1001 may include a pixel unit 100, a scan driver 200, a data driver 300, a sensing circuit 600, a power supply 400, and a controller 500.

[0231] The controller 500 can also control the operation of the sensing circuit 600. For example, the controller 500 can control the timing for supplying a reference voltage Vint to the pixel PX through the sensing line SSL and / or the timing for sensing the current generated in the pixel PX through the sensing line SSL.

[0232] The sensing circuit 600 can generate compensation values ​​for compensating the characteristic values ​​of the pixel PX based on the sensed values ​​(sense current) provided from the sensing line SSL. For example, the sensing circuit 600 can detect and compensate for changes in the threshold voltage and mobility of the driving transistor, as well as changes in the characteristics of the light-emitting elements included in the pixel PX.

[0233] In one embodiment, the sensing circuit 600 can supply a predetermined reference voltage Vint to the pixel unit 100 via the sensing line SSL during the transmit-off period of the blanking period and the scan period of the active period. In another embodiment, the reference voltage Vint can be supplied to the sensing circuit 600 from the power supply 400.

[0234] Figure 17 It shows that it includes Figure 16 A circuit diagram of an example pixel in a display device.

[0235] exist Figure 17 In, it can be used for reference. Figure 3 The same reference numerals are used for the constituent elements described, and redundant descriptions of these constituent elements may be omitted. Furthermore, Figure 17 The pixel PXij' can have the same Figure 3 The pixel PXij has a basically the same or similar structure, plus a sensing line SSLj connected to the third transistor T3.

[0236] Reference Figure 17 Pixel PXij' may include a light-emitting element LD, a first transistor T1 (e.g., a driving transistor), a second transistor T2, a third transistor T3, and a storage capacitor Cst.

[0237] The third transistor T3 can be connected between the sensing line SSLj and the second electrode (e.g., the second node N2) of the first transistor T1. When the first scan signal is supplied to the first scan line SL1_i, the third transistor T3 can be turned on to electrically connect the sensing line SSLj and the second node N2 (e.g., the second electrode of the first transistor T1).

[0238] The reference voltage Vint can be supplied to the second node N2 via the sensing line SSLj, or the sensed value generated at the second node N2 can be supplied to the sensing circuit (e.g., Figure 16 (of 600).

[0239] However, this is an example, and the construction and external compensation methods of pixel PXij' can be changed differently.

[0240] As described above, in the display device according to this embodiment of the present disclosure, since there is no frame delay because a transmit shutdown period is additionally inserted during the blanking period according to the change in frame rate, brightness flicker caused by changes in drive frequency or frame rate can be controlled.

[0241] Furthermore, in order to compensate for the excessive brightness degradation caused by the increased number of turn-off times of the light-emitting element due to the insertion of an emission-off period in the blanking period, the voltage difference between the source drive voltage and the reference voltage can be controlled (e.g., increased) according to the duration of the blanking period.

[0242] Therefore, the gate-source voltage of the first transistor is increased during the display period or effective period to increase the brightness of the light-emitting element, and the average brightness at any frame rate can be similar to the average brightness at the maximum frame rate.

[0243] Therefore, since brightness control for a frame is performed in real time, such as by counting based on blanking periods, inserting transmit-off periods, source drive voltage control, and / or reference voltage control, even in the presence of any frame rate changes, the average brightness in a variable frequency drive can be stabilized and image quality can be maximized.

[0244] While this disclosure has been described in conjunction with what is now considered to be actual embodiments, it is to be understood that the inventive concept is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, the display device comprising: Pixels are connected to each of the first scan line, the second scan line, and the data line; A scan driver is configured to supply a first scan signal to the first scan line and a second scan signal to the second scan line; The controller is configured to receive a control signal, divide a frame period into an active period and a blanking period based on the control signal, generate a count signal indicating the duration of the blanking period, and provide a power control signal based on the count signal. A data driver is configured to supply data signals to the data line; as well as The power supply is configured to control at least one of the source drive voltage for the data driver and the gate level voltage for the scan driver based on the power control signal. When the counting signal reaches a reference value, the controller supplies a start signal for outputting the first scan signal to the scan driver. The pixel includes: a light-emitting element; a first transistor connected between a first driving power supply and a second node, and including a gate electrode connected to the first node; and a third transistor that supplies a reference voltage to the second node in response to a first scan signal supplied to its gate electrode. The light-emitting element is connected between the second node and the second driving power supply, and the reference voltage is less than or equal to the voltage of the second driving power supply.

2. The display device according to claim 1, wherein The reference value is the duration of the first blanking period corresponding to the maximum frame rate of the display device.

3. The display device according to claim 2, wherein: When the frame rate detected based on the control signal is slower than the maximum frame rate, the blanking period includes consecutive first and second blanking periods, and The scan driver supplies the first scan signal to the first scan line during a first time period, which is included in the second blanking period, based on the start signal.

4. The display device according to claim 3, wherein: The second blanking period includes the consecutive first and second periods. The source drive voltage of the first level is supplied during the first blanking period and the first period, and When the supply of the first scan signal in the first time period ends, the source drive voltage changes from the first level to a second level that is higher than the first level.

5. The display device according to claim 4, wherein: The power supply gradually reduces the source drive voltage from the second level during the second time period, and The duration of the second blanking period is less than or equal to the duration of the first blanking period.

6. The display device according to claim 4, wherein The source drive voltage supplied during the effective period immediately following the second blanking period is the same as the source drive voltage at the end of the second blanking period.

7. The display device of claim 6, wherein, When the duration of the second blanking period is an integer multiple of the duration of the first blanking period, the source drive voltage supplied in the effective period immediately following the second blanking period has the first level.

8. The display device according to claim 4, wherein, The pixels also include: A second transistor, connected between the data line and the first node, and including a gate electrode connected to the second scan line; and A storage capacitor is connected between the first node and the light-emitting element.

9. The display device according to claim 8, wherein, The power supply also controls the reference voltage based on the power control signal.

10. The display device according to claim 9, wherein: The reference voltage of the third level is supplied during the first blanking period and the first time period, and When the supply of the first scan signal in the first time period ends, the reference voltage changes from the third level to a fourth level that is lower than the third level.

11. The display device according to claim 10, wherein: During the second time period, the power supply gradually increases the reference voltage from the fourth level, and The duration of the second blanking period is less than or equal to the duration of the first blanking period.

12. The display device according to claim 10, wherein, The reference voltage supplied during the effective period immediately following the second blanking period is the same as the reference voltage at the end of the second blanking period.

13. The display device according to claim 12, wherein, When the duration of the second blanking period is an integer multiple of the duration of the first blanking period, the reference voltage supplied in the effective period immediately following the second blanking period has the third level.

14. The display device according to claim 9, wherein, The effective time period includes a scanning time period, during which the data signal is written to the pixel by turning on the second transistor and the third transistor.

15. The display device according to claim 3, wherein, The controller includes: A frame rate detector detects the frame rate based on a variable frame rate signal and generates the counting signal. A voltage controller, in response to the counting signal, controls the source drive voltage and the reference voltage supplied to the source electrode of the driving transistor of the pixel; and The scan controller outputs the start signal in response to the counting signal.

16. A display device, the display device comprising: A pixel is connected to a first scan line, a second scan line, and a data line, and includes a first transistor and a third transistor. The first transistor generates a drive current for a light-emitting element, wherein the first transistor is connected between a first drive power supply and a second node and includes a gate electrode connected to the first node, and the third transistor supplies a reference voltage to the second node in response to a first scan signal supplied to its gate electrode. The light-emitting element is connected between the second node and a second drive power supply, and the reference voltage is less than or equal to the voltage of the second drive power supply. A scan driver supplies the first scan signal to the first scan line and the second scan signal to the second scan line; The controller divides a frame period into an active period and a blanking period based on an externally supplied control signal, and generates a counting signal and a power control signal that count the duration of the blanking period. The data driver supplies data signals to the data line; and The power supply, based on the power control signal, controls at least one of the reference voltage supplied to the source electrode of the first transistor and the gate level voltage supplied to the scan driver according to the duration of the blanking period. When the counting signal reaches the reference value, the scan driver outputs the first scan signal during the blanking period.

17. The display device according to claim 16, wherein, The reference value is the duration of the first blanking period corresponding to the maximum frame rate set in the display device.

18. The display device according to claim 17, wherein: When the frame rate detected based on the control signal is slower than the maximum frame rate, the blanking period includes consecutive first and second blanking periods, and The scan driver supplies the first scan signal to the first scan line during a first time period, which is included in the second blanking period.

19. The display device according to claim 18, wherein: The second blanking period includes the consecutive first and second periods. The reference voltage of the first level is supplied during the first blanking period and the first period. When the supply of the first scan signal in the first time period ends, the reference voltage changes from the first level to a second level that is lower than the first level.

20. The display device according to claim 19, wherein: The power supply gradually increases the reference voltage from the second level during the second time period, and The reference voltage supplied during the effective period immediately following the second blanking period is the same as the reference voltage at the end of the second blanking period.

21. A display device, the display device comprising: Multiple pixels are connected to power lines, data lines, and scan lines; The controller is configured to divide each of a plurality of variable frequency frame periods into a corresponding active period and a corresponding blanking period, determine the duration of at least one of the corresponding active period and the corresponding blanking period, and provide scan control output, data control output and power control output based on the determined duration; A scan driver, connected to the scan control output, is configured to supply scan signals to the scan lines; A data driver, connected to the data control output, is configured to supply data signals to the data line; as well as The power supply is configured to change at least one variable supply voltage for at least one of the data driver and the scan driver based on the power control output. Wherein, the at least one variable supply voltage includes at least one variable source drive voltage connected to at least one of the data driver and the plurality of pixels, the at least one variable source drive voltage controlling the data signal based on the determined duration, or The at least one variable supply voltage includes at least one variable reference voltage based on the determined duration, connected to the source electrodes of the plurality of pixels and the driving transistors.

22. The display device according to claim 21, wherein, The at least one variable supply voltage also includes at least one variable gate level voltage connected to the scan driver, the at least one variable gate level voltage controlling at least one of the gate on level and gate off level of the scan signal based on the determined duration.

23. The display device according to claim 21, wherein, The at least one variable supply voltage also includes at least one variable output connected to the scan driver, the at least one variable output controlling the timing of the scan signal supplied to the scan line during the corresponding blanking period based on the determined duration.

24. The display device according to claim 21, wherein, The at least one variable supply voltage also includes at least one variable output connected to the scan driver, the at least one variable output individually controlling the timing of the first scan signal and the second scan signal supplied to the first scan line and the second scan line of the same pixel during the corresponding blanking period based on the determined duration.

25. A display device, the display device comprising: Pixels are connected to each of the first scan line, the second scan line, and the data line; A scan driver is configured to supply a first scan signal to the first scan line and a second scan signal to the second scan line; The controller is configured to receive a control signal, divide a frame period into an active period and a blanking period based on the control signal, generate a count signal indicating the duration of the blanking period, and provide a power control signal based on the count signal. A data driver is configured to supply data signals to the data line; as well as The power supply is configured to control at least one of the source drive voltage for the data driver and the gate level voltage for the scan driver based on the power control signal. When the counting signal reaches a reference value, the controller supplies a start signal for outputting the first scan signal to the scan driver. The pixel includes: a light-emitting element; a first transistor connected between a first driving power supply and the light-emitting element, and including a gate electrode connected to a first node; a second transistor connected between the data line and the first node, and including a gate electrode connected to a second scan line; a third transistor supplying a reference voltage to a second node in response to a first scan signal supplied to its gate electrode, the first transistor and the light-emitting element being connected at the second node; and a storage capacitor connected between the first node and the light-emitting element. The power supply also controls the reference voltage based on the power control signal.

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