Indication device

Abstract

In a display device employing pixels with a built-in boost circuit, this technology provides a way to increase the amplitude of the pixel electrodes relative to the amplitude of the source line without reducing the number of pixels per row. [Solution] In the display device, the number of signal lines is doubled, and separate signal lines are provided for pixels in odd-numbered rows and pixels in adjacent even-numbered rows. By driving the scan lines simultaneously for odd-numbered and even-numbered rows, two rows are driven in the time of one horizontal period by writing to pixels in odd-numbered rows and pixels in adjacent even-numbered rows. This makes it possible to effectively halve the time of one horizontal period.

Description

Technical Field

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[0001] The present disclosure relates to a display device.

Background Art

[0002] As a display element using a polymer dispersed liquid crystal (PDLC) material, for example, Japanese Patent Application Laid-Open No. 5-61016 has been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present inventors have studied a transparent display device using a PDLC material, so-called a transparent display. In a transparent display, since a high voltage is applied to the PDLC, a dedicated source driver IC (integrated circuit) for outputting a high-voltage video signal and a dedicated gate driver IC for writing and holding a high voltage are required. Therefore, it is one of the causes of high cost factors such as the inability to use a low-voltage IC manufacturing process and the inability to use a general-purpose source driver IC or a general-purpose gate driver IC.

[0005] Therefore, a transparent display has been developed in which a dedicated source driver IC is not required by creating a booster circuit in a pixel while keeping the source driver IC at a normal (general-purpose) video output voltage and increasing the range of the liquid crystal applied voltage.

[0006] However, because each pixel incorporates a boost circuit, the number of source lines (also called signal lines) and gate lines (also called scan lines) increases compared to a typical pixel circuit. Furthermore, the increased number of pixel components leads to a decrease in the aperture ratio. Additionally, the boost drive increases the duration of one horizontal period. As a result, there are limitations on the number of pixels and frame rate.

[0007] The purpose of this disclosure is to provide a technology for a display device employing pixels with a built-in boost circuit that can increase the amplitude of the pixel electrode relative to the amplitude of the source line without reducing the number of pixels in a row.

[0008] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0009] A brief overview of some of the representative disclosures is as follows:

[0010] In other words, a display device according to one embodiment is Multiple pixels arranged in a matrix, A first scan line, a second scan line, a third scan line, and a fourth scan line extending in a first direction and arranged in a second direction intersecting the first direction, A first signal line and a second signal line extending in the second direction and arranged in the first direction, The plurality of pixels include a first pixel and a second pixel adjacent to the first pixel in the second direction, The first pixel comprises a first transistor, a second transistor, a third transistor, a first common electrode and a first pixel electrode separated by a liquid crystal, and a reference potential is supplied to the first common electrode. The gate of the first transistor is connected to the second scan line, one of the source and drain of the first transistor is connected to the first signal line, and the other of the source and drain of the first transistor is connected to the first pixel electrode via a first capacitive element. The gate of the second transistor is connected to the first scan line, one of the source and drain of the second transistor is connected to the first signal line, and the other of the source and drain of the second transistor is connected to the first pixel electrode. The gate of the third transistor is connected to the first scan line, one of the source and drain of the third transistor is connected to the other of the source and drain of the first transistor, and the other of the source and drain of the third transistor is connected to the first common electrode. The second pixel has a fourth transistor, a fifth transistor, a sixth transistor, a second common electrode and a second pixel electrode sandwiching the liquid crystal, and a reference potential is supplied to the second common electrode. The gate of the fourth transistor is connected to the fourth scan line, one of the source and drain of the fourth transistor is connected to the second signal line, and the other of the source and drain of the fourth transistor is connected to the second pixel electrode via a second capacitance element. The gate of the fifth transistor is connected to the third scan line, one of the source and drain of the fifth transistor is connected to the second signal line, and the other of the source and drain of the fifth transistor is connected to the second pixel electrode. The gate of the sixth transistor is connected to the third scan line, one of the source and drain of the sixth transistor is connected to the other of the source and drain of the fourth transistor, and the other of the source and drain of the sixth transistor is connected to the second common electrode.

[0011] Furthermore, a display device according to another embodiment is, Multiple pixels arranged in a matrix, A first scan line, a second scan line, and a third scan line extending in a first direction and arranged in a second direction intersecting the first direction, Including a first signal line and a second signal line extending in the second direction and arranged in the first direction, The plurality of pixels are arranged adjacent to each other in the second direction and include a first pixel and a second pixel, The first pixel has a first transistor, a second transistor, a third transistor, a first common electrode and a first pixel electrode separated by a liquid crystal, and a reference potential is supplied to the first common electrode. The gate of the first transistor is connected to the second scan line, one of the source and drain of the first transistor is connected to the first signal line, and the other of the source and drain of the first transistor is connected to the first pixel electrode via a first capacitive element. The gate of the second transistor is connected to the first scan line, one of the source and drain of the second transistor is connected to the first signal line, and the other of the source and drain of the second transistor is connected to the first pixel electrode. The gate of the third transistor is connected to the first scan line, one of the source and drain of the third transistor is connected to the other of the source and drain of the first transistor, and the other of the source and drain of the third transistor is connected to the first common electrode. The second pixel has a fourth transistor, a fifth transistor, a sixth transistor, a second common electrode and a second pixel electrode sandwiching the liquid crystal, and a reference potential is supplied to the second common electrode. The gate of the fourth transistor is connected to the third scan line, one of the source and drain of the fourth transistor is connected to the second signal line, and the other of the source and drain of the fourth transistor is connected to the second pixel electrode via a second capacitance element. The gate of the fifth transistor is connected to the second scan line, one of the source and drain of the fifth transistor is connected to the second signal line, and the other of the source and drain of the fifth transistor is connected to the second pixel electrode. The gate of the sixth transistor is connected to the second scan line, one of the source and drain of the sixth transistor is connected to the other of the source and drain of the fourth transistor, and the other of the source and drain of the sixth transistor is connected to the second common electrode.

Brief Description of the Drawings

[0012] [Figure 1] FIG. 1 is a circuit diagram of a pixel according to a comparative example. [Figure 2] FIG. 2 is a diagram showing a timing chart of the pixel in FIG. 1. [Figure 3] FIG. 3 is a diagram for explaining the voltage of a pixel electrode of the pixel in FIG. 1. [Figure 4] FIG. 4 is a diagram showing a configuration example of a display device according to Example 1. [Figure 5] FIG. 5 is a diagram showing a configuration example of two pixels shown in FIG. 4. [Figure 6] FIG. 6 is a diagram showing a timing chart of the display device according to Example 1. [Figure 7] FIG. 7 is a diagram showing a configuration example of a display device according to Example 2. [Figure 8] FIG. 8 is a diagram showing a configuration example of three pixels shown in FIG. 7. [Figure 9] FIG. 9 is a diagram showing a timing chart of the display device according to Example 2. [Figure 10A] FIG. 10A is a diagram schematically showing a liquid crystal layer 30 in a transparent state. [Figure 10B] FIG. 10B is a diagram schematically showing a liquid crystal layer 30 in a scattered state. [Figure 11A] FIG. 11A is a cross-sectional view showing a display panel PNL when the liquid crystal layer 30 is in a transparent state. [Figure 11B] FIG. 11B is a cross-sectional view showing a display panel PNL when the liquid crystal layer 30 is in a scattered state.

Modes for Carrying Out the Invention

[0013] The embodiments of this disclosure will be described below with reference to the drawings. It should be noted that the disclosure is merely an example, and modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the disclosure are naturally included within the scope of this disclosure. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of parts in a manner that is clearer than the actual embodiments, but these are merely examples and do not limit the interpretation of this disclosure.

[0014] First, the comparative example will be explained using Figures 1-3. Figure 1 is a circuit diagram of a pixel related to the comparative example. Figure 2 is a timing chart of the pixel in Figure 1. Figure 3 is a diagram illustrating the voltage of the pixel electrode of the pixel in Figure 1.

[0015] The pixel PXr in the comparative example shown in Figure 1 is an example of a configuration of a single pixel (also called a boost pixel) that incorporates a boost circuit. The pixel PXr is connected to a first scan line G1A and a second scan line G1B that extend in a first direction X and are arranged in a second direction Y that intersects with the first direction X, and to a first signal line S1A that extends in the second direction Y and is arranged in the first direction X.

[0016] Each pixel PXr comprises a first transistor TFT-A, a second transistor TFT-B, a third transistor TFT-C, and a common electrode CE and a pixel electrode PE separated by a liquid crystal LC. The common electrode CE is supplied with a reference potential (e.g., ground potential: 0V), which is a common potential VCOM, via a common potential wiring COM. The first transistor TFT-A, the second transistor TFT-B, and the third transistor TFT-C can be constructed using thin film transistors (TFTs). In transparent displays, polymer dispersed liquid crystal (PDLC) is used as the liquid crystal LC.

[0017] The gate of the first transistor TFT-A is connected to the second scan line G1B, one of the source and drain of the first transistor TFT-A is connected to the first signal line S1A, and the other of the source and drain of the first transistor TFT-A is connected to the pixel electrode PE via the first capacitive element CA.

[0018] The gate of the second transistor TFT-B is connected to the first scan line G1A, one of the source and drain of the second transistor TFT-B is connected to the first signal line S1A, and the other of the source and drain of the second transistor TFT-B is connected to the pixel electrode PE.

[0019] The gate of the third transistor TFT-C is connected to the first scan line G1A, one of the source and drain of the third transistor TFT-C is connected to the other of the source and drain of the first transistor TFT-A, and the other of the source and drain of the third transistor TFT-C is connected to the common electrode CE.

[0020] The timing will be explained using Figure 2. In Figure 2, the symbol - indicates negative polarity relative to the reference potential, and the symbol + indicates positive polarity relative to the reference potential. Also, one horizontal period (1H_PNL) of the display panel includes the first period P1 (also called the first half P1) and the second period P2 (also called the second half P2). One horizontal period (1H_PNL) of the display panel is, for example, the period during which display data is written to multiple pixels in one row of the display panel.

[0021] During the first half P1 of one horizontal period (1H_PNL) of the display panel, the first scan line G1A transitions from a low level (unselected state) to a high level (selected state), and both the second transistor TFT-B and the third transistor TFT-C are turned on. At this time, a voltage (+V1: for example, +6.1V) is written from the first signal line S1A to the capacitive element CA. Subsequently, the first scan line G1A transitions from a high level to a low level.

[0022] During the latter half of one horizontal period (1H_PNL) of the display panel, in P2, the second scan line G1B transitions from a low level (unselected state) to a high level (selected state), and the first transistor TFT-A is turned on. At this time, a voltage (+V1: e.g., +6.1V) is written from the first signal line S1A to the capacitive element CA. This causes the capacitive coupling by the capacitive element CA to raise the voltage of the pixel electrode PE. The voltage of the pixel electrode PE is raised (boosted) from, for example, +V1 (e.g., +6.1V) to +V2 (e.g., +14V). In the case of negative polarity, a potential of the opposite polarity is applied, and the voltage of the pixel electrode PE is lowered (stepped down) to, for example, -V2 (e.g., -14V).

[0023] After the display data is written to multiple pixels in the first row of the display panel, the data is then sequentially written to multiple pixels in the second row, and then to multiple pixels in the third row.

[0024] As a result, as shown in Figure 3, the voltage amplitude VppPE (amplitude between +V2 and -V2) of the pixel electrode PE can be made higher than the source output amplitude VppS (amplitude between +V1 and -V1) of the source driver IC, and the voltage applied to the liquid crystal LC can be made higher than the output voltage of the source driver IC.

[0025] However, in a typical pixel circuit, voltage is written to the pixel electrode only once during one horizontal period (1H_PNL). In a boost pixel, such as pixel PXr, it is necessary to alternately turn the transistors within the pixel (the first transistor TFT-A, the second transistor TFT-B, and the third transistor TFT-C) on and off during one horizontal period (1H_PNL). The scan line load is large, and it takes a considerable amount of time to alternately turn the transistors (the first transistor TFT-A, the second transistor TFT-B, and the third transistor TFT-C) on and off to write the voltage. Furthermore, transitioning scan lines G1A and G1B alternately from low level to high level, or from high level to low level, during one horizontal period (1H_PNL) requires the same amount of time as transitioning two lines of scan lines from low level to high level, or from high level to low level, in a typical pixel circuit.

[0026] Furthermore, driving a boosted pixel (PXr) requires switching the scan line twice during one horizontal period (1H_PNL), meaning that one horizontal period takes almost twice as long as driving a typical pixel (a non-boosted pixel). Therefore, although using a boosted pixel allows a higher voltage to be applied to the pixel electrode than the signal line output amplitude, the horizontal period is doubled, halving the number of rows that can be written in one frame. Consequently, the number of pixels (rows) that can be realized in a display panel using a boosted pixel is halved compared to a display device using a typical pixel.

[0027] Furthermore, as shown in Figure 1, the PXr pixel incorporates a boost circuit, resulting in an increase in the number of scan lines (second scan line G1B) compared to a typical pixel circuit. Additionally, the number of pixel components (second transistor TFT-B, third transistor TFT-C) increases, leading to a problem of reduced aperture ratio.

[0028] Furthermore, when the display device is a field-sequential drive such as a transparent display device, there are challenges such as the reduced illumination time of the LED (light-emitting diode) that illuminates the light-receiving part of the transparent light guide plate, which is installed to cover the transparent display part of the transparent display device.

[0029] Next, the examples will be described with reference to the drawings. [Examples]

[0030] Example 1 is a technique that can increase the number of pixels (rows) on which data is written in one horizontal period (1H_PNL) of the display panel compared to the comparative example. The number of source lines (signal lines) provided on the display panel is doubled, for example, by providing separate source lines (signal lines) for pixels in odd-numbered rows and pixels in adjacent even-numbered rows. By driving the gate lines (scan lines) simultaneously for odd-numbered and even-numbered rows and writing to the pixels, two rows can be driven in one horizontal period (1H_PNL), making it possible to effectively halve one horizontal period (1H_PNL).

[0031] Figure 4 shows an example configuration of the display device according to Example 1. Figure 5 shows an example configuration of the two pixels shown in Figure 4. Figure 6 shows a timing chart of the display device according to Example 1.

[0032] As shown in Figure 4, the display device 1 includes a display area 2 in which multiple pixels PX (PX11, PX12, ..., PX42) are arranged in a matrix, a gate drive circuit (GD) 3, and a signal line drive circuit (SD) 4. The display area 2 may also be referred to as a display panel.

[0033] The display area 2 includes multiple pixels PX and multiple scan lines GL (first scan line G1A, second scan line G1B, third scan line G2A, fourth scan line G2B, fifth scan line G3A, sixth scan line G3B, seventh scan line G4A, eighth scan line G4B, etc.) that extend in the first direction X and are arranged in the second direction Y that intersects with the first direction X. The multiple scan lines GL are connected to a gate drive circuit (GD) 3 and are configured to be driven by the gate drive circuit 3.

[0034] Furthermore, the display area 2 includes a plurality of signal lines SL (first signal line S1A, second signal line S1B, third signal line S2A, fourth signal line S2B, etc.) that extend in the second direction Y and are arranged in the first direction X. The plurality of signal lines SL are connected to the signal line drive circuit 4 and are configured to be driven by the signal line drive circuit 4.

[0035] The common potential wiring COM is connected to each pixel of multiple pixels PX and is configured to supply a reference potential, such as ground potential (0V).

[0036] A representative example of connecting multiple pixels PX, scan lines GL, and signal lines SL is described below.

[0037] Pixels PX11 and PX12 in the first row are connected to scan lines G1A and G1B. Pixel PX11 is connected to signal line S1A, and pixel PX12 is connected to signal line S2A.

[0038] Pixels PX21 and PX22 in the second row are connected to scan lines G2A and G2B. Pixel PX21 is connected to signal line S1B, and pixel PX22 is connected to signal line S2B.

[0039] Pixels PX31 and PX32 in the third row are connected to scan lines G3A and G3B. Pixel PX31 is connected to signal line S1A, and pixel PX32 is connected to signal line S2A.

[0040] Pixels PX41 and PX42 in the fourth row are connected to scan lines G4A and G4B. Pixel PX41 is connected to signal line S1B, and pixel PX42 is connected to signal line S2B.

[0041] In other words, a characteristic feature of Embodiment 1 is that, in multiple pixels PX, the signal line connecting a certain pixel (for example, the first pixel PX11) and another pixel adjacent to that pixel (for example, the second pixel PX21) in the second direction Y is different: for the first pixel (for example, the first pixel PX11), it is signal line S1A, while for the other pixel (for example, the second pixel PX21), it is not signal line S1A but signal line S1B.

[0042] Figure 5 shows a representative example of the pixel configuration of the first pixel PX11 and the second pixel PX21 adjacent to the first pixel PX11 in the second direction Y. The thin-film transistors TFTs (TFT-A, TFT-B, TFT-C) described herein are N-channel type, and are turned off when a low level (non-selective state) is applied to their gate, and turned on when a high level (selective state) is applied to their gate.

[0043] The first pixel PX11 has a first transistor TFT-A, a second transistor TFT-B, a third transistor TFT-C, and a first common electrode CE and a first pixel electrode PE separated by a liquid crystal LC. The first common electrode CE is supplied with a reference potential (e.g., ground potential: 0V) from a common potential wiring COM. A capacitive element CA is connected between the first pixel electrode PE and the first common electrode CE as a first retaining capacitance element.

[0044] The gate of the first transistor TFT-A is connected to the second scan line G1B, one of the source and drain of the first transistor TFT-A is connected to the first signal line S1A, and the other of the source and drain of the first transistor is connected to the first pixel electrode (PE) via the first capacitive element CA.

[0045] The gate of the second transistor TFT-B is connected to the first scan line G1A, one of the source and drain of the second transistor TFT-B is connected to the first signal line S1A, and the other of the source and drain of the second transistor TFT-B is connected to the first pixel electrode PE.

[0046] The gate of the third transistor TFT-C is connected to the first scan line G1A, one of the source and drain of the third transistor TFT-C is connected to the other of the source and drain of the first transistor TFT-A, and the other of the source and drain of the third transistor TFT-C is connected to the first common electrode CE.

[0047] The second pixel PX21 has a fourth transistor TFT-A, a fifth transistor TFT-B, a sixth transistor TFT-C, and a second common electrode CE and a second pixel electrode PE separated by a liquid crystal LC. The second common electrode CE is supplied with a reference potential (e.g., ground potential: 0V) from a common potential wiring COM. A capacitive element CA is connected between the second pixel electrode PE and the second common electrode CE as a second retaining capacitance element.

[0048] The gate of the fourth transistor TFT-A is connected to the fourth scan line G2B, one of the source and drain of the fourth transistor TFT-A is connected to the second signal line S1B, and the other of the source and drain of the fourth transistor TFT-A is connected to the second pixel electrode PE via the second capacitance element CA.

[0049] The gate of the fifth transistor TFT-B is connected to the third scan line G2A, one of the source and drain of the fifth transistor TFT-B is connected to the second signal line S1B, and the other of the source and drain of the fifth transistor TFT-B is connected to the second pixel electrode PE.

[0050] The gate of the sixth transistor TFT-C is connected to the third scan line G2A, one of the source and drain of the sixth transistor TFT-C is connected to the other of the source and drain of the fourth transistor TFT-A, and the other of the source and drain of the sixth transistor TFT-C is connected to the second common electrode CE.

[0051] The timing will be explained using Figure 6. In Figure 6, the symbol - indicates negative polarity with respect to the reference potential, and the symbol + indicates positive polarity with respect to the reference potential. Also, one horizontal period (1H_PNL) in the display area 2, which is the display panel, includes the first period P1 (also called the first period P1) and the second period P2 (also called the second period P2). Figure 6 depicts the first period P1, the second period P2 following the first period P1, the third period P3 following the second period P2, and the fourth period P4 following the third period P3. Furthermore, after the fourth period, the fifth period P5 following the fourth period P4, and the sixth period P6 following the fifth period P5 are also depicted. The first period P1 and the second period P2 are, for example, considered to be the first horizontal period, and the third period P3 and the fourth period P4 are, for example, considered to be the second horizontal period.

[0052] During the first period P1 and the second period P2, display data is written to multiple pixels in the first row (e.g., the first pixel PX11) and multiple pixels in the second row (e.g., the second pixel PX21). During the third period P3 and the fourth period P4, display data is written to multiple pixels in the third row (e.g., the third pixel PX31) and multiple pixels in the fourth row (e.g., the fourth pixel PX41). In the following explanation, the first pixel PX11, the second pixel PX21, the third pixel PX31, and the fourth pixel PX41 will be used as representative examples.

[0053] During the first period P1, the first scan line G1A and the third scan line G2A transition from a low level (unselected state) to a high level (selected state). The second transistor TFT-B and the third transistor TFT-C of the first pixel PX11 are both turned on. At this time, a voltage (+V1: for example, +6.1V) is written from the first signal line S1A to the first capacitance element CA of the first pixel PX11. Also, the fifth transistor TFT-B and the sixth transistor TFT-C of the second pixel PX21 are both turned on. At this time, a voltage (+V1: for example, +6.1V) is written from the second signal line S1B to the second capacitance element CA of the second pixel PX21. Subsequently, the first scan line G1A and the third scan line G2A transition from a high level to a low level. The second transistor TFT-B and third transistor TFT-C of the first pixel PX11, and the fifth transistor TFT-B and sixth transistor TFT-C of the second pixel PX21 are both turned off.

[0054] During the second period P2, the second scan line G1B and the fourth scan line G2B transition from a low level (unselected state) to a high level (selected state). The first transistor TFT-A of the first pixel PX11 is turned ON. At this time, a voltage (+V1: e.g., +6.1V) is written from the first signal line S1A to the first capacitance element CA of the first pixel PX11. As a result, the voltage of the first pixel electrode PE is raised (boosted) from, for example, +V1 (e.g., +6.1V) to +V2 (e.g., +14V). Also, the fourth transistor TFT-A of the second pixel PX21 is turned ON. At this time, a voltage (+V1: e.g., +6.1V) is written from the second signal line S1B to the second capacitance element CA of the second pixel PX21. As a result, the voltage of the second pixel electrode PE is boosted, for example, from +V1 (e.g., +6.1V) to +V2 (e.g., +14V). Subsequently, the second scan line G1B and the fourth scan line G2B transition from high level to low level. The first transistor TFT-A of the first pixel PX11 and the fourth transistor TFT-A of the second pixel PX21 are both turned off.

[0055] During the third period P3, the fifth scan line G3A and the seventh scan line G4A transition from a low level (unselected state) to a high level (selected state). Both transistors TFT-B and TFT-C of the third pixel PX31 are turned ON. At this time, a voltage (-V1: for example, -6.1V) is written from the first signal line S1A to the capacitive element CA of the third pixel PX31. Also, both transistors TFT-B and TFT-C of the fourth pixel PX41 are turned ON. At this time, a voltage (-V1: for example, -6.1V) is written from the second signal line S1B to the capacitive element CA of the fourth pixel PX41. Subsequently, the fifth scan line G3A and the seventh scan line G4A transition from a high level to a low level. Both transistors TFT-B and TFT-C of the third pixel PX31 and the fourth pixel PX41 are turned OFF.

[0056] During the fourth period P4, the sixth scan line G3B and the eighth scan line G4B transition from a low level (unselected state) to a high level (selected state). The transistor TFT-A of the third pixel PX31 is turned ON. At this time, a voltage (-V1: e.g., -6.1V) is written from the first signal line S1A to the capacitive element CA of the third pixel PX31. As a result, the voltage of the pixel electrode PE of the third pixel PX31 is pushed down (stepped down) from, for example, -V1 (e.g., -6.1V) to -V2 (e.g., -14V). Also, the transistor TFT-A of the fourth pixel PX41 is turned ON. At this time, a voltage (-V1: e.g., -6.1V) is written from the second signal line S1B to the capacitive element CA of the fourth pixel PX41. As a result, the voltage of the pixel electrode PE of the third pixel PX31 is pushed down (stepped down) from, for example, -V1 (e.g., -6.1V) to -V2 (e.g., -14V). Subsequently, the sixth scan line G3B and the eighth scan line G4B transition from high level to low level. Transistor TFT-A of the third pixel PX31 and transistor TFT-A of the fourth pixel PX41 are both turned off.

[0057] During the fifth period P5 and the sixth period P6, display data is written to multiple pixels in the fifth row (for example, the fifth pixel PX51) and multiple pixels in the sixth row (for example, the sixth pixel PX61), in the same manner as described above.

[0058] Through the operations described above, data will be written to each line of the display area 2 of the display device 1.

[0059] Therefore, it can be summarized as follows:

[0060] During the first period P1 and the second period P2, a positive (+) voltage is applied to the first signal line S1A and the second signal line S1B with respect to the reference potential. During the third period P3 and the fourth period P4, a voltage with negative polarity (-) relative to the reference potential is applied to the first signal line S1A and the second signal line S1B. During the first period P1, the first scan line G1A and the third scan line G2A transition in the order of low level, high level, and low level. During the second period P2, the second scan line G1B and the fourth scan line G2B transition in the order of low level, high level, and low level.

[0061] As described above, pixels with a built-in boost circuit can be realized without reducing the number of pixels (rows), the amplitude of the pixel electrode PE can be increased relative to the output amplitude of the source driver IC (signal line driving circuit 4), and the voltage applied to the liquid crystal LC can be increased.

[0062] In a boosted pixel, the horizontal period is twice that of a typical display pixel. So, if we let H be the horizontal period of a typical pixel, and the number of pixels (rows) is y, then for the entire screen... (y × H × 2) This will take some time.

[0063] By doubling the number of signal lines, the apparent horizontal period can be halved, (y × H × 2) ÷ 2 = (y × H) This allows for the same processing time as a standard pixel (not a boosted pixel), effectively reducing the horizontal processing time while ensuring sufficient writing time. [Examples]

[0064] The boosted pixel PX described in Example 1 has a configuration in which each pixel consists of one signal line, one capacitive element, three transistors, and two scan lines.

[0065] In the boosted pixel drive, during the first half of one horizontal period (periods P1 and P3), two transistors TFT-B and TFT-C are turned on to charge the capacitive element CA, and during the second half of one horizontal period (periods P2 and P4), the remaining transistor TFT-A is turned on to raise the voltage of the pixel electrode PE through capacitive coupling, driving the pixel electrode PE to a voltage higher than the voltage written to the signal line. In Example 1, the scan lines are turned on sequentially to drive the pixel.

[0066] In Example 2, two pixels adjacent to each other in the second direction Y share one scan line each. This allows for the simultaneous driving of two scan lines: one for controlling transistor TFT-A to raise the pixel voltage PE in the latter half of the horizontal period (P2) of the previous row, and another for controlling transistors TFT-B and TFT-C to write charge to the capacitive element CA in the first half of the horizontal period (P3) of the next row. This shortens the apparent horizontal period and improves the aperture ratio by reducing the number of scan lines.

[0067] In Example 2, during the first half of one horizontal period (P1), when the scan line of the nth row becomes high level, the signal line voltage (S1A) is written to one side of the capacitance CA of the nth row, and the voltage of the common potential wiring COM (0V) is written to the other side. During the second half of one horizontal period (P2), when the scan line of the (n+1)th row becomes high level, the signal line voltage (S1A) is written to the electrode side of the capacitance CA on the side where the voltage of the common potential wiring COM (0V) was written, and the pixel electrode (PE) is lifted by capacitive coupling. At the same time, the signal line voltage (S1B) is written to one side of the capacitance CA of the (n+1)th row pixel, and the voltage of the common potential wiring COM (0V) is written to the other side. The operation of driving is then repeated in a similar manner.

[0068] The following explanation will use diagrams.

[0069] Figure 7 shows an example configuration of the display device according to Example 2. Figure 8 shows an example configuration of the three pixels shown in Figure 7. Figure 9 shows a timing chart of the display device according to Example 2.

[0070] As shown in Figure 7, the display device 1a includes a display area 2 in which multiple pixels PX (PX11, PX12, ..., PX42) are arranged in a matrix, a gate drive circuit (GD) 3, and a signal line drive circuit (SD) 4. The display area 2 may also be referred to as a display panel.

[0071] The display area 2 includes multiple pixels PX and multiple scan lines GL (first scan line G1, second scan line G2, third scan line G3, fourth scan line G4, fifth scan line G5, etc.) that extend in a first direction X and are arranged in a second direction Y that intersects with the first direction X. The multiple scan lines GL are connected to a gate drive circuit (GD) 3 and are configured to be driven by the gate drive circuit 3.

[0072] Furthermore, the display area 2 includes a plurality of signal lines SL (first signal line S1A, second signal line S1B, third signal line S2A, fourth signal line S2B, etc.) that extend in the second direction Y and are arranged in the first direction X. The plurality of signal lines SL are connected to the signal line drive circuit 4 and are configured to be driven by the signal line drive circuit 4.

[0073] The common potential wiring COM is connected to each pixel of multiple pixels PX and is configured to supply a reference potential, such as ground potential (0V).

[0074] A representative example of connecting multiple pixels PX, scan lines GL, and signal lines SL is described below.

[0075] Pixels PX11 and PX12 in the first row are connected to scan lines G1 and G2. Pixel PX11 is connected to signal line S1A, and pixel PX12 is connected to signal line S2A.

[0076] Pixels PX21 and PX22 in the second row are connected to scan lines G2 and G3. Pixel PX21 is connected to signal line S1B, and pixel PX22 is connected to signal line S2B.

[0077] Pixels PX31 and PX32 in the third row are connected to scan lines G3 and G4. Pixel PX31 is connected to signal line S1A, and pixel PX32 is connected to signal line S2A.

[0078] Pixels PX41 and PX42 in the fourth row are connected to scan lines G4 and G5. Pixel PX41 is connected to signal line S1B, and pixel PX42 is connected to signal line S2B.

[0079] In other words, a characteristic feature of Embodiment 1 is that, in multiple pixels PX, the signal line connecting a certain pixel (for example, the first pixel PX11) and another pixel adjacent to that pixel (for example, the second pixel PX21) in the second direction Y is different: for the first pixel (for example, the first pixel PX11), it is signal line S1A, while for the other pixel (for example, the second pixel PX21), it is not signal line S1A but signal line S1B.

[0080] Figure 8 shows a representative example of the pixel configuration of the first pixel PX11 and the second pixel PX21 adjacent to the first pixel PX11 in the second direction Y.

[0081] The first pixel PX11 has a first transistor TFT-A, a second transistor TFT-B, a third transistor TFT-C, and a first common electrode CE and a first pixel electrode PE separated by a liquid crystal LC. The first common electrode CE is supplied with a reference potential, such as ground potential (0V), from a common potential wiring COM.

[0082] The gate of the first transistor TFT-A is connected to the second scan line G2, one of the source and drain of the first transistor TFT-A is connected to the first signal line S1A, and the other of the source and drain of the first transistor TFT-A is connected to the first pixel electrode PE via the first capacitive element CA.

[0083] The gate of the second transistor TFT-B is connected to the first scan line G1, one of the source and drain of the second transistor TFT-B is connected to the first signal line S1A, and the other of the source and drain of the second transistor TFT-B is connected to the first pixel electrode PE.

[0084] The gate of the third transistor TFT-C is connected to the first scan line G1, one of the source and drain of the third transistor TFT-C is connected to the other of the source and drain of the first transistor TFT-A, and the other of the source and drain of the third transistor TFT-C is connected to the first common electrode CE.

[0085] The second pixel PX21 has a fourth transistor TFT-A, a fifth transistor TFT-B, a sixth transistor TFT-C, and a second common electrode CE and a second pixel electrode PE separated by a liquid crystal LC. The second common electrode CE is supplied with a reference potential of 0V from the common potential wiring COM.

[0086] The gate of the fourth transistor TFT-A is connected to the third scan line G3, one of the source and drain of the fourth transistor TFT-A is connected to the second signal line S1B, and the other of the source and drain of the fourth transistor TFT-A is connected to the second pixel electrode PE via the second capacitance element CA.

[0087] The gate of the fifth transistor TFT-B is connected to the second scan line G2, one of the source and drain of the fifth transistor TFT-B is connected to the second signal line S1B, and the other of the source and drain of the fifth transistor TFT-B is connected to the second pixel electrode PE.

[0088] The gate of the sixth transistor TFT-C is connected to the second scan line G2, one of the source and drain of the sixth transistor TFT-C is connected to the other of the source and drain of the fourth transistor TFT-A, and the other of the source and drain of the sixth transistor TFT-C is connected to the second common electrode CE.

[0089] The timing will be explained using Figure 9. In Figure 9, the symbol - indicates negative polarity with respect to the reference potential, and the symbol + indicates positive polarity with respect to the reference potential. Also, one horizontal period (1H_PNL) in the display area 2, which is the display panel, includes the first period P1 (also called the first period P1) and the second period P2 (also called the second period P2). Figure 9 depicts the first period P1, the second period P2 following the first period P1, the third period P3 following the second period P2, and the fourth period P4 following the third period P3. Furthermore, after the fourth period, the fifth period P5 following the fourth period P4, and the sixth period P6 following the fifth period P5 are also depicted. The first period P1 and the second period P2 are, for example, considered to be the first horizontal period, and the third period P3 and the fourth period P4 are, for example, considered to be the second horizontal period.

[0090] During the first period P1 and the second period P2, display data is written to multiple pixels in the first row (for example, the first pixel PX11). During the second period P2 and the third period P3, display data is written to multiple pixels in the second row (for example, the second pixel PX21). During the third period P3 and the fourth period P4, display data is written to multiple pixels in the third row (for example, the third pixel PX31). During the fourth period P4 and the fifth period P5, display data is written to multiple pixels in the fourth row (for example, the fourth pixel PX41). During the fifth period P5 and the sixth period P6, display data is written to multiple pixels in the fifth row (for example, the fifth pixel PX51). In the following explanation, the first pixel PX11 and the second pixel PX21 will be used as representative examples.

[0091] During the first period P1, the first scan line G1 transitions from a low level (unselected state) to a high level (selected state). The second scan line G2 and the third scan line G3 are at a low level. As a result, both the second transistor TFT-B and the third transistor TFT-C of the first pixel PX11 are turned on. At this time, a voltage (+V1: for example, +6.1V) is written from the first signal line S1A to the first capacitive element CA of the first pixel PX11. The voltage of the second signal line S1B is -V1: for example, -6.1V. Subsequently, the first scan line G1 transitions from a high level to a low level. As a result, the second transistor TFT-B and the third transistor TFT-C are turned off.

[0092] During the second period P2, the second scan line G2 transitions from a low level (unselected state) to a high level (selected state). The first scan line G1 and the third scan line G3 are at a low level. As a result, the first transistor TFT-A of the first pixel PX11 is turned on. At this time, a voltage (+V1: e.g., +6.1V) is written from the first signal line S1A to the first capacitance element CA of the first pixel PX11. As a result, the voltage of the first pixel electrode PE is raised (boosted) from, for example, +V1 (e.g., +6.1V) to +V2 (e.g., +14V). Also, the fifth transistor TFT-B and the sixth transistor TFT-C of the second pixel PX21 are both turned on. At this time, a voltage (+V1: e.g., +6.1V) is written from the second signal line S1B to the second capacitance element CA of the second pixel PX21. After that, the second scan line G2 transitions from a high level to a low level. As a result, the first transistor TFT-A, the fifth transistor TFT-B, and the sixth transistor TFT-C are turned off.

[0093] During the third period P3, the third scan line G3 transitions from a low level (unselected state) to a high level (selected state). The first scan line G1 and the second scan line G2 are at a low level. As a result, the fourth transistor TFT-A of the second pixel PX21 is turned on. At this time, a voltage (+V1: e.g., +6.1V) is written from the second signal line S1B to the first capacitive element CA of the second pixel PX21. As a result, the voltage of the second pixel electrode PE is raised (boosted) from, for example, +V1 (e.g., +6.1V) to +V2 (e.g., +14V). Also, both transistors TFT-B and TFT-C of the third pixel PX31 are turned on. At this time, a voltage (-V1: e.g., -6.1V) is written from the first signal line S1A to the capacitive element CA of the third pixel PX31. After that, the third scan line G3 transitions from a high level to a low level. As a result, the fourth transistor TFT-A, and the third pixel PX31 transistors TFT-B and TFT-C are turned off.

[0094] During the fourth period P4, the fourth scan line G4 transitions from a low level (unselected state) to a high level (selected state). This turns on the transistor TFT-A of the third pixel PX31. A voltage (-V1: e.g., -6.1V) is written to the capacitive element CA of the third pixel PX31 from the first signal line S1A. As a result, the voltage of the third pixel electrode PE is stepped down from, for example, -V1 (e.g., -6.1V) to -V2 (e.g., -14V). Also, both the transistors TFT-B and TFT-C of the fourth pixel PX41 are turned on. At this time, a voltage (-V1: e.g., -6.1V) is written to the capacitive element CA of the fourth pixel PX41 from the second signal line S1B. After that, the fourth scan line G4 transitions from a high level to a low level.

[0095] During the fifth period P5 and the sixth period P6, the above operations are repeated, and display data is written to multiple pixels in the third row (for example, the third pixel PX31), multiple pixels in the fourth row (for example, the fourth pixel PX41), and multiple pixels in the fifth row (for example, the fifth pixel PX51).

[0096] Through the operations described above, data will be written to each line of the display area 2 of the display device 1.

[0097] Therefore, it can be summarized as follows: During the first period P1 and the second period P2, a voltage with positive polarity relative to the reference potential is continuously applied to the first signal line S1A. During the third period P3 and the fourth period P4, a voltage with negative polarity relative to the reference potential is continuously applied to the first signal line S1A. During the first period P1, a potential with negative polarity relative to the reference potential is applied to the second signal line S1B. During the second period P2 and the third period P3, a voltage with positive polarity relative to the reference potential is continuously applied to the second signal line S1B. During the fourth period P4, a voltage with negative polarity relative to the reference potential is applied to the second signal line S1B. During the first period P1, the first scan line G1 transitions in the order of low level, high level, and low level. During the second period P2, the second scan line G2 transitions in the order of low level, high level, and low level. During the third period P3, the third scan line G3 transitions in the order of low level, high level, and low level.

[0098] In this way, by simultaneously superimposing the driving of the first half of the horizontal period of the pixel in the nth row with the driving of the pixel in the (n+1)th row, the pixels in the yth row as a whole will be: (y+1)×H=(y×H)+H By increasing the processing time by only H, it can be done in almost the same amount of time as with typical pixels.

[0099] Conventional boosted pixels require twice the time for one horizontal period compared to a typical pixel, so in a display device where y rows exist across the entire screen, (y × H × 2) This requires twice the time, meaning the number of pixel rows that can be driven per frame is halved.

[0100] In Examples 1 and 2, the apparent horizontal period is equivalent to that of a typical pixel. In Example 2, since adjacent pixels above and below share scan lines, the number of scan lines per pixel can be reduced to the equivalent of one and a half. Therefore, Example 2 has a higher aperture ratio and is advantageous compared to Example 1.

[0101] As a result, pixels with built-in boost circuits can be realized without reducing the number of pixels (rows), the amplitude of the pixel electrode PE can be increased relative to the output amplitude of the source driver IC (signal line driving circuit 4), and the voltage applied to the liquid crystal LC can be increased. Furthermore, a transparent display with high display performance can be provided using a general-purpose source driver IC.

[0102] (Transparent display) Next, a transparent display will be described using Figures 10A, 10B, 11A, and 11B. Figure 10A is a schematic diagram showing the liquid crystal layer 30 in a transparent state. Figure 10B is a schematic diagram showing the liquid crystal layer 30 in a scattered state. Figure 11A is a cross-sectional view showing the display panel PNL when the liquid crystal layer 30 is in a transparent state. Figure 11B is a cross-sectional view showing the display panel PNL when the liquid crystal layer 30 is in a scattered state.

[0103] In the following description, the display devices 1 and 1a, which are transparent displays, are described as display panels, and the liquid crystal LC is described as the liquid crystal layer 30. Below, an example configuration of a display device equipped with a liquid crystal layer 30 which is a polymer-dispersed liquid crystal (PDLC) layer is described.

[0104] Figure 10A is a schematic diagram showing the transparent liquid crystal layer 30. As shown in Figure 10A, the liquid crystal layer 30 contains a liquid crystalline polymer 31 and liquid crystalline molecules 32. The liquid crystalline polymer 31 is obtained, for example, by polymerizing liquid crystalline monomers in a state where they are oriented in a predetermined direction by the orientation restricting force of the alignment films AF1 and AF2. The liquid crystalline molecules 32 are dispersed within the liquid crystalline monomers and are oriented in a predetermined direction depending on the orientation direction of the liquid crystalline monomers when the liquid crystalline monomers are polymerized. The alignment films AF1 and AF2 may be horizontal alignment films that orient the liquid crystalline monomers and liquid crystalline molecules 32 along the XY plane defined by the first direction X and the second direction Y, or they may be vertical alignment films that orient the liquid crystalline monomers and liquid crystalline molecules 32 along the third direction Z.

[0105] The liquid crystalline molecule 32 may be a positive-type molecule with positive dielectric anisotropy, or a negative-type molecule with negative dielectric anisotropy. The liquid crystalline polymer 31 and the liquid crystalline molecule 32 each have equivalent optical anisotropy. Alternatively, the liquid crystalline polymer 31 and the liquid crystalline molecule 32 each have approximately equivalent refractive index anisotropy. That is, the ordinary refractive index and the extraordinary refractive index of the liquid crystalline polymer 31 and the liquid crystalline molecule 32 are approximately equivalent. Note that the values ​​of the ordinary refractive index and the extraordinary refractive index of the liquid crystalline polymer 31 and the liquid crystalline molecule 32 do not need to be exactly the same, and deviations due to manufacturing errors, etc., are acceptable. Furthermore, the responsiveness of the liquid crystalline polymer 31 and the liquid crystalline molecule 32 to electric fields are different. That is, the responsiveness of the liquid crystalline polymer 31 to electric fields is lower than that of the liquid crystalline molecule 32 to electric fields.

[0106] The example shown in Figure 10A corresponds, for example, to a state where no voltage is applied to the liquid crystal layer 30 (a state where the potential difference between the pixel electrode PE and the common electrode CE is zero), or to a state where the second transparency voltage, described later, is applied to the liquid crystal layer 30.

[0107] As shown in Figure 10A, the optical axis Ax1 of the liquid crystalline polymer 31 and the optical axis Ax2 of the liquid crystalline molecule 32 are parallel to each other. In the illustrated example, both optical axes Ax1 and Ax2 are parallel to the third direction Z. Here, the optical axis corresponds to a line parallel to the direction of propagation of a light ray such that the refractive index is a single value regardless of the polarization direction.

[0108] As described above, the liquid crystalline polymer 31 and the liquid crystalline molecules 32 have approximately equivalent refractive index anisotropy, and furthermore, since the optical axes Ax1 and Ax2 are parallel to each other, there is almost no difference in refractive index between the liquid crystalline polymer 31 and the liquid crystalline molecules 32 in all directions, including the first direction X, the second direction Y, and the third direction Z. For this reason, light L1 incident on the liquid crystal layer 30 in the third direction Z is transmitted within the liquid crystal layer 30 without being substantially scattered. The liquid crystal layer 30 can maintain the parallelism of light L1. Similarly, light L2 and L3 incident in an oblique direction tilted with respect to the third direction Z are also hardly scattered within the liquid crystal layer 30. For this reason, high transparency is obtained. The state shown in Figure 10A is referred to as the "transparent state".

[0109] Figure 10B schematically shows the liquid crystal layer 30 in a scattering state. As shown in Figure 10B, as described above, the response of the liquid crystalline polymer 31 to the electric field is lower than the response of the liquid crystalline molecules 32 to the electric field. Therefore, when a voltage higher than the second transparency voltage and the first transparency voltage (described later) is applied to the liquid crystal layer 30, the orientation direction of the liquid crystalline polymer 31 hardly changes, while the orientation direction of the liquid crystalline molecules 32 changes in response to the electric field. In other words, as shown in the figure, the optical axis Ax1 is almost parallel to the third direction Z, while the optical axis Ax2 is tilted with respect to the third direction Z. Therefore, the optical axes Ax1 and Ax2 intersect each other. Consequently, a large refractive index difference occurs between the liquid crystalline polymer 31 and the liquid crystalline molecules 32 in all directions, including the first direction X, the second direction Y, and the third direction Z. As a result, the light L1 to L3 incident on the liquid crystal layer 30 is scattered within the liquid crystal layer 30. The state shown in Figure 10B is called the 'scattering state'.

[0110] The above-mentioned drive unit DR switches the liquid crystal layer 30 to at least one of a transparent state and a scattered state.

[0111] Figure 11A is a cross-sectional view showing a display panel PNL when the liquid crystal layer 30 is transparent. As shown in Figure 11A, illumination light L11 emitted from the light-emitting element LS enters the display panel PNL from the edge 20E and propagates through the transparent substrate 20, the liquid crystal layer 30, the transparent substrate 10, etc. When the liquid crystal layer 30 is transparent, the illumination light L11 is hardly scattered by the liquid crystal layer 30, so it hardly leaks out from the lower surface 10B of the transparent substrate 10 and the upper surface 20T of the transparent substrate 20. The transparent substrate 10 can be made up of, for example, a cover glass and an array substrate provided above the cover glass. The transparent substrate 20 can be made up of a transparent light guide plate and a counter substrate facing the array substrate provided below the transparent light guide plate. The liquid crystal layer 30 is provided between the array substrate and the counter substrate.

[0112] External light L12 incident on the display panel PNL is transmitted through the liquid crystal layer 30 with almost no scattering. In other words, external light incident on the display panel PNL from the bottom surface 10B is transmitted to the top surface 20T, and external light incident on the top surface 20T is transmitted to the bottom surface 10B. Therefore, when the display panel PNL is observed from the top surface 20T side, the user can see the background on the bottom surface 10B side by looking through the display panel PNL. Similarly, when the display panel PNL is observed from the bottom surface 10B side, the user can see the background on the top surface 20T side by looking through the display panel PNL.

[0113] Figure 11B is a cross-sectional view showing a display panel PNL when the liquid crystal layer 30 is in a scattering state. As shown in Figure 11B, illumination light L21 emitted from the light-emitting element LS enters the display panel PNL from the edge 20E and propagates through the transparent substrate 20, the liquid crystal layer 30, the transparent substrate 10, etc. In the illustrated example, the liquid crystal layer 30 between the pixel electrode PEα and the common electrode CE (the liquid crystal layer to which the voltage applied between the pixel electrode PEα and the common electrode CE is applied) is transparent, so the illumination light L21 is hardly scattered in the region of the liquid crystal layer 30 facing the pixel electrode PEα. On the other hand, the liquid crystal layer 30 between the pixel electrode PEβ and the common electrode CE (the liquid crystal layer to which the voltage applied between the pixel electrode PEβ and the common electrode CE is applied) is in a scattering state, so the illumination light L21 is scattered in the region of the liquid crystal layer 30 facing the pixel electrode PEβ. Of the illumination light L21, some scattered light L211 is emitted to the outside from the upper surface 20T, and some scattered light L212 is emitted to the outside from the lower surface 10B.

[0114] At the position overlapping with the pixel electrode PEα, the external light L22 incident on the display panel PNL is transmitted through the liquid crystal layer 30 with almost no scattering, similar to the external light L12 shown in Figure 11A. At the position overlapping with the pixel electrode PEβ, the external light L23 incident from the lower surface 10B is transmitted through the upper surface 20T after some of its light L231 is scattered by the liquid crystal layer 30. Similarly, the external light L24 incident from the upper surface 20T is transmitted through the lower surface 10B after some of its light L241 is scattered by the liquid crystal layer 30.

[0115] Therefore, when the display panel PNL is observed from the top surface 20T side, the color of the illumination light L21 can be seen at the position where it overlaps with the pixel electrode PEβ. In addition, since some of the external light L231 passes through the display panel PNL, the background on the bottom surface 10B side can also be seen by looking through the display panel PNL. Similarly, when the display panel PNL is observed from the bottom surface 10B side, the color of the illumination light L21 can be seen at the position where it overlaps with the pixel electrode PEβ. In addition, since some of the external light L241 passes through the display panel PNL, the background on the top surface 20T side can also be seen by looking through the display panel PNL. Note that at the position where it overlaps with the pixel electrode PEα, the liquid crystal layer 30 is transparent, so the color of the illumination light L21 is hardly visible, and the background can be seen by looking through the display panel PNL.

[0116] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of this disclosure also fall within the scope of this disclosure, insofar as they encompass the gist of this disclosure.

[0117] Within the scope of the ideas presented herein, a person skilled in the art will be able to conceive of various modifications and alterations, and such modifications and alterations will also be understood to fall within the scope of this disclosure. For example, any addition, deletion, or design change of components, or addition, omission, or modification of processes, to the above embodiments, as appropriate by a person skilled in the art, will also be included within the scope of this disclosure, as long as they retain the gist of this disclosure.

[0118] Furthermore, any other effects and advantages brought about by the embodiments described herein that are obvious from this specification or that can be appropriately conceived by those skilled in the art are naturally provided by this disclosure.

[0119] Various disclosures can be formed by appropriately combining the multiple components disclosed in the above embodiments. For example, some components may be removed from all the components shown in the embodiments. Furthermore, components from different embodiments may be appropriately combined. [Explanation of Symbols]

[0120] 1, 1a: Display device, 2: Display area, 3: Gate drive circuit (GD), 4: Signal line drive circuit (SD), PX: Multiple pixels, LC: Liquid crystal, CE: Common electrode, PE: Pixel electrode, SL: Signal line, TFT-A, TFT-B, TFT-C: Transistor, CA: Capacitive element.

Claims

1. Multiple pixels arranged in a matrix, A first scan line, a second scan line, a third scan line, and a fourth scan line extending in a first direction and arranged in a second direction intersecting the first direction, A first signal line and a second signal line extending in the second direction and arranged in the first direction, The plurality of pixels include a first pixel and a second pixel adjacent to the first pixel in the second direction, The first pixel comprises a first transistor, a second transistor, a third transistor, a first common electrode and a first pixel electrode separated by a liquid crystal, and a reference potential is supplied to the first common electrode. The gate of the first transistor is connected to the second scan line, one of the source and drain of the first transistor is connected to the first signal line, and the other of the source and drain of the first transistor is connected to the first pixel electrode via a first capacitive element. The gate of the second transistor is connected to the first scan line, one of the source and drain of the second transistor is connected to the first signal line, and the other of the source and drain of the second transistor is connected to the first pixel electrode. The gate of the third transistor is connected to the first scan line, one of the source and drain of the third transistor is connected to the other of the source and drain of the first transistor, and the other of the source and drain of the third transistor is connected to the first common electrode. The second pixel has a fourth transistor, a fifth transistor, a sixth transistor, a second common electrode and a second pixel electrode sandwiching the liquid crystal, and a reference potential is supplied to the second common electrode. The gate of the fourth transistor is connected to the fourth scan line, one of the source and drain of the fourth transistor is connected to the second signal line, and the other of the source and drain of the fourth transistor is connected to the second pixel electrode via a second capacitance element. The gate of the fifth transistor is connected to the third scan line, one of the source and drain of the fifth transistor is connected to the second signal line, and the other of the source and drain of the fifth transistor is connected to the second pixel electrode. A display device in which the gate of the sixth transistor is connected to the third scanning line, one of the source and drain of the sixth transistor is connected to the other of the source and drain of the fourth transistor, and the other of the source and drain of the sixth transistor is connected to the second common electrode.

2. In the display device according to claim 1, It has a first period, a second period following the first period, a third period following the second period, and a fourth period following the third period. During the first and second periods, a voltage of positive polarity relative to the reference potential is applied to the first and second signal lines. During the third and fourth periods, a voltage with negative polarity relative to the reference potential is applied to the first signal line and the second signal line. During the first period, the first scan line and the third scan line transition in the order of low level, high level, and low level. A display device in which, during the second period, the second scan line and the fourth scan line transition in the order of low level, high level, and low level.

3. In the display device according to claim 1, The liquid crystal is a polymer-dispersed liquid crystal, which is used in the display device.

4. Multiple pixels arranged in a matrix, A first scan line, a second scan line, and a third scan line extending in a first direction and arranged in a second direction intersecting the first direction, Including a first signal line and a second signal line extending in the second direction and arranged in the first direction, The plurality of pixels are arranged adjacent to each other in the second direction and include a first pixel and a second pixel, The first pixel has a first transistor, a second transistor, a third transistor, a first common electrode and a first pixel electrode separated by a liquid crystal, and a reference potential is supplied to the first common electrode. The gate of the first transistor is connected to the second scan line, one of the source and drain of the first transistor is connected to the first signal line, and the other of the source and drain of the first transistor is connected to the first pixel electrode via a first capacitive element. The gate of the second transistor is connected to the first scan line, one of the source and drain of the second transistor is connected to the first signal line, and the other of the source and drain of the second transistor is connected to the first pixel electrode. The gate of the third transistor is connected to the first scan line, one of the source and drain of the third transistor is connected to the other of the source and drain of the first transistor, and the other of the source and drain of the third transistor is connected to the first common electrode. The second pixel has a fourth transistor, a fifth transistor, a sixth transistor, a second common electrode and a second pixel electrode sandwiching the liquid crystal, and the reference potential is supplied to the second common electrode. The gate of the fourth transistor is connected to the third scan line, one of the source and drain of the fourth transistor is connected to the second signal line, and the other of the source and drain of the fourth transistor is connected to the second pixel electrode via a second capacitance element. The gate of the fifth transistor is connected to the second scan line, one of the source and drain of the fifth transistor is connected to the second signal line, and the other of the source and drain of the fifth transistor is connected to the second pixel electrode. A display device in which the gate of the sixth transistor is connected to the second scanning line, one of the source and drain of the sixth transistor is connected to the other of the source and drain of the fourth transistor, and the other of the source and drain of the sixth transistor is connected to the second common electrode.

5. In the display device according to claim 4, It has a first period, a second period following the first period, and a third period following the second period. During the first and second periods, a voltage with positive polarity relative to the reference potential is continuously applied to the first signal line. During the third and fourth periods, a voltage with negative polarity relative to the reference potential is continuously applied to the first signal line. During the first period, a potential with negative polarity relative to the reference potential is applied to the second signal line. During the second and third periods, a voltage with positive polarity relative to the reference potential is continuously applied to the second signal line. During the fourth period, a voltage with negative polarity relative to the reference potential is applied to the second signal line. During the first period, the first scan line transitions in the order of low level, high level, low level, During the second period, the second scan line transitions in the order of low level, high level, low level. A display device in which, during the third period, the third scan line transitions in the order of low level, high level, and low level.

6. In the display device according to claim 4, The liquid crystal is a polymer-dispersed liquid crystal, which is used in the display device.

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