Gate drive circuit adapted to high junction temperature environment and its turn-on and turn-off methods

Abstract

A gate drive circuit adapted to high junction temperature environments, and its turn-on and turn-off methods, are disclosed. The gate drive circuit includes a main three-terminal transistor, a turn-off circuit, and an auxiliary circuit. The added auxiliary circuit generates an auxiliary current signal, either in the same direction or opposite to the control signal current, to the control electrode of the main three-terminal transistor during the turn-on and turn-off processes within a preset time period. This disclosure enables the generation of corresponding positive or negative auxiliary current signals at the control electrode of the three-terminal transistor. During the conduction process, the auxiliary circuit can generate a reverse auxiliary current signal at the control electrode of the three-terminal transistor during the current rise phase, reducing the drive current of the turn-on signal to decrease di. d / dt, suppressing the turn-on current; during the turn-off process, the auxiliary circuit can generate a unidirectional auxiliary current signal at the control electrode of the three-terminal transistor in the current-decreasing segment, increasing the drive current of the turn-off signal and accelerating the turn-off speed.

Description

Technical Field

[0001] This disclosure belongs to the field of power electronics technology, specifically relating to a gate drive circuit adapted to high junction temperature environments and its turn-on and turn-off methods. Background Technology

[0002] In high-power applications, the system devices experience high current and corresponding losses, leading to a significant increase in junction temperature. Power devices made of traditional silicon (Si) materials have low temperature tolerance, narrow bandgap, and low blocking voltage, making them unsuitable for the requirements of next-generation power systems. As junction temperature increases, the electrical characteristics of three-terminal transistors change, and their switching characteristics also change accordingly. Traditional drives are not suitable for high junction temperature environments.

[0003] In power electronic devices, due to wiring, packaging, and other reasons, three-terminal transistors themselves and their circuits contain parasitic inductance and capacitance. Under these circumstances, high-speed switching three-terminal transistors have extremely high voltage and current change rates, which can easily lead to voltage overshoot, current overshoot, and oscillation problems. Summary of the Invention

[0004] To address the aforementioned technical problems, the primary objective of this disclosure is to provide a gate drive circuit adapted to high junction temperature environments that solves the problem of low temperature resistance in conventional drive circuits, reduces current and voltage overshoot during device switching, and thereby reduces losses.

[0005] The second objective of this disclosure is to provide a turn-on method based on the above-described gate drive circuit adapted to high junction temperature environments.

[0006] A third objective of this disclosure is to provide a turn-off method based on the above-described gate drive circuit adapted to high junction temperature environments.

[0007] To achieve the primary objective of this disclosure, the technical solution adopted in this disclosure is as follows:

[0008] A gate drive circuit adapted to high junction temperature environments includes:

[0009] The main three-terminal transistor can be turned on or off according to a control signal;

[0010] The on / off circuit connected to the control electrode of the main three-terminal transistor can send a control signal to the control electrode of the main three-terminal transistor.

[0011] An auxiliary circuit connected to the control electrode of the main three-terminal transistor is used to generate an auxiliary current signal that is in the same direction or opposite to the control signal current to the control electrode of the main three-terminal transistor within a preset time period when the main three-terminal transistor is in the turn-on and turn-off process.

[0012] Optionally, the turn-on / turn-off circuit includes a turn-on circuit and a turn-off circuit, the turn-on circuit is connected to the main three-terminal transistor, and the auxiliary circuit is connected to the main three-terminal transistor through the turn-off circuit.

[0013] Optionally, the shutdown circuit includes a first three-terminal transistor, a first resistor, a second resistor, and a current mirror source;

[0014] The first terminal of the first three-terminal transistor is connected to a voltage source;

[0015] The second terminal of the first three-terminal transistor is connected to the reference current terminal of the mirror current source and the auxiliary circuit respectively through the first resistor;

[0016] The output current terminal of the mirror current source is connected to the control electrode of the main three-terminal transistor after passing through the second resistor.

[0017] Optionally, the auxiliary circuit includes a second three-terminal transistor and a third resistor;

[0018] The first terminal of the second three-terminal transistor is connected to the voltage source;

[0019] The second terminal of the second three-terminal transistor is connected to the reference current terminal of the mirror current source through the third resistor.

[0020] Optionally, the mirror current source includes a reference three-terminal transistor and at least one output three-terminal transistor;

[0021] The reference power supply terminal of the mirror current source is connected to the first terminal of the reference three-terminal transistor, the control terminal of the reference three-terminal transistor, and the control terminal of the output three-terminal transistor, respectively.

[0022] The first terminal of the output three-terminal transistor is connected to the output current terminal of the mirror current source;

[0023] The second terminal of the reference three-terminal transistor and the second terminal of the output three-terminal transistor are connected to a negative voltage.

[0024] Optionally, the magnitude of the auxiliary current signal is:

[0025]

[0026] In the formula, For auxiliary current signal, The voltage of the voltage source. This is the Miller plateau voltage. This is the resistance value of the third resistor. This represents the number of three-terminal output transistors.

[0027] Optionally, the turn-on circuit includes a third three-terminal transistor and a fourth resistor;

[0028] The first terminal of the third three-terminal transistor is connected to a voltage source;

[0029] The second terminal of the third three-terminal transistor is connected to the control terminal of the main three-terminal transistor via a fourth resistor.

[0030] To achieve the second objective of this disclosure, the technical solution adopted in this disclosure is as follows:

[0031] A turn-on method based on the above-mentioned gate drive circuit adapted to high junction temperature environment, during the turn-on process of the main three-terminal transistor;

[0032] when and At that time, an auxiliary current signal opposite to the turn-on signal voltage is generated at the control electrode of the main three-terminal transistor; where, This refers to the first terminal current of the main three-terminal transistor. For load current, The voltage between the first and second terminals of the main three-terminal transistor. This refers to the bus voltage. and is a coefficient.

[0033] To achieve the third objective of this disclosure, the technical solution adopted in this disclosure is as follows:

[0034] A turn-off method based on the above-mentioned gate drive circuit adapted to high junction temperature environment, during the turn-on process of the main three-terminal transistor;

[0035] During the turn-off process of the main three-terminal transistor;

[0036] when At that time, an auxiliary current signal in the same direction as the turn-off signal current is generated at the control electrode of the main three-terminal transistor; where, The voltage between the first and second terminals of the main three-terminal transistor. Bus voltage and The coefficient is , and .

[0037] Optionally, during the turn-off process of the main three-terminal transistor;

[0038] when At that time, an auxiliary current signal in the same direction as the turn-off signal current is generated at the control electrode of the main three-terminal transistor; where, This refers to the first terminal current of the main three-terminal transistor. For load current, and The coefficient is , and .

[0039] This disclosure adds an auxiliary circuit to the conventional driving circuit, which can generate corresponding positive or reverse auxiliary current signals at the control electrode of the three-terminal transistor. During the conduction process, the auxiliary circuit can generate a reverse auxiliary current signal at the control electrode of the three-terminal transistor during the current rise phase, reducing the drive current of the turn-on signal to decrease... di d / dt It suppresses the current during turn-on; during the turn-off process, the auxiliary circuit can generate an auxiliary current signal in the same direction at the control electrode of the three-terminal transistor during the current drop segment, increasing the drive current of the turn-off signal and accelerating the turn-off speed.

[0040] This design avoids the problems of large current and voltage overshoots in traditional drive circuits, effectively shortens turn-on and turn-off times, reduces switching losses, and has significant application value in high junction temperature environments. At a junction temperature of 25 degrees Celsius, when the turn-on current and turn-off voltage overshoots are consistent, the turn-on and turn-off losses of this drive circuit are reduced by 37.7846% and 42.8304%, respectively, compared to traditional drive circuits; at a junction temperature of 200 degrees Celsius, the turn-on and turn-off losses of this drive circuit are reduced by 20.1158% and 49.1301%, respectively, compared to traditional drive circuits. Attached Figure Description

[0041] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0042] Figure 1 This is a circuit diagram of a gate drive circuit adapted to high junction temperature environments disclosed herein.

[0043] Figure 2 This is a schematic diagram of the voltage and current waveforms at different stages of the gate drive circuit adapted to high junction temperature environments disclosed herein.

[0044] Figure 3 This is a schematic diagram of the voltage and current waveforms at different times during the turn-off process of the gate drive circuit adapted to high junction temperature environments disclosed herein.

[0045] Figure 4 The diagram shows the drain current versus time curves during the gate drive circuit of this disclosure and the drive circuit of the prior art at a junction temperature of 200 degrees Celsius.

[0046] Figure 5 The curves showing the gate current versus time during the turn-on process of the gate drive circuit of this disclosure and the drive circuit of the prior art at a junction temperature of 200 degrees Celsius are shown.

[0047] Figure 6 The curves showing the drain-source voltage versus time during the gate drive circuit of this disclosure and the drive circuit of the prior art at a junction temperature of 200 degrees Celsius are provided.

[0048] Figure 7 The curves showing the drain current versus time during the turn-off process of the gate drive circuit of this disclosure and the drive circuit of the prior art at a junction temperature of 200 degrees Celsius are shown.

[0049] Figure 8 The figures show the gate current versus time curves during the turn-off process of the gate drive circuit of this disclosure and the drive circuit of the prior art at a junction temperature of 200 degrees Celsius.

[0050] Figure 9 The curves showing the drain-source voltage change over time during the turn-off process of the gate drive circuit of this disclosure and the drive circuit of the prior art at a junction temperature of 200 degrees Celsius are provided. Detailed Implementation

[0051] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0052] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0053] Three-terminal transistors include bipolar transistors (such as IGBTs) or field-effect transistors (such as MOSFETs).

[0054] First, the conduction and turn-off characteristics of a three-terminal transistor are analyzed. This disclosure uses a MOSFET device as an example, but the conduction and turn-off characteristics of other three-terminal transistors are similar to those of a MOSFET device.

[0055] See Figure 2 As shown, the turn-on process of a MOSFET device can be roughly divided into four stages: turn-on delay stage, current rise stage, voltage drop stage, and saturation turn-on stage.

[0056] During the current rise phase, the drive current charges the gate capacitance of the MOSFET device, and the gate voltage of the MOSFET device... V GS Above the turn-on threshold voltage V thAt this time, the MOSFET device begins to conduct. The static characteristic of the MOSFET device, the drain current, can be defined as:

[0057] (1)

[0058] In the formula, I d This refers to the drain current of the MOSFET device. g m For the transconductance of MOSFET devices, V GS This refers to the gate voltage of the MOSFET device. V th This refers to the turn-on threshold voltage of the MOSFET device.

[0059] Differentiating both sides of equation (1) above, the drain current can be obtained. I d The rising slope of the drain current I d The rising slope and gate drive current I g and input capacitance C iss It exhibits a functional relationship:

[0060] (2)

[0061] In the formula, C iss The input capacitance of the MOSFET device ( C iss = C gd + C gs That is, the capacitance between the gate and drain. C gd The capacitance between the gate and source C gs sum), I g Gate drive current

[0062] Current overshoot value during the opening process I rr The following formula can be used to calculate:

[0063] (3)

[0064] In the formula, Q rr For the reverse recovery charge of the anti-parallel diode, It is the MOSFET leakage current.

[0065] See Figure 3 As shown, the turn-off process is the reverse of the turn-on process. During the current decrease phase, due to the parasitic inductance of the power circuit, an overvoltage will be generated when the MOSFET device is turned off. U ov It can be calculated using equation (4):

[0066] (4)

[0067] In the formula, L loop This is the total parasitic inductance of the power circuit.

[0068] The drain current change rate during this stage can still be described by equation (2). That is, during the current decrease stage, increasing the drive current of the turn-off signal (the direction of the drive current during the turn-off process is opposite to the direction of the turn-on process) can suppress the turn-off overvoltage. Increasing the drive current of the turn-off signal during the turn-off delay stage, voltage rise stage, and gate discharge stage can accelerate the gate capacitor discharge process, speed up the switching speed, and reduce losses.

[0069] Therefore, the ideal conduction process of a MOSFET device is as follows:

[0070] 1) There is a large gate drive current during the turn-on delay phase. I g To shorten the conduction time;

[0071] 2) Reduce the drive current during the current rise phase to decrease... di d / dt Suppress the current passing through the switch;

[0072] 3) Increase the drive current during the voltage drop stage and saturation conduction stage to speed up the turn-on process.

[0073] The ideal MOSFET device turn-off process is as follows:

[0074] 1) Increase the drive current during the turn-off delay and voltage rise phases to accelerate the turn-off speed;

[0075] 2) Reduce the drive current during the current-decreasing phase to decrease... dV ds / dt Suppressing turn-off overvoltage;

[0076] 3) Increase the drive current and shorten the turn-off time during the gate discharge stage.

[0077] Based on the above theories, see [reference] Figure 1As shown, some embodiments of this disclosure provide a gate drive circuit adapted to high junction temperature environments. The gate drive circuit includes a main three-terminal transistor 1, an on / off circuit 2, and an auxiliary circuit 3. Both the off-off circuit 2 and the auxiliary circuit 3 are connected to the control electrode of the main three-terminal transistor 1.

[0078] The main three-terminal transistor 1 can be turned on or off according to a control signal; the control signal may include an on signal and an off signal; the three-terminal transistor receives an off signal to turn off the three-terminal transistor; the three-terminal transistor may be a transistor, U-IGBT, NPT-IGBT, N-type MOSFET device, P-type MOSFET device, SiC MOSFET or SiMOSFET, etc.; the model may be FF200R12KS4, FF300R12KS4, SCT30N120, SCT3030ALHR, SCT3017AL, SCT2120AF, SCT3017ALHR, SCT3022AL, etc.

[0079] The main three-terminal transistor 1 includes a control electrode, a first electrode, and a second electrode. When the three-terminal transistor is a MOSFET device or an IGBT, the control electrode is the gate, the first electrode is the drain or source, and the corresponding second electrode is the source or drain. When the three-terminal transistor is a triode, the control electrode is the base, the first electrode is the emitter or collector, and the corresponding second electrode is the collector or emitter.

[0080] The turn-on / turn-off circuit 2 can send a turn-on control signal to the control electrode of the main three-terminal transistor 1; the control signal output by the turn-on / turn-off circuit 2 can be a digital signal or an analog signal; the turn-on signal is used to turn on the main three-terminal transistor 1, and the turn-off signal is used to turn off the main three-terminal transistor 1; the turn-on / turn-off circuit 2 can include independent turn-on circuits and turn-off circuits, or it can be an integrated control circuit.

[0081] The auxiliary circuit 3 is used to generate an auxiliary current signal that is in the same direction or opposite to the control signal current to the control electrode of the main three-terminal transistor 1 within a preset time period when the main three-terminal transistor 1 is in the turn-on and turn-off process.

[0082] See Figure 2 , Figure 3As shown, during the turn-on process, in the current-rising phase of the main transistor 1, an auxiliary current signal opposite to the turn-on signal is input to the control electrode of the main three-terminal transistor 1 through the auxiliary circuit 3, reducing the drive current of the turn-on signal and suppressing the peak current during the turn-on process. In the current-falling phase of the turn-off process, an auxiliary current signal in the same direction as the turn-off signal is input to the control electrode of the main three-terminal transistor 1 through the auxiliary circuit 3, increasing the drive current of the turn-off signal and suppressing turn-off overvoltage. Furthermore, increasing the drive current of the turn-off signal during the turn-off delay phase, voltage rise phase, and gate discharge phase can accelerate the gate capacitor discharge process, increase the switching speed, and reduce losses.

[0083] The following embodiments illustrate the specific circuit layout of the gate drive circuit using an N-type MOSFET device as an example of the main three-terminal transistor 1. When the main three-terminal transistor 1 is another transistor, IGBT, or MOSFET, simply replacing the MOSFET device with another three-terminal transistor will not affect the implementation of this disclosure. The correspondence between the first terminal, the second terminal, the drain, and the source can also be changed according to the circuit requirements.

[0084] In one specific embodiment, see Figure 1 As shown, the turn-on / turn-off circuit 2 includes a turn-on circuit 21 and a turn-off circuit 22. The turn-on circuit 21 is connected to the main MOSFET device Q6, and the auxiliary circuit 3 is connected to the main MOSFET device Q6 through the turn-off circuit 2. The turn-on circuit 21 is used to input a turn-on signal to the main MOSFET device Q6 independently, and the turn-off circuit 2 is used to input a turn-off signal to the main MOSFET device Q6 independently. The turn-on circuit 21 and the turn-off circuit 22 are each driven independently by an external driving circuit. When a turn-on signal needs to be input to the main MOSFET device Q6, the external driving circuit can send a signal to the turn-on circuit 21; when a turn-off signal needs to be input to the main MOSFET device Q6, the external driving circuit can send a signal to the turn-off circuit 22.

[0085] In one specific embodiment, see Figure 1 As shown, the shutdown circuit 22 includes a first MOSFET device Q1 and a first resistor. R ioff,main Second resistor R g,off And mirror current source 23; the drain of the first MOSFET device 1 is connected to the voltage source VCC; the source of the first MOSFET device 1 is connected to the first resistor. R ioff,main The reference current terminal of the current mirror 23 and the auxiliary circuit 3 are connected respectively; the output current terminal of the current mirror 23 is connected through the second resistor. R g,offIt is connected to the gate of the main MOSFET device Q6. An external control signal is input from the gate of the first MOSFET device Q1, and after amplification, it can output a turn-off signal at the output current terminal of the mirror current source 23.

[0086] In one specific embodiment, see Figure 1 As shown, the auxiliary circuit 3 includes a second MOSFET device Q2 and a third resistor. R ion,ax The drain of the second MOSFET device 1 is connected to the voltage source VCC; the source of the second MOSFET device 1 is connected to the third resistor. R ion,ax It is then connected to the reference current terminal of the current mirror 23. An external control signal can control the auxiliary circuit 3 to output an auxiliary current signal through the gate of the second MOSFET device Q2. The current mirror 23 can output a current that is basically the same as or amplified from the reference current. The auxiliary circuit 3 can also input an auxiliary current signal to the gate of the main MOSFET device Q6 through an external control circuit.

[0087] In this embodiment, the current mirror 23 specifically includes a reference MOSFET device Q4 and at least one output MOSFET device Q5; the reference power supply terminal of the current mirror 23 is connected to the drain of the reference MOSFET device Q4, the drain gate of the reference MOSFET device Q4, and the gate of the output MOSFET device Q5, respectively; the drain of the output MOSFET device Q5 is connected to the output current terminal of the current mirror 23; the source of the reference MOSFET device Q4 and the source of the output MOSFET device Q5 are connected to the negative voltage -VEE.

[0088] In some embodiments, the turn-on circuit 21 includes a third MOSFET device Q3 and a fourth resistor. R g,on The drain of the third MOSFET device Q3 is connected to the voltage source VCC; the source of the third MOSFET device Q3 is connected to the gate of the main MOSFET device Q6 through a fourth resistor. The turn-on circuit 21 and the turn-off circuit 22 can also employ other structures found in the prior art.

[0089] The magnitude of the auxiliary current signal can be:

[0090]

[0091] In the formula, For auxiliary current signal, The voltage of the voltage source. This is the Miller plateau voltage. This is the resistance value of the third resistor. This is the resistance value of the fourth resistor. This refers to the number of output MOSFET devices. The magnitude of the auxiliary current signal can also be adjusted based on the suppression effect and the withstand capability of the MOSFET devices.

[0092] In other embodiments of this disclosure, a turn-on method based on the gate drive circuit adapted to high junction temperature environment described above is provided during the turn-on process of the main MOSFET device Q6;

[0093] The specific method for reducing the drive current and suppressing the peak value of the start-up process current during the current rise phase is as follows: during the current rise phase, when... and At this time, an auxiliary current signal opposite to the turn-on signal current is generated at the gate of the main MOSFET device Q6; where, This refers to the drain current of the main MOSFET device Q6. For load current, This refers to the drain-source voltage of the main MOSFET device Q6. This is the bus voltage; the purpose is to reduce the drive current to decrease d. I d / d t Suppressing peak current during the turn-on process; and The coefficient can be adjusted as needed.

[0094] In a preferred embodiment, and The value of satisfies , ,in This is the on-state voltage drop of the main MOSFET device Q6.

[0095] In other embodiments of this disclosure, a turn-off method based on the gate drive circuit adapted to high junction temperature environment described above is provided during the turn-off process of the main MOSFET device Q6;

[0096] During the current decrease phase, the specific method for increasing the drive current of the turn-off signal is as follows: when At this time, an auxiliary current signal in the same direction as the turn-off signal current is generated at the gate of the main MOSFET device Q6; where, This refers to the drain-source voltage of the main MOSFET device Q6. Bus voltage and The coefficient is , and It can suppress turn-off overvoltage during the turn-off process. and The coefficient can be adjusted according to the shutdown effect in the specific circuit.

[0097] In another preferred embodiment, during the turn-off process of the main MOSFET device Q6;

[0098] The specific method for increasing the drive current during the turn-off delay phase, voltage rise phase, and gate discharge phase is as follows: when At this time, an auxiliary current signal in the same direction as the turn-off signal current is generated at the gate of the main MOSFET device Q6; where, This refers to the drain current of the main MOSFET device Q6. For load current, and The coefficient is , and This can accelerate the gate capacitor discharge process, increase switching speed, and reduce losses. and The coefficient can also be adjusted according to the specific circuit settings.

[0099] exist and At that time, shut off auxiliary circuit 3 to prevent d V ds / d t If the voltage is too high, it will cause overvoltage.

[0100] This disclosed method adds an auxiliary circuit to the traditional MOSFET device drive circuit, generating corresponding forward or reverse currents at the MOSFET gate. This avoids the problem of large current and voltage overshoots in traditional MOSFET drive circuits, effectively shortening turn-on and turn-off times, reducing switching losses, and has significant application value in high junction temperature environments. At a junction temperature of 25 degrees Celsius, when the turn-on current and turn-off voltage overshoots are consistent, refer to [reference needed]. Figures 4 to 9 In actual testing, the gate drive circuit adapted to high junction temperature environments disclosed herein reduced the turn-on and turn-off losses by 37.7846% and 42.8304% respectively compared with the gate drive circuit of the prior art; at a junction temperature of 200 degrees, the losses were reduced by 20.1158% and 49.1301% respectively.

[0101] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0102] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0103] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A gate drive circuit adapted for high junction temperature environments, characterized by, include: The main three-terminal transistor can be turned on or off according to a control signal; The on / off circuit connected to the control electrode of the main three-terminal transistor can send a control signal to the control electrode of the main three-terminal transistor. An auxiliary circuit connected to the control electrode of the main three-terminal transistor is used to generate an auxiliary current signal that is in the same direction or opposite to the control signal current to the control electrode of the main three-terminal transistor within a preset time period when the main three-terminal transistor is in the turn-on and turn-off process. During the turn-on process of the main three-terminal transistor; When and then an auxiliary current signal opposite to the on signal voltage is generated at the control electrode of the main three-terminal transistor; where, is the first electrode current of the main three-terminal transistor, is the load current, is the voltage between the first and second electrode of the main three-terminal transistor, is the bus voltage; and is a coefficient; During the turn-off process of the main three-terminal transistor; when At that time, an auxiliary current signal in the same direction as the turn-off signal current is generated at the control electrode of the main three-terminal transistor; where, The first terminal current of the main three-terminal transistor. For load current, and Let be the coefficient, and .

2. The gate drive circuit adapted to high junction temperature environment as described in claim 1, characterized in that, The turn-on and turn-off circuit includes a turn-on circuit and a turn-off circuit. The turn-on circuit is connected to the main three-terminal transistor, and the auxiliary circuit is connected to the main three-terminal transistor through the turn-off circuit.

3. The gate drive circuit adapted to high junction temperature environment as described in claim 2, characterized in that, The shutdown circuit includes a first three-terminal transistor, a first resistor, a second resistor, and a current mirror source; The first terminal of the first three-terminal transistor is connected to a voltage source; The second terminal of the first three-terminal transistor is connected to the reference current terminal of the mirror current source and the auxiliary circuit respectively after passing through the first resistor; The output current terminal of the mirror current source is connected to the control electrode of the main three-terminal transistor after passing through the second resistor.

4. The gate drive circuit adapted to high junction temperature environment as described in claim 3, characterized in that: The auxiliary circuit includes a second three-terminal transistor and a third resistor; The first terminal of the second three-terminal transistor is connected to a voltage source; The second terminal of the second three-terminal transistor is connected to the reference current terminal of the mirror current source through the third resistor.

5. The gate drive circuit adapted to high junction temperature environment as described in claim 3, characterized in that: The mirror current source includes a reference three-terminal transistor and at least one output three-terminal transistor; The reference power supply terminal of the mirror current source is connected to the first terminal of the reference three-terminal transistor, the control terminal of the reference three-terminal transistor, and the control terminal of the output three-terminal transistor, respectively. The first terminal of the output three-terminal transistor is connected to the output current terminal of the mirror current source; The second terminal of the reference three-terminal transistor and the second terminal of the output three-terminal transistor are connected to a negative voltage.

6. The gate drive circuit adapted to high junction temperature environment as described in claim 5, characterized in that: The magnitude of the auxiliary current signal is: In the formula, For auxiliary current signal, The voltage of the voltage source. The Miller plateau voltage, This is the resistance value of the third resistor. This represents the number of three-terminal output transistors.

7. The gate drive circuit adapted to high junction temperature environment as described in claim 3, characterized in that: The turn-on circuit includes a third three-terminal transistor and a fourth resistor; The first terminal of the third three-terminal transistor is connected to a voltage source; The second terminal of the third three-terminal transistor is connected to the control terminal of the main three-terminal transistor via the fourth resistor.

8. A turn-off method based on the gate drive circuit adapted to high junction temperature environment according to any one of claims 1-7, characterized in that: During the turn-off process of the main three-terminal transistor; when At that time, an auxiliary current signal in the same direction as the turn-off signal current is generated at the control electrode of the main three-terminal transistor; where, The voltage between the first and second terminals of the main three-terminal transistor. Bus voltage and Let be the coefficient, and .

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