Complementary metal-oxide-semiconductor (CMOS) field effect devices
By employing a stacked body channel structure of first and second sublayers in CMOS devices, adjusting the energy difference at the band edge, and optimizing electron and hole conduction, the problems of limited on-current and excessive leakage current in traditional CMOS devices are solved, achieving high-efficiency electrical performance and compact design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
- Filing Date
- 2025-12-01
- Publication Date
- 2026-06-23
AI Technical Summary
Traditional shared-channel CMOS devices suffer from limited on-current and excessive leakage current, especially when the n-type MOSFET is turned on and the p-type MOSFET is turned off, leakage current is likely to occur from the n-type doped S/D region to the p-type doped S/D region.
A channel structure is adopted using a stack of first and second sublayers, where the first sublayer optimizes electron conduction and the second sublayer optimizes hole conduction. By adjusting the energy difference at the band edge, a heterogeneous structure is formed, which restricts electrons and holes respectively, thereby reducing leakage current.
It improves the on-current and reduces the leakage current while maintaining the compact size of the device, optimizes the drive current of n-type and p-type MOSFETs, reduces defects caused by epitaxial growth, and improves electrical performance.
Smart Images
Figure CN122269795A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a complementary metal-oxide-semiconductor (CMOS) field-effect device. Background Technology
[0002] Complementary metal-oxide-semiconductor (CMOS) field-effect devices utilize p-type and n-type MOSFETs (metal-oxide-semiconductor field-effect transistors) to create logic functions. A C2MOS device, also known as a shared-channel CMOS device, is a CMOS device in which a p-type MOSFET and an n-type MOSFET share the same channel and the same gate. In such a CMOS device, when the n-type MOSFET is activated, electrons will conduct through the same channel, and when the p-type MOSFET is activated, holes will conduct through the same channel. Summary of the Invention
[0003] The present invention aims to provide a CMOS device with improved electrical performance. Another objective is to provide a CMOS device with a small size. Other objectives and additional objectives may be understood from the following description.
[0004] According to a first aspect of the present invention, a CMOS device is provided, the CMOS device comprising:
[0005] Substrate;
[0006] A first n-type doped source / drain region (S / D region) and a second n-type doped S / D region are disposed above the substrate;
[0007] A first p-type doped S / D region and a second p-type doped S / D region are disposed above the substrate;
[0008] A first trench layer disposed above a substrate, the first trench layer comprising: a first sublayer and a second sublayer;
[0009] The first and second n-type doped S / D regions are disposed on the first side of the first channel layer, and the first and second p-type doped S / D regions are disposed on the second side of the first channel layer, with the second side opposite to the first side.
[0010] The first and second n-type doped S / D regions are adjacent to the first sublayer but not adjacent to the second sublayer.
[0011] The first and second p-type doped S / D regions are adjacent to the second sublayer but not adjacent to the first sublayer.
[0012] Wherein, the energy at the conduction band edge of the first sublayer is lower than the energy at the conduction band edge of the second sublayer; and
[0013] Among them, the energy of the valence band edge of the first sublayer is lower than the energy of the valence band edge of the second sublayer; and
[0014] A gate structure that is adjacent to the first and second sublayers of the first channel layer.
[0015] The substrate can be a silicon substrate. It is important to note that any reference to an element (e.g., the first channel) being disposed above the substrate implies that an intermediate layer or structure may exist between the substrate and the first channel. Therefore, this means that the first channel layer can be disposed on and in physical contact with the intermediate layer. This intermediate layer can be a functional gate structure or a portion thereof, or an intermediate dielectric layer.
[0016] As described above, a CMOS device includes a first channel layer. As explained below, a CMOS device may include additional channel layers. However, only the first channel layer and its associated S / D region and gate structure are discussed here. The first channel layer includes a first sublayer and a second sublayer. The first and second sublayers can be arranged very close together, for example, adjacent to each other. For example, the main surface of the first sublayer may be adjacent to the main surface of the second sublayer. Alternatively, the sidewalls of the first sublayer may be adjacent to the sidewalls of the second sublayer. In this way, the CMOS device can be as compact as a conventional C2MOS device. The first channel layer can be patterned as nanosheets or fins. Similarly, the individual sublayers of the first channel layer can also be patterned as nanosheets or fins. As previously mentioned, the gate structure is adjacent to the first and second sublayers of the first channel layer. For example, the gate structure may wrap around the first channel layer. Therefore, the gate structure can be a gate all around (also called a gate all around, or GAA) that wraps around the first channel layer. For example, the gate structure may be adjacent to the first and second sidewalls of the first channel layer, as well as the top and bottom surfaces of the first channel layer. The gate structure can be disposed between the first and second n-type doped S / D regions, or between the first and second p-type doped S / D regions. The gate structure described herein may include a gate spacer layer, a gate dielectric, and a gate metal.
[0017] Since the first and second n-type doped S / D regions are adjacent to the first sublayer, the first sublayer can conduct electrons between the first and second n-type doped S / D regions. Similarly, since the first and second p-type doped S / D regions are adjacent to the second sublayer, the second sublayer can conduct holes between the first and second p-type doped S / D regions.
[0018] Based on the above, the first and second n-type doped S / D regions and the first sublayer of the first channel layer can form part of an n-type MOSFET, while the first and second p-type doped S / D regions and the second sublayer of the first channel layer can form part of a p-type MOSFET, wherein the n-type MOSFET and the p-type MOSFET have a common gate structure.
[0019] In traditional shared-channel CMOS devices, both the n-type MOSFET and the p-type MOSFET are associated with a uniform channel, which is used to conduct electrons and holes. It has been recognized that such traditional shared-channel CMOS devices may suffer from limited on-current and / or excessive leakage current. For example, when the n-type MOSFET is turned on and the p-type MOSFET is turned off, leakage current may occur from one n-type doped S / D region to one p-type doped S / D region.
[0020] In contrast, in this invention, the first channel layer includes a first sublayer and a second sublayer, wherein the band arrangement is such that the energy of the conduction band edge of the first sublayer is lower than the energy of the conduction band edge of the second sublayer; and the energy of the valence band edge of the first sublayer is lower than the energy of the valence band edge of the second sublayer. For example, the band arrangements of the first and second sublayers may be staggered. Therefore, the band arrangement of the first and second sublayers may confine electrons in the first sublayer and holes in the second sublayer. This can improve the on-current and / or reduce the leakage current, while the CMOS device still maintains a compact size. Furthermore, this invention can optimize (or customize) the first sublayer to facilitate electron conduction, and / or optimize (or customize) the second sublayer to facilitate hole conduction. This may further improve the on-current.
[0021] The first sublayer can form part of an n-type MOSFET. Therefore, the first sublayer can be optimized for electron conduction. To this end, the first sublayer can be formed with a material that has a higher electron mobility, for example, higher than that of the second sublayer. The material of the first sublayer can be further configured such that the energy at its conduction band edge is lower than the energy at the conduction band edge of the second sublayer material. This configuration is beneficial for confining electrons within the first sublayer.
[0022] The second sublayer can form part of a p-type MOSFET. Therefore, the second sublayer can be optimized for hole conduction. This means that the formation of the second sublayer allows its material to have a higher hole mobility, for example, higher than that of the first sublayer. The material of the second sublayer can be further configured such that its valence band edge energy is higher than that of the first sublayer material. This configuration helps to confine holes within the second sublayer.
[0023] The first aspect of this invention is based on the insight that while prior art C2MOS devices have reduced cell area and gate capacitance compared to conventional CMOS devices, they still suffer from leakage current problems. In this context, leakage current can refer to the unnecessary flow of the main charge carriers of a MOSFET with a specific conductivity to another MOSFET with the opposite conductivity during forward bias.
[0024] The CMOS device of the present invention employs a channel comprising a stack of a first sublayer and a second sublayer. By making the energy of the conduction band edge of the first sublayer lower than that of the conduction band edge of the second sublayer, the electronic conduction performance of the first sublayer can be optimized. This configuration is advantageous for confining electrons within the first sublayer. By making the energy of the valence band edge of the first sublayer lower than that of the valence band edge of the second sublayer, the hole conduction performance of the second sublayer can be optimized. This configuration is advantageous for confining holes within the second sublayer. Furthermore, an interface can be formed between the first and second sublayers. This implies that the first sublayer can be adjacent to the second sublayer. The advantage of the above-described conduction band edge and valence band edge configuration is that a band alignment is formed at the interface, thereby reducing leakage current during forward bias of the CMOS device. As described above, this is achieved by confining the respective main charge carriers within their respective sublayers, or in other words, by "capturing" the respective main charge carriers within their respective sublayers.
[0025] Furthermore, the configuration of the conduction band edge and valence band edge indicates that the first and second sublayers can form a heterogeneous structure, meaning they can be formed from different materials. This provides greater freedom in the selection of materials for the first and second sublayers. Therefore, materials for the first and second sublayers can be chosen to minimize lattice mismatch. This allows for the reduction of defects caused by epitaxial growth, such as dislocations, in the channel layer, thereby improving the electrical performance of the device and resulting in high-quality CMOS devices. This also suggests that the materials for the first and second sublayers can be chosen to achieve high electron mobility in the first sublayer and high hole mobility in the second sublayer, thereby increasing the drive current of both n-type and p-type MOSFETs.
[0026] Furthermore, in existing C2MOS devices with a shared channel, the shared channel is typically formed from a single material. Therefore, conduction is often biased towards one type of conductivity, as the material is optimized for either electron or hole conduction. For example, the shared channel can be formed from Si. However, Si has a significantly higher electron mobility than hole mobility, thus optimizing electron conduction, which is more advantageous for n-type MOSFETs than for p-type MOSFETs. This results in high drive current for n-type MOSFETs and low drive current for p-type MOSFETs. The CMOS device of this invention avoids this problem through a channel comprising a first sublayer formed of a material capable of providing optimal electron conduction to improve the drive current of the n-type MOSFET, and a second sublayer formed of a material capable of providing optimal hole conduction to improve the drive current of the p-type MOSFET.
[0027] The first aspect of the invention is also based on the insight that a smaller footprint can be achieved by arranging the n-type doped and p-type doped S / D regions separately on the sides of the first channel layer. "Smaller footprint" here generally refers to the ability to provide a thinner and lighter device. Furthermore, by arranging the n-type doped and p-type doped S / D regions separately on the sides of the first channel layer (e.g., opposite sides), they can be well separated, allowing the first and second sublayers to be close to each other (e.g., adjacent to each other) without the n-type doped and p-type doped S / D regions contacting each other.
[0028] The relative spatial terms used in this document, such as “top,” “bottom,” “lower,” “vertical,” and “stacked on,” should be understood as indicating position or orientation within the semiconductor substrate reference frame. Specifically, these terms can be understood as relating to the normal direction of the substrate on which the channel layer stack is formed, or equivalently, to the bottom-up / stack direction of the channel layers. The term “side” or equivalent term used in this document refers to the surface of the channel layer / channel layer sublayer perpendicular to the substrate.
[0029] The term "CMOS device" does not necessarily mean that a CMOS device includes a pair of n-type MOSFETs and a p-type MOSFET. Rather, a CMOS device may include multiple pairs of n-type and p-type MOSFETs, such as two, three, four, five or more pairs.
[0030] The use of terms like "first," "second," etc., is primarily for readability and does not necessarily imply the need for more / all intermediate numbers. Therefore, CMOS devices are not limited to containing one or two channel layers. In fact, CMOS devices can contain more than two channel layers, each comprising a sublayer optimized for electron conduction and a sublayer optimized for hole conduction. For example, CMOS devices can contain three, four, five, or even more channel layers. These channel layers can be separated from each other by dielectric layers.
[0031] The second sublayer may contain Si. 1-x Ge x , where x is equal to or less than 1.
[0032] Therefore, the second sublayer can be formed of a material with relatively high hole mobility. This can increase the drive current of the p-type MOSFET.
[0033] The first sublayer may contain Si.
[0034] Therefore, the second sublayer can be formed from a material with relatively high electron mobility. This allows for an increase in the drive current of the n-type MOSFET.
[0035] The first sublayer can be under tensile strain. The second sublayer can be under compressive strain.
[0036] The energy difference between the edge of the conduction band of the first sublayer and the edge of the valence band of the second sublayer can be equal to or greater than 400 meV.
[0037] This energy difference provides a sufficient energy barrier to prevent interband tunneling. In other words, this energy difference prevents electrons in the conduction band of the first sublayer from tunneling into the valence band of the second sublayer. Similarly, this energy difference prevents holes in the valence band of the second sublayer from tunneling into the conduction band of the first sublayer. As a result, leakage current can be reduced.
[0038] The energy difference between the edge of the second sublayer conduction band and the edge of the first sublayer conduction band can be greater than 100 meV. The energy difference between the edge of the second sublayer valence band and the edge of the first sublayer valence band can be greater than 100 meV.
[0039] This energy difference can be viewed as band shifts in the conduction and valence bands, respectively. This energy difference provides a sufficient energy barrier for electrons and holes, thereby reducing leakage current.
[0040] The plane of the first channel layer can be set to be parallel to the substrate;
[0041] The first and second n-type doped S / D regions may be adjacent to at least one of the following: the top surface of the first sublayer; the bottom surface of the first sublayer; the side surface of the first sublayer; and
[0042] The first and second p-type doped S / D regions may be adjacent to at least one of the following: the top surface of the second sublayer; the bottom surface of the second sublayer; or the side surface of the second sublayer.
[0043] Alternatively, it can be stated that the main plane of the first channel layer can be set to be parallel to the main plane of the substrate.
[0044] The CMOS device may also include:
[0045] A second trench layer disposed above the first trench layer includes:
[0046] First sublayer and second sublayer;
[0047] Wherein, the second sublayer of the first channel layer is disposed above the first sublayer of the first channel layer, and the second sublayer of the second channel layer is disposed below the first sublayer of the second channel layer, and wherein the first and second p-type doped S / D regions are adjacent to the second sublayers of the first and second channel layers, or
[0048] The first sublayer of the first channel layer is disposed above the second sublayer of the first channel layer, and the first sublayer of the second channel layer is disposed below the second sublayer of the second channel layer. The first and second n-type doped S / D regions are adjacent to the first sublayers of the first and second channel layers.
[0049] When referring to the second channel layer, unless otherwise stated, the above discussion regarding the band arrangement, geometry, size, material, and configuration of the first channel layer and its sublayers also applies to the second channel layer and its sublayers.
[0050] The gate structure can be further adjacent to the first and second sublayers of the second channel layer.
[0051] The gate structure can form a common gate structure for the first and second channel layers. For example, both the first and second channel layers can employ a gate all-around (GAA) structure. The gate structure can surround the first and second channel layers. Therefore, the gate structure can control the first and second channel layers.
[0052] The CMOS device may also include first and second n-type doped S / D regions associated with the second channel, and first and second p-type doped S / D regions associated with the second channel.
[0053] The plane of the first channel layer can be set to be perpendicular to the substrate.
[0054] Alternatively, it can be stated that the main plane of the first channel layer can be set to be perpendicular to the main plane of the substrate. Attached Figure Description
[0055] The above and other objects, features, and advantages of the present invention will be better understood from the following illustrative and non-limiting detailed description with reference to the accompanying drawings. In the drawings, similar reference numerals are used for similar elements unless otherwise stated.
[0056] Figure 1-3 A perspective view of three CMOS devices is shown in schematic form. Detailed Implementation
[0057] The following examples illustrate three different CMOS devices. In the accompanying figures discussed below, the X, Y, and Z axes represent a first direction, a second direction transverse to the first direction, and a direction perpendicular to or from bottom to top, respectively. The X and Y directions can be specifically referred to as transverse or horizontal directions because they are parallel to the main plane of the substrate. The Z direction is parallel to the normal direction of the front side of the substrate. In finished CMOS devices, current primarily flows along the X direction. Whenever layer formation is mentioned, conventional semiconductor manufacturing techniques are preferred, such as metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and thin film deposition.
[0058] Now for reference Figure 1 The figure shows a first CMOS device 100. The CMOS device 100 includes a substrate 102. The substrate 102 can be a conventional semiconductor substrate suitable for, for example, complementary metal-oxide-semiconductor (CMOS). The substrate 102 can be, for example, a bulk semiconductor substrate such as a silicon substrate, a germanium (Ge) substrate, or a silicon-germanium (SiGe) substrate. Other examples include semiconductor-on-insulator (SOI) type substrates, such as silicon-on-insulator (Si-on-insulator), germanium-on-insulator (Ge-on-insulator), or silicon-germanium-on-insulator (SiGe-on-insulator).
[0059] The CMOS device 100 also includes a first channel layer 120. The first channel layer 120 may be adjacent to the substrate 102. However, as Figure 1 As shown, the first channel layer 120 is typically disposed above the substrate 102, with a gap between them. An intermediate layer may be disposed in this gap. For example, this intermediate layer may be part of a gate-all-around structure or a dielectric layer.
[0060] The first channel layer 120 includes a first sublayer 120a and a second sublayer 120b. The first sublayer 120a forms part of an n-type MOSFET. The second sublayer 120b forms part of a p-type MOSFET.
[0061] The first channel layer 120 is patterned to form nanosheets. Similarly, the individual sublayers of the first channel layer 120 are also patterned to form nanosheets.
[0062] CMOS device 100 includes a first n-type doped S / D region 112a and a second (not shown) n-type doped S / D region 112b. The first n-type doped S / D region 112a and the second n-type doped S / D region 112b are located above a substrate 102. The first and second n-type doped regions 112a and 112b are located on a first side of a first channel layer 120. More specifically, the first and second n-type doped regions 112a and 112b are located on the side of a first sublayer 120a. Therefore, the first and second n-type doped regions 112a and 112b are associated with the first sublayer 120a. The first and second n-type doped S / D regions 112a and 112b are adjacent to the first sublayer 120a but not adjacent to the second sublayer 120b. The first and second n-type doped S / D regions 112a and 112b may be adjacent to the side of the first sublayer 120a. The first and second n-type doped regions 112a and 112b and the first sublayer 120a together form part of the n-type MOSFET.
[0063] Similarly, the CMOS device 100 includes a first p-type doped S / D region 114a and a second p-type doped S / D region 114b. The first p-type doped S / D region 114a and the second p-type doped S / D region 114b are located above the substrate 102. The first and second p-type doped regions 114a and 114b are located on the second side of the first channel layer 120. More specifically, the first and second p-type doped regions 114a and 114b are located on the side of the second sublayer 120b. Therefore, the first and second p-type doped regions 114a and 114b are associated with the second sublayer 120b. The first and second p-type doped S / D regions 114a and 114b are adjacent to the second sublayer 120b but not adjacent to the first sublayer 120a. The first and second p-type doped S / D regions 114a and 114b may be adjacent to the side of the second sublayer 120b. The first and second p-type doped regions 114a and 114b and the second sublayer 120b together form part of the p-type MOSFET.
[0064] The second side is positioned opposite to the first side. Therefore, this means that the first n-type doped S / D regions 112a, 112b are positioned opposite to the first p-type doped S / D regions 114a, 114b.
[0065] S / D regions 112a, 112b, 114a, and 114b can be formed using methods known in the art. The formation of S / D regions 112a, 112b, 114a, and 114b may include a metal contact deposition process step. In other words, S / D regions 112a, 112b, 114a, and 114b may contain metal suitable for serving as an S / D region contact.
[0066] The second sublayer 120b may contain Si. 1-x Ge x In this context, x can be equal to or less than 1. For example, x can be 1; 0.9; 0.8; 0.7; 0.6; 0.5; 0.4; 0.3; 0.2; or 0.1. The first sublayer 120a may contain Si.
[0067] The first and second sublayers 120a and 120b can withstand strain. For example, the first sublayer 120a can withstand tensile strain, and the second sublayer 120b can withstand compressive strain.
[0068] The energy at the conduction band edge of the first sublayer 120a is lower than the energy at the conduction band edge of the second sublayer 120b. Furthermore, the energy at the valence band edge of the first sublayer 120a is lower than the energy at the valence band edge of the second sublayer 120b. This means that the first channel layer 120 can be formed from a heterostructure. In other words, the material forming the first sublayer 120a can be different from the material forming the second sublayer 120b. The materials of sublayers 120a and 120b can be selected to reduce leakage current and optimize electron or hole conduction.
[0069] The term "band offset" in this document refers to the relative alignment of energy bands at a semiconductor heterojunction. Therefore, the energy difference between the conduction band edge of the first sublayer 120a and the conduction band edge of the second sublayer 120b can be described as a band offset. The energy difference (i.e., band offset) between the conduction band edge of the second sublayer 120b and the conduction band edge of the first sublayer 120a can be greater than 100 meV. Similarly, the energy difference between the valence band edge of the second sublayer 120b and the valence band edge of the first sublayer 120a can be greater than 100 meV. As described above, these structures can reduce the leakage current during the forward bias of the CMOS device 100. Furthermore, the energy difference between the conduction band edge of the first sublayer 120a and the valence band edge of the second sublayer 120b can be equal to or greater than 400 meV. This structure can further reduce the leakage current. The above structure can be implemented by the following: the first sublayer 120a is formed, for example, of Si. The second sublayer can be formed simultaneously of Ge. Alternatively, the second sublayer can be formed, for example, of Si. 0.5 Ge 0.5 or Si 0.75 Ge 0.25 Formation. In addition, the advantage of forming the first and second sublayers 120a and 120b as nanosheets is that they can provide the aforementioned band shift, but other geometries are also conceivable.
[0070] Still referencing Figure 1 The plane of the first channel layer 120 is configured to be parallel to the substrate 102. The first and second n-type doped S / D regions 112a and 112b are adjacent to the sides of the first sublayer 120a. As described above, the first channel layer 120 does not need to be adjacent to the underlying substrate 102. Therefore, it is conceivable that the first and second n-type doped S / D regions 112a and 112b may further be adjacent to the bottom surface of the first sublayer 120a. Similarly, the first and second p-type doped S / D regions 114a and 114b may be adjacent to the sides of the second sublayer 120b. It is also conceivable that the first and second p-type doped S / D regions 114a and 114b may further be adjacent to the top surface of the second sublayer 120b.
[0071] and Figure 1Conversely, it is conceivable that the first and second sub-layers 120a and 120b do not need to completely overlap. For example, the second sub-layer 120b may further extend, for example, along the y-direction or the x-direction, such that the second sub-layer 120b protrudes beyond the first sub-layer 120a in the corresponding direction. As another example, the second sub-layer 120b may extend inward from the perimeter of the first sub-layer 120a. Therefore, this means that the first and second sub-layers 120a and 120b can partially overlap. It is understood that the dimensions of the sub-layers 120a and 120b can be varied to allow for partial overlap. For this purpose, it is conceivable that the first and second n-type doped S / D regions 112a and 112b can simultaneously be adjacent to the top surface, bottom surface, and sides of the first sub-layer 120a. Similarly, the first and second p-type doped S / D regions 114a and 114b can simultaneously be adjacent to the top surface, bottom surface, and side surface of the second sublayer 120b.
[0072] It should be noted that other ordering of any layers / elements in the CMOS device 100 is also conceivable. For example, although the first sublayer 120a is depicted as the bottom layer relative to the substrate 102, it is conceivable that the second sublayer 120b could be the bottom layer and the first sublayer 120a could be the top layer.
[0073] Still referencing Figure 1 A second channel layer 122 is disposed above the first channel layer 120. The second channel layer 122 includes a first sub-layer 122a and a second sub-layer 122b. A gap is provided between the first channel 120 and the second channel 122. An intermediate layer may be disposed in this gap. For example, such an intermediate layer may be part of a gate-all-around structure or a dielectric layer. Whenever the second channel layer 122 is mentioned, unless otherwise stated, the above discussion regarding the strip arrangement, geometry, size, material, and arrangement of the first channel layer 120 and its sub-layers 120a and 120b also applies to the second channel layer 122 and its sub-layers 122a and 122b.
[0074] The relative arrangement between the sublayers of the first channel layer 120 and the second channel layer 122 will be discussed further below. The second sublayer 120b of the first channel layer 120 is disposed above the first sublayer 120a of the first channel layer 120. Furthermore, the second sublayer 122b of the second channel layer 122 is disposed below the first sublayer 122a of the second channel layer 122. For example... Figure 1As shown, the second sublayer 120b of the first channel layer 120 directly faces the second sublayer 122b of the second channel layer 122. As described above, other layer / element arrangements of the CMOS device 100 are also conceivable. Therefore, it is conceivable that the first sublayer 120a of the first channel layer 120 can be disposed above the second sublayer 120b of the first channel layer 120. Correspondingly, the first sublayer 122a of the second channel layer 122 can be disposed below the second sublayer 122b of the second channel layer 122. This means that, in this case, the first sublayer 120a of the first channel layer 120 can directly face the first sublayer 122a of the second channel layer 122.
[0075] Gate structure 130 is adjacent to the second channel 122, and more specifically, to both the first sublayer 122a and the second sublayer 122b. More specifically, gate structure 130 may be adjacent to the top main surface and side surfaces of the first sublayer 122a. Similarly, gate structure 130 may be adjacent to the bottom main surface and side surfaces of the second sublayer 122b. Gate structure 130 may also be adjacent to the first channel 120, and more specifically, to the first and second sublayers 120a and 120b. For example, gate structure 130 may be adjacent to the top main surface and side surfaces of the second sublayer 120b. Similarly, gate structure 130 may be adjacent to the bottom main surface and side surfaces of the first sublayer 120a. It is conceivable that gate structure 130 forms a gate all-around (GAA). This GAA may surround the first channel layer 120 and the second channel layer 122. In other words, the gate structure 130 may be adjacent to the bottom, top, and side surfaces of the first channel layer 120 and the second channel layer 122, respectively. Therefore, the gate structure 130 can control the first channel layer 120 and the second channel layer 122. Furthermore, it also means that the gate structure 130 may extend between the first channel layer 120 and the second channel layer 122.
[0076] The CMOS device 100 also includes first and second n-type doped S / D regions 132a and 132b associated with the second channel layer 122. Therefore, the first and second n-type doped S / D regions 132a and 132b can form part of another n-type MOSFET. The CMOS device 100 also includes first and second p-type doped S / D regions 134a and 134b associated with the second channel layer 122. Therefore, the first and second p-type doped S / D regions 134a and 134b can form part of another p-type MOSFET. Whenever references are made to the first and second n-type doped S / D regions 132a, 132b / the first and second p-type doped S / D regions 134a, 134b, unless otherwise stated, the above discussion of the geometry, size, material, arrangement, etc. of the first and second n-type doped S / D regions 112a, 112b / the first and second p-type doped S / D regions 114a, 114b also applies to the first and second n-type doped S / D regions 132a, 132b / the first and second p-type doped S / D regions 134a, 134b.
[0077] Therefore, in the bottom-up direction, the layers / elements of the CMOS device 100 can be arranged in the following order: substrate 102; first sublayer 120a and first and second n-type doped source / drain regions 112a, 112b; second sublayer 120b and first and second p-type doped source / drain regions 114a, 114b; second sublayer 122b and first and second p-type doped source / drain regions 134a, 134b; first sublayer 122a and first and second n-type doped source / drain regions 132a, 132b.
[0078] However, as described above, other arrangements of the layers / elements of the CMOS device 100 are also conceivable. For example, in a bottom-up direction, the layers / elements of the CMOS device 100 may be arranged in the following order: substrate 102; second sublayer 120b and first and second p-type doped source / drain regions 114a, 114b; first sublayer 120a and first and second n-type doped source / drain regions 112a, 112b; first sublayer 122a and first and second n-type doped source / drain regions 132a, 132b; second sublayer 122b and first and second p-type doped source / drain regions 134a, 134b.
[0079] Now for reference Figure 2 The figure shows a second CMOS device 200; for clarity, the substrate is not shown. This CMOS device 200 is similar to... Figure 1The first CMOS device 100 shown is similar. Therefore, for the sake of brevity, a detailed discussion of the CMOS device 200 is omitted. Unless otherwise stated, the above discussion of the geometry, size, material, arrangement, etc., of the corresponding layers / elements in the first CMOS device 100 also applies to the corresponding layers / elements in the second CMOS device 200. In summary, the main difference between the second CMOS device 200 and the first CMOS device 100 is that the second CMOS device 200 has first and second p-type doped S / D regions 214a and 214b that are associated with both the first channel layer 120 and the second channel layer 122. Therefore, individual cells of the first and second p-type doped S / D regions 214a and 214b are adjacent to and associated with the first and second channel layers 120 and 122, respectively. In contrast, the first CMOS device 100 includes separate first and second p-type doped S / D regions 114a, 114b associated with the first channel layer 120, and separate first and second p-type doped S / D regions 134a, 134b associated with the second channel layer 122. The first and second p-type doped S / D regions 214a, 214b extend between the first and second channel layers 120, 122. The first and second p-type doped S / D regions 214a, 214b are adjacent to second sublayers 120b, 122b of the first and second channel layers 120, 122.
[0080] Another key difference between the second CMOS device 200 and the first CMOS device 100 is that the first and second n-type doped S / D regions 212a and 212b (associated with the first channel layer 120) are further adjacent to the bottom surface of the first channel layer 120 (i.e., adjacent to the bottom of the first sublayer 120a). Similarly, the first and second n-type doped S / D regions 232a and 232b (associated with the second channel layer 122) are adjacent to the top surface of the second channel layer 122 (i.e., adjacent to the top of the first sublayer 122a). Likewise, the order of the layers / elements may differ (e.g., the first sublayers 120a and 122a may be directly opposite each other). Therefore, it is conceivable that the first and second n-type doped S / D regions 212a and 212b could also form a single unit and further be adjacent to the first sublayers 120a and 122a of the first and second channel layers 120 and 122 simultaneously. In this case, a separate p-type doped S / D region associated with the first channel layer 120 and a separate p-type doped S / D region associated with the second channel layer 122 will be provided.
[0081] Now for reference Figure 3The figure shows a third CMOS device 300. The third CMOS device 300 includes a substrate 102 and a first channel layer 320, which includes a first sublayer 320a and a second sublayer 320b. The third CMOS device 300 also includes first and second n-type doped S / D regions 312a, 312b associated with the first sublayer 320a (i.e., they form part of an n-type MOSFET). The third CMOS device 300 also includes first and second p-type doped S / D regions 314a, 314b associated with the second sublayer 320b (i.e., they form part of a p-type MOSFET). The main difference between the third CMOS device 300 and the first and second CMOS devices 100, 200 is that the (main) plane of the first channel layer 320 is set perpendicular to the substrate 102. Therefore, the first channel layer 320 and its sublayers 320a, 320b can be formed as fin structures instead of nanosheets, which have large protrusions in the z-direction. The first and second n-type doped S / D regions 312a and 312b are arranged on the first side of the channel layer 320 (i.e., adjacent to the side of the first sublayer 320a). The first and second p-type doped S / D regions 314a and 314b are arranged on the second side of the channel layer 320 (i.e., adjacent to the side of the first sublayer 320b). The first side and the second side are arranged opposite to each other.
[0082] As shown in the figure, the gate structure 330 can span the channel layer 320. The gate structure 330 shown is adjacent to the first sublayer 320a and the second sublayer 320b of the first channel layer 320. The first channel layer 320 can be disposed above the substrate 102, such that the gate portion is located between the two. As an alternative to the bridging gate structure, the gate structure 330 can be formed as a GAA, which extends between the substrate 102 and the first channel layer 320.
[0083] It is worth noting that the above discussion, for example, regarding the formation methods and material selection of the substrate, S / D region, and channel layer, also applies to the corresponding layers / elements of the CMOS device 300.
[0084] Regardless of whether it is a first, second, or third CMOS device 100, 200, or 300, the first and second sublayers of the first channel layer can be disposed within a distance of 1-10 nm (e.g., 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 nm). The same applies to any second channel layer. In other words, the first and second sublayers of the second channel layer can be disposed within a distance of 1-10 nm (e.g., 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 nm).
[0085] The inventive concept has been described above primarily with reference to a limited number of examples. However, as will be readily understood by those skilled in the art, other examples besides those disclosed above are equally possible within the scope of the inventive concept as defined by the appended claims.
Claims
1. A complementary metal-oxide-semiconductor (CMOS) field-effect device (100; 200; 300), comprising: A substrate (102); a first n-type doped source / drain region, an S / D region (112a; 212a; 312a), and a second n-type doped S / D region (112b; 212b; 312b) disposed above the substrate (102); a first p-type doped S / D region (114a; 214a; 314a) and a second p-type doped S / D region (114b; 214b; 314b) disposed above the substrate (102); a first channel layer (120, 320) disposed above the substrate (102), the first channel layer (120; 320) comprising: a first sublayer (120a; 320a) and a second sublayer (120b; 320b); wherein the first and second n-type doped S / D regions (112a; 212a; 312a, 112b) are... The first and second p-type doped S / D regions (114a; 214a; 314a, 114b; 214b; 314b) are disposed on the first side of the first channel layer (120; 320), and the second and third p-type doped S / D regions (114a; 214a; 314a, 114b; 214b; 314b) are disposed on the second side of the first channel layer (120; 320), and the second side is opposite to the first side; wherein the first and second p-type doped S / D regions (112a; 212a; 312a, 112b; 212b; 312b) are adjacent to the first sublayer (120a; 320a), but not adjacent to the second sublayer (120b; 320b); wherein the first and second p-type doped S / D regions (114a; 214a; 314a, 114b; 214b; 314b) are adjacent to the second sublayer (120a; 320a). 320b) is adjacent to, but not adjacent to, the first sublayer (120a; 320a); wherein the energy of the conduction band edge of the first sublayer (120a; 320a) is lower than the energy of the conduction band edge of the second sublayer (120b; 320b); and wherein the energy of the valence band edge of the first sublayer (120a; 320a) is lower than the energy of the valence band edge of the second sublayer (120b; 320b); and the gate structure (130; 330) is adjacent to the first and second sublayers (120a; 320a, 120b; 320b) of the first channel layer (120; 320).
2. The CMOS device (100; 200; 300) as described in claim 1, wherein, The second sublayer (120b; 320b) contains Si 1-x Ge x , where x is equal to or less than 1.
3. The CMOS device (100; 200; 300) as described in any of the preceding claims, wherein, The first sublayer (120a; 320a) contains Si.
4. The CMOS device (100; 200; 300) as claimed in any of the preceding claims, wherein, The first sublayer (120a; 320a) is under tensile strain, and the second sublayer (120b; 320b) is under compressive strain.
5. The CMOS device (100; 200; 300) as claimed in any of the preceding claims, wherein, The energy difference between the conduction band edge of the first sublayer (120a; 320a) and the valence band edge of the second sublayer (120b; 320b) is equal to or greater than 400 meV.
6. The CMOS device (100; 200; 300) as claimed in any of the preceding claims, wherein, The energy difference between the conduction band edge of the second sublayer (120b; 320b) and the conduction band edge of the first sublayer (120a; 320a) is greater than 100 meV; Furthermore, the energy difference between the valence band edge of the second sublayer (120b; 320b) and the valence band edge of the first sublayer (120a; 320a) is greater than 100 meV.
7. The CMOS device (100; 200) as claimed in any of the preceding claims, wherein, The plane of the first channel layer (120) is configured to be parallel to the substrate (102); wherein the first and second n-type doped S / D regions (112a; 212a, 112b; 212b) are adjacent to at least one of the following: the top surface of the first sublayer (120a); the bottom surface of the first sublayer (120a); the side surface of the first sublayer (120a); and wherein the first and second p-type doped S / D regions (114a; 214a, 114b; 214b) are adjacent to at least one of the following: the top surface of the second sublayer (120b); the bottom surface of the second sublayer (120b); the side surface of the second sublayer (120b).
8. The CMOS device (200) of claim 7, further comprising: A second channel layer (122) disposed above a first channel layer (120) includes: a first sublayer (122a) and a second sublayer (122b); wherein the second sublayer (120b) of the first channel layer (120) is disposed above the first sublayer (120a) of the first channel layer (120), and the second sublayer (122b) of the second channel layer (122) is disposed below the first sublayer (122a) of the second channel layer (122), and wherein the first and second p-type doped S / D regions (214a, 214b) are adjacent to the second sublayer (120b, 214b) of the first and second channel layers (120, 122). 122b) adjacent, or wherein the first sublayer (120a) of the first channel layer (120) is disposed above the second sublayer (120b) of the first channel layer (120), the first sublayer (122a) of the second channel layer (122) is disposed below the second sublayer (122b) of the second channel layer (122), and wherein the first and second n-type doped S / D regions (112a, 112b) are adjacent to the first sublayer (120a, 122a) of the first and second channel layers (120, 122).
9. The CMOS device (200) as claimed in claim 8, wherein, The gate structure (130) is further adjacent to the first and second sub-layers (122a, 122b) of the second channel layer (122).
10. The CMOS device (200) of claim 8 or 9, further comprising first and second n-type doped S / D regions (232a, 232b) associated with the second channel (122), and first and second p-type doped S / D regions (214a, 214b) associated with the second channel (122).
11. The CMOS device (300) according to any one of claims 1-6, wherein, The plane of the first channel layer (320) is set to be perpendicular to the substrate (102).