A semiconductor device and its manufacturing method
By designing a fully floating structure in Nanosheet-GAAFET devices, the problem of large leakage current was solved, gate control performance and current drive capability were improved, power consumption was reduced, and device performance was enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2022-11-25
- Publication Date
- 2026-05-26
AI Technical Summary
Current Nanosheet-GAAFET devices have significant leakage current, leading to increased power consumption and reduced circuit speed.
Design a semiconductor device including a substrate, a source, a drain, and a channel structure. The channel structure is composed of multiple nanosheet stacks, and the gate surrounds the nanosheets. A cavity is located between the channel structure and the substrate and is formed by the channel structure, the source, the drain, and the substrate, constituting a fully floating structure.
Significantly improves gate control performance, reduces subthreshold swing, lowers leakage current and parasitic capacitance, increases drive current, and enhances device performance.
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Figure CN116031301B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. Traditional triple-gate or double-gate Fin Field-Effect Transistors (FinFETs) are limited below the 3-nanometer (nm) node. Since the Nanosheet-Gate all-round Fin Field-Effect Transistor (Nanosheet-GAAFET) breaks through the 3nm node limitation, it has received widespread attention and research.
[0003] Nanosheet-GAAFET is a novel device featuring a gate-around structure and horizontal nanosheets (NS) as the conductive channel. In terms of gate control, the gate-around structure offers superior gate control compared to FinFET devices, effectively suppressing short-channel effects. Regarding current drive, Nanosheet-GAAFET exhibits bulk-inverting inversion carriers, and the increased effective gate width and vertical nanosheet stacking design significantly enhance the device's current drive performance.
[0004] However, the leakage current of current Nanosheet-GAAFETs is relatively large, which increases the power consumption of the device. Summary of the Invention
[0005] In view of this, the purpose of this application is to provide a semiconductor device and a method for manufacturing the same, which can reduce the leakage current of the semiconductor device and improve the performance of the final manufactured semiconductor device.
[0006] This application provides a semiconductor device, the semiconductor device comprising:
[0007] Substrate;
[0008] A source, a drain, and a channel structure are disposed on one side of the substrate, the channel structure being located between the source and the drain, and the channel structure comprising a stack of multiple nanosheets.
[0009] A gate, the gate surrounding the nanosheet;
[0010] A cavity, the cavity being located at least between the channel structure and the substrate, the cavity being formed by the channel structure, the source, the drain and the substrate surrounding it.
[0011] Optionally, the cavity is used to fill a thermally conductive material or a cooling material.
[0012] Optionally, an isotropic process is used to remove a portion of the substrate corresponding to the channel structure to form the cavity between the substrate and the channel structure.
[0013] Optionally, the semiconductor device includes a stop layer located on the side of the source or drain near the cavity.
[0014] Optionally, a high-k dielectric layer may be disposed between the gate and the nanosheet, with a portion of the high-k dielectric layer located on the side of the channel structure closer to the cavity.
[0015] This application provides a method for manufacturing a semiconductor device, the method comprising:
[0016] A substrate is provided, and a stacked structure consisting of alternating layers of a first semiconductor layer and a second semiconductor layer is formed on one side of the substrate;
[0017] The stacked structure is etched to form a source region and a drain region, and a channel region is formed between the source region and the drain region;
[0018] A source and a drain are formed in the source region and the drain region, respectively.
[0019] The first semiconductor layer is replaced with a gate, the gate surrounds the second semiconductor layer, and a stack of multiple second semiconductor layers forms a channel structure;
[0020] A portion of the substrate corresponding to the thickness of the channel structure is removed to form the cavity between the substrate and the channel structure.
[0021] Optionally, removing the portion of the substrate thickness corresponding to the channel structure includes:
[0022] Starting from the target region, a portion of the substrate corresponding to the channel structure is removed using an isotropic process. The substrate includes the target region, which surrounds the source region, drain region, and channel region.
[0023] Optionally, before the source and drain regions are formed, the method further includes:
[0024] A stop layer is formed in the source region and the drain region.
[0025] Optionally, replacing the first semiconductor layer with a gate includes:
[0026] The first semiconductor layer is removed, and a plurality of gaps to be filled are formed between the second semiconductor layers;
[0027] The gate is filled in one of the multiple gaps to be filled.
[0028] Optionally, before filling the gate in the plurality of said gaps to be filled, the method further includes:
[0029] A high-k dielectric layer is formed on the surface of the second semiconductor layer.
[0030] This application provides a semiconductor device including a substrate, a source electrode, a drain electrode, and a channel structure disposed on one side of the substrate. The channel structure is located between the source electrode and the drain electrode and includes a stack of multiple nanosheets. A gate electrode surrounds the nanosheets. A cavity is located at least between the channel structure and the substrate. The cavity is formed by the channel structure, the source electrode, the drain electrode, and the substrate. That is, the cavity is located below the channel structure, the source electrode, and the drain electrode. There are no contacting film layers, which constitutes a fully floating structure. This can significantly improve the gate control performance of the semiconductor device, reduce the subthreshold swing of the semiconductor device, reduce leakage current and parasitic capacitance, increase drive current, and improve the performance of the semiconductor device. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1A A three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this application is shown;
[0033] Figure 1B , Figure 2 and Figure 1C Provided for the embodiments of this application Figure 1A The diagram shows cross-sectional structures of a semiconductor device in various directions.
[0034] Figure 3A , Figure 3B and Figure 3C Provided for the embodiments of this application Figure 1A The diagram shows cross-sectional structures of a semiconductor device in various directions.
[0035] Figure 4 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application is shown;
[0036] Figures 5-22 show schematic diagrams of the structure of a semiconductor device manufactured according to the manufacturing method of the semiconductor device provided in the embodiments of this application. Detailed Implementation
[0037] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0038] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0039] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.
[0040] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink. Traditional triple-gate or double-gate Fin Field-Effect Transistors (FinFETs) are limited at nodes below 3 nanometers (nm). Since Nanosheet Gate-all-round Fin Field-Effect Transistors (Nanosheet-GAAFETs) have broken through the 3nm node limitation, they have received widespread attention and research.
[0041] Nanosheet-GAAFET is a novel device featuring a gate-around structure and horizontal nanosheets (NS) as the conductive channel. In terms of gate control, the gate-around structure offers superior gate control compared to FinFET devices, effectively suppressing short-channel effects. Regarding current drive, Nanosheet-GAAFET exhibits bulk-inverting inversion carriers, and the increased effective gate width and vertical nanosheet stacking design significantly enhance the device's current drive performance.
[0042] However, the current stacked nanosheets have planar devices with poor gate control characteristics or thick bottom fins (sub-fins) at the bottom, which causes large leakage current in Nanosheet-GAAFETs, further increasing the power consumption of the device. In addition, the sub-fins also increase the parasitic capacitance of the device, resulting in a decrease in circuit speed.
[0043] Based on this, embodiments of this application provide a semiconductor device including a substrate, a source electrode, a drain electrode, and a channel structure disposed on one side of the substrate. The channel structure is located between the source electrode and the drain electrode and includes a stack of multiple nanosheets. A gate electrode surrounds the nanosheets, and a cavity is located at least between the channel structure and the substrate. The cavity is formed by the channel structure, the source electrode, the drain electrode, and the substrate surrounding it. In other words, the cavity is located below the channel structure, the source electrode, and the drain electrode, without any contacting film layers, thus forming a fully floating structure. This can significantly improve the gate control performance of the semiconductor device, reduce the subthreshold swing of the semiconductor device, reduce leakage current and parasitic capacitance, increase the drive current, and improve the performance of the semiconductor device.
[0044] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.
[0045] See Figure 1A The figure is a three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this application.
[0046] The semiconductor device provided in this embodiment includes a substrate 110, a source 131, a drain 132, a channel structure, and a gate 160.
[0047] In the embodiments of this application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, or the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.
[0048] In the embodiments of this application, a source 131, a drain 132, and a channel structure are disposed on one side of the substrate 110. The channel structure is disposed between the source 131 and the drain 132, and includes a stack of multiple nanosheets. The channel structure is obtained by removing the first semiconductor layer 121 from the stacked structure. The stacked structure is composed of alternating layers of the first semiconductor layer 121 and the second semiconductor layer 122. That is, the nanosheets in the channel structure are the second semiconductor layer 122 in the stacked structure. (Refer to...) Figure 1B and Figure 2 As shown, where, Figure 1B Provided for the embodiments of this application Figure 1A The diagram shows a cross-sectional view of the semiconductor device in the YY direction. Figure 2 Provided for the embodiments of this application Figure 1AThe diagram shows a cross-sectional structure of the semiconductor device in the XX direction. The cross-sectional structure in the YY direction is parallel to the gate line of the gate, and the cross-sectional structure in the XX direction is parallel to the fin line of the fin.
[0049] Specifically, the width of the nanosheets can be 5-50 nm, and the thickness of the nanosheets can be 3-20 nm.
[0050] In the embodiments of this application, there is a gap between the multiple nanosheets in the channel structure, and the gap is filled with a gate 160, that is, the gate 160 surrounds the nanosheets to form a ring gate structure.
[0051] In embodiments of this application, a cavity 200 is provided between the channel structure and the substrate 110, as referenced. Figure 1C As shown, Figure 1C Provided for the embodiments of this application Figure 1A The diagram shows a cross-sectional structure of the semiconductor device along the CC direction. The CC direction is parallel to the YY direction, meaning... Figure 1C This is obtained by cross-sectioning the source 131 or drain 132 of the semiconductor device in the direction parallel to the gate line. The cavity 200 is formed by the channel structure, source 131, drain 132, and substrate 110, meaning the channel structure and substrate 110 are not in contact, constituting a fully floating structure. In other words, there is a cavity below the channel structure, source 131, and drain 132, without any contacting film layers. This allows for the absence of large-area bottom fins under the nanosheet stack, which can significantly improve the gate control performance of the semiconductor device, reduce the subthreshold swing, reduce leakage current and parasitic capacitance, increase drive current, and improve the performance of the semiconductor device.
[0052] In practical applications, the source 131 or drain 132 is often formed using the (111) crystal plane, so the cross-section of the source 131 or drain 132 is rhomboid.
[0053] Specifically, the width of the cavity can be adjusted according to the actual situation, for example, from 100 nanometers to 10 micrometers.
[0054] In embodiments of this application, the cavity may also be filled with a thermally conductive or cooling material, which can increase the heat dissipation of the channel structure and improve the self-heating effect. The cooling material may be, for example, in the form of microfluidic water cooling.
[0055] In the embodiments of this application, the cavity 200 can be formed by removing a portion of the substrate 110 corresponding to the channel structure using an isotropic process. That is, the portion of the substrate 110 below the channel structure is hollowed out using an isotropic process to form the cavity 200.
[0056] In embodiments of this application, a stop layer 190 may be provided on the side of the source 131 or drain 132 near the cavity 200, as shown in the reference. Figure 3A , Figure 3B and Figure 3C As shown, the stop layer 190 can be used to remove a portion of the substrate 110 using an isotropic process without damaging the source 131 or drain 132. The material of the stop layer 190 can be selected to be a material that has etching selectivity with the material of the substrate 110.
[0057] As an example, the substrate 110 is made of silicon, and the stop layer 190 can be made of silicon-germanium.
[0058] In embodiments of this application, a high-k dielectric layer 150 may also be disposed between the gate 160 and the nanosheet, that is, the high-k dielectric layer 150 is disposed around the nanosheet, as shown in the reference. Figure 3A , Figure 3B and Figure 3C As shown, a portion of the high-k dielectric layer 150 is located on the side of the channel structure closest to the cavity 200. The high-k dielectric layer 150 allows for the removal of a portion of the substrate 110 using an isotropic process without damaging the channel structure. The material of the high-k dielectric layer 150 can be selected to have etching selectivity with the material of the substrate 110.
[0059] As an example, the material of the high-k dielectric layer 150 can be HfO2 or HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO x One or a combination of Ta2O5 or La2O3.
[0060] In embodiments of this application, the semiconductor device further includes a trench isolation 203, a second sidewall 205, an isolation layer 207, a top dielectric layer 170, and a contact electrode 180.
[0061] Shallow trench isolation 203 is disposed between different fins. The surface of the shallow trench isolation 203 away from the substrate 110 can be flush with, or higher than or lower than, the surface of the stacked structure in the fins near the substrate 110. The shallow trench isolation 203 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the channels on adjacent fins.
[0062] The second sidewall 205 is disposed on the side of the channel structure away from the substrate 110, and the gate 160 is located between the second sidewalls 205. The isolation layer 207 is disposed on the side of the source 131 or drain 132 away from the substrate 110, and the second sidewall 205 and the gate 160 are located between the isolation layers 207.
[0063] The top dielectric layer 170 covers the isolation layer 207, the second sidewall 205 and the gate 160. The top dielectric layer 170 has a contact electrode 180 for electrically leading out the source 131 or the drain 132.
[0064] Therefore, the embodiments of this application provide a semiconductor device including a substrate, a source electrode, a drain electrode, and a channel structure disposed on one side of the substrate. The channel structure is located between the source electrode and the drain electrode and includes a stack of multiple nanosheets. A gate electrode surrounds the nanosheets and a cavity is located at least between the channel structure and the substrate. The cavity is formed by the channel structure, the source electrode, the drain electrode, and the substrate. That is, there is a cavity below the channel structure, the source electrode, and the drain electrode, without any contacting film layers, which constitutes a fully floating structure. This can significantly improve the gate control performance of the semiconductor device, reduce the subthreshold swing of the semiconductor device, reduce leakage current and parasitic capacitance, increase the drive current, and improve the performance of the semiconductor device.
[0065] Based on the semiconductor device provided in the above embodiments, this application also provides a method for manufacturing a semiconductor device, and its working principle will be described in detail below with reference to the accompanying drawings.
[0066] See Figure 4 The figure is a schematic flowchart of a semiconductor device manufacturing method provided in an embodiment of this application.
[0067] The method for manufacturing a semiconductor device provided in this application includes the following steps:
[0068] S101, a substrate 110 is provided, and a stacked structure consisting of alternating layers of a first semiconductor layer 121 and a second semiconductor layer 122 is formed on one side of the substrate 110, with reference to... Figure 5A and Figure 5B As shown.
[0069] In the embodiments of this application, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, or the substrate 110 may be doped to obtain a P-type semiconductor substrate or an N-type semiconductor substrate, such as a P-type silicon substrate or an N-type silicon substrate.
[0070] As an example, the desired well depth can be achieved by implanting impurities into a bulk silicon substrate and then annealing it to form a highly doped well region. The doping type of the substrate 110 varies depending on the device type. For P-type semiconductor devices, the highly doped well region is an N-well, and the implanted impurities are n-type impurity ions, such as phosphorus (P) ions. For N-type semiconductor devices, the highly doped well region is a p-well, and the implanted impurities are p-type impurity ions, such as boron (B) ions.
[0071] In embodiments of this application, a stacked structure consisting of alternating layers of a first semiconductor layer 121 and a second semiconductor layer 122 can be formed on one side of the substrate 110, as shown in the reference. Figure 5A and Figure 5B As shown, where, Figure 5A Provided for the embodiments of this application Figure 1A The diagram shows a cross-sectional view of the semiconductor device in the YY direction. Figure 5B Provided for the embodiments of this application Figure 1A The diagram shows a cross-sectional structure of the semiconductor device in the XX direction. The cross-sectional structure in the YY direction is parallel to the gate line of the gate, and the cross-sectional structure in the XX direction is parallel to the fin line of the fin.
[0072] Specifically, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be the same. For example, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon or germanium. Alternatively, depending on the device type, the materials of the first semiconductor layer 121 and the second semiconductor layer 122 can be different. For example, for a P-type semiconductor device, the material of the first semiconductor layer 121 can be silicon, and the material of the second semiconductor layer 122 can be silicon-germanium. For an N-type semiconductor device, the material of the first semiconductor layer 121 can be silicon-germanium, and the material of the second semiconductor layer 122 can be silicon.
[0073] In practical applications, silicon oxide may be formed on the substrate 110. The stacked structure can be formed after the silicon oxide on the substrate 110 is removed and the substrate 110 is cleaned.
[0074] S102, etching is performed on the stacked structure to form the source region 101 and the drain region 102, reference. Figure 11A and Figure 11B As shown.
[0075] In embodiments of this application, the stacked structure can be etched to form a source region 101 and a drain region 102, wherein a channel region 103 is formed between the source region 101 and the drain region 102. (Refer to...) Figure 11A and Figure 11B As shown.
[0076] The specific process flow for forming the source region 101 and the drain region 102 is as follows:
[0077] S1021, Sidewall Transfer Process, Reference Figure 6A and Figure 6B As shown.
[0078] In the embodiments of this application, a self-aligned sidewall transfer process is used to form the first sidewall 201. The material of the first sidewall 201 is silicon nitride. The specific formation process is as follows: a sacrificial layer 202 is covered on the stacked structure. The material of the sacrificial layer 202 can be polycrystalline silicon or amorphous silicon. Part of the sacrificial layer 202 is etched away using photolithography to form a pattern. Silicon nitride material is deposited. Then, anisotropic etching is used to etch away the remaining sacrificial layer 202, so that only the first sidewall 201 on the stacked structure remains. The first sidewall 201 plays the role of a hard mask in the subsequent photolithography for forming fins.
[0079] S1022, forming fins, see reference. Figure 7A and Figure 7B As shown.
[0080] In the embodiments of this application, the stacked structure can be etched using an etching process to form multiple periodically distributed fins, as shown in the reference. Figure 7A and Figure 7B As shown, etching is performed using the first sidewall 201 as a mask to form a fin with a stacked structure. The upper part of the fin is the channel region 103 formed by the stacked structure, and the lower part of the fin is the substrate 110, forming a structure as shown. Figure 7A The fin shown is not only a stacked structure but also includes a single-crystal silicon structure extending into the substrate 110. The etching process can be dry etching or wet etching, and in one embodiment, reactive ion etching can be used. The fin will be used to form nanosheets for semiconductor devices. Although Figure 7A A fin is shown, and it should be understood that any suitable number and shape of fins can be used in practical applications.
[0081] S1022, forming shallow trench isolation 203 (STI), see reference. Figure 8A and Figure 8B As shown.
[0082] In embodiments of this application, shallow trench isolation 203 can be formed between different fins. Specifically, a dielectric insulating material can be deposited first, followed by a planarization process, such as CMP, and then a selective etch-back process of the dielectric insulating material to expose the three-dimensional fins, thereby forming shallow trench isolation 203 between adjacent fins. The surface of the shallow trench isolation 203 away from the substrate 110 can be flush with, or higher than, the surface of the stacked structure in the fins near the substrate 110. The shallow trench isolation 203 can be formed of a suitable dielectric material, such as silicon dioxide or silicon nitride. The function of the shallow trench isolation 203 is to separate the channels on adjacent fins.
[0083] In practical applications, when forming shallow trench isolation 203, the first sidewall 201 can also be removed.
[0084] S1023, forming a dummy gate 204, reference. Figure 9A and Figure 9B As shown.
[0085] In embodiments of this application, a dummy gate stack is formed on the exposed fin in a direction perpendicular to the fin lines, i.e., in the YY direction. The dummy gate stack is a multi-layer structure, including a gate insulating dielectric layer (not shown), a dummy gate 204, and a hard mask layer (not shown). The dummy gate stack can be formed using processes such as thermal oxidation, chemical vapor deposition, or sputtering. The dummy gate stack spans the stack structure above the fin, with multiple dummy gates periodically distributed along the fin line direction. The material of the dummy gate 204 can be polycrystalline silicon or amorphous silicon. The material of the hard mask layer can be oxides, carbides, organic materials, etc.
[0086] S1024, forming the second sidewall 205, see reference. Figure 10A and Figure 10B As shown.
[0087] In the embodiments of this application, second sidewalls 205 can be provided on both sides of the dummy gate stack along the fin direction, i.e., the XX direction, and the thickness of the second sidewalls 205 on both sides is the same. The material of the second sidewalls 205 can be a dielectric material with isolation properties, such as silicon nitride or doped silicon oxide.
[0088] In the embodiments of this application, after forming the dummy gate 204 and the second sidewall 205, the dummy gate 204 and the second sidewall 205 can be used as masks to perform source and drain etching on the stacked structure through an etching process, specifically source and drain etching on the fins. The source region 101 and the drain region 102 no longer have a stacked structure after etching. (Refer to...) Figure 11B As shown.
[0089] S103, source 131 and drain 132 are formed in source region 101 and drain region 102, respectively, reference. Figure 15A and Figure 15B As shown.
[0090] In the embodiments of this application, after etching the stacked structure to form the source region 101 and the drain region 102, a source 131 and a drain 132 can be formed in the source region 101 and the drain region 102, respectively. (Refer to...) Figure 14A and Figure 14B As shown.
[0091] Specifically, the source and drain materials may differ for different types of semiconductor devices. For P-type semiconductor devices, the source and drain materials are boron-doped germanium silicon, i.e., SiGe:B. For N-type semiconductor devices, the source and drain materials are phosphorus-doped silicon, i.e., Si:P.
[0092] In the embodiments of this application, before forming the source 131 and drain 132, a stop layer 190 may be formed in the source region 101 and drain region 102. The specific process flow is as follows:
[0093] S1031, forming a concave structure 401, reference. Figure 12A and Figure 12B As shown.
[0094] In the embodiments of this application, along the XX direction, the first semiconductor layer 121 in the stacked structure located in the channel region 103 is selectively etched, that is, only the first semiconductor layer 121 is etched, without damaging the second semiconductor layer 122. Along the XX direction, the portion of the first semiconductor layer 121 missing from the second semiconductor layer 122 forms a concave structure 401, that is, pull-back etching is performed, etching away a portion of the first semiconductor layer 121 from the source region 101 and drain region 102 towards the channel region 103. (Refer to...) Figure 12A and Figure 12B As shown.
[0095] S1032, forming the third sidewall 206, reference. Figure 13A and Figure 13B As shown.
[0096] In the embodiments of this application, after the first semiconductor layer 121 is etched, a dielectric material is deposited on the stacked structure located in the channel region 103, i.e., the periphery of the fins. The dielectric material is etched to form a third sidewall 206. The third sidewall 206 is flush with the second semiconductor layer 122 in a direction perpendicular to the plane of the substrate 110. That is, the concave structure 401 caused by etching in S1031 is filled by the third sidewall 206. The material of the third sidewall 206 can be silicon nitride or silicon oxide.
[0097] S1033, forming stop layer 190, reference. Figure 14A and Figure 14B As shown.
[0098] In the embodiments of this application, a stop layer 190 can be formed using an epitaxial process. Subsequently, the stop layer 190 can be used to prevent damage to the source 131 or drain 132 when a portion of the substrate 110 is removed using an isotropic process. The material of the stop layer 190 can be selected as a material that has etching selectivity with the material of the substrate 110.
[0099] As an example, the substrate 110 is made of silicon, and the stop layer 190 can be made of silicon-germanium.
[0100] In practical applications, for P-type semiconductor devices, the source and drain materials are boron-doped germanium silicon. In this case, the source 131 or drain 132 can be formed directly without the need for an additional process to form the stop layer 190. This can save process steps and reduce manufacturing costs. For N-type semiconductor devices, the source and drain materials are phosphorus-doped silicon. The stop layer 190 can be formed using epitaxial processes.
[0101] In embodiments of this application, after forming the source 131 and drain 132, the dummy gate 204 can be removed, see reference. Figure 16A and Figure 16B As shown.
[0102] In embodiments of this application, an isolation layer 207 can be deposited on the surfaces of the dummy gate 204, source 131, and drain 132 to prevent short circuits between the dummy gate 204 and the source 131 or drain 132 in subsequent steps. The isolation layer 207 is then subjected to a chemical mechanical polishing process to planarize it. Then, as... Figure 16A and Figure 16B As shown, the dummy gate 204 formed by the aforementioned polycrystalline silicon or amorphous silicon is etched or etched away by selective etching or etching processes, that is, the dummy gate 204 is removed.
[0103] S104, replace the first semiconductor layer 121 with the gate 160, as shown in Figures 17-19.
[0104] In embodiments of this application, the first semiconductor layer 121 can be replaced with the gate 160, as shown in Figures 17-19.
[0105] The specific process flow is as follows:
[0106] S1041, Remove the first semiconductor layer 121 of the channel region 103, Reference Figure 17A and Figure 17B As shown.
[0107] In embodiments of this application, the first semiconductor layer 121 of the channel region 103 can be removed, i.e., a nanosheet channel release process can be performed, so as to form a plurality of gaps 402 to be filled between the second semiconductor layers 122, see reference. Figure 17A and Figure 17B As shown.
[0108] Specifically, the first semiconductor layer 121 in the stacked structure located in the channel region 103 can be selectively etched to release the nanosheet channel. That is, the stacked structure exposed by the fins is processed to remove the first semiconductor layer 121 of each layer, which is the sacrificial layer, to release the nanosheets formed by the second semiconductor layer 122.
[0109] In the embodiments of this application, there are several possible ways to achieve nanosheet channel release for different types of devices:
[0110] In a first possible implementation, for both P-type and N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon-germanium. The silicon-germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-laminated nanosheet stack device. In the selective removal process, an etchant that selectively etches silicon-germanium at a faster rate than silicon can be used.
[0111] In a second possible implementation, for a P-type semiconductor device, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon. Silicon is selectively removed, leaving the second semiconductor layer 122, i.e., silicon-germanium, to form a silicon-germanium stacked nanosheet device. In the selective removal process, an etchant that selectively etches silicon at a faster rate than silicon-germanium can be used.
[0112] In a third possible implementation, for N-type semiconductor devices, the first semiconductor layer 121, i.e., the sacrificial layer, is made of silicon-germanium. The silicon-germanium is selectively removed, leaving the second semiconductor layer 122, i.e., silicon, to form a silicon-stacked nanosheet device. In the selective removal process, an etchant that selectively etches silicon-germanium at a faster rate than silicon can be used.
[0113] S1042, a high-k dielectric layer 150 is formed on the surface of the second semiconductor layer 122, reference. Figure 18A and Figure 18B As shown.
[0114] In embodiments of this application, after removing the first semiconductor layer 121, a high-k dielectric layer 150 can be formed on the surface of the second semiconductor layer 122. The high-k dielectric layer 150 surrounds the surface of the second semiconductor layer 122. (Refer to...) Figure 18A and Figure 18B As shown. Specifically, the material of the high-k dielectric layer 150 can be HfO2 or HfSiO2. x HfON, HfSiON, HfAlO x HfLaO x Al2O3, ZrO2, ZrSiO x One or a combination of Ta2O5 or La2O3.
[0115] S1043, fill the gate 160 in multiple gaps 402 to be filled, reference Figure 19A and Figure 19B As shown.
[0116] In the embodiments of this application, after the nanosheet channel is released, there are multiple gaps 402 to be filled between the multiple second semiconductor layers 122. A gate 160 can be filled into these gaps 402, and the gate 160 surrounds the second semiconductor layers 122, forming a gate-ring structure. The stack of multiple second semiconductor layers 122 forms a channel structure, i.e., a nanosheet channel for a semiconductor device. (Refer to...) Figure 19A and Figure 19B As shown.
[0117] In practical applications, in addition to forming the gate 160 in the gap 402 to be filled, the gate 160 also covers the space after the isolation layer 207 and the dummy gate 204 is removed. The gate 160 covered by the isolation layer 207 can be chemically mechanically polished to perform planarization.
[0118] S105, Remove the portion of substrate 110 corresponding to the thickness of the channel structure, reference. Figure 22A , Figure 22B and Figure 22C As shown.
[0119] In the embodiments of this application, a portion of the substrate 110 corresponding to the channel structure can be removed, that is, the substrate 110 under the channel structure and the source 131 or drain 132 can be removed to form a cavity 200 between the substrate 110 and the channel structure, forming a fully floating structure and improving the performance of the semiconductor device.
[0120] refer to Figure 21 The diagram shown is a top view of a semiconductor device according to an embodiment of this application. Figure 21 The diagram shows that the substrate 110 includes a source region 101, a drain region 102, and a channel region 103. The target region 104 is the region in the substrate 110 other than the source region 101, the drain region 102, and the channel region 103. The target region 104 may surround the source region 101, the drain region 102, and the channel region 103.
[0121] Specifically, starting from target region 104, the isolation layer 207 is etched to form via 208. Then, isotropic etching is performed on the substrate 110 located in target region 104. This isotropic process removes a portion of the substrate 110 corresponding to the channel structure. (Refer to...) Figure 22A , Figure 22B and Figure 22C As shown.
[0122] In the embodiments of this application, when a portion of the substrate 110 is removed using an isotropic process, the materials of the stop layer 190, the high-K dielectric layer 150, the isolation layer 207, and the shallow trench isolation 203 all have a high selectivity ratio with the material of the substrate 110, and therefore will not be damaged.
[0123] Specifically, isotropic processes can be dry etching or wet etching, such as wet etching using TMAH solution.
[0124] In embodiments of this application, after forming the gate 160, dielectric deposition can be performed on the top of the semiconductor device away from the substrate 110 to form a top dielectric layer 170, as shown in the reference. Figure 20A , Figure 20B and Figure 20C As shown, after forming the top dielectric layer 170, an isotropic process can be performed to form the cavity 200. This allows the top dielectric layer 170 to protect the gate 160, preventing the gate 160 from being affected when etching away the substrate 110, thus improving the performance of the semiconductor device.
[0125] In the embodiments of this application, after forming the cavity 200, contact hole etching is performed in the top dielectric layer 170, etching down to the surface of the source 131 or drain 132. Metal material is deposited in the contact holes to form the contact electrodes 180 of the source 131 or drain 132. (Refer to...) Figure 3A and Figure 3B As shown, subsequent processes include multi-layer back-end interconnection and passivation protection.
[0126] In practical applications, when removing a portion of the substrate 110, the isolation layer 207 of the target region 104 is etched to form vias 208. A dielectric material can be deposited using plasma-enhanced chemical vapor deposition to fill the etched vias 208. (Refer to...) Figure 3C As shown.
[0127] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. In particular, structural embodiments are generally similar to method embodiments and are therefore described simply; relevant details can be found in the descriptions of the method embodiments.
[0128] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.
Claims
1. A semiconductor device, characterized by, The semiconductor device includes: Substrate; A source, a drain, and a channel structure are disposed on one side of the substrate, the channel structure being located between the source and the drain, and the channel structure comprising a stack of multiple nanosheets. A gate, the gate surrounding the nanosheet; A cavity is located between the channel structure, the source, the drain, and the substrate, and the cavity is formed by the channel structure, the source, the drain, and the substrate surrounding it; specifically, a portion of the substrate corresponding to the thickness of the channel structure is removed using an isotropic process to form the cavity between the substrate and the channel structure; the semiconductor device includes a stop layer located on the side of the source or the drain near the cavity.
2. The semiconductor device according to claim 1, wherein The cavity is used to fill thermally conductive or cooling materials.
3. The semiconductor device of claim 1, wherein A high-k dielectric layer is disposed between the gate and the nanosheet, with a portion of the high-k dielectric layer located on the side of the channel structure closer to the cavity.
4. A method for manufacturing a semiconductor device, characterized in that, The method includes: A substrate is provided, and a stacked structure consisting of alternating layers of a first semiconductor layer and a second semiconductor layer is formed on one side of the substrate; The stacked structure is etched to form a source region and a drain region, and a channel region is formed between the source region and the drain region; A stop layer is formed in the source region and the drain region; A source and a drain are formed in the source region and the drain region, respectively. The first semiconductor layer is replaced with a gate, the gate surrounds the second semiconductor layer, and a stack of multiple second semiconductor layers forms a channel structure; A portion of the substrate corresponding to the channel structure is removed to form a cavity between the substrate and the channel structure, the source, and the drain; specifically, starting from a target region, a portion of the substrate corresponding to the channel structure is removed using an isotropic process, the substrate including the target region, the target region surrounding the source region, the drain region, and the channel region.
5. The manufacturing method according to claim 4, characterized in that, The step of replacing the first semiconductor layer with a gate includes: The first semiconductor layer is removed, and a plurality of gaps to be filled are formed between the second semiconductor layers; The gate is filled in one of the multiple gaps to be filled.
6. The manufacturing method according to claim 5, characterized in that, Before filling the gates in the plurality of said gaps to be filled, the method further includes: A high-k dielectric layer is formed on the surface of the second semiconductor layer.