Isolation and interconnection based copolymer organic semiconductor devices and methods of fabrication

Abstract

The application discloses a kind of copolymer organic semiconductor devices based on isolation and interconnection and preparation method, including substrate, photoetching blocking layer, insulating isolation layer, N organic field effect transistor and N-1 interconnection line;Photoetching blocking layer includes isolation layer and inorganic dielectric layer;Isolation layer is opened with N longitudinal through isolation groove along length direction;Inorganic dielectric layer includes lower dielectric layer and upper dielectric layer;Lower dielectric layer is located in N isolation, and upper dielectric layer is laid on the top of isolation layer and lower dielectric layer;Each organic field effect transistor includes semiconductor layer, source, drain and gate;Semiconductor layer is laid in the isolation groove at the bottom of corresponding lower dielectric layer section, and its material is organic copolymer.The application effectively utilizes isolation groove and photoetching blocking layer, and the semiconductor layer of different semiconductor materials is wrapped and isolated, so as to realize the integration of different organic field effect transistors on the same substrate, and the organic field effect transistor can realize effective interconnection.

Description

Technical Field

[0001] This invention relates to a testing device, and more particularly to a copolymer organic semiconductor device based on isolation and interconnection, and its preparation method. Background Technology

[0002] Currently, the fabrication technology for individual organic field-effect transistors is relatively mature. However, most organic field-effect transistors use solution spin coating processes, which makes it impossible to fabricate devices with different polarities or different semiconductor materials on the same substrate. This greatly hinders the integration and diversification of organic field-effect transistors and limits the development of organic chips.

[0003] The manufacturing of integrated circuits requires isolation technology to separate different devices on a unified substrate. This is because different devices have different potentials and need to be insulated from each other; otherwise, the devices would conduct directly through the semiconductor layer, making it impossible to form a circuit. Chip isolation technologies mainly include PN junction isolation, LOCOS isolation, and shallow trench isolation. However, these isolation technologies all require photolithography. Due to the unique properties of organic materials, traditional fabrication methods cannot be fully applied to organic semiconductors, because the developing solution used in the photolithography process and the NMP solution or acetone solution used in the cleaning steps can dissolve the semiconductor material and the organic dielectric layer material.

[0004] Device isolation and interconnect technology requires not only isolation techniques but also chemical mechanical polishing (CMP). This is because circuit interconnects involve multi-layer wiring, and repeated thin-film deposition and photolithography can roughen the surface, introducing numerous defects. CMP planarizes the device surface, achieving high planarity, low surface roughness, and low defects, allowing for successful subsequent photolithography. However, this technique uses chemical reagents, which can potentially erode the semiconductor layer and even the organic dielectric layer. Since the semiconductor layer is a thin film manufactured using solution spin-coating, its adhesion to the substrate is low, and it can withstand low stress; it can be easily scraped off with metal tweezers, making it unable to withstand the high stress of CMP. Therefore, the use of interconnect technology cannot achieve effective device isolation, hindering the implementation of CMOS processes based on organic field-effect transistors (OFETs), significantly impeding the integration of OFETs, and even impacting the development of organic integrated circuits. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a copolymer organic semiconductor device and preparation method based on isolation and interconnection. The copolymer organic semiconductor device and preparation method based on isolation and interconnection effectively utilizes isolation trenches and photolithography blocking layers to encapsulate and isolate semiconductor layers of different semiconductor materials, thereby realizing the integration of different organic field-effect transistors on the same substrate, and the organic field-effect transistors can achieve effective interconnection.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] An organic copolymer semiconductor device based on isolation and interconnection includes a substrate, a photolithographic blocking layer, an insulating isolation layer, N organic field-effect transistors, an external source metal, an external drain metal, and N-1 interconnects; wherein N≥2.

[0008] The substrate, photolithography barrier layer, and insulating isolation layer are stacked sequentially from bottom to top.

[0009] The photolithography blocking layer includes an isolation layer and an inorganic dielectric layer; wherein, the isolation layer has N longitudinally penetrating isolation trenches along its length; the inorganic dielectric layer includes a lower dielectric layer and an upper dielectric layer; the lower dielectric layer includes N lower dielectric layer segments located on top of the N isolation trenches; the upper dielectric layer is laid on top of the isolation layer and the lower dielectric layer.

[0010] Each organic field-effect transistor includes a semiconductor layer, a source, a drain, and a gate.

[0011] The semiconductor layer is placed in the isolation trench at the bottom of the corresponding lower dielectric layer segment, and its material is an organic copolymer.

[0012] Both the source and drain include a source / drain metal body and source / drain metal leads; the source / drain metal leads include a lower metal via, a transitional source / drain metal, and an upper metal via, which are electrically connected sequentially from bottom to top.

[0013] The source / drain metal body is embedded in the corresponding lower dielectric layer segment, and the lower metal via is set in the upper dielectric layer, with its bottom electrically connected to the source / drain metal body; the transition source / drain metal and the upper metal via are both set in the insulating isolation layer.

[0014] In N organic field-effect transistors, the outermost source is called the external source, and the remaining N-1 sources are called the internal sources; in N organic field-effect transistors, the outermost drain is called the external drain, and the remaining N-1 drains are called the internal drains.

[0015] The external source electrode is provided with the external source metal on its top, and the external drain electrode is provided with the external drain metal on its top.

[0016] The N-1 internal sources and N-1 internal drains are connected by N-1 interconnects.

[0017] The external source metal, external drain metal, and N-1 interconnects are all located on top of the insulating isolation layer.

[0018] By changing the gate bias voltage of N organic field-effect transistors, the N-type / P-type polarity conversion of the corresponding organic field-effect transistors can be achieved.

[0019] The dielectric constant K of the photolithographic barrier layer is no less than 3, and the sidewall width of each isolation trench can reach 2μm.

[0020] The photolithography barrier layer is SiO2, Si3N4, Al2O3, phosphosilicate glass, borosilicate glass, or semi-insulating polycrystalline silicon.

[0021] The thicknesses of the substrate, isolation layer, semiconductor layer, lower dielectric layer, upper dielectric layer, and insulating isolation layer are 0.5 mm, 100 nm, 50 nm, 50 nm, 250 nm, and 1 μm, respectively; the thicknesses of the source / drain metal body, lower metal via, transition source / drain metal, and upper metal via are 50 nm, 250 nm, 80 nm, and 920 nm, respectively; and the thicknesses of the external source metal, external drain metal, and N-1 interconnects are all 50 nm.

[0022] The semiconductor layer is made of organic compounds such as pentacene, DPPT-TT, P3HT, or naphthalimide-based N-type polymers.

[0023] A method for fabricating a copolymer organic semiconductor device based on isolation and interconnection includes the following steps.

[0024] Step 1: Grow the isolation layer: Grow an isolation layer on a clean substrate and etch N longitudinally penetrating isolation trenches along the length of the isolation layer.

[0025] Step 2, depositing a semiconductor layer: deposit a semiconductor layer made of organic copolymer material on the top of each isolation tank.

[0026] Step 3: Deposit the lower dielectric layer segment: In the isolation trench at the top of each semiconductor layer, a lower dielectric layer segment is deposited, and the top of the lower dielectric layer segment is flush with the top of the isolation layer; all lower dielectric layer segments are collectively referred to as the lower dielectric layer.

[0027] Step 4: Evaporation of source / drain metal body: Two vias are etched in each lower dielectric layer segment, and source / drain metal body is vapor-deposited in each via.

[0028] Step 5: Growth of the upper dielectric layer: An upper dielectric layer of not less than 200 nm is generated on top of the isolation layer and the lower dielectric layer. The top of the upper dielectric layer can be polished flat using CMP process. The isolation layer, the lower dielectric layer and the upper dielectric layer together constitute the photolithography barrier layer, and all of them are made of the same inorganic material.

[0029] Step 6: Deposit lower metal vias: Etch a via 2 in the upper dielectric layer directly above each source / drain metal body, and deposit the same metal as the source / drain metal body into each via 2 to form a lower metal via.

[0030] Step 7: Evaporate transition source / drain metal and gate: Evaporate a layer of metal identical to the source / drain metal body on top of each lower metal via to form transition source / drain metal; at the same time, evaporate a gate on top of the upper dielectric layer between two adjacent transition source / drain metals.

[0031] Step 8: Generate an insulating isolation layer: Deposit an insulating isolation layer of not less than 900nm on top of the upper dielectric layer. The insulating isolation layer covers the transition source drain metal and the gate, forming an isolation between the transition source drain metal and the gate. The top of the insulating isolation layer can be polished flat using CMP process.

[0032] Step 9: Deposit upper metal vias: Etch a via three in the insulating layer directly above each transition source / drain metal, and deposit the same metal as the source / drain metal body into each via three to form upper metal vias.

[0033] Step 10: Evaporate external source metal, external drain metal, and N-1 interconnects: The outermost source of the N organic field-effect transistors is called the external source, and the remaining N-1 sources are called internal sources; the outermost drain of the N organic field-effect transistors is called the external drain, and the remaining N-1 drains are called internal drains; Evaporate external source metal on top of the external source and external drain metal on top of the external drain; Simultaneously, Evaporate N-1 interconnects on top of the insulating isolation layer to connect the N-1 internal sources and N-1 internal drains respectively.

[0034] In step 4, the evaporation rate of the source / drain metal body, in step 6, the evaporation rate of the lower metal via, and in step 9, the evaporation rate of the upper metal via all do not exceed 0.2 Å / s; in step 7, the evaporation rates of the transition source / drain metal, the gate, and in step 10, the external source metal, the external drain metal, and the N-1 interconnects all do not exceed 1 Å / s.

[0035] In step 4, the evaporation rate of the source / drain metal body, in step 6, the evaporation rate of the lower metal via, and in step 9, the evaporation rate of the upper metal via all do not exceed 0.1 Å / s; in step 7, the transition source / drain metal, the gate, and in step 10, the external source metal, the external drain metal, and the N-1 interconnects are all evaporated using three layers: upper, middle, and lower. The evaporation rates of the lower and upper layers do not exceed 0.1 Å / s, and the evaporation rate of the middle layer is 0.5 Å / s.

[0036] The cross-sectional widths of both through-hole 2 and through-hole 3 do not exceed the cross-sectional width of the source / drain metal body.

[0037] The present invention has the following beneficial effects:

[0038] 1. This invention utilizes materials such as SiO2, Si3N4, and Al2O3 as isolation trenches and photolithography barrier layers. This not only protects the semiconductor layer material from contamination and damage caused by organic solvents such as developer, NMP, and acetone during photolithography, but also firmly encapsulates the semiconductor layer material. The isolation trenches effectively reduce the spacing between devices. Furthermore, the high dielectric constant of inorganic materials such as SiO2 enhances the isolation performance of the devices, requiring only a few micrometers of width to achieve good isolation. Therefore, it enables the isolation of different devices on the same substrate, eliminating the need for increased spacing or laser-induced substrate ablation for interconnection. This significantly improves integration, repeatability, manufacturability, stability, and device performance. Simultaneously, it exhibits low equipment dependence, simple fabrication process, low cost, and high yield.

[0039] 2. In this invention, the inorganic dielectric layer and the isolation layer use the same inorganic material, such as SiO2. While encapsulating the semiconductor layer, the inorganic dielectric layer and the isolation layer have better fusion and encapsulation, and the thickness of the dielectric layer can be more precisely controlled, which greatly improves the gate control performance of the device and effectively reduces the leakage current of the device.

[0040] 3. Inorganic materials such as SiO2 have high stress, which enables the effective use of CMP process in subsequent interconnect technologies to ensure the flatness of each layer of material in the device.

[0041] 4. By using materials such as SiO2, Si3N4, and Al2O3 as the inorganic dielectric layer, this invention can provide better gate control performance and significantly improve the conduction characteristics of the device. Attached Figure Description

[0042] Figure 1 This diagram shows a structural schematic of a copolymer organic semiconductor device based on isolation and interconnection according to the present invention.

[0043] Figure 2The flowchart shows a method for fabricating a copolymer organic semiconductor device based on isolation and interconnection according to the present invention.

[0044] The components include: 1. Substrate; 2. Isolation layer; 3. Semiconductor layer; 4. Lower dielectric layer; 5. Source / drain metal body; 6. Upper dielectric layer; 7. Lower metal via; 8. Insulating isolation layer; 9. Transition source / drain metal; 10. Gate; 11. Upper metal via; 12. External source metal; 13. External drain metal; 14. Interconnect. Detailed Implementation

[0045] The present invention will now be described in further detail with reference to the accompanying drawings and specific preferred embodiments.

[0046] In the description of this invention, it should be understood that the terms "left side," "right side," "upper part," "lower part," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. "First," "second," etc., do not indicate the importance of the components, and therefore should not be construed as a limitation of this invention. The specific dimensions used in this embodiment are only for illustrating the technical solution and do not limit the scope of protection of this invention.

[0047] like Figure 1 As shown, a copolymer organic semiconductor device based on isolation and interconnection includes a substrate 1, a photolithographic barrier layer, an insulating isolation layer, N organic field-effect transistors, an external source metal 12, an external drain metal 13, and N-1 interconnect lines 14; wherein N≥2, and in this embodiment, N=2 is used as an example for detailed description.

[0048] The substrate, photolithography barrier layer, and insulating isolation layer are stacked sequentially from bottom to top.

[0049] The substrate material mentioned above can be any one of glass substrate, flexible plastic, bulk silicon, silicon wafer, silicon carbide, gallium nitride, gallium arsenide, indium phosphide and germanium silicon, etc. In this embodiment, a glass substrate with a thickness of 0.5 mm is preferred.

[0050] The photolithography barrier layer includes an isolation layer 2 and an inorganic dielectric layer. The dielectric constant K value of the photolithography barrier layer is not less than 3, and is preferably SiO2, Si3N4, Al2O3, phosphosilicate glass, borosilicate glass, or semi-insulating polycrystalline silicon. In this embodiment, the isolation layer and the inorganic dielectric layer are made of the same material, and are preferably SiO2. SiO2 has a high dielectric constant, which improves the isolation performance of the device, requiring only a few micrometers of subsequent isolation trench width to achieve good isolation. On the other hand, SiO2 has high stress, and the adhesion between SiO2 and the glass substrate is better than that of organic semiconductor materials, which allows for the effective use of CMP process in subsequent interconnect technology to ensure the flatness of each layer of material in the device.

[0051] In addition, since the inorganic dielectric layer and the isolation layer use the same inorganic material, the inorganic dielectric layer and the isolation layer have better fusion and encapsulation while wrapping the subsequent semiconductor layer, and the thickness of the dielectric layer can be more precisely controlled, which greatly improves the gate control performance of the device and effectively reduces the leakage current of the device.

[0052] The isolation layer has N=2 longitudinally penetrating isolation trenches along its length. The depth of the isolation trenches is preferably 100nm, and the sidewall width of each isolation trench can reach 2μm. The isolation trenches, while effectively ensuring isolation, significantly reduce the spacing between organic field-effect transistors. This eliminates the need for interconnection between different devices by increasing spacing or using laser ablation of the substrate, greatly improving integration, repeatability, manufacturability, stability, and device performance.

[0053] The inorganic dielectric layer includes a lower dielectric layer 4 and an upper dielectric layer 6; the lower dielectric layer includes N lower dielectric layer segments located on top of N isolation trenches, preferably each with a thickness of 50 nm; the upper dielectric layer is laid on top of the isolation layer and the lower dielectric layer, preferably with a thickness of 250 nm.

[0054] The thickness of the above-mentioned insulating layer is preferably 1 μm, and its material is preferably borosilicate glass (BPSG).

[0055] Each organic field-effect transistor includes a semiconductor layer 3, a source, a drain, and a gate 10.

[0056] The semiconductor layer is disposed in the isolation trench at the bottom of the corresponding lower dielectric layer segment. Its material is an organic copolymer, preferably an organic compound such as pentacene, DPPT-TT, P3HT or naphthalimide-based N-type polymer, etc. In this embodiment, DPPT-TT dissolved in DCB is preferred.

[0057] The semiconductor layer material within each isolation trench can be the same or different, depending on actual needs. The preferred thickness of the semiconductor layer is 50 nm.

[0058] Both the source and drain include a source / drain metal body 5 and source / drain metal leads; the source / drain metal leads include a lower metal via 7, a transition source / drain metal 9 and an upper metal via 11, which are electrically connected from bottom to top.

[0059] The source / drain metal body is embedded in the corresponding lower dielectric layer segment, preferably with a thickness of 50 nm; the lower metal via is disposed in the upper dielectric layer and its bottom is electrically connected to the source / drain metal body, preferably with a thickness of 250 nm; the transition source / drain metal and the upper metal via are both disposed in the insulating isolation layer, preferably with thicknesses of 80 nm and 920 nm, respectively.

[0060] In N organic field-effect transistors, the outermost source is called the external source, and the remaining N-1 sources are called the internal sources; in N organic field-effect transistors, the outermost drain is called the external drain, and the remaining N-1 drains are called the internal drains.

[0061] An external source metal 12 is provided on the top of the external source electrode, and an external drain metal 13 is provided on the top of the external drain electrode.

[0062] The N-1 internal sources and N-1 internal drains are connected by N-1 interconnects 14.

[0063] The external source metal, external drain metal, and N-1 interconnects are all located on top of the insulating isolation layer, and the thickness of each layer is preferably 50nm.

[0064] Furthermore, the source, drain, gate, external source metal, external drain metal, and N-1 interconnects are preferably any one of Ni, Cu, Ti, Ag, Au, Al, Pt, Pd, Ir, metal alloys, polycrystalline silicon, and graphite electrodes. In this embodiment, Cu is preferred.

[0065] This invention enables the conversion of the N-type / P-type polarity of corresponding organic field-effect transistors by changing the gate bias voltage of N organic field-effect transistors.

[0066] like Figure 2 As shown, a method for fabricating a copolymer organic semiconductor device based on isolation and interconnection includes the following steps.

[0067] Step 1: Growth of the isolation layer

[0068] Step 1-1: Clean the substrate: Sonicate the 0.5 mm thick glass substrate in acetone, alcohol and deionized water for 5 min each, then place it on a heating table and dry it at 100 ℃ for 10 min.

[0069] Steps 1-2: Growth of the isolation layer: Place the cleaned substrate in a room temperature PECVD instrument, evacuate the vacuum to below 3 mTorr, then first introduce SiH4 gas for 84 s, followed by N2O gas for 144 s, and control the thickness of the isolation layer to 100 nm.

[0070] Steps 1-3: Etching isolation trenches. N longitudinally penetrating isolation trenches are etched along the length of the isolation layer. Specifically, the preferred method is to place a glass substrate coated with SiO2 onto a spin-coated photoresist, and after pre-baking, exposure in hard mode with a photomask, post-baking, exposure in Flood-E mode without a photomask, and development, place the substrate into an etching machine, introduce O2, and then control the etching thickness to 100nm.

[0071] Step 2: Deposit a semiconductor layer. A semiconductor layer made of an organic copolymer material is deposited on the top of each isolation tank. The preferred deposition method is as follows: 5 mg / ml DPPT-TT / DCB solution is dropped onto the surface, and the process is performed according to the parameters (speed, acceleration, time) set in the spin coater. Then, the surface is heated at 80°C for 5 minutes, followed by annealing at 150°C for 1 hour. The spin coater operation according to the set parameters is existing technology. Specifically, the spin coater is operated at an acceleration of 200-800 rpm and 150-250 rpm / s for 8-13 seconds; at 1000-2000 rpm and 200-800 rpm / s for 40-100 seconds; and then decelerated to 0 rpm at an acceleration of -200 to -800 rpm for 2-8 seconds to spin coat the substrate surface. In this embodiment, the semiconductor layer uses the same material. However, depending on the specific needs, the materials used for each semiconductor layer in each isolation tank can be different.

[0072] Step 3: Deposit the lower dielectric layer segment: In the isolation trench at the top of each semiconductor layer, a lower dielectric layer segment is deposited, and the top of the lower dielectric layer segment is flush with the top of the isolation layer; all lower dielectric layer segments are collectively referred to as the lower dielectric layer.

[0073] The preferred method for depositing the lower dielectric layer segment is as follows: the glass substrate is placed in a room temperature PECVD instrument, the vacuum degree is evacuated to below 3 mTorr, and then SiH4 gas is first introduced for 84 s, followed by N2O gas for 144 s, and the thickness of the lower dielectric layer segment 4 is controlled to be 50 nm.

[0074] Step 4: Evaporation of source and outlet metal bodies

[0075] Step 4-1: Etch two vias in each lower dielectric layer segment. The preferred etching method is as follows: Place the glass substrate coated with dielectric layer 4 in a grinding machine, grind and clean it, then spin-coat photoresist, and after pre-baking, exposure in hard mode with a photomask, post-baking, exposure in flood-E mode without a photomask, and development, place the substrate in an etching machine, introduce O2, and then control the etching thickness to 50nm.

[0076] Step 4-2: Source / drain metal bodies are deposited within each via at a deposition rate not exceeding 0.2 Å / s, more preferably not exceeding 0.1 Å / s. In this embodiment, the specific deposition method is as follows: the substrate is placed in a deposition apparatus to deposit 50 nm of Cu metal at a deposition rate of 0.1 Å / s. The deposition rate determines the density of the deposited metal. Using a lower deposition rate for the source / drain metal can improve the surface smoothness of the metal, reduce the threshold voltage of the device, and improve performance. Alternatively, the source / drain metal bodies can be deposited using magnetron sputtering, which is also within the scope of this invention.

[0077] Step 5: Grow the upper medium layer

[0078] Step 5-1: Generate an upper dielectric layer of not less than 200 nm on top of the isolation layer and the lower dielectric layer. The preferred growth method is as follows: Place the substrate with the source and drain electrodes deposited at room temperature in a PECVD instrument, evacuate the vacuum to below 3 mTorr, then first introduce SiH4 gas for 7 min, followed by N2O gas for 8 min, and control the thickness of the dielectric layer 6 to be 250 nm.

[0079] In this invention, the inorganic dielectric layer is grown in two stages, which simplifies the fabrication steps of the source and drain electrodes, improves the quality of the electrodes, reduces etching errors, and minimizes defects.

[0080] Step 5-2, Polishing: The top of the upper dielectric layer is polished flat using CMP technology. In this invention, because the photolithography barrier layer uses inorganic materials such as SiO2 with high stress, the flatness of each layer of the device can be guaranteed.

[0081] Step 6: Evaporate metal through-holes

[0082] Step 6-1: Etch a via two in the upper dielectric layer directly above each source / drain metal body. The preferred etching method is as follows: Place the glass substrate coated with the inorganic dielectric layer in a grinding machine, grind and clean it, then spin-coat photoresist, and after pre-baking, exposure in hard mode with a photomask, post-baking, exposure in Flood-E mode without a photomask, and development, place the substrate in an etching machine, introduce O2, and then control the etching thickness to 250nm.

[0083] Step 6-2: A metal identical to the source / drain metal body is deposited within each via to form a lower metal via. The preferred method for depositing the lower metal via is to place the etched substrate in an electron beam evaporation apparatus, controlling the Cu metal evaporation rate to not exceed 0.2 Å / s, more preferably not exceeding 0.1 Å / s (in this embodiment, it is 0.1 Å / s), with a deposited film thickness of 250 nm. Using a lower evaporation rate for the lower metal via can reduce via defects and improve connectivity.

[0084] The cross-sectional width of the aforementioned through-hole two does not exceed the cross-sectional width of the source / drain metal body.

[0085] Step 7: Evaporate the transition source / drain metal and gate.

[0086] Step 7-1: Evaporate transition source / drain metal: Evaporate a layer of metal identical to the source / drain metal body on the top of each lower metal via to form transition source / drain metal; at the same time, evaporate a gate on the top of the upper dielectric layer between two adjacent transition source / drain metals.

[0087] The specific evaporation method for the aforementioned transition source drain metal and gate is as follows: After the glass substrate with the through holes filled is placed in a grinding machine, after grinding and cleaning, photoresist is spin-coated, and after pre-baking, hard mode exposure with a photomask, post-baking, flood-E mode exposure without a photomask, and development, the substrate is placed in an evaporation apparatus to evaporate 80nm of Cu metal.

[0088] The evaporation rates of the transition source / drain metal and the gate are all no more than 1 Å / s, preferably no more than 0.5 Å / s. In this embodiment, the transition source / drain metal and the gate are both deposited in three layers: first, 5 nm of Cu metal is deposited at a rate of 0.1 Å / s; then, 70 nm of Cu metal is deposited at a rate of 0.5 Å / s; and finally, 5 nm of Cu metal is deposited at a rate of 0.1 Å / s.

[0089] Step 7-2, Deposit gate: Deposit a gate on top of the upper dielectric layer between two adjacent transition source / drain metals. For the specific method of gate deposition, refer to the transition source / drain metal in Step 7-1.

[0090] Step 8: Generate an insulating layer

[0091] A insulating isolation layer of at least 900 nm is preferably deposited on top of the upper dielectric layer using a CVD method. This insulating isolation layer encapsulates the transition source / drain metal and the gate, forming an isolation between them. The aforementioned insulating isolation layer is preferably borosilicate glass (BPSG) of approximately 1 μm, doped with a small amount of boron and phosphorus in silicon dioxide.

[0092] Once the insulating layer has been deposited, the top of it is preferably polished smooth using the CMP process.

[0093] Step 9: Evaporate metal through-holes

[0094] Step 9-1: Etch a via three in the insulating isolation layer directly above each transition source drain metal. The preferred etching method is as follows: Place the glass substrate coated with the dielectric layer in a grinding machine, grind and clean it, then spin-coat photoresist, and after pre-baking, exposure in hard mode with a photomask, post-baking, exposure in Flood-E mode without a photomask, and development, place the substrate in an etching machine, introduce O2, and then control the etching thickness to 1μm.

[0095] Step 9-2: Deposit the same metal as the source / drain metal body into each via three to form an upper metal via. The specific deposition method is as follows: place the substrate with the etched via in a magnetron sputtering instrument and control the evaporation rate of the metal Cu to not exceed 0.2 Å / s, more preferably not exceed 0.1 Å / s, and in this embodiment it is 0.1 Å / s. The thickness of the deposited film is 1 μm.

[0096] The cross-sectional width of the aforementioned via three does not exceed the cross-sectional width of the source / drain metal body, but is preferably larger than the cross-sectional width of via two. After etching, via two and via three, after metallization, serve as wire connections. It is not necessary to etch large holes, even those the same size as the source / drain electrodes. If the holes are too wide, the gate electrode will not be able to completely cover the source electrode portion, causing device failure. Furthermore, thicker source / drain electrodes will result in a smaller gap between the gate electrode and the source / drain electrodes, significantly increasing device leakage and also leading to device failure.

[0097] Step 10: Evaporate external source metal, external drain metal, and N-1 interconnects: The outermost source of the N organic field-effect transistors is called the external source, and the remaining N-1 sources are called internal sources; the outermost drain of the N organic field-effect transistors is called the external drain, and the remaining N-1 drains are called internal drains; Evaporate external source metal on top of the external source and external drain metal on top of the external drain; Simultaneously, Evaporate N-1 interconnects on top of the insulating isolation layer to connect the N-1 internal sources and N-1 internal drains respectively.

[0098] The deposition rates of the external source metal, external drain metal, and N-1 interconnects all do not exceed 1 Å / s, preferably not exceeding 0.5 Å / s. In this embodiment, the external source metal, external drain metal, and N-1 interconnects are all deposited in three layers: first, 5 nm of Cu metal is deposited at a rate of 0.1 Å / s; then, 40 nm of Cu metal is deposited at a rate of 0.5 Å / s; and finally, 5 nm of Cu metal is deposited at a rate of 0.1 Å / s.

[0099] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A copolymer organic semiconductor device based on isolation and interconnection, characterized in that: It includes a substrate, a photolithographic barrier layer, an insulating isolation layer, N organic field-effect transistors, an external source metal, an external drain metal, and N-1 interconnects; where N ≥ 2; The substrate, photolithography barrier layer, and insulating isolation layer are stacked sequentially from bottom to top; The photolithography blocking layer includes an isolation layer and an inorganic dielectric layer; wherein, the isolation layer has N longitudinally penetrating isolation trenches along its length; the inorganic dielectric layer includes a lower dielectric layer and an upper dielectric layer; the lower dielectric layer includes N lower dielectric layer segments located on top of the N isolation trenches; the upper dielectric layer is laid on top of the isolation layer and the lower dielectric layer; Each organic field-effect transistor includes a semiconductor layer, a source, a drain, and a gate; The semiconductor layer is disposed in the isolation trench at the bottom of the corresponding lower dielectric layer segment, and its material is an organic copolymer; Both the source and drain include a source / drain metal body and source / drain metal leads; the source / drain metal leads include a lower metal via, a transitional source / drain metal, and an upper metal via, which are electrically connected sequentially from bottom to top. The source / drain metal body is embedded in the corresponding lower dielectric layer segment, and the lower metal via is set in the upper dielectric layer, with its bottom electrically connected to the source / drain metal body; the transition source / drain metal and the upper metal via are both set in the insulating isolation layer. In N organic field-effect transistors, the outermost source is called the external source, and the remaining N-1 sources are called the internal sources; in N organic field-effect transistors, the outermost drain is called the external drain, and the remaining N-1 drains are called the internal drains. The external source electrode is provided with the external source metal at its top, and the external drain electrode is provided with the external drain metal at its top; N-1 internal sources and N-1 internal drains are connected to each other through N-1 interconnects; The external source metal, external drain metal, and N-1 interconnects are all located on top of the insulating isolation layer.

2. The copolymer organic semiconductor device based on isolation and interconnection according to claim 1, characterized in that: By changing the gate bias voltage of N organic field-effect transistors, the N-type / P-type polarity conversion of the corresponding organic field-effect transistors can be achieved.

3. The copolymer organic semiconductor device based on isolation and interconnection according to claim 1, characterized in that: The dielectric constant K of the photolithographic barrier layer is no less than 3, and the sidewall width of each isolation trench can reach 2μm.

4. The copolymer organic semiconductor device based on isolation and interconnection according to claim 2, characterized in that: The photolithography barrier layer is SiO2, Si3N4, Al2O3, phosphosilicate glass, borosilicate glass, or semi-insulating polycrystalline silicon.

5. The copolymer organic semiconductor device based on isolation and interconnection according to claim 1, characterized in that: The thicknesses of the substrate, isolation layer, semiconductor layer, lower dielectric layer, upper dielectric layer, and insulating isolation layer are 0.5 mm, 100 nm, 50 nm, 50 nm, 250 nm, and 1 μm, respectively; the thicknesses of the source / drain metal body, lower metal via, transition source / drain metal, and upper metal via are 50 nm, 250 nm, 80 nm, and 920 nm, respectively; and the thicknesses of the external source metal, external drain metal, and N-1 interconnects are all 50 nm.

6. The copolymer organic semiconductor device based on isolation and interconnection according to claim 1, characterized in that: The semiconductor layer is made of organic compounds such as pentacene, DPPT-TT, P3HT, or naphthalimide-based N-type polymers.

7. A method for fabricating a copolymer organic semiconductor device based on isolation and interconnection, characterized in that: Includes the following steps: Step 1: Growing an isolation layer: Grow an isolation layer on a clean substrate and etch N longitudinally penetrating isolation trenches along the length of the isolation layer; Step 2, depositing a semiconductor layer: deposit a semiconductor layer made of organic copolymer material on the top of each isolation tank; Step 3: Deposit lower dielectric layer segments: In the isolation trench at the top of each semiconductor layer, a lower dielectric layer segment is deposited, and the top of the lower dielectric layer segment is flush with the top of the isolation layer; all lower dielectric layer segments are collectively referred to as the lower dielectric layer; Step 4: Evaporation of source / drain metal body: Two vias are etched in each lower dielectric layer segment, and source / drain metal body is vapor-deposited in each via. Step 5: Growth of the upper dielectric layer: An upper dielectric layer of not less than 200 nm is generated on top of the isolation layer and the lower dielectric layer. The top of the upper dielectric layer can be polished smooth using CMP process. The isolation layer, the lower dielectric layer, and the upper dielectric layer together constitute the photolithography barrier layer, and all of them are made of the same inorganic material; Step 6: Deposit lower metal vias: Etch a via 2 in the upper dielectric layer directly above each source / drain metal body, and deposit the same metal as the source / drain metal body into each via 2 to form a lower metal via. Step 7: Evaporate transition source / drain metal and gate: Evaporate a layer of metal identical to the source / drain metal body on top of each lower metal via to form transition source / drain metal; at the same time, evaporate a gate on top of the upper dielectric layer between two adjacent transition source / drain metals. Step 8: Generate an insulating isolation layer: Deposit an insulating isolation layer of not less than 900nm on top of the upper dielectric layer. The insulating isolation layer covers the transition source drain metal and the gate, forming an isolation between the transition source drain metal and the gate. The top of the insulating isolation layer can be polished smooth using CMP process. Step 9: Deposit upper metal vias: Etch a via three in the insulating layer directly above each transition source / drain metal, and deposit the same metal as the source / drain metal body into each via three to form upper metal vias; Step 10: Evaporate external source metal, external drain metal, and N-1 interconnects: The outermost source of the N organic field-effect transistors is called the external source, and the remaining N-1 sources are called internal sources; the outermost drain of the N organic field-effect transistors is called the external drain, and the remaining N-1 drains are called internal drains; Evaporate external source metal on top of the external source and external drain metal on top of the external drain; Simultaneously, Evaporate N-1 interconnects on top of the insulating isolation layer to connect the N-1 internal sources and N-1 internal drains respectively.

8. The method for fabricating a copolymer organic semiconductor device based on isolation and interconnection according to claim 7, characterized in that: In step 4, the evaporation rate of the source / drain metal body, in step 6, the evaporation rate of the lower metal via, and in step 9, the evaporation rate of the upper metal via all do not exceed 0.2 Å / s; in step 7, the evaporation rates of the transition source / drain metal, the gate, and in step 10, the external source metal, the external drain metal, and the N-1 interconnects all do not exceed 1 Å / s.

9. The method for fabricating a copolymer organic semiconductor device based on isolation and interconnection according to claim 8, characterized in that: In step 4, the evaporation rate of the source / drain metal body, in step 6, the evaporation rate of the lower metal via, and in step 9, the evaporation rate of the upper metal via all do not exceed 0.1 Å / s; in step 7, the transition source / drain metal, the gate, and in step 10, the external source metal, the external drain metal, and the N-1 interconnects are all evaporated using three layers: upper, middle, and lower. The evaporation rates of the lower and upper layers do not exceed 0.1 Å / s, and the evaporation rate of the middle layer is 0.5 Å / s.

10. The method for fabricating a copolymer organic semiconductor device based on isolation and interconnection according to claim 7, characterized in that: The cross-sectional widths of both through-hole 2 and through-hole 3 do not exceed the cross-sectional width of the source / drain metal body.

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