Display panel and display device

Abstract

The present disclosure relates to the field of display technology, and provides a display panel and a display device. The display panel includes a second initial signal line and a third initial signal line, wherein the second initial signal line extends along the first direction in the orthographic projection of the substrate, and the third initial signal line extends along the second direction in the orthographic projection of the substrate, and the second initial signal line can provide an initialization signal for the first transistor or the seventh transistor. At least part of the segments of the orthographic projection of the third initial signal line in the extension direction of the orthographic projection of the substrate are located on the same side of the orthographic projection of the substrate in the first direction of the second conductive portion. The second initial signal line forms a grid structure, thereby improving the display uniformity of the display panel at low grayscale, reducing the current difference between the middle part and the two side parts of the display panel, and preventing the problem of light and dark alternation at low grayscale caused by different cross-voltages of OLED devices at different positions of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, and flexibility. At present, the application of OLED display screens is becoming more and more extensive. In the related technology, OLED display screens cannot meet people's demand for high-quality display quality. It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the invention

[0003] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a display device.

[0004] According to one aspect of the present disclosure, a display panel is provided, the display panel comprising a plurality of pixel driving circuits arrayed along a first direction and a second direction, the pixel driving circuit being used to drive a light-emitting device to emit light, the first direction and the second direction intersecting, the pixel driving circuit comprising a driving transistor and a second transistor, the first electrode of the second transistor being connected to a gate electrode of the driving transistor, and the second electrode being connected to the first electrode of the driving transistor, the display panel further comprising: a substrate; a first conductive layer located on one side of the substrate, the first conductive layer comprising: a first conductive portion, the first conductive portion being used to form a gate electrode of the driving transistor; a second conductive layer located on a side of the first conductive layer away from the substrate, the second conductive layer comprising: a plurality of first initial signal lines, the orthographic projection of which on the substrate extends along the first direction and is spaced apart along the second direction, the first initial signal line being used to provide a first initialization signal to the gate electrode of the driving transistor; a plurality of second initial signal lines, the plurality of first initial signal lines being used to provide a first initialization signal to the gate electrode of the driving transistor; Two initial signal lines extend along the first direction on the orthographic projection of the substrate and are spaced apart along the second direction, the second initial signal line being used to provide a second initialization signal for the first electrode of the light-emitting device; a third conductive layer being located on the side of the second conductive layer away from the substrate, the third conductive layer comprising: a second conductive portion extending along the second direction on the orthographic projection of the substrate, the second conductive portion being used to connect the first conductive portion to the first electrode of the second transistor; a third initial signal line extending along the second direction on the orthographic projection of the substrate, the third initial signal line and the second initial signal line and / or the first initial signal line being located in a different conductive layer, and the third initial signal line connecting a plurality of the second initial signal lines or connecting a plurality of the first initial signal lines; wherein the distance between the orthographic projection of at least a portion of the third initial signal line on the substrate and the orthographic projection of the second conductive portion on the substrate in the first direction is greater than zero, and the first initialization signal is different from the second initialization signal.

[0005] In an exemplary embodiment of the present disclosure, the third initial signal line is located in the third conductive layer, and the third initial signal line is connected to the second initial signal line through a via.

[0006] In an exemplary embodiment of the present disclosure, the first direction is a row direction, the second direction is a column direction, and the pixel driving circuit further includes: a first transistor and a seventh transistor, wherein the first electrode of the first transistor is connected to the first initial signal line, the second electrode is connected to the gate of the driving transistor, and the gate is connected to the first reset signal line; the first electrode of the seventh transistor is connected to the second initial signal line, the second electrode is connected to the first electrode of the light-emitting device, and the gate is connected to the second reset signal line; wherein the positive projection of the first initial signal line in the pixel driving circuit of this row on the substrate is located on a side away from the positive projection of the second initial signal line in the pixel driving circuit of the adjacent previous row on the substrate.

[0007] In an exemplary embodiment of the present disclosure, the third conductive layer also includes: a third connecting portion, connected to the second electrode of the seventh transistor through a first via; a fifth conductive portion, connected to the first initial signal line through a tenth via, and the fifth conductive portion is also connected to the first electrode of the first transistor through a second via, and the orthographic projection of the fifth conductive portion in the pixel driving circuit of this row on the substrate is located on a side of the orthographic projection of the second initial signal line in the pixel driving circuit of an adjacent previous row on the substrate, away from the orthographic projection of the first via in the pixel driving circuit of an adjacent previous row on the substrate.

[0008] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, a fifth transistor and a sixth transistor, the first electrode of the first transistor is connected to the first initial signal line, the second electrode is connected to the gate of the driving transistor, the first electrode of the fifth transistor is connected to the second electrode of the driving transistor, the first electrode of the sixth transistor is connected to the first electrode of the driving transistor, and the second electrode is connected to the anode of the light-emitting device; the display panel further includes: an active layer, located between the base substrate and the first conductive layer, the active layer including: a third active portion, used to form a channel region of the driving transistor; a fifth active portion, used to form The channel region of the fifth transistor; the sixth active portion, used to form the channel region of the sixth transistor; the fourteenth active portion, connected between the sixth active portion and the third active portion; the eighth active portion, connected to the side of the sixth active portion away from the fourteenth active portion, the eighth active portion includes a seventh sub-active portion and an eighth sub-active portion, the seventh sub-active portion is connected to the sixth active portion and extends in the column direction of the orthographic projection of the substrate, the eighth sub-active portion is connected to the seventh sub-active portion and extends in the row direction of the orthographic projection of the substrate, and the end of the eighth sub-active portion away from the seventh sub-active portion is connected to the first via hole The third connecting portion; the first active portion, comprising a first sub-active portion, a second sub-active portion, a third sub-active portion and a ninth sub-active portion, the first sub-active portion is used to form a first channel region of the first transistor, the third sub-active portion is used to form a second channel region of the first transistor, the third sub-active portion is connected between the first sub-active portion and the third sub-active portion, the ninth sub-active portion is connected to a side of the first sub-active portion away from the third sub-active portion, and the ninth sub-active portion is connected to the fifth conductive portion through a second via hole; wherein the fifth active portion has a first distance from the sixth active portion, and the eighth sub-active portion has a There is a first extension length, and the ratio of the first extension length to the first distance is greater than or equal to 1 / 4 and less than or equal to 1 / 2; in the same column of pixel driving circuits, the orthographic projection of the fifth conductive part on the substrate and the orthographic projection of the third connecting part on the substrate are both located on the same side of the orthographic projection of the third initial signal line on the substrate, and in two pixel driving circuits located in adjacent rows of the same column, a line segment connecting the tenth via hole and the first via hole has a first angle between the orthographic projection of the substrate and the orthographic projection of the fifth conductive part on the substrate, and the first angle is greater than or equal to 175° and less than or equal to 180°.

[0009] In an exemplary embodiment of the present disclosure, the active layer also includes: a tenth active portion, connected to a side of the second sub-active portion away from the third sub-active portion, the tenth active portion being connected to the second conductive portion through a third via; the fifth conductive portion extends along the second direction on the orthographic projection of the substrate, and in the same column of pixel driving circuits, the orthographic projection of the fifth conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate are both located on the same side of the orthographic projection of the third initial signal line on the substrate; in the same pixel driving circuit, a line segment connecting the third via and the second via has a second angle between the orthographic projection of the substrate and the orthographic projection of the second conductive portion on the substrate, and the second angle is greater than or equal to 175° and less than or equal to 180°.

[0010] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a sixth transistor, a first electrode of the sixth transistor is connected to the first electrode of the driving transistor, a second electrode is connected to the light-emitting device, and a gate is connected to an enable signal line; the first conductive layer further includes: the enable signal line, the orthographic projection of which on the substrate extends along the first direction, and a partial structure of the enable signal line is used to form the gate of the sixth transistor; the first reset signal line, the orthographic projection of which on the substrate extends along the first direction and is located on a side where the orthographic projection of the first conductive portion on the substrate is away from the orthographic projection of the enable signal line on the substrate, and a partial structure of the first reset signal line is used to form the gate of the first transistor; The second reset signal line, whose orthographic projection on the substrate extends along the first direction and is located on a side where the orthographic projection of the enable signal line on the substrate is away from the orthographic projection of the first conductive portion on the substrate, and a partial structure of the second reset signal line is used to form the gate of the seventh transistor; wherein the second reset signal line in the pixel driving circuit of this row is multiplexed as the first reset signal line in the pixel driving circuit of the next row; the orthographic projection of the second initial signal line in the pixel driving circuit of this row on the substrate and the orthographic projection of the first initial signal line in the pixel driving circuit of the next row on the substrate are located between the orthographic projection of the enable signal line in the pixel driving circuit of this row on the substrate and the orthographic projection of the second reset signal line on the substrate.

[0011] In an exemplary embodiment of the present disclosure, the third conductive layer also includes: a first power line, which extends along the second direction in the orthographic projection of the base substrate; wherein the third initial signal line has a second distance from the first power line in the first direction, and the ratio of the second distance to the first distance is greater than or equal to 0.8 and less than or equal to 1.2.

[0012] In an exemplary embodiment of the present disclosure, the third conductive layer also includes: a first power line, which extends along the second direction in the orthographic projection of the base substrate; wherein the third initial signal line has a third distance from the second conductive portion in the first direction, and the ratio of the third distance to the first distance is greater than or equal to 1 / 3 and less than or equal to 1 / 2.

[0013] In an exemplary embodiment of the present disclosure, the third initial signal line includes a first extension portion, a second extension portion and a third extension portion, the second extension portion is connected between the first extension portion and the third extension portion, and there is a third angle between the second extension portion and the first extension portion, and between the second extension portion and the third extension portion, and the third angle is greater than or equal to 90° and less than or equal to 180°.

[0014] In an exemplary embodiment of the present disclosure, the gate of the second transistor is connected to the first scanning signal line, the pixel driving circuit further includes a sixth transistor, the first electrode of the sixth transistor is connected to the first electrode of the driving transistor, and the gate is connected to the enable signal line; the display panel further includes: an active layer, located between the base substrate and the first conductive layer, the active layer including: a second active portion, including a fourth sub-active portion, a fifth sub-active portion and a sixth sub-active portion connected in sequence, the fourth sub-active portion is used to form a first channel region of the second transistor, and the sixth sub-active portion is used to form a second channel region of the second transistor; the sixth active portion is used to form a channel region of the sixth transistor; a fourteenth active portion, the positive projection of which on the base substrate extends along the column direction and is connected between the fourth sub-active portion and the sixth active portion; the first conductive layer further includes: the first scanning signal line, located on the base substrate The orthographic projection extends along the first direction, and a partial structure of the first scanning signal line is used to form the gate of the second transistor; the orthographic projection of the enable signal line on the substrate extends along the first direction and covers the orthographic projection of the sixth active portion on the substrate, and a partial structure of the enable signal line is used to form the gate of the sixth transistor; the orthographic projections of the first extension portion and the third extension portion on the substrate are located on the side of the orthographic projection of the fourteenth active portion on the substrate toward the orthographic projection of the first conductive portion on the substrate, and the distance between the orthographic projection of the first extension portion on the substrate and the orthographic projection of the first conductive portion on the substrate in the first direction is greater than the distance between the orthographic projection of the second extension portion or the third extension portion on the substrate and the orthographic projection of the first conductive portion on the substrate in the first direction.

[0015] In an exemplary embodiment of the present disclosure, the first direction is a row direction, the second direction is a column direction, the display panel includes a first pixel driving circuit column and a second pixel driving circuit column spaced in sequence in the row direction, and the third initial signal line is located in the first pixel driving circuit column.

[0016] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a first transistor, a first electrode of the first transistor is connected to the first initial signal line, a second electrode is connected to the gate of the driving transistor, and the gate is connected to the first reset signal line; the display panel also includes: an active layer, located between the base substrate and the first conductive layer, the active layer includes: a first active portion, including a first sub-active portion, a second sub-active portion and a third sub-active portion connected in sequence, the first sub-active portion is used to form a first channel region of the first transistor, and the third sub-active portion is used to form a second channel region of the first transistor; the display panel also includes: a first conductive layer, located between the active layer and the second conductive layer The first conductive layer includes: the first reset signal line, the orthographic projection of the first reset signal line on the substrate extends along the row direction, the orthographic projection of the first reset signal line on the substrate is located between the orthographic projection of the first conductive part on the substrate and the orthographic projection of the first initial signal line on the substrate, the orthographic projection of the first reset signal line on the substrate covers the orthographic projection of the first sub-active part on the substrate and the orthographic projection of the third sub-active part on the substrate, and a partial structure of the first reset signal line is used to form the gate of the first transistor; wherein the orthographic projection of the first initial signal line on the substrate covers the orthographic projection of the second sub-active part on the substrate.

[0017] In an exemplary embodiment of the present disclosure, a width of the first initial signal line in the second direction is greater than a width of the first initial signal line in the second direction.

[0018] In an exemplary embodiment of the present disclosure, the display panel also includes: a fourth conductive layer, located on a side of the third conductive layer away from the base substrate, the fourth conductive layer including: a second power line, the orthographic projection of the base substrate extending along the second direction; an anode flat portion, connected to the second power line; an anode connecting portion, separated from the anode flat portion and connected to the third connecting portion through a via; a pixel defining layer, located on a side of the fourth conductive layer away from the base substrate, including a plurality of pixel openings, the orthographic projection of the pixel opening on the base substrate being located on the orthographic projection of the anode flat portion on the base substrate.

[0019] In an exemplary embodiment of the present disclosure, the first direction is a row direction, the second direction is a column direction, and the display panel includes a first pixel driving circuit column and a second pixel driving circuit column that are sequentially spaced apart in the row direction; an extension length of an orthographic projection of the third connection portion in the first pixel driving circuit column on the substrate is different from an extension length of an orthographic projection of the third connection portion in the second pixel driving circuit column on the substrate.

[0020] In an exemplary embodiment of the present disclosure, the extension length of the orthographic projection of the third connection portion in the first pixel driving circuit column on the substrate is shorter than the extension length of the orthographic projection of the third connection portion in the second pixel driving circuit column on the substrate; the third connection portion includes a first via contact portion and a second via contact portion, the first via contact portion is connected to the second electrode of the seventh transistor through the first via, and the second via contact portion is connected to the anode connection portion through the via; in the second pixel driving circuit column, the orthographic projection of the second via contact portion on the substrate is located on the side of the orthographic projection of the first via contact portion on the substrate facing the orthographic projection of the second conductive portion on the substrate, and the distance between the orthographic projection of the second via contact portion on the substrate and the orthographic projection of the second conductive portion on the substrate in the first direction is greater than the distance between the orthographic projection of the first via contact portion on the substrate and the orthographic projection of the second conductive portion on the substrate in the first direction.

[0021] In an exemplary embodiment of the present disclosure, the orthographic projections of the first via contact portion and the second via contact portion located in the first pixel driving column on the substrate overlap with the orthographic projections of the second initial signal line on the substrate; the orthographic projections of the first via contact portion and the second via contact portion located in the second pixel driving circuit column on the substrate do not overlap with the orthographic projections of the second initial signal line on the substrate, and the orthographic projection of the second via contact portion on the substrate overlaps with the orthographic projection of the third conductive portion in the same pixel driving circuit on the substrate.

[0022] According to another aspect of the present disclosure, a display device is also provided, comprising the display panel described in any embodiment of the present disclosure.

[0023] The display panel provided by the present disclosure provides a reset signal for the gate of the driving transistor through the first initial signal line, and provides a reset signal for the first electrode of the light-emitting device through the second initial signal line. The reset signals provided by the first initial signal line and the second initial signal line are different, so that the gate of the driving transistor and the first electrode of the light-emitting element can be better reset, so that in the black state, the OLED display substrate can be guaranteed to have a lower brightness, and the display uniformity is improved. The third initial signal is connected to the first initial signal line or the second initial signal line, so that the first initial signal line or the second initial signal line forms a grid structure, so that the display uniformity of the display panel at low gray scale can be improved, and the current difference between the middle part and the two side parts of the display panel can be reduced, and the light and dark alternation problem at low gray scale can be prevented from being caused by different cross-voltage of OLED devices at different positions of the display panel. In addition, the design space of the third initial signal line is larger, so that the third initial signal line can avoid the first node where the driving transistor is connected to the first transistor, reduce interference with the first node, and further improve display uniformity.

[0024] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0026] Figure 1 A schematic diagram of a circuit structure of a pixel driving circuit in a display panel according to an embodiment of the present disclosure;

[0027] Figure 2 for Figure 1 A timing diagram of each node in a driving method of a pixel driving circuit;

[0028] Figure 3 A structural diagram of a display panel according to an embodiment of the present disclosure;

[0029] Figure 4 for Figure 3 A structural layout of the first conductive layer;

[0030] Figure 5 for Figure 3 The structural layout of the second conductive layer;

[0031] Figure 6 for Figure 3 The structural layout of the third conductive layer;

[0032] Figure 7 for Figure 3 The structural layout of the fourth conductive layer;

[0033] Figure 8 for Figure 3 The structural layout of the active layer in the

[0034] Fig. 9 for Figure 3 The structural layout of the middle pixel definition layer;

[0035] Fig.10 for Figure 3 A stacked structure layout of an active layer and a first conductive layer;

[0036] Fig.11 for Figure 3 A stacked structure layout of an active layer and a second conductive layer;

[0037] Fig.12 for Figure 3 A stacked structure layout of an active layer and a third conductive layer;

[0038] Fig.13 for Figure 3 A stacked structure layout of a third conductive layer and a fourth conductive layer;

[0039] Fig.14 for Figure 3 A stacked structure layout of an active layer, a first conductive layer and a pixel defining layer;

[0040] Fig.15 for Figure 6 A partial enlarged view of the third initial signal line;

[0041] Fig.16 for Figure 3 A stacked structure layout of an active layer, a second conductive layer and a third conductive layer of a sub-pixel;

[0042] Fig.17 for Figure 3 Cross-sectional view along AA direction. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0044] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0045] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0046] Figure 1 The circuit structure diagram of a pixel driving circuit in a display panel according to an embodiment of the present disclosure is shown in FIG. The pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first electrode of the first transistor T1 is connected to the first initial signal terminal INIT1, the second electrode is connected to the first node N1, and the gate is connected to the reset signal terminal Re1; the first electrode of the second transistor T2 is connected to the gate of the driving transistor T3, the second electrode is connected to the third node N3, and the gate is connected to the first scanning signal terminal S1; the gate of the driving transistor T3 is connected to the first node N1; the first electrode of the fourth transistor T4 is connected to the data signal terminal DATA, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first scanning signal terminal S1; the first electrode of the fifth transistor T5 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the first power supply terminal VDD, and the gate is connected to the enable signal terminal EM; the first electrode of the sixth transistor T6 is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal INIT2, the second electrode is connected to the second electrode of the sixth transistor T6, and the gate is connected to the reset signal terminal Re2. The capacitor C is connected between the gate of the driving transistor T3 and the first power supply terminal VDD. The pixel driving circuit can be connected to a light emitting unit OLED to drive the light emitting unit OLED to emit light, and the light emitting unit OLED can be connected between the second electrode of the sixth transistor T6 and the second power supply terminal VSS. Among them, the transistors T1-T7 can all be P-type transistors.

[0047] It should be noted that the transistors used in each embodiment of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode.

[0048] Figure 2 for Figure 1 A timing diagram of each node in a driving method of a pixel driving circuit. Among them, S1 represents the timing of the first scanning signal terminal S1, Re1 represents the timing of the reset signal terminal Re1, Re2 represents the timing of the reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal DATA. The driving method of the pixel driving circuit may include a reset stage t1, a compensation stage t2, and a light-emitting stage t3. In the reset stage t1: the reset signal terminal Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N. In the compensation stage t2: the reset signal terminal Re2 and the first scanning signal terminal S1 output low-level signals, the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, and at the same time, the data signal terminal DATA outputs a driving signal to write a voltage Vdata+Vth to the node N, wherein Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3, and the second initial signal terminal INIT2 inputs an initial signal to the second electrode of the sixth transistor T6. Light-emitting stage t3: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata+Vth stored in the capacitor C. According to the driving transistor output current formula I=(μWCox / 2L)(Vgs-Vth) 2 , where μ is carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The output current of the driving transistor in the pixel driving circuit of the present disclosure is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0049] The display panel provided by the exemplary embodiment may include a plurality of pixel driving circuits distributed in an array along a first direction and a second direction, the pixel driving circuit is used to drive the light emitting device to emit light, the first direction and the second direction intersect, the pixel driving circuit includes a driving transistor and a second transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode is connected to the first electrode of the driving transistor. The pixel driving circuit may be as follows Figure 1As shown, of course, in other exemplary embodiments, the pixel driving circuit in the display panel may also be other structures, for example, 8T1C, 9T1C, etc. Figure 3 is a structural diagram of a display panel according to an embodiment of the present disclosure, Figure 4 for Figure 3 The structural layout of the first conductive layer in Figure 5 for Figure 3 The structural layout of the second conductive layer in Figure 6 for Figure 3 The structural layout of the third conductive layer in Figure 3-6 As shown, the display panel may also include: a base substrate, a first conductive layer 2, a second conductive layer 3, and a third conductive layer 4; the first conductive layer 2 is located on one side of the base substrate, and the first conductive layer 2 may include a first conductive portion 21, and the first conductive portion 21 is used to form a gate of the driving transistor; the second conductive layer 3 is located on the side of the first conductive layer 2 away from the base substrate, and the second conductive layer 3 may include a plurality of first initial signal lines Vinit1 and a plurality of second initial signal lines Vinit2, the orthographic projections of the plurality of first initial signal lines on the base substrate extend along the first direction and are spaced apart along the second direction, and the first initial signal lines are used to provide a first initialization signal for the gate of the driving transistor; the orthographic projections of the plurality of second initial signal lines Vinit2 on the base substrate extend along the first direction X and are spaced apart along the second direction Y, and the second initial signal lines Vinit2 are used to provide a second initialization signal for the first pole of the light-emitting device; the third conductive layer 4 is located The second conductive layer 3 is on the side away from the substrate, and the third conductive layer 4 may include a second conductive part 42 and a third initial signal line Vinit3. The orthographic projection of the second conductive part 42 on the substrate extends along the second direction Y, and the second conductive part 42 is used to connect the first conductive part 21 to the first electrode of the second transistor; the orthographic projection of the third initial signal line Vinit3 on the substrate extends along the second direction Y, the third initial signal line Vinit3 and the second initial signal line Vinit2 and / or the first initial signal line Vinit1 are located in different conductive layers, and the third initial signal line Vinit3 connects multiple second initial signal lines Vinit2 or connects multiple first initial signal lines Vinit1; wherein, the distance between the orthographic projection of at least part of the segment of the third initial signal line Vinit3 on the substrate and the orthographic projection of the second conductive part on the substrate in the first direction X is greater than zero, and the first initialization signal is different from the second initialization signal.

[0050] The display panel provided by the present disclosure provides a reset signal for the gate of the driving transistor through the first initial signal line, and provides a reset signal for the first electrode of the light-emitting device through the second initial signal line. The reset signals provided by the first initial signal line and the second initial signal line are different, so that the gate of the driving transistor and the first electrode of the light-emitting element can be better reset, so that in the black state, the OLED display substrate can be guaranteed to have a lower brightness, and the display uniformity is improved. The third initial signal is connected to the first initial signal line or the second initial signal line, so that the first initial signal line or the second initial signal line forms a grid structure, so that the display uniformity of the display panel at low gray scale can be improved, and the current difference between the middle part and the two side parts of the display panel can be reduced, and the light and dark alternation problem at low gray scale can be prevented from being caused by different cross-voltage of OLED devices at different positions of the display panel. In addition, the design space of the third initial signal line is larger, so that the third initial signal line can avoid the first node where the driving transistor is connected to the first transistor, reduce interference with the first node, and further improve display uniformity.

[0051] like Figure 3 As shown, in this exemplary embodiment, the first direction X may be a row direction, and the second direction Y may be a column direction. The first initialization signal and the second initialization signal may not be equal, so the pixel driving circuit may provide different initialization signals to the first node N1 and the first electrode of the light-emitting device according to actual needs. For example, the effective level voltage of the first initialization signal may be set to -3V, and the effective level voltage of the second initialization signal may be set to -4V, which can ensure that the display screen has low brightness in the black state and improve the picture display effect.

[0052] like Figure 3 As shown, in one embodiment of the present disclosure, the third initial signal line Vinit3 can be arranged in the third conductive layer 4, and the third initial signal line Vinit3 can be connected to the second initial signal line Vinit2 through the via H12, so that the second initial signal line Vinit2 forms a grid structure. The second initial signal line Vinit2 forms a grid structure so that the design space of the switching part position of the OLED device is larger, and is no longer limited to the position close to the sixth transistor, so that the third initial signal line Vinit3 in the column direction does not need to avoid the switching hole connected to the OLED device, so that the third initial signal line Vinit3 can extend along a straight line without bending, thereby reducing the space occupied by the third initial signal line Vinit3 and reducing the difficulty of routing. Of course, in other exemplary embodiments of the present disclosure, the third initial signal line Vinit3 can also be located in other conductive layers, such as located in the fourth conductive layer 5, etc., which all belong to the protection scope of the present disclosure.

[0053] like Figure 3 , 5As shown, in this exemplary embodiment, the positive projection of the first initial signal line Vinit1 on the substrate extends along the first direction and is spaced along the second direction, and the positive projection of the first initial signal line Vinit1 in the pixel driving circuit of this row on the substrate is located on the side away from the positive projection of the second initial signal line Vinit2 in the pixel driving circuit of the adjacent previous row on the substrate. The positive projection of the first conductive part 21 in the pixel driving circuit of the adjacent previous row on the substrate substrate. That is, the first initial signal line Vinit1 in the pixel driving circuit of this row is closer to the driving transistor in the pixel driving circuit of this row than the second initial signal line Vinit2 in the pixel driving circuit of the previous row, thereby making it possible for the OLED device transfer hole in the pixel driving circuit of this row to avoid the transfer hole of the first transistor in the pixel driving circuit of the next row connected to the first initial signal line Vinit1, thereby improving the adjustment range of the transfer hole of the OLED device.

[0054] It should be understood that in this exemplary embodiment, a certain structure A extends along the B direction, which means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along the B direction, and the length of the main part extending along the B direction is greater than the length of the secondary part extending along other directions.

[0055] like Figure 3 , 6 As shown, in this exemplary embodiment, the display panel may include a first sub-pixel R, a second sub-pixel B, and a third sub-pixel G arranged in an array along the row and column directions, the first sub-pixel R, the second sub-pixel B, and the third sub-pixel G all include the pixel driving circuit described in the present disclosure, the first sub-pixel R and the second sub-pixel B are located in the same column and are alternately arranged in the column direction, and the third sub-pixel G is located in another column and is arranged in an array in the column direction. The pixel column where the first sub-pixel R and the second sub-pixel B are located is the first pixel driving circuit column P1, and the pixel column where the third sub-pixel G is located is the second pixel driving circuit column P2, and the first pixel driving circuit column P1 and the second pixel driving circuit column P2 can be arranged at intervals in the row direction. In this exemplary embodiment, the third initial signal line Vinit3 can be arranged only in some pixel columns. Exemplarily, the third initial signal line Vinit3 can be arranged only in the first pixel driving circuit column P1, and the third initial signal line Vinit3 can not be arranged in the second pixel driving circuit column P2. Of course, in other exemplary embodiments of the present disclosure, the third initial signal line Vinit3 may be arranged only in the second pixel driving circuit column P2, or the third initial signal line Vinit3 may be arranged in both the first pixel driving circuit column P1 and the second pixel driving circuit column P2, all of which fall within the protection scope of the present disclosure.

[0056] like Figure 3As shown, in this exemplary embodiment, the display panel may further include an active layer 1 and a pixel defining layer 6, wherein the base substrate, the active layer 1, the first conductive layer 2, the second conductive layer 3, the third conductive layer 4, the fourth conductive layer 5, and the pixel defining layer 6 are sequentially stacked, and an insulating layer may be provided between the above functional layers. The first conductive layer 2 may be a first gate metal layer (Gate1 layer), the second conductive layer 3 may be a second gate metal layer (Gate2 layer), the third conductive layer 4 may be a first metal wiring layer (SD1 layer), and the fourth conductive layer 5 may be a second metal wiring layer (SD2 layer). Figure 7-11 As shown, Figure 7 for Figure 3 The structural layout of the fourth conductive layer in Figure 8 for Figure 3 The structural layout of the active layer, Fig. 9 for Figure 3 The structural layout of the pixel definition layer in the middle. Fig.10 for Figure 3 The stacked structure layout of the active layer and the first conductive layer, Fig.11 for Figure 3 The stacked structure layout of the active layer and the second conductive layer, Fig.12 for Figure 3 The stacked structure layout of the active layer and the third conductive layer, Fig.13 for Figure 3 The stacked structure layout of the third conductive layer and the fourth conductive layer, Fig.14 for Figure 3 A stacked structure layout of an active layer, a first conductive layer and a pixel defining layer.

[0057] like Figure 3 , 8As shown, in this exemplary embodiment, the active layer 1 may include a first active portion 11, a second active portion 12, a third active portion 13, a fourth active portion 14, a fifth active portion 15, a sixth active portion 16, and a seventh active portion 17, wherein the first active portion 11 includes a first sub-active portion 111, a second sub-active portion 112, a third sub-active portion 113, and a ninth sub-active portion 119, the first sub-active portion 111 is used to form a first channel region of the first transistor T1, and the third sub-active portion 113 is used to form the second channel region of the first transistor T1, the second sub-active portion 112 is connected between the first sub-active portion 111 and the third sub-active portion 113, the ninth sub-active portion 119 is connected to the side of the first sub-active portion 111 away from the third sub-active portion 113, and the ninth sub-active portion 119 is used to connect the fifth conductive portion 45 located in the third conductive layer 4 through the second via H2 to achieve the first electrode of the first transistor T1 connected to the first initial signal line Vinit1. The second active portion 12 includes a fourth sub-active portion 124, a fifth sub-active portion 125 and a sixth sub-active portion 126 connected in sequence, the fourth sub-active portion 124 is used to form the first channel region of the second transistor T2, and the sixth sub-active portion 126 is used to form the second channel region of the second transistor T2. The third active portion 13 is used to form the channel region of the driving transistor T3. The fourth active portion 14 is used to form the channel region of the fourth transistor T4, the fifth active portion 15 is used to form the channel region of the fifth transistor T5, the sixth active portion 16 is used to form the channel region of the sixth transistor, and the seventh active portion 17 is used to form the channel region of the seventh transistor T7. Figure 8As shown, the active layer 1 may further include an eighth active portion 18, a ninth active portion 19, a tenth active portion 10, an eleventh active portion 101, a twelfth active portion 102, a thirteenth active portion 103 and a fourteenth active portion 104, wherein the fourteenth active portion 104 is connected between the sixth active portion 16 and the third active portion 13, the eighth active portion 18 is connected to the sixth active portion 16 and is located on a side of the sixth active portion 16 away from the fourteenth active portion 104, and the eighth active portion 18 may be The seventh sub-active portion 187 and the eighth sub-active portion 188 are included. The seventh sub-active portion 187 is connected between the seventh active portion 17 and the sixth active portion 16 and the orthographic projection of the seventh sub-active portion 187 on the substrate extends along the column direction. The eighth sub-active portion 188 is connected to the seventh sub-active portion 187 and the orthographic projection on the substrate extends along the row direction. The end of the eighth sub-active portion 188 away from the seventh sub-active portion is connected to the third connection portion 43 of the third conductive layer 4 through the first via H1. As described above, the second initial signal line Vinit2 forms a grid structure, which can make the design space of the transition portion position of the OLED device larger, and is no longer limited to the position close to the sixth transistor T6, that is, the eighth sub-active portion 188 can extend a certain length in the row direction in the direction away from the sixth transistor T6, so that the third connection portion 43 is a certain distance away from the second transistor T6. Exemplarily, the fifth active portion 15 and the sixth active portion 16 may have a first distance L1, the eighth sub-active portion 188 has a first extension length L0, and L0 / L1 may be between 1 / 4 and 1 / 2, for example, 1 / 4, 1 / 3, 1 / 2, etc. The ninth active portion 19 is connected to the seventh active portion 17, and the ninth active portion 19 is located on the side of the seventh active portion 17 away from the sixth active portion 16. The ninth active portion 19 is connected to the third initial signal line Vinit3 located in the third conductive layer 4 through the via H13, so as to achieve the connection of the second electrode of the seventh transistor T7 located in the first pixel driving circuit column P1 to the second initial signal line Vinit2. In addition, the ninth active portion 19 located in the second pixel driving circuit column P2 is connected to the sixth conductive portion 46 located in the third conductive layer 4 through the via H13, so that the first electrode of the seventh transistor T7 located in the second pixel driving circuit column P2 is connected to the second initial signal line Vinit2. The tenth active portion 10 is connected between the third sub-active portion 113 and the sixth sub-active portion 126, and is used to realize that the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2. The eleventh active portion 101 is connected between the fifth active portion 15 and the fourth active portion 14, and is used to realize that the second electrode of the fourth transistor T4 is connected to the first electrode of the fifth transistor T5. The twelfth active portion 102 is connected to the side of the fifth active portion 15 away from the eleventh active portion 101, and the twelfth active portion 102 is connected to the first power line Vdd located in the third conductive layer 4 through the via H8, so as to realize that the second electrode of the fifth transistor T5 is connected to the first power line Vdd.The thirteenth active portion 103 is connected to the fourth active portion 14, and the thirteenth active portion 103 is located on a side of the fourth active portion 14 away from the third active portion 13. The thirteenth active portion 103 is used to connect the data signal line Vdata of the third conductive layer 4 to achieve connecting the first electrode of the fourth transistor T4 to the data signal line Vdata. The active layer 1 can be formed of polycrystalline silicon semiconductor material, and accordingly, the transistor in the display panel of the present disclosure can be a P-type low-temperature polycrystalline silicon thin film transistor.

[0058] like Figure 3 , 4 As shown in Figures 1 and 11, in this exemplary embodiment, in addition to the first conductive portion 21, the first conductive layer 2 may also include a first reset signal line Re1, a first scan signal line S1, an enable signal line EM, and a second reset signal line Re2, wherein the orthographic projections of the first reset signal line Re1, the first scan signal line S1, the enable signal line EM, and the second reset signal line Re2 on the substrate all extend in the row direction and are arranged in sequence in the column direction. The orthographic projections of the first reset signal line Re1 and the second reset signal line Re2 on the substrate all extend in the row direction, the orthographic projection of the first reset signal line Re1 on the substrate covers the orthographic projections of the first sub-active portion 111 on the substrate and the orthographic projections of the third sub-active portion 113 on the substrate, a partial structure of the first reset signal line Re1 is used to form the gate of the first transistor T1, and the first reset signal line Re1 can be used to provide Figure 1 The positive projection of the second reset signal line Re2 on the substrate covers the positive projection of the seventh active portion 17 on the substrate. Part of the structure of the second reset signal line Re2 is used to form the gate of the seventh transistor T7. The second reset signal line Re2 can be used to provide Figure 1 In this exemplary embodiment, the reset signal lines in the pixel driving circuits of different rows can be reused. For example, the second reset signal line Re2 in the pixel driving circuit of this row can be reused as the first reset signal line Re1 in the pixel driving circuit of the next row. By reusing the reset signal line, the number of signal lines can be reduced and the structure of the display panel can be simplified. In the case of reusing the reset signal line, the reset signal line can be used to provide the pixel driving circuit of this row with a reset signal line. Figure 1 The reset signal terminal Re1 in the upper row provides a pixel driving circuit Figure 1 The orthographic projection of the enable signal line EM on the substrate extends along the row direction, and the orthographic projection of the enable signal line EM on the substrate covers the fifth active portion 15 and the sixth active portion 16. Part of the structure of the enable signal line EM is used to form the gate of the sixth transistor T6, and part of the structure is used to form the gate of the fifth transistor T5. At the same time, the enable signal line EM can provide Figure 1The enable signal terminal EM in the first scanning signal line S1 extends along the row direction in the orthographic projection of the substrate. The orthographic projection of the first scanning signal line S1 on the substrate covers the orthographic projections of the fourth sub-active portion 124 and the sixth sub-active portion 126 on the substrate. The partial structure of the first scanning signal line S1 is used to form the gate of the second transistor T2. The orthographic projection of the first scanning signal line S1 on the substrate also covers the orthographic projection of the fourth active portion 14 on the substrate. The partial structure of the first scanning signal line S1 is used to form the gate of the fourth transistor T4. At the same time, the first scanning signal line S1 can be used to provide Figure 1 In addition, the first conductive layer 2 may further include a first conductive portion 21, the first conductive portion 21 is located between the first scan signal line S1 and the enable signal line EM, the orthographic projection of the first conductive portion 21 on the base substrate covers the orthographic projection of the third active portion 13 on the base substrate, and a partial structure of the first conductive portion 21 is used to form the gate of the driving transistor T3 and the first electrode of the storage capacitor C. In this exemplary embodiment, the display panel may perform a conductor processing on the active layer 110 using the first conductive layer 220 as a mask, that is, the active layer 110 covered by the first conductive layer 220 forms a channel region of the transistor, and the area not covered by the first conductive layer 220 forms a conductor structure.

[0059] It should be understood that the orthographic projection of a certain structure A on the substrate described in this exemplary embodiment covers the orthographic projection of another structure B on the substrate, which can be understood as the outline of the projection of B on the plane of the substrate is completely inside the outline of the projection of A in the same plane.

[0060] like Figure 3 , 5 As shown, in this exemplary embodiment, the widths of the first initial signal line Vinit1 and the second initial signal line Vinit2 in the column direction can be set to be different. Exemplarily, the width d1 of the first initial signal line in the column direction can be set to be greater than the width d2 of the second initial signal line in the column direction. The "width in the column direction" refers to the width of the main part of the two signal lines extending in the row direction in the column direction. The square resistance value of the signal line has a negative correlation with its width, that is, the larger the line width, the smaller the square resistance. Setting the line width of one of the two signal lines to be wider can effectively reduce the overall square resistance of the two signal lines; at the same time, setting one of the two to have a wider line width can also help to fully utilize the space of the display substrate while reducing resistance to improve the display effect. The width d1 of the first initialization signal line in the column direction is set to be greater than the width d2 of the second initialization signal line in the column direction. In a specific embodiment of the present disclosure, the width d1 of the first initialization signal line can be 1.3 to 2.4 times the width d2 of the second initialization signal line.

[0061] like Figure 3 , 5 As shown in Figures 1 and 11, in this exemplary embodiment, the second conductive layer 3 may include, in addition to the first initial signal line Vinit1 and the second initial signal line Vinit2, a third conductive portion 33 and a seventh conductive portion 37, wherein the third conductive portion 33 is used to form another electrode plate of the storage capacitor C, and the orthographic projection of the third conductive portion 33 on the substrate overlaps with the orthographic projection of the first conductive portion 21 on the substrate. The third conductive portion 33 is connected to the eleventh active portion 101 of the active layer 1 through the via H6, so that the second electrode of the fifth transistor T5 is connected to the second electrode of the storage capacitor C. The seventh conductive portion 37 is connected to a stable voltage source, and the seventh conductive portion 37 is located between the third conductive portion 33 and the first initial signal line Vinit1, as shown in Figures 1 and 11. Figure 5 , 11As shown, the seventh conductive portion 37 is connected to a stable voltage source, and the seventh conductive portion 37 may include a first sub-conductive portion 371, the orthographic projection of the first sub-conductive portion 371 on the substrate may extend along the column direction Y, and the orthographic projection of the first sub-conductive portion 371 on the substrate at least partially overlaps with the orthographic projection of the fifth sub-active portion 125 on the substrate (for example, the width of the first sub-conductive portion 371 in the row direction may be set to be greater than the width of the fifth sub-active portion 125 in the row direction), and the fifth sub-active portion 125 is a conductive structure, which is connected to form the second transistor T2 trench. The fourth sub-active portion 124 and the sixth sub-active portion 126 in the channel area, the orthographic projection of the first sub-conductive portion 371 on the substrate covers the orthographic projection of the fifth sub-active portion 125 on the substrate. Because the seventh conductive portion 37 is connected to a stable voltage source, the seventh conductive portion 37 can stabilize the fifth sub-active portion 125, thereby reducing the leakage of the second transistor T2, and preventing the influence of the pixel data voltage change of the adjacent column on the pixel, thereby reducing the voltage fluctuation of the pixel driving circuit driving the transistor T3 in the light-emitting stage, thereby improving the picture quality. The seventh conductive portion 37 may further include a second sub-conductive portion 372, the orthographic projection of the second sub-conductive portion 372 on the substrate at least partially overlapping with the orthographic projection of the tenth active portion 10 on the substrate (for example, the width of the second sub-conductive portion 372 in the row direction may be set to be greater than the width of the tenth active portion 10 in the row direction), so that the second sub-conductive portion 372 may stabilize the voltage on the tenth active portion 10, thereby eliminating or reducing the noise influence of the data signal line Vdata or other signal lines on the tenth active portion 10. Since the tenth active portion 10 is connected to the first electrode of the first transistor T1 and the gate of the driving transistor T3, the voltage stabilization of the tenth active portion 10 may reduce the voltage fluctuation of the driving transistor T3 of the pixel driving circuit during the light-emitting stage. In addition, the seventh conductive portion 37 may further include a third sub-conductive portion 373, the third sub-conductive portion 373 is connected to the second sub-conductive portion 372, the orthographic projection of the third sub-conductive portion 373 on the substrate may extend along the column direction Y, the orthographic projection of the third sub-conductive portion 373 on the substrate is located between the orthographic projection of the tenth active portion 10 on the substrate and the orthographic projection of the data signal line Vdata on the substrate, and the alternating voltage of the data signal line Vdata may be shielded from interfering with the tenth active portion 10, thereby improving the voltage stabilizing effect of the seventh conductive portion 37 on the tenth active portion 10. In this exemplary embodiment, in combination with Figure 3 , Figure 5 and Fig.11 , the seventh conductive portion 37 can be connected to the first power line Vdd through the via H4 at the position of the second sub-conductive portion 372, so as to provide a stable voltage source for the seventh conductive portion 37 through the first power line Vdd. Of course, in other exemplary embodiments of the present disclosure, a stable voltage source can also be provided in other ways. In addition, it should be understood that there is a conductive connection portion between the first sub-conductive portion 371 and the second sub-conductive portion 372.

[0062] like Fig.11 As shown, in this exemplary embodiment, the orthographic projection of the first initial signal line on the substrate can cover the orthographic projection of the second sub-active portion 112 on the substrate. Exemplarily, the first initial signal line may include a first component 38 and a second component 39, the width of the first component 38 in the column direction is smaller than the width of the second component 39 in the column direction, and the orthographic projection of the second component 39 on the substrate covers the orthographic projection of the second sub-active portion 112 on the substrate, that is, the first initial signal line is widened at the position of the second sub-active portion 112, thereby preventing the conductive part between the double gates of the first transistor T1 from being affected by other parts of the pixel driving circuit, so as to improve the display effect.

[0063] In this exemplary embodiment, the third initial signal line Vinit3 may be located in the third conductive layer 4, and the third initial signal line Vinit3 may extend in a straight line in the column direction. The third initial signal line Vinit3 extending in a straight line in the column direction may reduce space occupation and reduce wiring difficulty. Fig.15 As shown, Fig.15 for Figure 6 In the locally enlarged view of the third initial signal line, the third initial signal line Vinit3 may not extend in a straight line. Exemplarily, the third initial signal line Vinit3 may include a first extension portion 401, a second extension portion 402 and a third extension portion 403. The second extension portion 402 is connected between the first extension portion 401 and the third extension portion 403. There is a third angle θ between the second extension portion 402 and the first extension portion 401, and between the second extension portion 402 and the third extension portion 403. The third angle θ is greater than or equal to 90° and less than or equal to 180°, for example, it can be 90°, 120°, 150°, 180°, etc. The orthographic projections of the second extension portion 402 and the third extension portion 403 on the substrate substrate are located between the orthographic projections of the first scanning signal line S1 on the substrate substrate and the orthographic projections of the enable signal line EM on the substrate substrate, and the orthographic projections of the second extension portion 402 and the third extension portion 403 on the substrate substrate do not overlap with the orthographic projections of the fourteenth active portion 104 on the substrate substrate, that is, the third initial signal line Vinit3 is bent at a position close to the driving transistor T3, and by bending at this position, the third initial signal line Vinit3 can avoid Figure 1 The first electrode of the middle driving transistor T3 is connected to the third node N3 of the sixth transistor T6, so as to reduce the loading of the second initial signal line Vinit2 and the third node N3 and alleviate the afterimage.

[0064] like Figure 6 , 15As shown, in this exemplary embodiment, the orthographic projections of the second extension portion 402 and the third extension portion 403 on the substrate substrate may be located on the side where the orthographic projection of the fourteenth active portion 104 on the substrate substrate faces the orthographic projection of the first conductive portion 21 on the substrate substrate, that is, the second extension portion 402 is bent in a direction close to the second conductive portion 42, and the distance between the orthographic projection of the first extension portion 401 on the substrate substrate and the orthographic projection of the first conductive portion 21 on the substrate substrate in the row direction X is greater than the distance between the orthographic projections of the second extension portion 402 and the third extension portion 403 on the substrate substrate and the orthographic projection of the first conductive portion 21 on the substrate substrate in the row direction X. Of course, in other exemplary embodiments of the present disclosure, the third initial signal line Vinit3 may also be bent in a direction away from the second conductive portion 42, in which case the distance between the second extension portion 402, the third extension portion 403 and the second conductive portion 42 in the row direction is greater than the distance between other parts of the third initial signal line Vinit3 and the second conductive portion 42 in the row direction, all of which belong to the protection scope of the present disclosure.

[0065] like Figure 6 As shown, in this exemplary embodiment, the orthographic projection of the second conductive portion 42 on the substrate extends along the column direction, and the second conductive portion 42 can be connected to the first conductive portion 21 through the via H5 and connected to the tenth active portion 10 through the third via H3, so that the gate of the driving transistor T3 is connected to the second electrode of the first transistor T1 and the first electrode of the second transistor T2. In addition, the third conductive layer 4 can also include a first power line Vdd, a second connecting portion 44 and a sixth conductive portion 46. The orthographic projection of the first power line Vdd on the substrate extends along the column direction. The first power line Vdd can be connected to the twelfth active portion 102 through the via H8 to achieve the connection of the second electrode of the fifth transistor T5 to the first power line Vdd. The first power line Vdd can provide Figure 1The first power supply terminal VDD in the second pixel driving circuit column P2. The second connecting portion 44 is used to connect to the fourth connecting portion 54 located in the fourth conductive layer 5. The orthographic projection of the sixth conductive portion 46 on the base substrate extends along the column direction, and the sixth conductive portion 46 and the second initial signal line Vinit2 can be connected through the via H11, and the sixth conductive portion 46 and the ninth active portion 19 are connected through the via H1, so as to realize that the first electrode of the seventh transistor T7 located in the second pixel driving circuit column P2 is connected to the second initial signal line Vinit2. In addition, in this exemplary embodiment, the third initial signal line Vinit3 and the first power line Vdd may have a second distance L2 in the row direction, and the ratio of the second distance L2 to the first distance L1 may be between 0.8 and 1.2, for example, it may be 0.8, 0.9, 1.0, 1.2, etc. The third initial signal line Vinit3 and the second conductive part 42 may have a third distance L3 in the row direction, and the ratio of the third distance L3 to the first distance L1 may be between 1 / 3 and 1 / 2, for example, 1 / 3, 5 / 12, etc. By increasing the spacing between the third initial signal line Vinit3 and the first power line Vdd in the row direction and the spacing between the third initial signal line Vinit3 and the second conductive part 42 in the row direction, the interference of parasitic capacitance on the signal can be further reduced.

[0066] like Figure 6 As shown, in this exemplary embodiment, the third conductive layer 4 may further include a third connecting portion 43 and a fifth conductive portion 45, wherein the third connecting portion 43 may be connected to the eighth sub-active portion 188 through the first via hole H1, so as to realize that the third connecting portion 43 is connected to the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The fifth conductive portion 45 extends along the column direction in the orthographic projection of the base substrate, and the fifth conductive portion 45 may be connected to the first initial signal line Vinit1 through the tenth via hole H10 and connected to the ninth sub-active portion 119 through the second via hole H2, so that the first electrode of the first transistor T1 is connected to the first initial signal line Vinit1. Fig.16 for Figure 3 The stacked structure layout of the active layer, the second conductive layer and the third conductive layer of a sub-pixel in FIG. Figure 6 , 16As shown, in the same column of pixel driving circuits, the orthographic projection of the fifth conductive portion 45 on the substrate substrate and the orthographic projection of the third connecting portion 43 on the substrate substrate are both located on the same side of the orthographic projection of the third initial signal line Vinit3 on the substrate substrate, and in two pixel driving circuits located in adjacent rows of the same column, a line segment connecting the tenth via H10 and the first via H1 has a first angle α between the orthographic projection of the substrate substrate and the orthographic projection of the fifth conductive portion 45 on the substrate substrate, and the first angle α may be between 175° and 180°, for example, 175°, 176°, 178°, 180°, etc., that is, in two adjacent rows of pixel driving circuits in the same column, the fifth conductive portion 45 is extended to The third connection part 43 partially overlaps in the column direction, which increases the risk of overlapping between the fifth conductive part 45 and the third connection part 43 to a certain extent. In this exemplary embodiment, the orthographic projection of the fifth conductive part 45 in the pixel driving circuit of this row on the substrate substrate is located on the side of the orthographic projection of the second initial signal line Vinit2 in the pixel driving circuit of the adjacent previous row on the substrate substrate away from the orthographic projection of the first via H1 in the pixel driving circuit of the adjacent previous row on the substrate substrate, that is, the fifth conductive part 45 and the first via H1 are at least separated by the second initial signal line Vinit2, so that the fifth conductive part 45 can avoid the third connection part 43, so that the fifth conductive part 45 and the third connection part 43 do not overlap.

[0067] In addition, if Fig.16 As shown, in the same column of pixel driving circuits, the orthographic projection of the fifth conductive portion 45 on the substrate substrate and the orthographic projection of the second conductive portion 42 on the substrate substrate are both located on the same side of the orthographic projection of the third initial signal line Vinit3 on the substrate substrate. In the same pixel driving circuit, the line segment connecting the third via H3 and the second via H2 has a second angle β between the orthographic projection of the substrate substrate and the orthographic projection of the second conductive portion 42 on the substrate substrate. The second angle β may be between 175° and 180°, for example, 175°, 176°, 178°, 180°, etc. It can be seen that the second conductive portion 42 and the fifth conductive portion 45 are relatively arranged in the reverse direction of the column. Therefore, when the third initial signal line Vinit3 is connected to the first initial signal line Vinit1, the third initial signal line Vinit3 needs to be bent to avoid the second conductive part 42. In this exemplary embodiment, the second initial signal line Vinit2 is formed into a grid structure by connecting the third initial signal line Vinit3 to the second initial signal line Vinit2. Therefore, the third initial signal line Vinit3 does not need to avoid the second conductive part 42 in the column direction. The third initial signal line Vinit3 can be extended in a straight line in the column direction, thereby reducing space occupancy and reducing routing difficulty.

[0068] like Figure 6As shown, in this exemplary embodiment, the extension length of the orthographic projection of the third connection portion 43 in the first pixel driving circuit column P1 on the substrate substrate may be different from the extension length of the orthographic projection of the third connection portion 43 in the second pixel driving circuit column P2 on the substrate substrate. Exemplarily, the extension length of the orthographic projection of the third connection portion 43 in the first pixel driving circuit column P1 on the substrate substrate may be less than the extension length of the orthographic projection of the third connection portion 43 in the second pixel driving circuit column P2 on the substrate substrate, by setting the extension length of the orthographic projection of the third connection portion 43 of the second pixel driving circuit column P2 on the substrate substrate to be greater than the extension length of the orthographic projection of the third connection portion 43 in the first pixel driving circuit column P1 on the substrate substrate. Specifically, the third connection portion 43 may include a first via contact portion 431 and a second via contact portion 432, the first via contact portion 431 being connected to the second electrode of the seventh transistor through the first via H1, and the second via contact portion 432 being connected to the anode connection portion located in the fourth conductive layer 5 through a via. 52, in the second pixel driving circuit column P2, the orthographic projection of the second via contact portion 432 on the substrate is located on the side of the orthographic projection of the first via contact portion 431 on the substrate facing the orthographic projection of the second conductive portion 42 on the substrate, and the distance between the orthographic projection of the second via contact portion 432 on the substrate and the orthographic projection of the second conductive portion 42 on the substrate in the row direction is greater than the distance between the orthographic projection of the first via contact portion 431 on the substrate and the orthographic projection of the second conductive portion 42 on the substrate in the row direction, that is, the second via contact portion 432 deviates from the extension direction of the second conductive portion 42, so that the second via contact portion 432 can avoid the second conductive portion 42, so that the third connecting portion 43 will not be short-circuited with the second conductive portion 42. Exemplarily, the second via contact portion 432 can be offset in a direction away from the first power line Vdd of the pixel driving circuit column to avoid the second conductive portion 42. It should be understood that the second via contact portion 432 may also be offset in other directions, as long as the second via contact portion 432 deviates from the pixel opening of the sub-pixel and does not overlap with the second conductive portion 42. Figure 6 As shown, in this exemplary embodiment, the orthographic projections of the first via contact portion 431 and the second via contact portion 432 located in the first pixel driving column on the substrate substrate may overlap with the orthographic projection of the second initial signal line Vinit2 on the substrate substrate, the orthographic projections of the first via contact portion 431 and the second via contact portion 432 located in the second pixel driving circuit column on the substrate substrate do not overlap with the orthographic projection of the second initial signal line Vinit2 on the substrate substrate, and the orthographic projection of the second via contact portion 432 on the substrate substrate may overlap with the orthographic projection of the third conductive portion 33 in the same pixel driving circuit on the substrate substrate.

[0069] like Figure 7 , 14As shown, in this exemplary embodiment, the fourth conductive layer 5 may include a data signal line Vdata and a second power line 55, the data signal line Vdata extends in the column direction on the orthographic projection of the substrate, the data signal line Vdata is connected to the fourth connection portion 54, the fourth connection portion 54 may be connected to the second connection portion 44 of the third conductive layer 4 and the thirteenth active portion 103 of the active layer 1 through the via H9, so that the first electrode of the fourth transistor T4 is connected to the data signal line Vdata, and the data signal line Vdata can be used to provide Figure 1 The orthographic projection of the second power line 55 on the substrate extends along the column direction and overlaps with the orthographic projection of the first power line Vdd on the substrate. The second power line 55 is connected to the first power line Vdd through a via hole, so that the second power line 55 and the first power line Vdd are connected in parallel, which can significantly reduce the voltage drop of the Vdd signal during transmission and improve the display effect.

[0070] like Figure 7As shown, in this exemplary embodiment, the fourth conductive layer 5 may also include an anode flat portion, which is connected to the second power line 55, and each anode flat portion is arranged directly below the anode of the light-emitting device in the sub-pixel, that is, in the same sub-pixel, the orthographic projection of the anode flat portion on the substrate substrate overlaps with the orthographic projection of the anode on the substrate substrate at least partially, and the orthographic projection of the pixel opening on the substrate substrate is located within the orthographic projection of the anode flat portion on the substrate substrate. The anode flat portion can be used to improve the flatness of the anode, improve color deviation, and enhance the display effect. Furthermore, the orthographic projection of the anode of the light-emitting device on the substrate substrate can completely cover the orthographic projection of the anode flat portion on the substrate substrate, that is, the outline of the orthographic projection of the anode flat portion on the substrate substrate is completely located inside the outline of the orthographic projection of the anode of the light-emitting device on the substrate substrate. Exemplarily, the display panel may include a first anode flat portion 511 located at a first sub-pixel R, a second anode flat portion 512 located at a second sub-pixel B, and a third anode flat portion 513 located at a third sub-pixel G. The orthographic projection of the anode of the first sub-pixel R on the substrate can completely cover the orthographic projection of the first anode flat portion 511 on the substrate, the orthographic projection of the anode of the second sub-pixel B on the substrate can completely cover the orthographic projection of the second anode flat portion 512 on the substrate, and the orthographic projection of the anode of the third sub-pixel G on the substrate can completely cover the orthographic projection of the third anode flat portion 513 on the substrate. Generally, the signal lines such as the first power line Vdd and the second power line 55 made of the third conductive layer 4 and the fourth conductive layer 5 located on the side of the anode close to the display substrate have a large thickness in a direction perpendicular to the substrate, and the insulating layer above the signal line cannot be completely flattened, resulting in uneven light-emitting layer above the flat layer, and asymmetric protrusions appearing on the anode and the light-emitting layer above the anode, which in turn causes color shift when observed from the left and right sides of the normal line of the display substrate at the same angle as the display substrate. In this exemplary embodiment, by arranging a flat anode portion under the anodes of different sub-pixels, and the flat anode portion is completely located inside the positive projection of the anode, the corresponding position of the anode of each sub-pixel can be flattened, thereby further improving the color deviation. In addition, the shape and size of the flat anode portion of the sub-pixel emitting light of different colors can be different. For example, the area of ​​the first flat anode portion 511 can be larger than the area of ​​the second flat anode portion and the area of ​​the third flat anode portion. Of course, in other exemplary embodiments of the present disclosure, the shape and size of the flat anode portions of different sub-pixels can also be the same.

[0071] like Figure 7As shown, the fourth conductive layer 5 may further include an anode connection portion 52. In the same sub-pixel, the anode connection portion 52 is separated from the anode flat portion, and the anode connection portion 52 is used to connect the anode of the light-emitting device in the pixel defining layer. In this exemplary embodiment, the orthographic projections of the anode connection portion 52 of the R sub-pixel and the anode connection portion 52 of the B sub-pixel on the substrate overlap with the orthographic projections of the eighth sub-active portion 188 at the corresponding position on the substrate. The anode connection portion 52 of the R sub-pixel is located between the anode flat portion of the sub-pixel in this row and the anode flat portion of the sub-pixel in the next row, the anode connection portion 52 of the B sub-pixel is located between the anode flat portion of the sub-pixel in this row and the anode flat portion of the sub-pixel in the next row, and the anode connection portion 52 of the G sub-pixel is located between the anode flat portion of the sub-pixel in this row and the anode flat portion of the sub-pixel in the previous row. As shown Fig.13 As shown, the anode connection portion 52 of the R sub-pixel can be connected to the third connection portion 43 at the corresponding position in the third conductive layer 4 through the first via hole H1 at the position, thereby realizing the connection between the anode of the light-emitting device in the R sub-pixel and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The anode connection portion 52 of the B sub-pixel is connected to the third connection portion 43 at the corresponding position in the third conductive layer 4 through the first via hole H1 at the position, thereby realizing the connection between the anode of the light-emitting device in the B sub-pixel and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The anode connection portion 52 of the G sub-pixel is connected to the first via contact portion 431 at the corresponding position in the third conductive layer 4 through the first via hole H1 at the position, thereby realizing the connection between the anode of the light-emitting device in the G sub-pixel and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0072] like Fig. 9 As shown, in this exemplary embodiment, the display panel may further include a pixel defining layer 6, the pixel defining layer 6 includes a pixel opening, and the orthographic projection of the pixel opening on the substrate overlaps with the orthographic projection of the anode flat portion at the corresponding position of the fourth conductive layer 5 on the substrate. The first sub-pixel R may include a first main body portion 611 and a first extension portion 612, the second sub-pixel B may include a second main body portion 621 and a second extension portion 622, and the third sub-pixel G may include a third main body portion 623. Fig.14 As shown, in this exemplary embodiment, the orthographic projection of the first extension portion 612 on the substrate can overlap with the orthographic projection of the channel region of the second transistor T2 in the adjacent third sub-pixel G on the substrate, thereby reducing the leakage of the second transistor T2 in the third sub-pixel G and preventing the Figure 1The first node N1 in the first sub-pixel R is affected, thereby improving the uniformity of the displayed image. Similarly, the orthographic projection of the second extension portion 622 on the substrate substrate can overlap with the orthographic projection of the channel region of the second transistor T2 in the adjacent third sub-pixel G on the substrate substrate, achieving the same effect. The first sub-pixel R may further include a shielding portion 624, the orthographic projection of the shielding portion 624 on the substrate substrate can overlap with the orthographic projection of the channel region of the second transistor T2 in the sub-pixel on the substrate substrate, thereby reducing the leakage of the second transistor T2 of the first sub-pixel R and improving the uniformity of the displayed image.

[0073] Fig.17 for Figure 3 In the cross-sectional view along the AA direction, the display panel may also include a buffer layer 72, a first insulating layer 73, a second insulating layer 74, a first dielectric layer 75, a passivation layer 77, and a second dielectric layer 77, wherein the substrate 71, the buffer layer 72, the active layer 1, the first insulating layer 73, the first conductive layer 2, the second insulating layer 74, the second conductive layer 3, the first dielectric layer 75, the third conductive layer 4, the passivation layer 76, the second dielectric layer 77, the fourth conductive layer 5, and the anode structure layer 5 are stacked in sequence. The first insulating layer 73 and the second insulating layer 74 may be silicon oxide layers, the first dielectric layer 75 and the second dielectric layer 77 may be silicon nitride layers, and the materials of the passivation layer 77 and the buffer layer 72 may be silicon oxide, silicon nitride, etc. The substrate 71 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material. The material of the first conductive layer 2 and the second conductive layer 3 may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum / titanium alloy or a laminate, etc. The material of the third conductive layer 4 and the fourth conductive layer 5 may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum / titanium alloy or a laminate, etc., or a titanium / aluminum / titanium laminate.

[0074] The present disclosure also provides a display device, which may include the display panel described in any embodiment of the present disclosure.

[0075] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the generality of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of pixel driving circuits distributed in an array along a first direction and a second direction, the pixel driving circuit is used to drive the light-emitting device to emit light, the first direction and the second direction intersect, the pixel driving circuit includes a driving transistor and a second transistor, a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode is connected to the first electrode of the driving transistor, and the display panel also includes: substrate substrate; A first conductive layer is located on one side of the substrate, and the first conductive layer includes: a first conductive portion, wherein the first conductive portion is used to form a gate of the driving transistor; The second conductive layer is located on a side of the first conductive layer away from the substrate, and the second conductive layer includes: a plurality of first initial signal lines, the orthographic projections of which on the substrate extend along the first direction and are spaced apart along the second direction, the first initial signal lines being used to provide a first initialization signal for the gate of the driving transistor; a plurality of second initial signal lines, wherein the orthographic projections of the plurality of second initial signal lines on the substrate extend along the first direction and are spaced apart along the second direction, and the second initial signal lines are used to provide a second initialization signal for the first electrode of the light-emitting device; A third conductive layer is located on a side of the second conductive layer away from the substrate, and the third conductive layer includes: A second conductive portion, the orthographic projection of the base substrate extending along a second direction, the second conductive portion being used to connect the first conductive portion to a first electrode of a second transistor; a third initial signal line, wherein the orthographic projection of the substrate extends along the second direction, the third initial signal line and the second initial signal line and / or the first initial signal line are located in a different conductive layer, and the third initial signal line is connected to a plurality of the second initial signal lines or connected to a plurality of the first initial signal lines; The distance between the orthographic projection of at least part of the third initial signal line on the base substrate and the orthographic projection of the second conductive portion on the base substrate in the first direction is greater than zero, and the first initialization signal is different from the second initialization signal.

2. The display panel according to claim 1, characterized in that: The third initial signal line is located in the third conductive layer, and the third initial signal line is connected to the second initial signal line through a via hole.

3. The display panel according to claim 2, characterized in that: The first direction is a row direction, the second direction is a column direction, the pixel driving circuit further comprises: a first transistor and a seventh transistor, the first electrode of the first transistor is connected to the first initial signal line, the second electrode is connected to the gate of the driving transistor, and the gate is connected to a first reset signal line; the first electrode of the seventh transistor is connected to the second initial signal line, the second electrode is connected to the first electrode of the light-emitting device, and the gate is connected to a second reset signal line; Among them, the positive projection of the first initial signal line in this row of pixel driving circuits on the substrate is located on the side of the positive projection of the second initial signal line in the adjacent previous row of pixel driving circuits on the substrate away from the positive projection of the first conductive part in the adjacent previous row of pixel driving circuits on the substrate.

4. The display panel according to claim 3, characterized in that: The third conductive layer further comprises: A third connecting portion, connected to the second electrode of the seventh transistor through a first via hole; A fifth conductive portion is connected to the first initial signal line through a tenth via hole, and the fifth conductive portion is also connected to the first electrode of the first transistor through a second via hole. The positive projection of the fifth conductive portion in the pixel driving circuit of this row on the substrate is located on a side away from the positive projection of the second initial signal line in the pixel driving circuit of the adjacent previous row on the substrate substrate.

5. The display panel according to claim 4, characterized in that: The pixel driving circuit further includes a first transistor, a fifth transistor and a sixth transistor, wherein a first electrode of the first transistor is connected to the first initial signal line, a second electrode is connected to the gate electrode of the driving transistor, a first electrode of the fifth transistor is connected to the second electrode of the driving transistor, a first electrode of the sixth transistor is connected to the first electrode of the driving transistor, and a second electrode is connected to the anode electrode of the light emitting device; The display panel further includes: An active layer is located between the substrate and the first conductive layer, and the active layer includes: a third active portion, used to form a channel region of the driving transistor; a fifth active portion, used to form a channel region of the fifth transistor; a sixth active portion, used to form a channel region of the sixth transistor; a fourteenth active portion connected between the sixth active portion and the third active portion; an eighth active portion connected to a side of the sixth active portion away from the fourteenth active portion, the eighth active portion comprising a seventh sub-active portion and an eighth sub-active portion, the seventh sub-active portion being connected to the sixth active portion and extending in a column direction on an orthographic projection of the substrate, the eighth sub-active portion being connected to the seventh sub-active portion and extending in a row direction on an orthographic projection of the substrate, and an end of the eighth sub-active portion away from the seventh sub-active portion being connected to the third connecting portion through the first via hole; a first active portion, comprising a first sub-active portion, a second sub-active portion, a third sub-active portion and a ninth sub-active portion, wherein the first sub-active portion is used to form a first channel region of the first transistor, the third sub-active portion is used to form a second channel region of the first transistor, the third sub-active portion is connected between the first sub-active portion and the third sub-active portion, the ninth sub-active portion is connected to a side of the first sub-active portion away from the third sub-active portion, and the ninth sub-active portion is connected to the fifth conductive portion through the second via hole; There is a first distance between the fifth active portion and the sixth active portion, the eighth sub-active portion has a first extension length, and a ratio of the first extension length to the first distance is greater than or equal to 1 / 4 and less than or equal to 1 / 2; In the same column of pixel driving circuits, the orthographic projection of the fifth conductive portion on the substrate and the orthographic projection of the third connecting portion on the substrate are both located on the same side of the orthographic projection of the third initial signal line on the substrate, and in two pixel driving circuits located in adjacent rows of the same column, a line segment connecting the tenth via and the first via has a first angle between the orthographic projection of the substrate and the orthographic projection of the fifth conductive portion on the substrate, and the first angle is greater than or equal to 175° and less than or equal to 180°.

6. The display panel according to claim 5, characterized in that: The active layer further comprises: a tenth active portion connected to a side of the second sub-active portion away from the third sub-active portion, the tenth active portion being connected to the second conductive portion through a third via hole; The orthographic projection of the fifth conductive portion on the substrate extends along the second direction, and in the same column of pixel driving circuits, the orthographic projection of the fifth conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate are both located on the same side of the orthographic projection of the third initial signal line on the substrate; in the same pixel driving circuit, a line segment connecting the third via hole and the second via hole has a second angle between the orthographic projection of the substrate and the orthographic projection of the second conductive portion on the substrate, and the second angle is greater than or equal to 175° and less than or equal to 180°.

7. The display panel according to claim 3, characterized in that: The pixel driving circuit further comprises a sixth transistor, a first electrode of the sixth transistor is connected to the first electrode of the driving transistor, a second electrode is connected to the light emitting device, and a gate is connected to an enable signal line; The first conductive layer further comprises: The enable signal line, an orthographic projection of which on the substrate extends along a first direction, and a partial structure of the enable signal line is used to form a gate of the sixth transistor; The first reset signal line, whose orthographic projection on the base substrate extends along the first direction and is located on a side where the orthographic projection of the first conductive portion on the base substrate is away from the orthographic projection of the enable signal line on the base substrate, and a partial structure of the first reset signal line is used to form a gate of the first transistor; The second reset signal line, whose orthographic projection on the base substrate extends along the first direction and is located on a side where the orthographic projection of the enable signal line on the base substrate is away from the orthographic projection of the first conductive portion on the base substrate, and a partial structure of the second reset signal line is used to form the gate of the seventh transistor; The second reset signal line in the pixel driving circuit of the current row is multiplexed as the first reset signal line in the pixel driving circuit of the next row; The orthographic projection of the second initial signal line in the pixel driving circuit of this row on the substrate and the orthographic projection of the first initial signal line in the pixel driving circuit of the adjacent next row on the substrate are located between the orthographic projection of the enable signal line in the pixel driving circuit of this row on the substrate and the orthographic projection of the second reset signal line on the substrate.

8. The display panel according to claim 5, characterized in that: The third conductive layer further comprises: A first power line, the orthographic projection of which on the base substrate extends along the second direction; The third initial signal line has a second distance from the first power line in the first direction, and a ratio of the second distance to the first distance is greater than or equal to 0.8 and less than or equal to 1.

2.

9. The display panel according to claim 5, characterized in that: The third conductive layer further comprises: A first power line, the orthographic projection of which on the base substrate extends along the second direction; The third initial signal line has a third distance from the second conductive portion in the first direction, and a ratio of the third distance to the first distance is greater than or equal to 1 / 3 and less than or equal to 1 / 2.

10. The display panel according to claim 1, characterized in that: The third initial signal line includes a first extension portion, a second extension portion and a third extension portion, the second extension portion is connected between the first extension portion and the third extension portion, and there is a third angle between the second extension portion and the first extension portion, and between the second extension portion and the third extension portion, and the third angle is greater than or equal to 90° and less than or equal to 180°.

11. The display panel according to claim 10, characterized in that: The gate of the second transistor is connected to the first scanning signal line, and the pixel driving circuit further comprises a sixth transistor, a first electrode of the sixth transistor is connected to the first electrode of the driving transistor, and a gate is connected to the enable signal line; The display panel further includes: An active layer is located between the substrate and the first conductive layer, and the active layer includes: a second active portion, comprising a fourth sub-active portion, a fifth sub-active portion and a sixth sub-active portion connected in sequence, the fourth sub-active portion being used to form a first channel region of the second transistor, and the sixth sub-active portion being used to form a second channel region of the second transistor; a sixth active portion, used to form a channel region of the sixth transistor; A fourteenth active portion, the orthographic projection of which on the base substrate extends along the column direction and is connected between the fourth sub-active portion and the sixth active portion; The first conductive layer further comprises: The first scanning signal line, an orthographic projection of the substrate extending along the first direction, and a partial structure of the first scanning signal line is used to form a gate of the second transistor; The enable signal line extends along the first direction when projected on the base substrate, and covers the sixth active portion when projected on the base substrate, and a partial structure of the enable signal line is used to form a gate of the sixth transistor; The orthographic projections of the first extension portion and the third extension portion on the substrate are located on a side of the orthographic projection of the fourteenth active portion on the substrate that faces the orthographic projection of the first conductive portion on the substrate, and the distance between the orthographic projection of the first extension portion on the substrate and the orthographic projection of the first conductive portion on the substrate in the first direction is greater than the distance between the orthographic projection of the second extension portion or the third extension portion on the substrate and the orthographic projection of the first conductive portion on the substrate in the first direction.

12. The display panel according to claim 1, characterized in that: The first direction is a row direction, the second direction is a column direction, the display panel includes a first pixel driving circuit column and a second pixel driving circuit column sequentially spaced in the row direction, and the third initial signal line is located in the first pixel driving circuit column.

13. The display panel according to claim 1, characterized in that: The pixel driving circuit comprises a first transistor, a first electrode of the first transistor is connected to the first initial signal line, a second electrode is connected to the gate of the driving transistor, and the gate is connected to the first reset signal line; The display panel further includes: An active layer is located between the substrate and the first conductive layer, and the active layer includes: a first active portion, comprising a first sub-active portion, a second sub-active portion and a third sub-active portion connected in sequence, wherein the first sub-active portion is used to form a first channel region of the first transistor, and the third sub-active portion is used to form a second channel region of the first transistor; The display panel further includes: A first conductive layer is located between the active layer and the second conductive layer, and the first conductive layer includes: The orthographic projection of the first reset signal line on the substrate extends along the row direction, the orthographic projection of the first reset signal line on the substrate is located between the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the first initial signal line on the substrate, the orthographic projection of the first reset signal line on the substrate covers the orthographic projection of the first sub-active portion on the substrate and the orthographic projection of the third sub-active portion on the substrate, and a partial structure of the first reset signal line is used to form the gate of the first transistor; The orthographic projection of the first initial signal line on the base substrate covers the orthographic projection of the second sub-active portion on the base substrate.

14. The display panel according to claim 13, characterized in that: A width of the first initial signal line in the second direction is greater than a width of the first initial signal line in the second direction.

15. The display panel according to claim 5, characterized in that: The display panel further includes: A fourth conductive layer is located on a side of the third conductive layer away from the substrate, and the fourth conductive layer includes: A second power line, the orthographic projection of which on the base substrate extends along the second direction; an anode flat portion connected to the second power line; an anode connecting portion, separated from the anode flat portion and connected to the third connecting portion through a via hole; The pixel defining layer is located on a side of the fourth conductive layer away from the base substrate, and includes a plurality of pixel openings, wherein the orthographic projections of the pixel openings on the base substrate are located on the orthographic projections of the anode flat portion on the base substrate.

16. The display panel according to claim 15, characterized in that: The first direction is a row direction, the second direction is a column direction, and the display panel includes a first pixel driving circuit column and a second pixel driving circuit column sequentially spaced in the row direction; An extension length of an orthographic projection of the third connection portion in the first pixel driving circuit column on the base substrate is different from an extension length of an orthographic projection of the third connection portion in the second pixel driving circuit column on the base substrate.

17. The display panel according to claim 16, characterized in that: An extension length of an orthographic projection of the third connection portion in the first pixel driving circuit column on the substrate is smaller than an extension length of an orthographic projection of the third connection portion in the second pixel driving circuit column on the substrate; The third connection portion includes a first via contact portion and a second via contact portion, the first via contact portion is connected to the second electrode of the seventh transistor through the first via hole, and the second via contact portion is connected to the anode connection portion through a via hole; In the second pixel driving circuit column, the orthographic projection of the second via contact portion on the base substrate is located on the side of the orthographic projection of the first via contact portion on the base substrate facing the orthographic projection of the second conductive portion on the base substrate, and the distance between the orthographic projection of the second via contact portion on the base substrate and the orthographic projection of the second conductive portion on the base substrate in the first direction is greater than the distance between the orthographic projection of the first via contact portion on the base substrate and the orthographic projection of the second conductive portion on the base substrate in the first direction.

18. The display panel according to claim 17, characterized in that: The orthographic projections of the first via contact portion and the second via contact portion located in the first pixel driving column on the base substrate overlap with the orthographic projection of the second initial signal line on the base substrate; The orthographic projections of the first via contact portion and the second via contact portion located in the second pixel driving circuit column on the base substrate do not overlap with the orthographic projection of the second initial signal line on the base substrate, and the orthographic projection of the second via contact portion on the base substrate partially overlaps with the orthographic projection of the third conductive portion in the same pixel driving circuit on the base substrate.

19. A display device, characterized in that: A display panel comprising any one of claims 1-18.

Images