Drive control circuit and drive control method
By introducing a PMOS switch and a discharge regulation module into the NMOS power transistor drive control circuit, different discharge paths are used to discharge the gate parasitic capacitance in stages when the PWM signal changes, which solves the problems of electromagnetic interference and overvoltage breakdown and reduces conduction loss.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI NATLINEAR ELECTRONICS CO LTD
- Filing Date
- 2022-01-17
- Publication Date
- 2026-06-23
Smart Images
Figure CN114400876B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design and application, and in particular to a drive control circuit and drive control method. Background Technology
[0002] NMOS power transistors are widely used in various switching power supply circuits due to their high reliability and cost-effectiveness. However, if the drain voltage of an NMOS power transistor changes drastically during operation, it will generate electromagnetic interference (EMI).
[0003] Figure 1 This is an existing NMOS power transistor drive control circuit. The NMOS power transistor drive control circuit adopts a totem pole structure, wherein the PMOS switch PM10 is the upper drive transistor and the NMOS switch NM11 is the lower drive transistor. Specifically, the source of the PMOS switch PM10 is connected to the power supply voltage VDD, the gate is connected to the PWM signal, and the drain is connected to the gate of the NMOS power transistor NM10; the gate of the NMOS switch NM11 is connected to the PWM signal, the drain is connected to the gate of the NMOS power transistor NM10, and the source is grounded.
[0004] The gate parasitic capacitance of the NMOS power transistor NM10 includes the parasitic capacitance Cgd between its gate and drain and the parasitic capacitance Cgs between its gate and source. When the PWM signal changes from high to low, the PMOS switch PM10 changes from off to on, charging the gate parasitic capacitance of the NMOS power transistor NM10 with maximum current, thus turning on the NMOS power transistor NM10. When the PWM signal changes from low to high, the NMOS switch NM11 changes from off to on, discharging the gate parasitic capacitance of the NMOS power transistor NM10 with maximum current, thus turning off the NMOS power transistor NM10.
[0005] like Figure 2 As shown, after the NMOS switch NM11 is turned on, it discharges the gate parasitic capacitance of the NMOS power transistor NM10, causing the gate voltage of the NMOS power transistor NM10 to go through four changing stages, thereby turning off the NMOS power transistor NM10. These four changing stages are: the first changing stage Ta0-Ta1, the second changing stage Ta1-Ta2, the third changing stage Ta2-Ta3, and the fourth changing stage Ta3-Ta4. The duration t of the first changing stage Ta0-Ta1, the second changing stage Ta1-Ta2, and the third changing stage Ta2-Ta3 is... Ta0-Ta1 tTa1-Ta2 t Ta2-Ta3 They are respectively:
[0006]
[0007]
[0008]
[0009] Among them, R NM11 g is the on-resistance when the NMOS switch NM11 is turned on. NM10 Vthn10 is the transconductance of the NMOS power transistor NM10 during the Miller platform stage, Ids-max is the maximum drain current of the NMOS power transistor NM10, and Vsw is the drain voltage of the NMOS power transistor NM10 before it is turned off.
[0010] Because the shorter the time the gate voltage of the NMOS power transistor NM10 is in the Miller plateau phase, the greater its drain voltage rise rate dv / dt, resulting in stronger electromagnetic interference (EMI) signals and larger overshoot amplitudes. Larger overshoot amplitudes can lead to overvoltage breakdown of the NMOS power transistor. Therefore, to improve the EMI and overvoltage breakdown problems of the NMOS power transistor drive control circuit, the commonly used method is to increase the on-resistance of the NMOS switch. However, as shown in the above formula, increasing the on-resistance of the NMOS switch will increase the duration t of the first change phase Ta0-Ta1 and the third change phase Ta2-Ta3. Ta0-Ta1 t Ta2-Ta3 It will also increase accordingly, and t Ta0-Ta1 and t Ta2-Ta3 The increase in resistance increases the conduction loss and heat generation of the NMOS power transistor, which in turn leads to thermal breakdown of the NMOS power transistor. Therefore, when using the above-mentioned NMOS power transistor drive control circuit, it is difficult to select an NMOS switch with a suitable on-resistance value, which leads to electromagnetic interference and overvoltage breakdown problems in the NMOS power transistor drive control circuit, thereby degrading the performance of the system. Summary of the Invention
[0011] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a drive control circuit and drive control method to improve the electromagnetic interference problem and overvoltage breakdown problem existing in the prior art.
[0012] To achieve the above and other related objectives, the present invention provides a drive control circuit for driving and controlling an NMOS power transistor with gate parasitic capacitance. The drive control circuit includes a PMOS switch and a discharge regulation module.
[0013] The gate of the PMOS switch is connected to a PWM signal, the source is connected to a power supply voltage, and the drain is connected to the gate of the NMOS power transistor.
[0014] The discharge regulation module is connected between the gate and ground of the NMOS power transistor and is controlled by the PWM signal. When the PWM signal changes from low level to high level, it follows the gate voltage change of the NMOS power transistor and discharges the gate parasitic capacitance of the NMOS power transistor in stages based on different discharge paths.
[0015] Optionally, the discharge regulation module includes: a first discharge regulation unit, a second discharge regulation unit, and a third discharge regulation unit, all connected between the gate of the NMOS power transistor and ground, and controlled by the PWM signal, wherein...
[0016] The first discharge regulation unit is used to form a discharge path from the gate parasitic capacitance of the NMOS power transistor to ground during the first change phase of the gate voltage of the NMOS power transistor.
[0017] The second discharge regulation unit is used to form a discharge path from the gate parasitic capacitance of the NMOS power transistor to ground during the first to sixth changes of the gate voltage of the NMOS power transistor.
[0018] The third discharge regulation unit is used to form a discharge path from the gate parasitic capacitance of the NMOS power transistor to ground during the fifth and sixth changes of the gate voltage of the NMOS power transistor.
[0019] Optionally, the first discharge regulation unit includes: a first NMOS transistor and a driving section, wherein,
[0020] The gate of the first NMOS transistor is connected to the output terminal of the driving section, the drain is connected to the gate of the NMOS power transistor, and the source is grounded.
[0021] The driving section is connected between the gate of the NMOS power transistor and ground, and is controlled by the PWM signal. It is used to generate and output a driving signal during the first change phase of the gate voltage of the NMOS power transistor to control the first NMOS transistor to turn on.
[0022] Optionally, the configuration includes a second NMOS transistor, a first PMOS transistor, a third PMOS transistor, and a first resistor; wherein the gate of the second NMOS transistor is connected to the PWM signal, its drain is connected to the drain and gate of the first PMOS transistor, and its source is grounded; the source of the first PMOS transistor is connected to the drain and gate of the second PMOS transistor; the source of the second PMOS transistor is connected to the gate of the NMOS power transistor, and its gate is connected to the gate of the third PMOS transistor; the source of the third PMOS transistor is connected to the gate of the NMOS power transistor, and its drain is grounded through the first resistor, serving as the output terminal of the driving section.
[0023] Optionally, the second discharge regulation unit includes a third NMOS transistor and a current-limiting resistor; wherein the gate of the third NMOS transistor is connected to the PWM signal, the drain is connected to the gate of the NMOS power transistor, and the source is grounded through the current-limiting resistor.
[0024] Optionally, the third discharge regulation unit includes: a control section and a discharge section, wherein,
[0025] The control section is connected between the power supply voltage and ground, and is controlled by the gate voltage of the NMOS power transistor. It is used to generate and output effective control signals during the fifth and sixth changes of the gate voltage of the NMOS power transistor.
[0026] The discharge section is connected between the gate of the NMOS power transistor and ground, and is controlled by the PWM signal and the control signal. When the control signal is valid, it is used to form a discharge path from the gate parasitic capacitance of the NMOS power transistor to ground.
[0027] Optionally, the control section includes: a fourth NMOS transistor, a first transistor, and a second resistor; wherein the gate of the fourth NMOS transistor is connected to the gate of the NMOS power transistor, the drain is connected to the power supply voltage through the second resistor and outputs a control signal, and the source is connected to the base of the first transistor; the collector of the first transistor is connected to the drain of the fourth NMOS transistor, and the emitter is grounded.
[0028] Optionally, the discharge section includes a fifth NMOS transistor and a sixth NMOS transistor; wherein the gate of the fifth NMOS transistor is connected to the control signal, the drain is connected to the gate of the NMOS power transistor, and the source is connected to the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor is connected to the PWM signal, and the source is grounded.
[0029] Optionally, when the second discharge unit includes the third NMOS transistor and the current-limiting resistor, the sum of the on-resistance of the fifth NMOS transistor and the on-resistance of the sixth NMOS transistor is less than the sum of the on-resistance of the third NMOS transistor and the resistance of the current-limiting resistor.
[0030] The present invention also provides a driving control method for driving and controlling an NMOS power transistor with gate parasitic capacitance, the driving control method comprising:
[0031] When the PWM signal changes from high level to low level, the gate parasitic capacitance of the NMOS power transistor is charged to the power supply voltage, and the NMOS power transistor changes from the off state to the on state.
[0032] When the PWM signal changes from low level to high level, it follows the gate voltage change of the NMOS power transistor and discharges the gate parasitic capacitance of the NMOS power transistor in stages based on different discharge paths, so that the NMOS power transistor changes from the on state to the off state.
[0033] Optionally, the gate parasitic capacitance of the NMOS power transistor is discharged in stages based on three different discharge paths, specifically including:
[0034] During the first change phase of the gate voltage of the NMOS power transistor, the gate parasitic capacitance of the NMOS power transistor is discharged based on the first discharge path and the second discharge path.
[0035] During the second, third, and fourth stages of the gate voltage change of the NMOS power transistor, the gate parasitic capacitance of the NMOS power transistor is discharged based on the second discharge path.
[0036] During the fifth and sixth stages of the gate voltage change of the NMOS power transistor, the gate parasitic capacitance of the NMOS power transistor is discharged based on the second and third discharge paths.
[0037] As described above, the drive control circuit and drive control method of the present invention have the following beneficial effects: the drive control circuit of the present invention can improve the overvoltage breakdown problem of the drain voltage and the electromagnetic interference problem of the NMOS power transistor by increasing the duration of the Miller plateau stage during the turn-off process of the NMOS power transistor; at the same time, it can also reduce the gate voltage drop time during the turn-off process of the NMOS power transistor, thereby reducing the conduction loss. Attached Figure Description
[0038] Figure 1 The diagram shows a schematic of an existing NMOS power transistor drive control circuit.
[0039] Figure 2This diagram illustrates the waveform changes of drain current, drain voltage, and gate voltage during the discharge process of an existing NMOS power transistor.
[0040] Figure 3 The diagram shown is a schematic of the drive control circuit of the present invention.
[0041] Figure 4 The diagram shows the waveform changes of drain current, drain voltage, and gate voltage during the discharge process of the NMOS power transistor of this invention.
[0042] Component designation explanation
[0043] 1. Discharge Regulation Module
[0044] 11 First Discharge Regulation Unit
[0045] 111 Driver Section
[0046] 12 Second Discharge Regulation Unit
[0047] 13 Third Discharge Regulation Unit
[0048] 131 Control Section
[0049] 132 Discharge Section Detailed Implementation
[0050] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0051] Please see Figures 3-4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0052] like Figure 3 As shown, this embodiment provides a drive control circuit for driving and controlling an NMOS power transistor NM20 with gate parasitic capacitance. The drive control circuit includes a PMOS switch PM20 and a discharge regulation module 1.
[0053] The gate parasitic capacitance of the NMOS power transistor NM20 includes the parasitic capacitance Cgd between the gate and drain of the NMOS power transistor NM20 and the parasitic capacitance Cgs between the gate and source of the NMOS power transistor NM20. In this embodiment, the drive control circuit enables the NMOS power transistor NM20 to be turned on and off by charging and discharging the gate parasitic capacitance of the NMOS power transistor NM20.
[0054] The gate of the PMOS switch PM20 is connected to a PWM signal, the source is connected to the power supply voltage VDD, and the drain is connected to the gate of the NMOS power transistor NM20. In this embodiment, when the PWM signal changes from a high level to a low level, the PMOS switch PM20 turns on, charging the gate parasitic capacitance of the NMOS power transistor NM20 to the power supply voltage VDD, thus turning on the NMOS power transistor NM20.
[0055] The discharge regulation module 1 is connected between the gate and ground of the NMOS power transistor NM20 and is controlled by the PWM signal. When the PWM signal changes from low level to high level, it follows the gate voltage change of the NMOS power transistor NM20 and discharges the gate parasitic capacitance of the NMOS power transistor NM20 in stages based on different discharge paths, so that the NMOS power transistor NM20 is turned off.
[0056] Specifically, the discharge regulation module 1 includes a first discharge regulation unit 11, a second discharge regulation unit 12, and a third discharge regulation unit 13, all of which are connected between the gate of the NMOS power transistor NM20 and ground, and are controlled by the PWM signal.
[0057] The first discharge regulation unit 11 is used to regulate the gate voltage V of the NMOS power transistor NM20. GATE In the first stage of change, a discharge path is formed from the gate parasitic capacitance of the NMOS power transistor NM20 to ground.
[0058] More specifically, the first discharge regulation unit includes a first NMOS transistor NM21 and a driving section 111, wherein the gate of the first NMOS transistor NM21 is connected to the output terminal of the driving section 111, the drain is connected to the gate of the NMOS power transistor NM20, and the source is grounded; the driving section 111 is connected between the gate of the NMOS power transistor NM20 and ground, and is controlled by the PWM signal, for generating and outputting a driving signal during the first change phase of the gate voltage of the NMOS power transistor NM20, so as to control the first NMOS transistor NM21 to be turned on.
[0059] As an example, the driving section 111 includes a second NMOS transistor NM22, a first PMOS transistor PM21, a third PMOS transistor PM23, and a first resistor R21; wherein, the gate of the second NMOS transistor NM22 is connected to the PWM signal, the drain is connected to the drain and gate of the first PMOS transistor PM11, and the source is grounded; the source of the first PMOS transistor PM21 is connected to the drain and gate of the second PMOS transistor PM22; the source of the second PMOS transistor PM22 is connected to the gate of the NMOS power transistor NM20, and the gate is connected to the gate of the third PMOS transistor PM23; the source of the third PMOS transistor is connected to the gate of the NMOS power transistor NM20, and the drain is grounded through the first resistor R21, and serves as the output terminal of the driving section 111.
[0060] In this embodiment, when the PWM signal changes from low level to high level, the second NMOS transistor NM22 is turned on, and the gate voltage V of the NMOS power transistor NM20 is... GATE When Vthp1 > (Vthp2), the first PMOS transistor PM21 and the second PMOS transistor PM22 are turned on. The second PMOS transistor PM22 generates a drain current. Since the second PMOS transistor PM22 and the third PMOS transistor PM23 form a current mirror, the drain current of the third PMOS transistor PM23 is proportional to the drain current of the second PMOS transistor PM22. Therefore, the third PMOS transistor PM23 generates a drain current. The drain current of the third PMOS transistor PM23 passes through the first resistor R21, causing the gate voltage of the first NMOS transistor NM21 to be higher than its threshold voltage (that is, the third PMOS transistor PM23 generates an effective drive signal). The first NMOS transistor NM21 is turned on, thereby discharging the gate parasitic capacitance of the NMOS power transistor NM20 through the first NMOS transistor NM21. This discharge continues until the gate voltage Vthp1 + Vthp2 of the NMOS power transistor NM20 is reached. GATE <(Vthp1+Vthp2), at this time, the first PMOS transistor PM21 and the second PMOS transistor PM22 are turned off, the drain current of the third PMOS transistor PM23 decreases to 0, the gate voltage of the first NMOS transistor NM21 drops to 0 (that is, the drive signal generated by the third PMOS transistor PM23 is invalid), and the first NMOS transistor NM21 is turned off. Since only when the gate voltage V of the NMOS power transistor NM20 is <(Vthp1+Vthp2), GATE In the first change phase, the gate voltage V of the NMOS power transistor NM20 GATE>(Vthp1+Vthp2), therefore, the first NMOS transistor NM21 only operates when the gate voltage V of the NMOS power transistor NM20 is... GATE The first change stage discharges the gate parasitic capacitance of the NMOS power transistor NM20. Here, Vthp1 is the threshold voltage of the first PMOS transistor PM21, and Vthp2 is the threshold voltage of the second PMOS transistor. Optionally, the threshold voltages of the first PMOS transistor PM21 and the second PMOS transistor PM22 are the same, both being Vthp. In this case, V... GATE >(Vthp1+Vthp2) can be represented as V GATE >2*Vthp, V GATE <(Vthp1+Vthp2) can be represented as V GATE <2*Vthp. It should be noted that the gate voltage V of the NMOS power transistor NM20 is... GATE In the first stage of change, in addition to the first NMOS transistor NM21 discharging the gate parasitic capacitance of the NMOS power transistor NM20, the branch containing the second NMOS transistor NM22 also discharges the gate parasitic capacitance of the NMOS power transistor NM20. Since the branch containing the second NMOS transistor NM22 includes both the first PMOS transistor PM21 and the second PMOS transistor PM22, the discharge current of this branch is very small. Therefore, the drain current of the second NMOS transistor NM22 is negligible compared to the drain current of the first NMOS transistor NM21.
[0061] The second discharge regulation unit 12 is used to regulate the gate voltage V of the NMOS power transistor NM20. GATE From the first change stage to the sixth change stage, a discharge path is formed from the gate parasitic capacitance of the NMOS power transistor NM20 to ground.
[0062] More specifically, the second discharge regulation unit 12 includes: a third NMOS transistor NM23 and a current-limiting resistor Rc; wherein, the gate of the third NMOS transistor NM23 is connected to the PWM signal, the drain is connected to the gate of the NMOS power transistor NM20, and the source is grounded through the current-limiting resistor Rc.
[0063] In this embodiment, when the PWM signal changes from low to high, the third NMOS transistor NM23 is turned on, discharging the gate parasitic capacitance of the NMOS power transistor NM20; due to the gate voltage V of the NMOS power transistor NM20... GATE From the first to the sixth change phase, the PWM signal remains high. Therefore, the third NMOS transistor NM23 operates at the gate voltage V of the NMOS power transistor NM20. GATEIn all six stages of the change process, the transistor is turned on and discharges the gate parasitic capacitance of the NMOS power transistor NM20. Furthermore, since the source of the third NMOS transistor NM23 is connected to a current-limiting resistor Rc, the drain current of the third NMOS transistor NM23 is limited by the current-limiting resistor Rc. Therefore, the gate voltage V of the NMOS power transistor NM20... GATE In the first stage of change, when the on-resistance of the first NMOS transistor NM21 is much smaller than that of the third NMOS transistor, the drain current of the third NMOS transistor NM23 can be ignored compared with the drain current of the first NMOS transistor NM21.
[0064] The third discharge regulation unit 13 is used to adjust the gate voltage V of the NMOS power transistor NM20. GATE The fifth and sixth change stages form a discharge path from the gate parasitic capacitance of the NMOS power transistor NM20 to ground.
[0065] More specifically, the third discharge regulation unit 13 includes a control section 131 and a discharge section 132, wherein the control section 131 is connected between the power supply voltage VDD and ground, and is controlled by the gate voltage V of the NMOS power transistor NM20. GATE Used to measure the gate voltage V of the NMOS power transistor NM20 GATE In the fifth and sixth change stages, a valid control signal is generated and output; the discharge section 132 is connected between the gate and ground of the NMOS power transistor NM20 and is controlled by the PWM signal and the control signal, and is used to form a discharge path from the gate parasitic capacitance of the NMOS power transistor NM20 to ground when the control signal is valid.
[0066] As an example, the control section 131 includes: a fourth NMOS transistor NM24, a first transistor Q21, and a second resistor R22; wherein, the gate of the fourth NMOS transistor NM24 is connected to the gate of the NMOS power transistor NM20, the drain is connected to the power supply voltage VDD through the second resistor R22 and outputs a control signal, and the source is connected to the base of the first transistor Q21; the collector of the first transistor Q21 is connected to the drain of the fourth NMOS transistor NM24, and the emitter is grounded. The discharge section 132 includes: a fifth NMOS transistor NM25 and a sixth NMOS transistor NM26; wherein, the gate of the fifth NMOS transistor NM25 is connected to the control signal, the drain is connected to the gate of the NMOS power transistor NM20, and the source is connected to the drain of the sixth NMOS transistor NM26; the gate of the sixth NMOS transistor NM26 is connected to the PWM signal, and the source of the sixth NMOS transistor NM26 is grounded.
[0067] In this embodiment, when the gate voltage V of the NMOS power transistor NM20 GATE When Vthn4 > (Vthn4 + Vbe1), the fourth NMOS transistor NM24 and the first transistor Q21 are turned on, where Vthn4 is the threshold voltage of the fourth NMOS transistor NM24 and Vbe1 is the voltage difference between the base and emitter of the first transistor Q21. When the fourth NMOS transistor NM24 and the first transistor Q21 are turned on, the gate voltage of the fifth NMOS transistor NM25 is pulled down to ground (the control signal generated by the fourth NMOS transistor NM24 is invalid), causing the fifth NMOS transistor NM25 to turn off, and the third discharge unit 13 cannot form a discharge path; when the gate voltage V of the NMOS power transistor NM20 is... GATE When V<(Vthn4+Vbe1), the fourth NMOS transistor NM24 and the transistor Q21 are both off. The gate voltage of the fifth NMOS transistor NM25 is pulled up to VDD by the second resistor R22 (the fourth NMOS transistor NM24 generates the effective control signal), and the fifth NMOS transistor NM25 is turned on. At this time, if the PWM signal is high, the sixth NMOS transistor NM26 is turned on. The fifth NMOS transistor NM25 and the sixth NMOS transistor NM26 discharge the parasitic gate capacitance of the power transistor NM20. Because the gate voltage Vthn4+Vbe1 of the NMOS power transistor NM20 is Vthn4+Vbe1... GATE In the fifth and sixth change stages, the control section 131 generates valid control signals, therefore, the fifth NMOS transistor and the sixth NMOS transistor are in the NMOS power transistor NM20 gate voltage V GATE The fifth and sixth change stages discharge the gate capacitance of the NMOS power transistor NM20.
[0068] Furthermore, when the second discharge unit 12 includes the third NMOS transistor NM23 and a current-limiting resistor, the sum of the on-resistance of the fifth NMOS transistor NM25 and the on-resistance of the sixth NMOS transistor NM26 is less than the sum of the on-resistance of the third NMOS transistor NM23 and the resistance of the current-limiting resistor Rc. In this embodiment, the on-resistances of the fifth NMOS transistor NM25 and the sixth NMOS transistor NM26 are designed to be very small, so that the sum of the on-resistances of the fifth NMOS transistor NM25 and the sixth NMOS transistor NM26 is much smaller than the sum of the resistance of the third NMOS transistor NM23 and the current-limiting resistor Rc. Therefore, the drain current flowing through the third NMOS transistor NM23 is negligible compared to the drain current flowing through the fifth NMOS transistor NM25 and the sixth NMOS transistor NM26.
[0069] Accordingly, this embodiment also provides a driving control method for driving and controlling an NMOS power transistor NM20 with gate parasitic capacitance, the driving control method comprising:
[0070] 1) When the PWM signal changes from high level to low level, the gate parasitic capacitance of the NMOS power transistor NM20 is charged to the power supply voltage VDD, and the NMOS power transistor NM20 changes from the off state to the on state.
[0071] In this embodiment, the above-mentioned drive control circuit is used to charge and discharge the gate parasitic capacitance of the NMOS power transistor NM20. When the PWM signal changes from high level to low level, the PMOS switch PM20 is turned on, so that the gate parasitic capacitance of the NMOS power transistor NM20 is charged to the power supply voltage VDD, and the NMOS power transistor NM20 is turned on.
[0072] 2) When the PWM signal changes from low level to high level, following the gate voltage change of the NMOS power transistor NM20, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged in stages based on different discharge paths, and the NMOS power transistor NM20 changes from the on state to the off state.
[0073] Specifically, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged in stages based on three different discharge paths (first discharge path, second discharge path, and third discharge path). Figure 4 As shown), specifically:
[0074] 21) At the gate voltage V of the NMOS power transistor NM20 GATE In the first change stage, the gate parasitic capacitance of the NMOS power transistor is discharged based on the first discharge path and the second discharge path.
[0075] The gate voltage V of the NMOS power transistor NM20 GATE During the first change phase Tb0 to Tb1, the gate voltage V of the NMOS power transistor NM20... GATE The voltage drops from VDD to (VDD-2*Vthp), where Vthp is the threshold voltage of the first PMOS transistor PM21 and the second PMOS transistor PM22. During this first change phase, the gate voltage V of the NMOS power transistor NM20 decreases. GATE >2*Vthp, and V GATE >Vthn3,V GATE>(Vthn4+Vbe1), where Vthn3 is the threshold voltage of the third NMOS transistor NM23, Vthn4 is the threshold voltage of the fourth NMOS transistor NM24, and Vbe1 is the voltage difference between the base and emitter of the first transistor Q21. Therefore, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged through the first discharge path formed by the first discharge adjustment unit 11 and the second discharge path formed by the second discharge adjustment unit 12. That is, the parasitic capacitance of the NMOS power transistor NM20 is discharged through the branch where the first NMOS transistor NM21 is located, the branch where the second NMOS transistor NM22 is located, and the branch where the third NMOS transistor NM23 is located. Since the drain current of the third NMOS transistor NM23 is negligible compared to the drain current of the first NMOS transistor NM21, and the drain current of the second NMOS transistor NM22 is also negligible compared to the drain current of the first NMOS transistor, it is equivalent to discharging the parasitic capacitance of the NMOS power transistor NM20 only through the branch containing the first NMOS transistor NM21. At this time, the duration t of the first change phase Tb0~Tb1... Tb0-Tb1 The following formula can be used for estimation:
[0076]
[0077] Among them, R NM21 Vthp is the on-resistance of the first NMOS transistor NM21, the threshold voltage of the first PMOS transistor PM21 and the second PMOS transistor PM22, Cgs is the parasitic capacitance between the gate and source of the NMOS power transistor NM20, Cgd is the parasitic capacitance between the gate and drain of the NMOS power transistor NM20, and VDD is the power supply voltage.
[0078] 22) At the gate voltage V of the NMOS power transistor NM20 GATE In the second stage of change, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged based on the second discharge path.
[0079] The gate voltage V of the NMOS power transistor NM20 GATE In the second change phase Tb1~Tb2, the gate voltage V of the NMOS power transistor NM20... GATE The voltage drops from (VDD-2*Vthp) to the Miller plateau voltage Vmiller. During this second change phase, the gate voltage V of the NMOS power transistor NM20... GATE <2*Vthp, and V GATE>(Vthn4+Vbe1), where Vthp is the threshold voltage of the first PMOS transistor PM21 and the second PMOS transistor PM22, Vthn4 is the threshold voltage of the fourth NMOS transistor NM24, and Vbe1 is the voltage difference between the base and emitter of the first transistor Q21. Therefore, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged through the second discharge path formed by the second discharge adjustment unit 12, that is, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged through the branch where the third NMOS transistor NM23 is located, and the discharge current is determined by the on-resistance of the third NMOS transistor NM23 and the resistance value of the current limiting resistor Rc. The duration t of the second change stage Tb1~Tb2 Tb1-Tb2 The following formula can be used for estimation:
[0080]
[0081] Among them, R NM23 R is the on-resistance of the third NMOS transistor NM23, Vthp is the threshold voltage of the first PMOS transistor PM21 and the second PMOS transistor PM22, and R is the on-resistance of the third NMOS transistor NM23. c Cgs is the resistance value of the current limiting resistor, Cgd is the parasitic capacitance value between the gate and source of the NMOS power transistor NM20, VDD is the power supply voltage value, and Vmiller is the Miller plateau voltage value.
[0082] 23) At the gate voltage V of the NMOS power transistor NM20 GATE In the third stage of change, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged based on the second discharge path.
[0083] The gate voltage V of the NMOS power transistor NM20 GATE The third change phase, Tb2 to Tb3, corresponds to the Miller plateau phase. During this phase, the gate voltage V of the NMOS power transistor NM20... GATE The Miller plateau voltage Vmiller remains essentially constant, and the drain current Ids of the NMOS power transistor NM20 remains essentially constant, while its drain voltage Vsw rises from 0 to its maximum value Vsw-max. During the Miller plateau phase, the discharge path formed is consistent with the second change phase; that is, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged through the second discharge path formed by the second discharge adjustment unit 12, which is also the gate parasitic capacitance of the NMOS power transistor NM20 is discharged through the branch containing the third NMOS transistor NM23. The duration t of the third change phase Tb2~Tb3 is...Tb2-Tb3 The following formula can be used for estimation:
[0084]
[0085] Among them, R NM23 R is the on-resistance value of the third NMOS transistor NM23. c Let g be the resistance value of the current-limiting resistor. NM20 V is the transconductance value of the NMOS power transistor NM20 at the Miller plateau stage, Cgd is the parasitic capacitance value between the gate and drain of the NMOS power transistor NM20, and V SW I is the drain voltage value of the NMOS power transistor NM20 before it is turned off. ds_max V represents the maximum drain current of the NMOS power transistor NM20. miller V is the Miller plateau voltage value. thn20 The threshold voltage of the NMOS power transistor NM20 is given.
[0086] 24) At the gate voltage V of the NMOS power transistor NM20 GATE In the fourth stage of change, the gate parasitic capacitance of the NMOS power transistor is discharged based on the second discharge path.
[0087] The gate voltage V of the NMOS power transistor NM20 GATE In the fourth change phase Tb3~Tb4, the gate voltage V of the NMOS power transistor NM20 is... GATE As the Miller plateau voltage Vmiller decreases to (Vthn4 + Vbe1), the drain current Ids of the NMOS power transistor NM20 begins to decrease from its maximum current Ids-max, where Vthn4 is the threshold voltage of the fourth NMOS transistor NM24, and Vbe1 is the voltage difference between the base and emitter of the first transistor Q21. During this fourth change phase, the gate voltage V of the NMOS power transistor NM20... GATE >(Vthn4+Vbe1), and V GATE >Vthn3, where Vthn3 is the threshold voltage of the third NMOS transistor NM23. During this stage, the formed discharge path is consistent with the second change stage, that is, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged through the second discharge path formed by the second adjustment unit 12, which is also the gate parasitic capacitance of the NMOS power transistor NM20 is discharged through the branch containing the third NMOS transistor NM23. The duration t of the fourth change stage Tb3~Tb4 Tb3-Tb4 The following formula can be used for estimation:
[0088]
[0089] Among them, R NM23 R is the on-resistance value of the third NMOS transistor NM23. c V is the resistance value of the current-limiting resistor, Cgs is the parasitic capacitance value between the gate and source of the NMOS power transistor NM20, Cgd is the parasitic capacitance value between the gate and drain of the NMOS power transistor NM20, and V miller Vthn4 is the Miller plateau voltage value, Vthn4 is the threshold voltage of the fourth NMOS transistor NM24, and Vthn4 is the threshold voltage of the fourth NMOS transistor NM24. be1 This is the voltage difference between the base and emitter of the transistor Q21.
[0090] 25) At the gate voltage V of the NMOS power transistor NM20 GATE In the fifth stage of change, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged based on the second discharge path and the third discharge path.
[0091] The gate voltage V of the NMOS power transistor NM20 GATE In the fifth change stage Tb4~Tb5, the gate voltage V of the NMOS power transistor NM20 GATE From (Vthn4 + Vbe1) down to the threshold voltage Vthn20 of the NMOS power transistor NM20, the drain current Ids of the NMOS power transistor NM20 drops to 0, where Vthn20 is the threshold voltage of the NMOS power transistor NM20, Vthn4 is the threshold voltage of the fourth NMOS transistor NM24, and Vbe1 is the voltage between the base and emitter of the first transistor Q21. During the fifth change phase, due to the gate voltage V of the NMOS power transistor NM20... GATE >Vthn20, and V GATE >Vthn3,V GATE<(Vthn4+Vbe1), where Vthn3 is the threshold voltage of the third NMOS transistor NM23. Therefore, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged through the second discharge path formed by the second discharge adjustment unit 12 and the third discharge path formed by the third discharge adjustment unit 13, that is, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged through the branch where the third NMOS transistor NM23 is located and the branch where the fifth NMOS transistor NM25 is located. Since the source of the third NMOS transistor NM23 is connected to the current-limiting resistor Rc, the drain current flowing through the third NMOS transistor NM23 is limited. Simultaneously, the sum of the on-resistance of the third NMOS transistor NM23 and the resistance of the current-limiting resistor Rc is much smaller than the sum of the on-resistances of the fifth NMOS transistor NM25 and the sixth NMOS transistor NM26. Therefore, the drain current flowing through the third NMOS transistor NM23 is negligible compared to the current flowing through the fifth NMOS transistor NM25 and the sixth NMOS transistor NM26. Thus, it is equivalent to discharging the gate parasitic capacitance of the NMOS power transistor NM20 only through the branch containing the fifth NMOS transistor NM25. At this time, the duration t of the fifth change phase Tb4~Tb5 is... Tb4-Tb5 The following formula can be used for estimation:
[0092]
[0093] Among them, R NM25 R is the on-resistance of the fifth NMOS transistor NM25. NM26 Cgs is the on-resistance of the sixth NMOS transistor NM26, Cgd is the parasitic capacitance between the gate and source of the NMOS power transistor NM20, Vthn4 is the threshold voltage of the fourth NMOS transistor NM24, and V be1 V is the voltage difference between the base and emitter of transistor Q21. thn20 This is the threshold voltage value of the NMOS power transistor NM20.
[0094] 26) At the gate voltage V of the NMOS power transistor NM20 GATE In the sixth change stage, the gate parasitic capacitance of the NMOS power transistor NM20 is discharged based on the second discharge path and the third discharge path.
[0095] The gate voltage V of the NMOS power transistor NM20 GATE In the sixth change stage Tb5~Tb6, the gate voltage V of the NMOS power transistor NM20 GATE >Vthn3, and V GATE<(Vthn3+Vbe1), where Vthn3 is the threshold voltage of the third NMOS transistor NM23, Vthn4 is the threshold voltage of the fourth NMOS transistor NM24, and Vbe1 is the voltage difference between the base and emitter of the first transistor Q21. The third NMOS transistor NM23, the fifth NMOS transistor NM25, and the sixth NMOS transistor NM26 remain conducting. The second discharge path formed by the second discharge adjustment unit 12 and the third discharge adjustment unit 13, and the third discharge path discharge the gate parasitic capacitance of the NMOS power transistor NM20. The drain current Ids of the NMOS power transistor NM20 remains 0, and its gate voltage V... GATE The threshold voltage Vthn20 drops to 0. This is due to the NMOS power transistor NM20's gate voltage V... GATE As the discharge current gradually decreases to 0, the theoretical time for the Tb5 to Tb6 stage is infinite. However, the NMOS power transistor NM20 is already turned off during this stage, so there will be no power loss. Therefore, no further calculations are needed.
[0096] The drive control circuit and drive control method described in this embodiment can increase the duration t of the Miller plateau stage, which is also the third change stage, by increasing the resistance value of the current-limiting resistor Rc. Tb2-Tb3 This reduces the drain voltage rise rate dv / dt of the NMOS power transistor NM20, thereby improving electromagnetic interference and over-breakdown. Furthermore, by reducing the on-resistance of the first NMOS transistor NM21, the fifth NMOS transistor NM25, and the sixth NMOS transistor NM26, the duration of the first change phase Tb0~Tb1 and the fifth change phase Tb4~Tb5 can be reduced, thereby reducing the conduction loss and heat generation of the NMOS power transistor NM20.
[0097] Furthermore, since different types of MOSFETs typically have different threshold voltages, appropriate first PMOS transistors PM21 and PM22 can be selected based on the threshold voltages of different types of PMOS transistors to minimize (VDD-2*Vthp-Vmiller), thereby reducing the duration t of the second change phase Tb1~Tb2. Tb1-Tb2 A suitable fourth NMOS transistor, NM24, can be selected based on the threshold voltage of different types of NMOS transistors, so that (Vmller-Vthn4-V) Q21 The smaller the value, the shorter the duration t of the fourth change phase Tb3~Tb4. Tb3-Tb4 By reducing the duration of the two aforementioned change phases, the conduction losses during the NMOS power transistor's turn-off process can be further reduced.
[0098] In summary, the drive control circuit and method of this invention can improve the problems of drain voltage overvoltage breakdown and electromagnetic interference in NMOS power transistors by increasing the duration of the Miller plateau phase during the turn-off process; it can also reduce the gate voltage drop time during the turn-off process, thereby reducing conduction losses. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0099] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A drive control circuit for driving and controlling an NMOS power transistor with gate parasitic capacitance, characterized in that, The drive control circuit includes: a PMOS switch and a discharge regulation module, wherein... The gate of the PMOS switch is connected to a PWM signal, the source is connected to a power supply voltage, and the drain is connected to the gate of the NMOS power transistor. The discharge regulation module is connected between the gate and ground of the NMOS power transistor and is controlled by the PWM signal. When the PWM signal changes from low level to high level, it follows the gate voltage change of the NMOS power transistor and discharges the gate parasitic capacitance of the NMOS power transistor in stages based on different discharge paths. The discharge regulation module includes a first discharge regulation unit, which includes a first NMOS transistor and a driving section. The gate of the first NMOS transistor is connected to the output terminal of the driving section, the drain is connected to the gate of the NMOS power transistor, and the source is grounded. The driving section is connected between the gate of the NMOS power transistor and ground, and is controlled by the PWM signal. It is used to generate and output a driving signal during the first change phase of the gate voltage of the NMOS power transistor to control the first NMOS transistor to turn on. The driving section includes: a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a first resistor. The gate of the second NMOS transistor is connected to the PWM signal, the drain is connected to the drain and gate of the first PMOS transistor, and the source is grounded. The source of the first PMOS transistor is connected to the drain and gate of the second PMOS transistor. The source of the second PMOS transistor is connected to the gate of the NMOS power transistor, and the gate is connected to the gate of the third PMOS transistor. The source of the third PMOS transistor is connected to the gate of the NMOS power transistor, and the drain is grounded through the first resistor, serving as the output terminal of the driving section.
2. The drive control circuit according to claim 1, characterized in that, The discharge regulation module includes a first discharge regulation unit, a second discharge regulation unit, and a third discharge regulation unit, all connected between the gate and ground of the NMOS power transistor and controlled by the PWM signal. The first discharge regulation unit is used to form a discharge path from the gate parasitic capacitance of the NMOS power transistor to ground during the first change phase of the gate voltage of the NMOS power transistor. The second discharge regulation unit is used to form a discharge path from the gate parasitic capacitance of the NMOS power transistor to ground during the first to sixth changes of the gate voltage of the NMOS power transistor. The third discharge regulation unit is used to form a discharge path from the gate parasitic capacitance of the NMOS power transistor to ground during the fifth and sixth changes of the gate voltage of the NMOS power transistor.
3. The drive control circuit according to claim 2, characterized in that, The second discharge regulation unit includes a third NMOS transistor and a current-limiting resistor; wherein the gate of the third NMOS transistor is connected to the PWM signal, the drain is connected to the gate of the NMOS power transistor, and the source is grounded through the current-limiting resistor.
4. The drive control circuit according to claim 2, characterized in that, The third discharge regulation unit includes a control section and a discharge section, wherein... The control section is connected between the power supply voltage and ground, and is controlled by the gate voltage of the NMOS power transistor. It is used to generate and output effective control signals during the fifth and sixth changes of the gate voltage of the NMOS power transistor. The discharge section is connected between the gate of the NMOS power transistor and ground, and is controlled by the PWM signal and the control signal. When the control signal is valid, it is used to form a discharge path from the gate parasitic capacitance of the NMOS power transistor to ground.
5. The drive control circuit according to claim 4, characterized in that, The control section includes: a fourth NMOS transistor, a first transistor, and a second resistor; wherein, the gate of the fourth NMOS transistor is connected to the gate of the NMOS power transistor, the drain is connected to the power supply voltage through the second resistor and outputs a control signal, and the source is connected to the base of the first transistor; the collector of the first transistor is connected to the drain of the fourth NMOS transistor, and the emitter is grounded.
6. The drive control circuit according to claim 5, characterized in that, The discharge section includes a fifth NMOS transistor and a sixth NMOS transistor; wherein, the gate of the fifth NMOS transistor is connected to the control signal, the drain is connected to the gate of the NMOS power transistor, and the source is connected to the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor is connected to the PWM signal, and the source is grounded.
7. The drive control circuit according to claim 6, characterized in that, When the second discharge regulation unit includes a third NMOS transistor and a current-limiting resistor, the sum of the on-resistance of the fifth NMOS transistor and the on-resistance of the sixth NMOS transistor is less than the sum of the on-resistance of the third NMOS transistor and the resistance of the current-limiting resistor.
8. A drive control method, implemented based on the drive control circuit of any one of claims 1-7, for driving and controlling an NMOS power transistor with gate parasitic capacitance, characterized in that, The drive control method includes: When the PWM signal changes from high level to low level, the gate parasitic capacitance of the NMOS power transistor is charged to the power supply voltage, and the NMOS power transistor changes from the off state to the on state. When the PWM signal changes from low level to high level, it follows the gate voltage change of the NMOS power transistor and discharges the gate parasitic capacitance of the NMOS power transistor in stages based on different discharge paths, so that the NMOS power transistor changes from the on state to the off state.
9. The drive control method according to claim 8, characterized in that, The gate parasitic capacitance of the NMOS power transistor is discharged in stages using three different discharge paths, specifically including: During the first change phase of the gate voltage of the NMOS power transistor, the gate parasitic capacitance of the NMOS power transistor is discharged based on the first discharge path and the second discharge path. During the second, third, and fourth stages of the gate voltage change of the NMOS power transistor, the gate parasitic capacitance of the NMOS power transistor is discharged based on the second discharge path. During the fifth and sixth stages of the gate voltage change of the NMOS power transistor, the gate parasitic capacitance of the NMOS power transistor is discharged based on the second and third discharge paths.