An oxide thin film transistor, a manufacturing method thereof, and a display device

Abstract

The application provides an oxide thin film transistor, a manufacturing method thereof and a display device. The oxide thin film transistor comprises a gate electrode, a metal oxide active layer and a source-drain metal layer on a substrate. The metal oxide active layer comprises a first metal oxide layer and a second metal oxide layer stacked in a direction away from the substrate. The first metal oxide layer is a carrier transport layer, and the second metal oxide layer is a carrier isolation layer. The electron mobility of the carrier transport layer is greater than that of the carrier isolation layer. The first metal oxide layer comprises two main surfaces facing the substrate and away from the substrate, and further comprises a side surface around the main surface. The second metal oxide layer covers the side surface of the first metal oxide layer. The reliability of the oxide thin film transistor active layer can be improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an oxide thin-film transistor, its fabrication method, and a display device. Background Technology

[0002] In related technologies, the mobility and stability of oxide thin film transistors are improved by designing multilayer oxide thin film transistors, specifically by setting up a multilayer active layer with high mobility and high impedance. However, the inventors of this application discovered during the research process that multilayer oxide thin film transistors have at least one problem: poor reliability of the active layer, which affects the display effect. Summary of the Invention

[0003] This invention provides an oxide thin-film transistor, its fabrication method, and a display device to solve the problem of poor reliability of the active layer in stacked oxide thin-film transistors, which affects the display effect.

[0004] In a first aspect, embodiments of the present invention provide an oxide thin-film transistor, including a gate, a metal oxide active layer, and a source / drain metal layer located on a substrate. The metal oxide active layer includes a first metal oxide layer and a second metal oxide layer stacked along a direction away from the substrate. The first metal oxide layer is a carrier transport layer, and the second metal oxide layer is a carrier isolation layer. The electron migration rate of the carrier transport layer is greater than that of the carrier isolation layer.

[0005] The first metal oxide layer includes two main surfaces facing the substrate and away from the substrate, and the first metal oxide layer also includes side surfaces located around the main surfaces, and the second metal oxide layer covers the side surfaces of the first metal oxide layer.

[0006] In some embodiments, the source / drain metal layer is located on the side of the second metal oxide layer away from the first metal oxide layer, and a via or a blind via is formed on the second metal oxide layer. The via or the blind via extends in a direction perpendicular to the substrate, and the source / drain metal layer is electrically connected to the first metal oxide layer through the via or the blind via.

[0007] In some embodiments, the material of the first metal oxide layer comprises an amorphous metal oxide, and the material of the second metal oxide layer comprises a crystalline metal oxide.

[0008] In some embodiments, the crystallization peaks of the material in the second metal oxide layer in the X-ray diffraction pattern are located in the range of 29° to 32°.

[0009] In some embodiments, the materials of the first metal oxide layer and the second metal oxide layer include indium gallium zinc oxide (IGZO), and under the same etching environment, the etching rate of the second metal oxide layer is 1 to 10 times that of the etching rate of the first metal oxide layer.

[0010] In some embodiments, the band gap of the first metal oxide layer is 2.3 to 2.8 eV, and the band gap of the second metal oxide layer is 2.8 to 3.5 eV.

[0011] In some embodiments, the active layer further includes a third metal oxide layer located on the side of the first metal oxide layer away from the second metal oxide layer, wherein the range of the orthogonal projection of the first metal oxide layer onto the third metal oxide layer is less than or equal to the range of the third metal oxide layer, and the material and degree of crystallinity of the third metal oxide layer are the same as those of the second metal oxide layer.

[0012] In some embodiments, the active layer further includes a fourth metal oxide layer located on the side of the second metal oxide layer away from the first metal oxide layer, and the fourth metal oxide layer covers the side surface of the second metal oxide layer in a direction perpendicular to the substrate.

[0013] The fourth metal oxide layer material includes IGZO, the degree of crystallinity of the fourth metal oxide layer is greater than the degree of crystallinity of the material of the second metal oxide layer, and the band gap of the fourth metal oxide layer is 3.0 to 3.5 electron volts.

[0014] In some embodiments, the atomic percentage of indium in the fourth metal oxide layer is less than the atomic percentage of indium in the second metal oxide layer.

[0015] In some embodiments, the atomic ratio of indium, gallium, and zinc in the metal of the fourth metal oxide layer is 2:5~8:5~8.

[0016] Secondly, embodiments of the present invention also provide an oxide thin film transistor, including a gate, a metal oxide active layer and a source / drain metal layer located on a substrate. The metal oxide active layer includes a first metal oxide layer and a second metal oxide layer stacked along a direction away from the substrate. The first metal oxide layer is a carrier transport layer and the second metal oxide layer is a carrier isolation layer. The electron migration rate of the first metal oxide layer is greater than that of the second metal oxide layer.

[0017] The source / drain metal layer is located on the side of the second metal oxide layer away from the first metal oxide layer. A via or a blind via is formed on the second metal oxide layer. The via or the blind via extends in a direction perpendicular to the substrate. The source / drain metal layer is electrically connected to the first metal oxide layer through the via or the blind via.

[0018] Thirdly, embodiments of the present invention also provide a display device, including an oxide thin-film transistor as described in either the first or second aspect.

[0019] Fourthly, embodiments of the present invention also provide a method for fabricating an oxide thin-film transistor, including the steps of fabricating an active layer, fabricating source / drain metal layers, and fabricating a gate, wherein the step of fabricating the active layer includes:

[0020] The pattern of the first metal oxide layer is created using a target mask through a first patterning process.

[0021] The target mask is used to create a pattern of a second metal oxide layer through a second patterning process. The electron migration rate of the first metal oxide layer is greater than that of the second metal oxide layer. The linewidth of the first patterning process is greater than that of the second patterning process. The exposure time of the first patterning process is less than that of the second patterning process. The development time of the first patterning process is less than that of the second patterning process.

[0022] In some embodiments, the linewidth of the first patterning process is 0.1 to 0.5 micrometers greater than the linewidth of the second patterning process; and / or

[0023] The exposure time of the first patterning process is 30 to 200 milliseconds shorter than the exposure time of the second patterning process; and / or

[0024] The development time of the first patterning process is 1 to 10 seconds shorter than the development time of the second patterning process.

[0025] This application embodiment reduces the possibility of oxygen in the first metal oxide layer diffusing through the side region of the first metal oxide layer during subsequent high-temperature processes by using a second metal oxide layer to cover the side of the first metal oxide layer. This reduces the possibility of the source and drain metal layers being oxidized to form an oxide layer, helps to avoid increased resistance between structures, reduces structural deformation, and thus helps to improve the reliability of the active layer of the oxide thin film transistor. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of an oxide thin-film transistor in one embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of the structure of the first metal oxide layer in one embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the via structure on the second metal oxide layer in one embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of the structure of the blind hole on the second metal oxide layer in one embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of the structure of another oxide thin-film transistor in one embodiment of the present invention;

[0032] Figure 6 This is the X-ray diffraction (XRD) pattern of the second metal oxide layer in this embodiment;

[0033] Figure 7 This is the crystal lattice diagram of the second metal oxide layer in this embodiment;

[0034] Figure 8 This is a schematic diagram of the structure of another oxide thin-film transistor in one embodiment of the present invention;

[0035] Figure 9 This is a schematic diagram of the structure of another oxide thin-film transistor in one embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] This invention provides an oxide thin-film transistor (OTTFT). It should be understood that the TFT mentioned in this embodiment specifically refers to an oxide thin-film transistor.

[0038] like Figure 1 As shown, in one embodiment, the TFT is disposed on a substrate 101 and includes a gate (not shown), a metal oxide active layer 102 and a source / drain metal layer 103 located on the substrate 101. The metal oxide active layer 102 includes a first metal oxide layer 1021 and a second metal oxide layer 1022 stacked along a direction away from the substrate 101.

[0039] like Figure 1 As shown, in this embodiment, the source / drain metal layer 103 includes a first sublayer 1031, a second sublayer 1032, and a third sublayer 1033 stacked together. The materials of the first sublayer 1031 and the third sublayer 1033 can be niobium-molybdenum alloy, and the material of the second sublayer 1032 can be copper.

[0040] The first metal oxide layer 1021, also known as the carrier transport layer, is used to realize the transport of carriers. The source and drain metal layers 103 include the source and the drain. During the operation of the TFT, carriers flow from the source into the carrier transport layer, and after being transported by the carrier transport layer, they flow to the drain, thereby realizing the transmission of electrical signals.

[0041] The second metal oxide layer 1022, also known as the carrier isolation layer, is used to isolate carriers to reduce the possibility of carriers flowing in other directions. The carrier isolation layer is also used to prevent carriers from other structures from flowing into the carrier transport layer and interfering with the electrical signals being transmitted in the carrier transport layer.

[0042] The electron migration rate of the carrier transport layer is greater than that of the carrier isolation layer. In some optional embodiments, the band gap of the first metal oxide layer 1021 is 2.3 to 2.8 eV, and the band gap of the second metal oxide layer 1022 is 2.8 to 3.5 eV.

[0043] like Figure 2 As shown, the first metal oxide layer 1021 includes two main surfaces 1021a facing the substrate 101 and facing away from the substrate 101, and the first metal oxide layer 1021 also includes side surfaces 1021b located around the main surfaces 1021a.

[0044] like Figure 1 and Figure 2 As shown, in this embodiment, the two main surfaces 1021a are respectively Figure 1 The first metal oxide layer 1021 has its upper and lower surfaces covered by the first metal oxide layer 1021, and the second metal oxide layer 1022 covers the side surface 1021b of the first metal oxide layer 1021 to prevent the side surface 1021b of the first metal oxide layer 1021 from contacting other structures.

[0045] Generally, the first metal oxide layer 1021 is formed by a deposition process. That is, the main surface 1021a of the first metal oxide layer 1021 is formed by a deposition process, and the density of the main surface 1021a is relatively high. On the other hand, the side surface 1021b of the first metal oxide layer 1021 is formed by etching the deposited semiconductor layer through a patterning process, and its density is lower than that of the main surface 1021a.

[0046] The fabrication process of display substrates and other structures including TFTs typically includes a high-temperature annealing process. This process may cause oxygen to overflow and diffuse in the first metal oxide layer 1021. Furthermore, the diffused oxygen may react with other structures. For example, it may react with copper contained in the source / drain metal layer 103 to form an oxide layer. This oxide layer will cause an increase in the resistance between structures, affecting the transport of charge carriers. This oxide layer may also cause changes in the thickness of the structure, thereby causing deformation in the area near the side 1021b of the first metal oxide layer 1021.

[0047] By using the second metal oxide layer 1022 to cover the side surface 1021b of the first metal oxide layer 1021, the possibility of oxygen in the first metal oxide layer 1021 diffusing through the side surface 1021b region of the first metal oxide layer 1021 during subsequent high-temperature processes is reduced. This reduces the possibility of the source / drain metal layer 103 being oxidized to form an oxide layer, helps to avoid increased resistance between structures, reduces structural deformation, and thus helps to improve the reliability of the metal oxide active layer 102 of the oxide thin film transistor.

[0048] In yet another embodiment of the present invention, a TFT is also provided.

[0049] like Figure 3 As shown, the TFT in this embodiment includes a gate, a metal oxide active layer 102 and a source / drain metal layer 103 located on a substrate 101. The metal oxide active layer 102 includes a first metal oxide layer 1021 and a second metal oxide layer 1022 stacked along the direction away from the substrate 101. The first metal oxide layer 1021 and the second metal oxide layer 1022 can be specifically referred to in the above embodiment.

[0050] like Figure 3 and Figure 4 As shown, in this embodiment, a via 1022a or a blind via 1022b is formed on the second metal oxide layer 1022 along a direction perpendicular to the substrate 101, and the source / drain metal layer 103 is electrically connected to the first metal oxide layer 1021 through the via 1022a or the blind via 1022b.

[0051] In one embodiment, such as Figure 3As shown, a via 1022a formed on the second metal oxide layer 1022 penetrates the second metal oxide layer 1022 in a direction perpendicular to the substrate 101.

[0052] In another embodiment, such as Figure 4 As shown, the blind hole 1022b formed on the second metal oxide layer 1022 extends only a certain length within the second metal oxide layer 1022 in a direction perpendicular to the substrate 101, and does not penetrate the second metal oxide layer 1022.

[0053] It should be understood that the carrier mobility of the second metal oxide layer 1022 is relatively low, which may affect the transport of carriers. Therefore, in the technical solution of this embodiment, vias 1022a or blind vias 1022b are further formed on the second metal oxide layer 1022.

[0054] Please also refer to Figure 3 and Figure 5 When a via 1022a is provided, the source / drain metal layer 103 can directly make electrical contact with the first metal oxide layer 1021 through the via 1022a, which reduces the contact resistance between the first metal oxide layer 1021 and the source / drain metal layer 103, which helps to reduce carrier loss and improve the transmission effect of electrical signals.

[0055] It should be understood that for the first metal oxide layer 1021, a conductor-enhancing process can be added to make the area where the first metal oxide layer 1021 is in direct electrical contact with the source and drain metal layers 103 conductive. In this way, the portion of the first metal oxide layer 1021 located between the source and drain actually forms the channel region of the TFT, and the area where the first metal oxide layer 1021 is in direct electrical contact with the source and drain is a conductive region, which helps to improve the carrier transport effect.

[0056] Please continue reading. Figure 3 and Figure 5 When a via 1022a is formed on the second metal oxide layer 1022, a portion of the main surface of the first metal oxide layer 1021 will be exposed. This portion of the first metal oxide layer 1021 is affected by the external environment and may become conductive to a certain extent even without a conductor-forming process. Therefore, forming a via 1022a to expose a portion of the first metal oxide layer 1021 will not adversely affect the performance of the TFT.

[0057] When a blind hole 1022b is formed on the second metal oxide layer 1022, the thickness of the second metal oxide layer 1022 between the first metal oxide layer 1021 and the source / drain metal layer 103 is relatively low in the region corresponding to the blind hole 1022b, and its resistance is also relatively low, which can also improve the carrier transport effect.

[0058] Please also refer to Figure 2 , Figure 3 and Figure 5 In another embodiment of this application, the technical solutions of the above two embodiments are combined.

[0059] Specifically, the second metal oxide layer 1022 covers the side surface 1021b of the first metal oxide layer 1021, and vias 1022a or blind vias 1022b are formed on the second metal oxide layer 1022. This can improve the protection of the side surface 1021b of the first metal oxide layer 1021 and reduce the resistance between the first metal oxide layer 1021 and the source / drain metal layer 103, which helps to improve the reliability of the TFT.

[0060] It should be understood that the following optional technical solutions of this application can all be applied to any of the above embodiments.

[0061] In some alternative embodiments, the material of the first metal oxide layer 1021 comprises an amorphous metal oxide, and the material of the second metal oxide layer 1022 comprises a crystalline metal oxide.

[0062] Amorphous metal oxides have relatively high carrier density, which can provide better carrier migration. In practice, the second metal oxide layer 1022 can be recrystallized by high-temperature annealing or other methods to improve its crystallinity. By using amorphous metal oxides to form the first metal oxide layer 1021 and using crystalline metal oxides to form the second metal oxide layer 1022, the first metal oxide layer 1021 can have a relatively high carrier mobility, while the second metal oxide layer 1022 has a relatively low carrier mobility.

[0063] like Figure 6 As shown, Figure 6 This is the X-ray diffraction (XRD) pattern of the second metal oxide layer 1022 in this embodiment, where the horizontal axis is in degrees. In some optional embodiments, XRD analysis of the first metal oxide layer 1021 and the second metal oxide layer 1022 reveals that the first metal oxide layer 1021 does not have obvious crystallization peaks, while crystallization peaks can be observed in the XRD pattern of the second metal oxide layer 1022 in the range of 29° to 32°.

[0064] Furthermore, such as Figure 7 As shown, Figure 7The image shows the lattice pattern of the second metal oxide layer 1022 in this embodiment. In the image of the second metal oxide layer 1022 obtained by HRTEM (High Resolution Transmission Electron Microscope), obvious lattice and electron diffraction spots can be observed.

[0065] In some alternative embodiments, the materials of the first metal oxide layer 1021 and the second metal oxide layer 1022 include indium gallium zinc oxide (IGZO), and under the same etching environment, the etching rate of the second metal oxide layer 1022 is 1 to 10 times that of the etching rate of the first metal oxide layer 1021.

[0066] The same etching environment refers to being in the same etching solution or the same etching gas environment. In this embodiment, the first metal oxide layer 1021 and the second metal oxide layer 1022 both include the same material. In this way, etching can be carried out in the same etching environment during the etching process, which helps to simplify the production process.

[0067] Furthermore, the etching rate of the second metal oxide layer 1022 is 1 to 10 times that of the etching rate of the first metal oxide layer 1021. In one embodiment, the etching rate of the second metal oxide layer 1022 is 6 to 10 times that of the etching rate of the first metal oxide layer 1021. By controlling the second metal oxide layer 1022 to have a higher etching rate, the adverse effects on the first metal oxide layer 1021 during the etching process of the second metal oxide layer 1022 can be reduced, thereby reducing the possibility of the first metal oxide layer 1021 being etched.

[0068] In some optional embodiments, the metal oxide active layer 102 further includes a third metal oxide layer 1023.

[0069] like Figure 8 As shown, the third metal oxide layer 1023 is located on the side of the first metal oxide layer 1021 away from the second metal oxide layer 1022. The range of the orthographic projection of the first metal oxide layer 1021 onto the third metal oxide layer 1023 is less than or equal to the range of the third metal oxide layer 1023. Since the second metal oxide layer 1022 covers the side of the first metal oxide layer 1021, it can be understood that the second metal oxide layer 1022 and the third metal oxide layer 1023 enclose the first metal oxide layer 1021 to protect the first metal oxide layer 1021, reduce the possibility of the first metal oxide layer 1021 contacting other structures, and effectively avoid the influence of adverse conditions such as water and oxygen intrusion on the first metal oxide layer 1021 that realizes the carrier transport function in the active metal oxide layer 102.

[0070] The material and degree of crystallinity of the third metal oxide layer 1023 are the same as those of the second metal oxide layer 1022. This results in better bonding conditions between the second metal oxide layer 1022 and the third metal oxide layer 1023, which helps to improve the coverage and protection effect on the first metal oxide layer 1021.

[0071] In some alternative embodiments, the metal oxide active layer 102 further includes a fourth metal oxide layer 1024.

[0072] like Figure 9 As shown, the fourth metal oxide layer 1024 is located on the side of the second metal oxide layer 1022 away from the first metal oxide layer 1021, that is, the fourth metal oxide layer 1024 is located on the side of the metal oxide active layer 102 closer to the TFT gate. The fourth metal oxide layer 1024 covers the side of the second metal oxide layer 1022.

[0073] The fourth metal oxide layer 1024 is made of IGZO. The crystallinity of the fourth metal oxide layer 1024 is greater than that of the second metal oxide layer 1022. The band gap of the fourth metal oxide layer 1024 is 3.0 to 3.5 electron volts.

[0074] When a via is formed in the second metal oxide layer 1022, a via is also formed at a corresponding position in the fourth metal oxide layer 1024. Conversely, if no via is formed in the second metal oxide layer 1022, a via can also be formed in the fourth metal oxide layer 1024. Forming vias in the fourth metal oxide layer 1024 helps reduce the influence of the fourth metal oxide layer 1024 on the resistance between the source / drain metal layer 103 and the first metal oxide layer 1021, thereby improving the reliability of the TFT.

[0075] It should be understood that the fourth metal oxide layer 1024 is used to protect the first metal oxide layer 1021 and the second metal oxide layer 1022. Therefore, the carrier mobility of the fourth metal oxide layer 1024 is lower than that of the second metal oxide layer 1022, the etching rate is higher than that of the second metal oxide layer 1022, the crystallinity is higher than that of the second metal oxide layer 1022, and the band gap is higher than that of the second metal oxide layer 1022, thereby realizing the protection of the second metal oxide layer 1022 by the fourth metal oxide layer 1024.

[0076] In some embodiments, the fourth metal oxide layer 1024 is a protective layer provided for the gate of the TFT, mainly used to prevent the gate from affecting the fourth metal oxide layer 1024. Accordingly, when fabricating the fourth metal oxide layer 1024, the bandgap width of the fourth metal oxide can be adjusted accordingly to reduce the possible impact of charge carriers in the gate on the first metal oxide layer 1021.

[0077] In some alternative embodiments, the atomic percentage of indium in the metal material in the fourth metal oxide layer 1024 is less than the atomic percentage of indium in the metal material in the second metal oxide layer 1022.

[0078] It should be understood that in this embodiment, the materials of the second metal oxide layer 1022 and the fourth metal oxide layer 1024 are the same, both being IGZO, but the proportions of different metals are different. The proportion of indium in the second metal oxide layer 1022 is greater than 20%, while the proportion of indium in the fourth metal oxide layer 1024 is less than 20%, specifically 5% to 20% in this embodiment. In some optional embodiments, the atomic ratio of indium, gallium, and zinc in the metal of the fourth metal oxide layer 1024 is 2:5~8:5~8. By reducing the atomic percentage of indium in the metal material of the fourth metal oxide layer 1024, the crystallinity of the fourth metal oxide layer 1024 can be improved, making the lattice order of the fourth metal oxide layer 1024 stronger, thereby making the electron mobility of the fourth metal oxide layer 1024 lower.

[0079] In some other alternative embodiments, more metal oxide layers may be provided as needed, such as a fifth metal oxide layer with lower electron mobility provided on the fourth metal oxide layer 1024, to further improve the protection effect.

[0080] In some other alternative embodiments, the thickness of the first metal oxide layer 1021 is 10 to 60 nanometers, and the thickness of the second metal oxide layer 1022 is 10 to 80 nanometers. Further, in one embodiment, the total thickness of the first metal oxide layer 1021 and the second metal oxide layer 1022 is no greater than 100 nanometers, and the thickness of the second metal oxide layer 1022 is greater than the thickness of the first metal oxide layer 1021.

[0081] This invention also provides a display device including the oxide thin-film transistor described in any of the preceding embodiments.

[0082] Since this embodiment includes all the technical solutions of the above-described oxide thin-film transistor embodiments, it can achieve at least all of the above-described technical effects, and will not be repeated here.

[0083] This invention also provides a method for fabricating an oxide thin-film transistor, including the steps of fabricating an active layer, fabricating source / drain metal layers, and fabricating a gate, wherein the step of fabricating the active layer includes:

[0084] The pattern of the first metal oxide layer is created using a target mask through a first patterning process.

[0085] The target mask is used to create the pattern of the second metal oxide layer through a second patterning process.

[0086] In this embodiment, the linewidth of the first patterning process is greater than that of the second patterning process, the exposure time of the first patterning process is less than that of the second patterning process, and the development time of the first patterning process is less than that of the second patterning process. In this embodiment, the electron migration rate of the first metal oxide layer is greater than that of the carrier isolation layer.

[0087] In some embodiments, the linewidth of the first patterning process is 0.1 to 0.5 micrometers greater than the linewidth of the second patterning process; the exposure time of the first patterning process is 30 to 200 milliseconds less than the exposure time of the second patterning process; and the development time of the first patterning process is 1 to 10 seconds less than the development time of the second patterning process.

[0088] In this embodiment, by controlling the exposure time, development time, and linewidth of the patterning process, it is possible to achieve the effect of the first metal oxide layer covering the edge of the second metal oxide layer while using the same mask for patterning.

[0089] Furthermore, during the patterning process of the second metal oxide layer, in order to reduce the possibility of over-etching causing the first metal oxide layer to be etched, the reaction parameters can be further adjusted, such as reducing the concentration of the etching solution or reducing the arc path of the etching gas, to reduce the etching rate. Since the etching rate of the first metal oxide layer is less than that of the second metal oxide layer, by further controlling the reaction conditions, the possible impact on the first metal oxide layer can be further reduced, and the possibility of over-etching can be reduced.

[0090] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An oxide thin-film transistor, characterized in that, It includes a gate, a metal oxide active layer, and a source / drain metal layer located on a substrate. The metal oxide active layer includes a first metal oxide layer and a second metal oxide layer stacked along a direction away from the substrate. The first metal oxide layer is a carrier transport layer, and the second metal oxide layer is a carrier isolation layer. The electron migration rate of the carrier transport layer is greater than that of the carrier isolation layer. The first metal oxide layer includes two main surfaces facing the substrate and facing away from the substrate. The first metal oxide layer also includes side surfaces located around the main surfaces. The side surfaces of the first metal oxide layer are less dense than the main surfaces. The second metal oxide layer covers the side surfaces of the first metal oxide layer. The active metal oxide layer further includes a fourth metal oxide layer, which is located on the side of the second metal oxide layer away from the first metal oxide layer, and in a direction perpendicular to the substrate, the fourth metal oxide layer covers the side of the second metal oxide layer. The carrier mobility of the fourth metal oxide layer is lower than that of the second metal oxide layer, the etching rate of the fourth metal oxide layer is greater than that of the second metal oxide layer, the crystallinity of the fourth metal oxide layer is greater than that of the second metal oxide layer, and the band gap of the fourth metal oxide layer is greater than that of the second metal oxide layer.

2. The oxide thin-film transistor according to claim 1, characterized in that, The source / drain metal layer is located on the side of the second metal oxide layer away from the first metal oxide layer. A via or a blind via is formed on the second metal oxide layer. The via or the blind via extends in a direction perpendicular to the substrate. The source / drain metal layer is electrically connected to the first metal oxide layer through the via or the blind via.

3. The oxide thin-film transistor according to claim 1, characterized in that, The material of the first metal oxide layer includes an amorphous metal oxide, and the material of the second metal oxide layer includes a crystalline metal oxide.

4. The oxide thin-film transistor according to claim 3, characterized in that, The crystallization peaks of the material in the second metal oxide layer in the X-ray diffraction pattern are located in the range of 29° to 32°.

5. The oxide thin-film transistor according to claim 3, characterized in that, The materials of the first metal oxide layer and the second metal oxide layer include indium gallium zinc oxide (IGZO), and under the same etching environment, the etching rate of the second metal oxide layer is 1 to 10 times that of the first metal oxide layer.

6. The oxide thin-film transistor according to any one of claims 1 to 5, characterized in that, The band gap of the first metal oxide layer is 2.3 to 2.8 electron volts, and the band gap of the second metal oxide layer is 2.8 to 3.5 electron volts.

7. The oxide thin-film transistor according to claim 5, characterized in that, The band gap of the fourth metal oxide layer is 3.0 to 3.5 electron volts.

8. The oxide thin-film transistor according to claim 7, characterized in that, The percentage of indium atoms in the fourth metal oxide layer is less than the percentage of indium atoms in the second metal oxide layer.

9. The oxide thin-film transistor according to claim 8, characterized in that, The atomic ratio of indium, gallium, and zinc in the fourth metal oxide layer is 2:5~8:5~8.

10. An oxide thin-film transistor, characterized in that, It includes a gate, a metal oxide active layer, and a source / drain metal layer located on a substrate. The metal oxide active layer includes a first metal oxide layer and a second metal oxide layer stacked along a direction away from the substrate. The first metal oxide layer is a carrier transport layer, and the second metal oxide layer is a carrier isolation layer. The electron mobility of the first metal oxide layer is greater than that of the second metal oxide layer. The first metal oxide layer includes two main surfaces facing the substrate and facing away from the substrate. The first metal oxide layer also includes side surfaces located around the main surfaces. The side surfaces of the first metal oxide layer are less dense than the main surfaces. The second metal oxide layer covers the side surfaces of the first metal oxide layer. The source / drain metal layer is located on the side of the second metal oxide layer away from the first metal oxide layer. A via or a blind via is formed on the second metal oxide layer. The via or the blind via extends in a direction perpendicular to the substrate. The source / drain metal layer is electrically connected to the first metal oxide layer through the via or the blind via. The active metal oxide layer further includes a fourth metal oxide layer, which is located on the side of the second metal oxide layer away from the first metal oxide layer, and in a direction perpendicular to the substrate, the fourth metal oxide layer covers the side of the second metal oxide layer. The carrier mobility of the fourth metal oxide layer is lower than that of the second metal oxide layer, the etching rate of the fourth metal oxide layer is greater than that of the second metal oxide layer, the crystallinity of the fourth metal oxide layer is greater than that of the second metal oxide layer, and the band gap of the fourth metal oxide layer is greater than that of the second metal oxide layer.

11. A display device, characterized in that, The oxide thin-film transistor includes any one of claims 1 to 10.

12. A method for fabricating an oxide thin-film transistor, characterized in that, A method for fabricating an oxide thin-film transistor as described in any one of claims 1 to 10, comprising the steps of fabricating an active layer, fabricating source / drain metal layers, and fabricating a gate, wherein the step of fabricating the active layer includes: The pattern of the first metal oxide layer is created using a target mask through a first patterning process. The target mask is used to create a pattern of a second metal oxide layer through a second patterning process. The electron migration rate of the first metal oxide layer is greater than that of the second metal oxide layer. The linewidth of the first patterning process is greater than that of the second patterning process. The exposure time of the first patterning process is less than that of the second patterning process. The development time of the first patterning process is less than that of the second patterning process.

13. The method according to claim 12, characterized in that, The linewidth of the first patterning process is 0.1 to 0.5 micrometers greater than the linewidth of the second patterning process; and / or The exposure time of the first patterning process is 30 to 200 milliseconds shorter than the exposure time of the second patterning process; and / or The development time of the first patterning process is 1 to 10 seconds shorter than the development time of the second patterning process.

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