Array substrate, display panel and display device

Abstract

This disclosure provides an array substrate, a display panel, and a display device. The array substrate includes: a substrate (1); a low-temperature polysilicon thin-film transistor (2) located on the substrate (1), the low-temperature polysilicon thin-film transistor (2) including a polysilicon active layer (21) and a first gate (22) stacked on the substrate (1); an oxide thin-film transistor (3) located on the substrate (1), the oxide thin-film transistor (3) including an oxide active layer (31) and a second gate (32) stacked on the substrate (1); a light-shielding layer (35), the overlapping area of ​​the projection of the light-shielding layer (35) on the substrate (1) and the orthographic projection of the oxide active layer (31) on the substrate (1) is S1; the overlapping area of ​​the projection of the light-shielding layer (35) on the substrate (1) and the orthographic projection of the polysilicon active layer (21) on the substrate (1) is S2, wherein S1 is greater than S2.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for the resolution, power consumption, and image quality of display products. To meet these requirements, Low Temperature Polycrystalline Oxide (LTPO) technology is often used to fabricate the pixel driving circuit in the driving backplane of display products. This LTPO technology utilizes both Low Temperature Polycrystalline Silicon Thin Film Transistors (LTPS TFTs) and Metal Oxide Thin Film Transistors (Oxide TFTs) as functional transistors in the pixel driving circuit. Due to the high mobility of LTPS TFTs, the charging speed of the pixel capacitor can be accelerated, while Metal Oxide TFTs have lower leakage current. Combining the advantages of these two transistors helps in the development of high-resolution, low-power, and high-image-quality display products. Summary of the Invention

[0003] This disclosure provides an array substrate, comprising:

[0004] Substrate;

[0005] A low-temperature polycrystalline silicon thin-film transistor is located on the substrate, and the low-temperature polycrystalline silicon thin-film transistor includes a polycrystalline silicon active layer and a first gate layer stacked on the substrate.

[0006] An oxide thin-film transistor is located on the substrate, the oxide thin-film transistor including an oxide active layer and a second gate stacked on the substrate;

[0007] A light-shielding layer, wherein the overlapping area of ​​the projection of the light-shielding layer on the substrate and the orthogonal projection of the oxide active layer on the substrate is S1; and the overlapping area of ​​the projection of the light-shielding layer on the substrate and the orthogonal projection of the polysilicon active layer on the substrate is S2, wherein S1 is greater than S2.

[0008] In one possible implementation, the light-shielding layer is the same layer and material as the first gate.

[0009] In one possible implementation, the light-shielding layer is located between the layer containing the first gate and the layer containing the oxide active layer.

[0010] In one possible implementation, the light-shielding layer is located between the layer containing the polysilicon active layer and the layer containing the substrate.

[0011] In one possible implementation, the first gate and the second gate are made of the same material, and the light-shielding layer is made of the same material as the second gate.

[0012] In one possible implementation, the oxide active layer is located on the side of the first gate opposite to the substrate.

[0013] The oxide active layer has a first buffer layer between it and the first gate.

[0014] In one possible implementation, a second buffer layer is provided between the substrate and the polysilicon active layer;

[0015] A barrier layer is also provided between the second buffer layer and the substrate.

[0016] A first gate insulating layer is provided between the polysilicon active layer and the first gate;

[0017] A second gate insulating layer is provided between the oxide active layer and the second gate;

[0018] The side of the second gate opposite to the substrate also has an interlayer dielectric layer.

[0019] In one possible implementation, the light-shielding layer is located between the layer containing the first gate and the layer containing the oxide active layer, and a third gate insulating layer is also provided between the first buffer layer and the first gate.

[0020] The light-shielding layer is located between the first buffer layer and the third gate insulating layer.

[0021] In one possible implementation, the light-shielding layer is located between the layer containing the polysilicon active layer and the layer containing the substrate, and the light-shielding layer is located between the second buffer layer and the barrier layer.

[0022] In one possible implementation, the side of the interlayer dielectric layer facing away from the substrate also has a source-drain layer, the source-drain layer including a first source, a first drain, a second source, and a second drain;

[0023] The first source electrode is connected to the source region of the polysilicon active layer through a first via, and the first drain electrode is connected to the drain region of the polysilicon active layer through a second via.

[0024] The second source is connected to the oxide active layer through a third via, and the second drain is connected to the oxide active layer through a fourth via.

[0025] In one possible implementation, the side of the source / drain layer facing away from the substrate has a first planarization layer;

[0026] The side of the first planarization layer opposite to the substrate has a connecting electrode;

[0027] The side of the connecting electrode facing away from the substrate has a second planarization layer;

[0028] The side of the second planarization layer opposite to the substrate has an anode;

[0029] The anode is connected to the connecting electrode through a fifth via penetrating the second planarization layer, and the connecting electrode is connected to the first drain through a sixth via penetrating the first planarization layer.

[0030] In one possible implementation, the anode has a pixel definition layer on the side facing away from the substrate; the pixel definition layer has spacers on the side facing away from the substrate; and the pixel definition layer has a cutout area that exposes the anode.

[0031] This disclosure also provides a display panel, which includes the array substrate as described in this disclosure.

[0032] This disclosure also provides a display device, which includes the display panel as described in this disclosure. Attached Figure Description

[0033] Figure 1 A schematic diagram of an array substrate structure with a light-shielding layer disposed below an oxide thin-film transistor provided in an embodiment of this disclosure;

[0034] Figure 2 A schematic diagram of another array substrate structure with a light-shielding layer disposed below the oxide thin film transistor provided in the embodiments of this disclosure;

[0035] Figure 3 A schematic diagram of another array substrate structure with a light-shielding layer disposed below the oxide thin film transistor provided in the embodiments of this disclosure;

[0036] Figure 4 A schematic diagram of an array substrate structure for an oxide thin-film transistor without a light-shielding layer below, provided in an embodiment of this disclosure;

[0037] Figure 5 A schematic diagram of a specific array substrate structure for an oxide thin-film transistor provided in an embodiment of this disclosure, without a light-shielding layer underneath;

[0038] Figure 6 A schematic diagram of a specific array substrate structure with a light-shielding layer disposed below the oxide thin film transistor provided in the embodiments of this disclosure;

[0039] Figure 7 This is a schematic diagram of another specific array substrate structure with a light-shielding layer disposed below the oxide thin film transistor provided in the embodiments of this disclosure;

[0040] Figure 8 This is a schematic diagram of another specific array substrate structure with a light-shielding layer disposed below the oxide thin film transistor provided in the embodiments of this disclosure. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0042] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0043] See Figure 1 As shown, this disclosure provides an array substrate, which includes:

[0044] Substrate 1;

[0045] The low-temperature polycrystalline silicon thin-film transistor 2 is located on a substrate 1. The low-temperature polycrystalline silicon thin-film transistor 2 includes a polycrystalline silicon active layer 21 and a first gate 22 (the first gate 22 is located on the side of the polycrystalline silicon active layer 21 away from the substrate 1) that are sequentially stacked on the substrate 1.

[0046] The oxide thin film transistor 3 is located on the substrate 1. The orthographic projection of the oxide thin film transistor 3 on the substrate 1 does not overlap with the orthographic projection of the low-temperature polycrystalline silicon thin film transistor 2 on the substrate 1. The oxide thin film transistor 3 includes an oxide active layer 31 and a second gate 32 (the second gate 32 is located on the side of the oxide active layer 31 away from the substrate 1) that are stacked sequentially on the substrate 1.

[0047] The light-shielding layer 35 has an overlap area of ​​S1 between its projection on the substrate 1 and the orthogonal projection of the oxide active layer 31 on the substrate 1; the overlap area of ​​S2 between its projection on the substrate 1 and the orthogonal projection of the polysilicon active layer 21 on the substrate 1, wherein S1 is greater than S2.

[0048] The array substrate provided in this embodiment has a transparent film layer between the polysilicon active layer 21 and the substrate 1 in the region where the low-temperature polysilicon thin-film transistor 2 is located. The oxide thin-film transistor 3 includes an oxide active layer 31 and a second gate 32 sequentially stacked on the substrate 1. The overlapping area of ​​the projection of the light-shielding layer 35 on the substrate 1 and the orthogonal projection of the oxide active layer 31 on the substrate 1 is S1; the overlapping area of ​​the projection of the light-shielding layer 35 on the substrate 1 and the orthogonal projection of the polysilicon active layer 21 on the substrate 1 is S2, where S1 is greater than S2. This allows the high mobility characteristics of the low-temperature polysilicon thin-film transistor 2 to be used in transistors requiring high switching speeds, while the low leakage current characteristics of the oxide thin-film transistor 3 can be used in transistors requiring high leakage current control. This enables the array substrate to simultaneously have high switching speeds and low leakage current performance.

[0049] In a specific implementation, the overlap area S2 between the projection of the light-shielding layer 35 onto the substrate 1 and the orthographic projection of the polysilicon active layer 21 onto the substrate 1 can be zero. That is, no light-shielding layer is provided between the polysilicon active layer 21 and the substrate 1, and the film layer between the polysilicon active layer 21 and the substrate 1 is a transparent film layer in the region where the low-temperature polysilicon thin-film transistor 2 is located. For example, combined with... Figure 1 As shown, a barrier layer 6 may be present between the polycrystalline silicon active layer 21 and the substrate 1, and a second buffer layer 52 located between the barrier layer 6 and the polycrystalline silicon active layer 21. In this case, both the barrier layer 6 and the second buffer layer 52 in the region where the low-temperature polycrystalline silicon thin film transistor 2 is located are transparent films, which is the region where the low-temperature polycrystalline silicon thin film transistor 2 is located.

[0050] In specific implementation, the oxide thin film transistor 3 only loads the gate signal on the second gate 32. That is, the oxide thin film transistor 3 is a single gate and a top gate type thin film transistor. Even if a light-shielding layer is provided in the area where the oxide thin film transistor 3 is located, the light-shielding layer is only used as a light-shielding film layer and does not load the driving gate signal.

[0051] It should be noted that polycrystalline silicon material has high mobility, low power consumption, and high reliability. Therefore, the low-temperature polycrystalline silicon thin-film transistor 2 can be used as a gate driver and / or multiplexer (MUX) of the driving element of a thin-film transistor driving a display device. Preferably, the low-temperature polycrystalline silicon thin-film transistor 2 can be used as a driving transistor in the pixel circuit of an organic light-emitting display device. The band gap of oxide semiconductor material is larger than that of silicon material, which prevents electrons from passing through the band gap in the off state, and the cutoff current is low. Therefore, the oxide thin-film transistor 3 is suitable for thin-film transistors that are kept on for short periods and off for long periods. In addition, due to the low cutoff current, the size of the auxiliary capacitor can be reduced. Therefore, the oxide thin-film transistor 3 is suitable for high-resolution display elements. Exemplarily, the oxide thin-film transistor 3 can be used as a switching transistor in the pixel circuit of an organic light-emitting display device. In addition, the substrate 1 can be a flexible substrate such as polyimide (PI) or a rigid substrate such as glass, which is not limited here. The low-temperature polycrystalline silicon thin-film transistor 2 can specifically be a top-gate type low-temperature polycrystalline silicon thin-film transistor 2. The oxide thin-film transistor 3 can specifically be a top-gate type oxide thin-film transistor 3.

[0052] In specific implementation, combined with Figure 4 As shown, the film layer between the oxide active layer 31 and the substrate 1 is a transparent film layer in the region where the oxide thin-film transistor 3 is located. For example, combined with Figure 4 As shown, a barrier layer 6 may be present between the oxide active layer 31 and the substrate 1, and a second buffer layer 52 located between the barrier layer 6 and the polysilicon active layer 21. In this case, both the barrier layer 6 and the second buffer layer 52 in the region where the oxide thin film transistor 3 is located are transparent films. That is, no light-shielding layer is provided between the polysilicon active layer 21 and the substrate 1 in the region where the oxide thin film transistor 3 is located.

[0053] For specific implementation, see Figure 1 , Figure 2 , Figure 3 As shown, the projection of the light-shielding layer 35 onto the substrate 1 covers the orthogonal projection of the oxide active layer 31 onto the substrate 1.

[0054] Specifically, in combination Figure 1As shown, the light-shielding layer 35 and the first gate 22 can be located on the same layer. The material of the light-shielding layer 35 can be molybdenum, molybdenum, aluminum, copper, titanium / aluminum / titanium, or other metals or alloys; alternatively, the material of the light-shielding layer 35 can be a black organic material, such as black organic resin; alternatively, the material of the light-shielding layer 35 can be carbon black; alternatively, the material of the light-shielding layer 35 can be black pigment. The materials of the light-shielding layer 35 and the first gate 22 can be the same or different. The material of the first gate 22 can be molybdenum, molybdenum, aluminum, copper, titanium / aluminum / titanium, or other metals or alloys. The material of the first gate 32 can be molybdenum, molybdenum, aluminum, copper, titanium / aluminum / titanium, or other metals or alloys. The materials of the first source 23 and the first drain 24 can be molybdenum, molybdenum, aluminum, copper, titanium / aluminum / titanium, or other metals or alloys. The materials of the second source 33 and the second drain 34 can be molybdenum, molybdenum, aluminum, copper, titanium / aluminum / titanium, or other metals or alloys.

[0055] The thickness of the light-shielding layer 35 can be specifically as follows: Specifically, the thickness of the light-shielding layer 35 can be... Specifically, the thickness of the light-shielding layer 35 can be... Specifically, the thickness of the light-shielding layer 35 can be... Specifically, the thickness of the light-shielding layer 35 can be... Specifically, the thickness of the light-shielding layer 35 can be... Specifically, the thickness of the light-shielding layer 35 can be... Specifically, the thickness of the light-shielding layer 35 can be... Specifically, the thickness of the light-shielding layer 35 can be... Specifically, the thickness of the light-shielding layer 35 can be...

[0056] Specifically, the light-shielding layer 35 is on the same layer and made of the same material as the first gate 22. Specifically, the material of the light-shielding layer 35 can be molybdenum, or other metals or alloys such as aluminum, copper, or titanium / aluminum / titanium.

[0057] Specifically, in combination Figure 2 As shown, the light-shielding layer 35 is located between the layer containing the first gate 22 and the layer containing the oxide active layer 31. For example, as... Figure 3 As shown, the light-shielding layer 35 is located between the layer containing the polysilicon active layer 21 and the layer containing the substrate 1.

[0058] In practice, the first gate 22 and the second gate 32 are made of the same material, and the light-shielding layer 35 is made of the same material as the second gate 32.

[0059] In specific implementation, combined with Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, the oxide active layer 31 is located on the side of the first gate 22 facing away from the substrate 1; a first buffer layer 51 is provided between the oxide active layer 31 and the first gate 22. Specifically, a second buffer layer 52 is provided between the substrate 1 and the polysilicon active layer 21; a barrier layer 6 is also provided between the second buffer layer 52 and the substrate 1; a first gate insulating layer 41 is provided between the polysilicon active layer 21 and the first gate 22; a second gate insulating layer 42 is provided between the oxide active layer 31 and the second gate 32; an interlayer dielectric layer 7 is also provided on the side of the second gate 32 facing away from the substrate 1.

[0060] In specific implementation, combined with Figure 3 As shown, when the light-shielding layer 35 is located between the layer containing the first gate 22 and the layer containing the oxide active layer 31, a third gate insulating layer 43 is also present between the first buffer layer 51 and the first gate 22; the light-shielding layer 35 is located between the first buffer layer 51 and the third gate insulating layer 43.

[0061] In specific implementation, combined with Figure 4 As shown, when the light-shielding layer 35 is located between the layer containing the polysilicon active layer 31 and the layer containing the substrate 1, and the light-shielding layer 35 is located between the second buffer layer 52 and the barrier layer 6.

[0062] In specific implementation, combined with Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, the side of the interlayer dielectric layer 7 facing away from the substrate 1 also has a source-drain layer, which includes a first source 23, a first drain 24, a second source 33, and a second drain 34. The first source 23 is connected to the source region of the polysilicon active layer 21 through a first via K1, and the first drain 24 is connected to the drain region of the polysilicon active layer 21 through a second via K2. The second source 33 is connected to the oxide active layer 31 through a third via K3, and the second drain 34 is connected to the oxide active layer 31 through a fourth via K4.

[0063] In specific implementation, combined with Figure 5 , Figure 6 , Figure 7 , Figure 8 As shown, where, Figure 5 for Figure 1 The corresponding specific array substrate structure diagram Figure 6 for Figure 2 The corresponding specific array substrate structure diagram Figure 7 for Figure 3 The corresponding specific array substrate structure diagram Figure 8 for Figure 4The corresponding specific array substrate structure diagram shows that the source and drain layers have a first planarization layer 81 on the side away from the substrate 1; the first planarization layer 81 has a connecting electrode 9 on the side away from the substrate 1; the connecting electrode 9 has a second planarization layer 82 on the side away from the substrate 1; the second planarization layer 82 has an anode 10 on the side away from the substrate 1; the anode 10 is connected to the connecting electrode 9 through a fifth via K5 penetrating the second planarization layer 82, and the connecting electrode 9 is connected to the first drain 24 through a sixth via K6 penetrating the first planarization layer 81.

[0064] In a specific implementation, a storage capacitor electrode is also provided on the layer where the connecting electrode 9 is located, and a storage capacitor is disposed on the same layer therewith. The material of the storage capacitor electrode can be the same as the material of the first gate 22, or the same as the material of the second gate 32, or the same as the material of the first source 23 and the first drain 24, or the same as the material of the second source 33 and the second drain 34. The storage capacitor electrode can be connected to a fixed potential, or it can be loaded with the same potential as the light-shielding layer 35, or it can be different.

[0065] The potential applied to the light-shielding layer can be the same as the potential applied to the power supply line VDD (voltage source potential); it can also be the same as the potential applied to the initialization signal line; it can also be the same as the potential applied to the cathode (cathode potential VSS); or it can be other fixed potentials, for example, a fixed potential range of -10V to +10V, or a fixed potential range of -5V to +5V, or a fixed potential range of -3V to +3V, or a fixed potential range of -1V to +1V, or a fixed potential range of -0.5V to +0.5V, or a fixed potential range of 0V, or a fixed potential range of 0.1V, or a fixed potential range of 10.1V, or a fixed potential range of 0.2V, or a fixed potential range of -0.2V, or a fixed potential range of 0.3V, or a fixed potential range of -0.3V.

[0066] Specifically, the potential applied to the light-shielding layer 35 can be greater than the potential applied to the cathode (cathode potential VSS) and less than the potential applied to the power line VDD; or, the potential applied to the light-shielding layer 35 can be greater than the potential applied to the initialization signal line and less than the potential applied to the power line VDD.

[0067] In specific implementation, combined with Figure 5 , Figure 6 , Figure 7 , Figure 8 As shown, the side of the anode 10 facing away from the substrate 1 has a pixel definition layer 11; the side of the pixel definition layer 11 facing away from the substrate 1 has a spacer 12; the pixel definition layer 11 has a cutout area that exposes the anode 10.

[0068] Specifically, the materials of the first gate 22, the second gate 32, and the light-shielding layer 35 can be metals or alloys such as molybdenum, aluminum, copper, and titanium / aluminum / titanium, and are not limited here. The material of the oxide active layer 31 can be indium gallium zinc oxide (IGZO). The material of the barrier layer 6 can be silicon oxide (SiOx) / silicon nitride (SiNx) / silicon oxide (SiOx) / silicon nitride (SiNx) stacked sequentially. The material of the first buffer layer 51 can be silicon oxide (SiOx) / silicon nitride (SiNx) / silicon oxide (SiOx) stacked sequentially. The material of the second buffer layer 52 can be silicon oxide (SiOx). The material of the first insulating layer 41 can be silicon oxide (SiOx). The material of the second insulating layer 42 can be silicon oxide (SiOx). The material of the third insulating layer 43 can be silicon oxide (SiOx). The material of the interlayer dielectric layer 7 can be silicon oxide (SiOx). The material of the first planarization layer 81 can be silicon nitride (SiNx). The second planarization layer 82 can be made of silicon nitride (SiNx).

[0069] In a specific embodiment, the first insulating layer 41, the second insulating layer 42, the third insulating layer 43, and the interlayer dielectric layer 7 can be made of the same material, such as silicon oxide (SiOx). For example, the oxygen content of each film layer can be the same or different; when the oxygen content of each film layer is the same or approximately the same, there is no obvious boundary between the film layers.

[0070] It should be noted that "approximately" in this disclosure means an error of no more than 10%.

[0071] This disclosure also provides a display panel, which includes the array substrate provided in this disclosure. The display panel can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure. Since the principle by which this display panel solves the problem is similar to that of the display substrate described above, the implementation of the display panel provided in this disclosure can refer to the implementation of the display substrate provided in this disclosure, and repeated details will not be repeated.

[0072] This disclosure also provides a display device, which includes the display panel provided in this disclosure embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Other essential components of the display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure. Furthermore, since the principle by which this display device solves the problem is similar to that of the display panel described above, the implementation of this display device can refer to the embodiments of the display panel described above, and repeated details will not be repeated.

[0073] The array substrate provided in this embodiment has a transparent film layer between the polysilicon active layer 21 and the substrate 1 in the region where the low-temperature polysilicon thin-film transistor 2 is located. The oxide thin-film transistor 3 includes an oxide active layer 31 and a second gate 32 stacked sequentially on the substrate 1. The oxide thin-film transistor 3 loads a gate signal only on the second gate 32. This allows the high mobility characteristics of the low-temperature polysilicon thin-film transistor 2 to be used in transistors requiring high switching speeds, while the low leakage current characteristics of the oxide thin-film transistor 3 can be used in transistors requiring high leakage current control. This enables the array substrate to have both high switching speed and low leakage current performance.

[0074] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0075] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Therefore, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The array substrate comprises: a substrate substrate; a low-temperature polysilicon thin film transistor on the substrate substrate, the low-temperature polysilicon thin film transistor comprising a polysilicon active layer and a first gate arranged in layers on the substrate substrate; an oxide thin film transistor on the substrate substrate, the oxide thin film transistor comprising an oxide active layer and a second gate arranged in layers on the substrate substrate; a light shielding layer, the overlapping area of the light shielding layer on the substrate substrate and the orthographic projection of the oxide active layer on the substrate substrate is S1; the overlapping area of the light shielding layer on the substrate substrate and the orthographic projection of the polysilicon active layer on the substrate substrate is S2, wherein S1 is greater than S2; wherein the oxide active layer is located on the side of the first gate away from the substrate substrate; the oxide active layer and the first gate have a first buffer layer therebetween; wherein the substrate substrate and the polysilicon active layer have a second buffer layer therebetween; the second buffer layer and the substrate substrate further have a barrier layer therebetween; the polysilicon active layer and the first gate have a first gate insulating layer therebetween; the oxide active layer and the second gate have a second gate insulating layer therebetween; the side of the second gate away from the substrate substrate further has an interlayer dielectric layer thereon; wherein the thickness of the light shielding layer is 1000 Å-5000 Å; the light shielding layer is located between the layer where the polysilicon active layer is located and the layer where the substrate substrate is located, and the light shielding layer is located between the second buffer layer and the barrier layer, the light shielding layer is loaded with a fixed potential, the fixed potential is greater than the cathode potential and less than the power line potential.

2. The array substrate of claim 1, wherein, The material of the first gate and the second gate is the same, and the material of the light shielding layer is the same as that of the second gate.

3. The array substrate of claim 1, wherein, The side of the interlayer dielectric layer away from the substrate substrate further has a source-drain layer, the source-drain layer comprising a first source, a first drain, a second source and a second drain; the first source is connected to the source region of the polysilicon active layer through a first via, and the first drain is connected to the drain region of the polysilicon active layer through a second via; the second source is connected to the oxide active layer through a third via, and the second drain is connected to the oxide active layer through a fourth via.

4. The array substrate of claim 3, wherein the side of the source-drain layer away from the substrate substrate has a first planar layer; the side of the first planar layer away from the substrate substrate has a connecting electrode; the side of the connecting electrode away from the substrate substrate has a second planar layer; the side of the second planar layer away from the substrate substrate has an anode; the anode is in conduction with the connecting electrode through a fifth via penetrating through the second planar layer, and the connecting electrode is in conduction with the first drain through a sixth via penetrating through the first planar layer.

5. The array substrate of claim 4, wherein, the side of the anode away from the substrate substrate has a pixel definition layer; the side of the pixel definition layer away from the substrate substrate has a spacer; the pixel definition layer has a hollow area exposing the anode.

6. A display panel, wherein, The array substrate comprises any one of claims 1-5.

7. A display device, wherein, The display panel as claimed in claim 6 is included.

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