Metal oxide thin film transistor and manufacturing method thereof, array substrate
By using a single-layer silicon nitride gate insulating layer and a titanium oxide layer in a metal oxide thin-film transistor to isolate hydrogen diffusion, the problems of microscopic defects and complex manufacturing processes in the prior art are solved, achieving simplified manufacturing processes and excellent driving performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KUSN INFOVISION OPTOELECTRONICS
- Filing Date
- 2022-03-28
- Publication Date
- 2026-06-26
AI Technical Summary
Existing metal oxide thin-film transistors have microstructural defects during the film formation process, making them susceptible to acid corrosion and diffusion of foreign substances. Furthermore, the fabrication process is complex, making it difficult to obtain thin-film transistors with excellent driving performance.
A single-layer silicon nitride gate insulating layer and a titanium oxide layer are used. By doping oxygen ions in the titanium layer to form a transparent insulating layer, hydrogen diffusion into the metal oxide semiconductor layer is isolated, and the process is simplified by omitting the etch barrier layer.
This method achieves a simple manufacturing process and obtains a metal oxide thin-film transistor with excellent driving performance, avoiding the impact of hydrogen diffusion on the semiconductor layer and reducing the complexity of the manufacturing process.
Smart Images
Figure CN114678427B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and in particular to a metal oxide thin-film transistor, its fabrication method, and an array substrate. Background Technology
[0002] In recent years, oxide semiconductor thin film transistors (AOS TFTs) have attracted widespread attention in the industry due to their excellent electrical and optical properties. However, thin film transistors using metal oxide semiconductors as the active layer material typically employ vapor deposition methods such as sputtering, atomic layer deposition (ALD), pulsed laser deposition (PLD), and metal-organic chemical vapor deposition (MOCVD), or liquid phase deposition methods such as solution coating and inkjet printing. The metal oxide semiconductor films deposited by any of these methods contain numerous microstructural defects, such as micropores, vacancies, dislocations, and various crystallographic defects like bond length / bond angle strain. Therefore, the resulting films are usually amorphous.
[0003] Common amorphous indium gallium zinc oxide semiconductor thin film transistors (a-IGZO TFTs) are characterized by their high electron mobility (>10 cm⁻¹). 2 With its advantages such as low power consumption, simple process, fast response speed, good large-area uniformity, and high transmittance in the visible light range, it is considered a core component of the driving circuit of Active Matrix Organic Light Emitting Diode (AMOLED) and Active Matrix Liquid Crystal Display (AMLCD). It is also considered the most competitive backplane driving technology as displays develop towards larger size, flexibility, and portability.
[0004] However, due to the aforementioned defects within amorphous metal oxide semiconductor films, these crystallographic defects provide efficient channels for the infiltration and diffusion of foreign molecules / atoms, making them more susceptible to acid corrosion and contamination by foreign substances compared to crystalline metal oxide films.
[0005] Existing metal-oxide thin-film transistors are mainly classified into coplanar type, etch stop layer (ESL) type, and back channel etch (BCE) type. Figure 1 This is a schematic diagram of a cross-sectional structure of an existing metal oxide thin-film transistor (METS). This METS is of the etch-stop layer type, such as... Figure 1 As shown, a metal-oxide-semiconductor (MOS) thin-film transistor (MTBT) includes a gate 2, a gate insulating layer 3, a MOS semiconductor layer 4, an etch barrier layer 5, and source / drain electrode layers 6 sequentially disposed on a substrate 1. First, the gate insulating layer 3 is typically made of silicon nitride. During the silicon nitride deposition process, hydrogen-containing gas is present. To prevent hydrogen diffusion from the silicon nitride, a silicon oxide layer 3a is deposited on the side of the gate insulating layer 3 closest to the MOS semiconductor layer 4. However, the isolation performance of the silicon oxide layer 3a is limited and cannot completely block hydrogen diffusion to the MOS semiconductor layer 4. Second, the source / drain electrode layers 6 typically include copper. During the patterning formation of the source / drain electrode layers 6, to prevent the etching solution from affecting the performance of the MOS semiconductor layer 4, an additional etch barrier layer 5 is required at the channel location to protect the MOS semiconductor layer 4 compared to amorphous silicon semiconductor materials. Forming this MOS thin-film transistor requires at least five film deposition processes, and at least two different materials must be deposited in the gate insulating layer 3. The entire process is complex, and it is difficult to obtain a MOS thin-film transistor with excellent driving performance. Summary of the Invention
[0006] The purpose of this invention is to provide a metal oxide thin film transistor that has a simple manufacturing process and excellent driving performance.
[0007] This invention provides a metal oxide thin-film transistor (METS), comprising a substrate and a gate formed on the substrate; the METS further comprises: a gate insulating layer formed on the substrate and covering the gate; a titanium oxide layer formed on the gate insulating layer; a source and a drain formed on the gate insulating layer, the source comprising a source bottom layer and a source top layer having the same pattern, the drain comprising a drain bottom layer and a drain top layer having the same pattern, the source bottom layer and the drain bottom layer being made of titanium, the source bottom layer and the drain bottom layer being formed in the same layer as the titanium oxide layer; the source top layer and the drain top layer being formed of a non-titanium metal layer; and a metal oxide semiconductor layer formed on the source top layer and the drain top layer, the metal oxide semiconductor layer being located between the source top layer and the drain top layer and covering a portion of the source top layer and the drain top layer, and the titanium oxide layer being located between the source top layer and the drain top layer.
[0008] Furthermore, the gate insulating layer is made of a single layer of silicon nitride.
[0009] Furthermore, the material of the non-titanium metal layer is copper or molybdenum.
[0010] The present invention also provides a method for fabricating a metal oxide thin-film transistor, comprising: forming a gate on a substrate; forming a gate insulating layer on the substrate covering the gate; sequentially depositing a titanium layer and a non-titanium metal layer on the gate insulating layer; patterning the non-titanium metal layer to form a source top layer and a drain top layer and exposing a portion of the titanium layer; doping the exposed titanium layer with oxygen ions using the source top layer and the drain top layer as protective layers to form a titanium oxide layer; and forming a metal oxide semiconductor layer over the titanium oxide layer between the source top layer and the drain top layer and covering a portion of the source top layer and the drain top layer.
[0011] Furthermore, doping the titanium layer with oxygen ions to form a titanium oxide layer includes: exposing the titanium layer to an oxygen plasma and then annealing it at a high temperature.
[0012] Furthermore, the portion of the titanium layer located below the top source electrode layer forms the bottom source electrode layer, and the bottom source electrode layer and the top source electrode layer form the source electrode; the portion of the titanium layer located below the top drain electrode layer forms the bottom drain electrode layer, and the bottom drain electrode layer and the top drain electrode layer form the drain electrode.
[0013] Furthermore, the gate insulating layer is made of a single layer of silicon nitride.
[0014] The present invention also provides an array substrate comprising the above-described metal oxide thin film transistor.
[0015] Furthermore, it also includes a first insulating protective layer, a planarization layer, a first electrode, a second insulating protective layer, and a second electrode stacked sequentially on top of the metal oxide semiconductor layer, wherein the second electrode is connected to the drain electrode via a first via.
[0016] Furthermore, the array substrate has a display area and a non-display area. The metal oxide thin film transistor is disposed in the display area. The non-display area includes a first metal layer formed on the same layer as the gate, a second metal layer formed on the same layer as the source bottom layer and the drain bottom layer, a third metal layer formed on the same layer as the source top layer and the drain top layer, and a conductive layer formed on the same layer as the second electrode. The first metal layer is connected to the second metal layer via a second via, and the third metal layer is connected to the conductive layer via a third via. The third via is located above the second via and is interconnected with it.
[0017] The metal-oxide-slim thin-film transistor, its fabrication method, and array substrate provided by this invention utilize oxygen ions to dope a titanium layer formed below the metal-oxide-semiconductor layer, creating a transparent insulating titanium oxide layer that blocks hydrogen diffusion from the gate insulating layer into the metal-oxide-semiconductor layer. This eliminates the need for an additional hydrogen diffusion barrier layer on the gate insulating layer and eliminates the need for an etch barrier layer on the metal-oxide-semiconductor layer, simplifying the fabrication process and resulting in a metal-oxide-slim thin-film transistor with excellent driving performance.
[0018] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the other objects, features and advantages of the above-mentioned metal oxide thin film transistor and its fabrication method and array substrate of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0019] Figure 1 This is a schematic diagram of the cross-sectional structure of an existing metal oxide thin-film transistor.
[0020] Figures 2a to 2f This is a schematic diagram illustrating the fabrication process of a metal oxide thin-film transistor according to a preferred embodiment of the present invention.
[0021] Figure 3 This is a schematic cross-sectional view of the array substrate according to a preferred embodiment of the present invention. Detailed Implementation
[0022] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation methods, structures, features, and effects of the metal oxide thin-film transistor and its fabrication method, as well as the array substrate, proposed according to the present invention:
[0023] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the present invention.
[0024] Figures 2a to 2f This is a schematic diagram illustrating the fabrication process of a metal-oxide-slim thin-film transistor according to a preferred embodiment of the present invention. The fabrication method of the metal-oxide-slim thin-film transistor provided in this embodiment includes:
[0025] Step S1: As Figure 2a As shown, a gate 21 is formed on the substrate 10.
[0026] Specifically, a substrate 10 is provided, which may be, for example, a transparent hard or soft substrate, and the material is not limited herein. The gate 21 can be formed on the substrate 10 by a photolithography process, which mainly includes film deposition, photoresist coating, exposure, development, etching, and photoresist removal, etc., which are well known to those skilled in the art and will not be described in detail here. The gate 21 may include one or more of molybdenum, aluminum, copper, and titanium, or may include an alloy composed of at least two of the above metals.
[0027] Step S2: As Figure 2b As shown, a gate insulating layer 30 covering the gate 21 is formed on the substrate 10.
[0028] The material of the gate insulating layer 30 can be silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x ), or silicon dioxide (SiO2), etc. x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x ) and silicon nitride (SiN) x A multilayer composite material formed by combining multiple components.
[0029] In this embodiment, to simplify the manufacturing process, the gate insulating layer 30 is preferably a single layer of silicon nitride (SiN). x Made from ( ).
[0030] Step S3: As Figure 2c As shown, a titanium layer 4a and a non-titanium metal layer 4b are sequentially deposited on the gate insulating layer 30.
[0031] Preferably, the material of the non-titanium metal layer 4b is copper or molybdenum.
[0032] Step S4: As Figure 2d As shown, the non-titanium metal layer 4b is patterned to form the source top layer 42a and the drain top layer 42b, exposing part of the titanium layer 4a.
[0033] Specifically, during the photolithography process, an etchant that does not damage the titanium layer 4a is selectively used to pattern the non-titanium metal layer 4b to form the source top layer 42a and the drain top layer 42b.
[0034] Step S5: As Figure 2e As shown, a titanium oxide layer 411 is formed by doping oxygen ions into the exposed titanium layer 4a with the source top layer 42a and the drain top layer 42b as protective layers.
[0035] Specifically, the method for forming a titanium oxide layer 411 by doping the titanium layer 4a with oxygen ions includes: exposing the titanium layer 4a to an oxygen plasma, wherein the oxygen plasma conditions are a power of 0.47 watts per square meter (W / cm²). 2 The process pressure is 200 m Torr, and then annealed at a high temperature of 280°C for 1 hour.
[0036] The titanium oxide layer 411 formed in the above steps is a transparent insulating material, and the titanium oxide layer 411 can effectively prevent hydrogen from diffusing upward in the gate insulating layer 30 made of silicon nitride material. Therefore, when making the gate insulating layer 30, the gate insulating layer 30 only needs to be made of a single layer of silicon nitride material. There is no need to set an additional silicon oxide layer to form a multi-layer structure to prevent hydrogen from diffusing upward and affecting the driving performance of the subsequently formed metal oxide semiconductor layer 50.
[0037] Protected by the source top layer 42a and drain top layer 42b, the titanium layer 4a below the source top layer 42a and drain top layer 42b is not doped with oxygen ions, maintaining its original conductivity. The portion of the titanium layer 4a located below the source top layer 42a forms the source bottom layer 41a (e.g., Figure 2f As shown), the source bottom layer 41a and the source top layer 42a form source 421 (as shown). Figure 2f (As shown); the portion of the titanium layer 4a located below the top layer 42b of the drain electrode forms the bottom layer 41b of the drain electrode (as shown). Figure 2f As shown), the bottom layer 41b and the top layer 42b of the drain form the drain 422 (as shown). Figure 2f (As shown).
[0038] Step S6: As Figure 2f As shown, a metal oxide semiconductor layer 50 is formed above the titanium oxide layer 411 between the source top layer 42a and the drain top layer 42b, and covers a portion of the source top layer 42a and the drain top layer 42b.
[0039] The metal oxide semiconductor layer 50 may optionally contain oxides of at least one or more elements selected from zinc, indium, gallium, tin, aluminum, silicon, scandium, titanium, vanadium, yttrium, zirconium, niobium, molybdenum, hafnium, tantalum, tungsten, and lanthanides. Typical metal oxide semiconductor materials include indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), and indium gallium zinc tin oxide (IGZTO). In this embodiment, the material of the metal oxide semiconductor layer 50 is amorphous indium gallium zinc oxide (IGZO).
[0040] The method for fabricating a metal-oxide-semiconductor thin-film transistor provided in this invention involves doping a titanium layer formed below the metal-oxide-semiconductor layer with oxygen ions to create a transparent, insulating titanium oxide layer that blocks hydrogen diffusion from the gate insulating layer into the metal-oxide-semiconductor layer. The gate insulating layer is made of a single layer of silicon nitride, eliminating the need for an additional barrier layer to prevent hydrogen diffusion. Furthermore, no etching barrier layer is required on the metal-oxide-semiconductor layer. This simplifies the fabrication process and yields a metal-oxide-semiconductor thin-film transistor with excellent driving performance.
[0041] The present invention also relates to a metal oxide thin film transistor, which is fabricated by the above-described method for fabricating a metal oxide thin film transistor.
[0042] Specifically, such as Figure 2f As shown, the metal oxide thin-film transistor includes:
[0043] substrate 10;
[0044] Gate 21 is formed on substrate 10;
[0045] A gate insulating layer 30 is formed on the substrate 10 and covers the gate 21;
[0046] A titanium oxide layer 411 is formed on the gate insulating layer 30;
[0047] Source 421 and drain 422 are formed on gate insulating layer 30. Source 421 includes a source bottom layer 41a and a source top layer 42a with the same pattern, and drain 422 includes a drain bottom layer 41b and a drain top layer 42b with the same pattern. The source bottom layer 41a and drain bottom layer 41b are made of titanium and are formed in the same layer as titanium oxide layer 411. The source top layer 42a and drain top layer 42b are formed of non-titanium metal layer 4b.
[0048] A metal oxide semiconductor layer 50 is formed on the source top layer 42a and the drain top layer 42b. The metal oxide semiconductor layer 50 is located between the source top layer 42a and the drain top layer 42b and covers a portion of the source top layer 42a and the drain top layer 42b, as well as the titanium oxide layer 411 located between the source top layer 42a and the drain top layer 42b.
[0049] Furthermore, the gate insulating layer 30 is made of a single layer of silicon nitride material.
[0050] Furthermore, the material of the non-titanium metal layer 4b is copper or molybdenum.
[0051] The present invention also relates to an array substrate comprising a plurality of the aforementioned metal oxide thin-film transistors. The plurality of metal oxide thin-film transistors are arranged in an array.
[0052] Furthermore, such as Figure 3 As shown, the array substrate has a display area 101 and a non-display area 102, and metal-oxide-semiconductor thin-film transistors are disposed in the display area 101. The array substrate also includes a first insulating protective layer 61, a planarization layer 62, a first electrode 63, a second insulating protective layer 64, and a second electrode 65, which are sequentially stacked above the metal-oxide-semiconductor layer 50. The second electrode 65 is connected to the drain 422 via a first via 64a, which penetrates the second insulating protective layer 64, the planarization layer 62, and the first insulating protective layer 61. In this embodiment, the first electrode 63 is a common electrode, and the second electrode 65 is a pixel electrode. The specific structure of the array substrate is well known to those skilled in the art and will not be described in detail here.
[0053] The structure of the non-display area 102 is fabricated synchronously with the structure of the display area 101. The non-display area 102 is used to fabricate driving circuits, etc. Specifically, the non-display area 102 includes a first metal layer 211 formed on the same layer as the gate 21, a second metal layer 412 formed on the same layer as the source bottom layer 41a and the drain bottom layer 41b, a third metal layer 423 formed on the same layer as the source top layer 42a and the drain top layer 42b, and a conductive layer 651 formed on the same layer as the second electrode 65. The first metal layer 211 is connected to the second metal layer 412 via a second via 30a, and the third metal layer 423 is connected to the conductive layer 651 via a third via 64b. The third via 64b is located above the second via 30a and is interconnected with it. The second via 30a is formed when fabricating the gate insulating layer 30, and the third via 64b is fabricated simultaneously with the first via 64a. This embodiment only provides a connection method for the conductive structure of the non-display area 102, but is not limited to this.
[0054] The metal oxide thin-film transistor and its fabrication method and array substrate provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A metal-oxide-slim thin-film transistor, comprising a substrate (10) and a gate (21) formed on the substrate (10), characterized in that, Also includes: A gate insulating layer (30) is formed on the substrate (10) and covers the gate (21). A titanium oxide layer (411) is formed on the gate insulating layer (30); A source electrode (421) and a drain electrode (422) are formed on the gate insulating layer (30). The source electrode (421) includes a source bottom layer (41a) and a source top layer (42a) with the same pattern. The drain electrode (422) includes a drain bottom layer (41b) and a drain top layer (42b) with the same pattern. The source bottom layer (41a) and the drain bottom layer (41b) are made of titanium. The source bottom layer (41a) and the drain bottom layer (41b) are formed in the same layer as the titanium oxide layer (411). The source top layer (42a) and the drain top layer (42b) are formed of a non-titanium metal layer (4b). as well as A metal oxide semiconductor layer (50) is formed on the source top layer (42a) and the drain top layer (42b). The metal oxide semiconductor layer (50) is located between the source top layer (42a) and the drain top layer (42b) and covers a portion of the source top layer (42a) and the drain top layer (42b) as well as the titanium oxide layer (411) located between the source top layer (42a) and the drain top layer (42b).
2. The metal oxide thin-film transistor as claimed in claim 1, characterized in that, The gate insulating layer (30) is made of a single layer of silicon nitride.
3. The metal oxide thin-film transistor as described in claim 1, characterized in that, The material of the non-titanium metal layer (4b) is copper or molybdenum.
4. A method for fabricating a metal oxide thin-film transistor, characterized in that, include: A gate (21) is formed on the substrate (10); A gate insulating layer (30) covering the gate (21) is formed on the substrate (10). A titanium layer (4a) and a non-titanium metal layer (4b) are sequentially deposited on the gate insulating layer (30). The non-titanium metal layer (4b) is patterned to form a source top layer (42a) and a drain top layer (42b) and exposes part of the titanium layer (4a). Using the source top layer (42a) and the drain top layer (42b) as protective layers, oxygen ions are doped onto the exposed titanium layer (4a) to form a titanium oxide layer (411). as well as A metal oxide semiconductor layer (50) is formed over the titanium oxide layer (411) between the source top layer (42a) and the drain top layer (42b) and covers a portion of the source top layer (42a) and the drain top layer (42b).
5. The method for fabricating a metal oxide thin-film transistor as described in claim 4, characterized in that, The process of forming a titanium oxide layer (411) by doping the titanium layer (4a) with oxygen ions includes: exposing the titanium layer (4a) to an oxygen plasma and then annealing it at a high temperature.
6. The method for fabricating a metal oxide thin-film transistor as described in claim 4, characterized in that, The portion of the titanium layer (4a) located below the source top layer (42a) forms the source bottom layer (41a), and the source bottom layer (41a) and the source top layer (42a) form the source (421); the portion of the titanium layer (4a) located below the drain top layer (42b) forms the drain bottom layer (41b), and the drain bottom layer (41b) and the drain top layer (42b) form the drain (422).
7. The method for fabricating a metal oxide thin-film transistor as described in claim 4, characterized in that, The gate insulating layer (30) is made of a single layer of silicon nitride.
8. An array substrate comprising a metal oxide thin-film transistor as described in any one of claims 1 to 3.
9. The array substrate as described in claim 8, characterized in that, It also includes a first insulating protective layer (61), a planarization layer (62), a first electrode (63), a second insulating protective layer (64), and a second electrode (65) stacked sequentially on the metal oxide semiconductor layer (50), wherein the second electrode (65) is connected to the drain (422) via a first through hole (64a).
10. The array substrate as claimed in claim 9, characterized in that, The array substrate has a display area (101) and a non-display area (102). The metal oxide thin film transistor is disposed in the display area (101). The non-display area (102) includes a first metal layer (211) formed in the same layer as the gate (21), a second metal layer (412) formed in the same layer as the source bottom layer (41a) and the drain bottom layer (41b), a third metal layer (423) formed in the same layer as the source top layer (42a) and the drain top layer (42b), and a conductive layer (651) formed in the same layer as the second electrode (65). The first metal layer (211) is connected to the second metal layer (412) via a second via (30a). The third metal layer (423) is connected to the conductive layer (651) via a third via (64b). The third via (64b) is located above the second via (30a) and is interconnected with it.