Display device

Abstract

A display device capable of preventing defects of pixels due to external electrostatic discharge includes a first pixel including a first node, a second pixel adjacent to the first pixel and including a second node, and a normally-off thin film transistor including a first electrode, a second electrode, and a gate electrode, the first electrode being connected to the first node of the first pixel, the second electrode being connected to the second node of the second pixel, wherein a cutoff voltage is applied to the gate electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0142518, filed on October 29, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] The embodiments of the present invention generally relate to a display device. Background Technology

[0004] Display devices visually display data. They are used as displays for miniaturized products such as mobile phones or tablet computers, and as displays for large products such as large-screen televisions.

[0005] The display device includes multiple pixels, each of which receives electrical signals and emits light to display an image to the outside. Each pixel includes a light-emitting element. As an example, an organic light-emitting display device includes an organic light-emitting diode (OLED) as the light-emitting element. Typically, organic light-emitting display devices operate by including thin-film transistors and organic light-emitting diodes on a substrate and allowing the organic light-emitting diodes to emit light simultaneously.

[0006] Recently, as the purposes of display devices have diversified, various designs have been attempted to improve the quality of display devices.

[0007] The information disclosed in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0008] The device constructed according to an exemplary embodiment of the present invention can solve potential problems in a display device by preventing defects in one or more pixels of the display device caused by external electrostatic discharge, which is caused by a semiconductor pattern formed in the shape of an island on a wafer or substrate.

[0009] This potential problem can be solved by forming a semiconductor pattern as a single unit on a substrate or wafer in essentially one direction, thereby dissipating any externally supplied electrostatic discharge along this one direction to the semiconductor pattern and thus reducing or eliminating any potential damage to the pixels caused by the semiconductor pattern.

[0010] One or more embodiments include a display device that can prevent pixel defects caused by external electrostatic discharge.

[0011] The technical problems addressed in this disclosure are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art.

[0012] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the inventive concept.

[0013] According to one or more embodiments, a display device includes: a first pixel including a first node; a second pixel adjacent to the first pixel and including a second node; and a normally off thin-film transistor including a first electrode, a second electrode, and a gate electrode, the first electrode being connected to the first node of the first pixel, the second electrode being connected to the second node of the second pixel, wherein a cutoff voltage is applied to the gate electrode.

[0014] The normally cut-off thin-film transistor may further include a semiconductor pattern that connects the first node to the second node.

[0015] The first pixel may further include: a first light-emitting element; a first driving thin-film transistor configured to control the current flowing through the first light-emitting element according to a first gate-source voltage; a first emission control thin-film transistor configured to connect a first node to the source of the first driving thin-film transistor in response to an emission control signal; and a first gate initialization thin-film transistor configured to apply a first initialization voltage to the gate of the first driving thin-film transistor in response to a first scan signal, wherein the driving voltage is applied to the first node.

[0016] The cutoff voltage can be the driving voltage.

[0017] The second pixel may further include: a second light-emitting element; a second driving thin-film transistor configured to control the current flowing through the second light-emitting element according to a second gate-source voltage; and a second gate initialization thin-film transistor configured to apply a first initialization voltage to the gate of the second driving thin-film transistor in response to a second scan signal, wherein the first initialization voltage is applied to the second node when the second gate initialization thin-film transistor is turned on in response to the second scan signal.

[0018] The second gate-initialized thin-film transistor may include a plurality of thin-film transistors connected in series with each other, and the second node may be arranged among the plurality of thin-film transistors.

[0019] The second node can be in a floating state when multiple thin-film transistors are turned off in response to the second scan signal.

[0020] The first pixel may further include an anode-initialized thin-film transistor configured to apply a second initialization voltage to the anode of the first light-emitting element in response to a second scan signal.

[0021] The first pixel may further include: a storage capacitor including a top electrode and a bottom electrode, a driving voltage being applied to the top electrode and the bottom electrode being connected to the gate of the first driving thin-film transistor; a scanning thin-film transistor configured to transmit a data voltage to the source of the first driving thin-film transistor in response to a third scanning signal; a compensation thin-film transistor configured to operate in response to the third scanning signal and connected between the drain and the gate of the first driving thin-film transistor; and a second emission control thin-film transistor configured to connect the drain of the first driving thin-film transistor to the anode of the first light-emitting element in response to an emission control signal.

[0022] The second pixel may further include: a second light-emitting element; a second driving thin-film transistor configured to control the current flowing through the second light-emitting element according to a second gate-source voltage; and a second gate initialization thin-film transistor configured to apply a first initialization voltage to the gate of the second driving thin-film transistor in response to a second scan signal, wherein the second node may be the source or drain of the second gate initialization thin-film transistor.

[0023] The display device may further include a data line extending in a first direction, wherein the first pixel may be adjacent to the second pixel in the first direction.

[0024] The first pixel can be electrically insulated from the second pixel by a normally cut-off thin-film transistor.

[0025] The gate electrode of a normally cut-off thin-film transistor can be connected to a first electrode, and a cut-off voltage can be applied to the first electrode.

[0026] According to one or more embodiments, a display device includes: a plurality of pixels, each arranged in a first direction and including a light-emitting element, a first node and a second node, a driving voltage being applied to the first node and a first initialization voltage being selectively applied to the second node; and a plurality of normally cut-off thin-film transistors arranged alternately with the plurality of pixels in the first direction, wherein each of the plurality of normally cut-off thin-film transistors physically connects a first node of a first pixel to a second node of a second pixel among two adjacent pixels of the plurality of pixels.

[0027] The display device may further include a semiconductor pattern extending continuously in a first direction as an integral part, wherein the semiconductor pattern may include a plurality of pixel regions and a plurality of transistor regions, the plurality of pixel regions being included in a plurality of pixels respectively, and the plurality of transistor regions being included in a plurality of normally off thin-film transistors respectively.

[0028] Each of the plurality of pixels may further include: a driving thin-film transistor configured to control the current flowing through the light-emitting element according to a gate-source voltage; a scanning thin-film transistor configured to transmit a data voltage to the driving thin-film transistor in response to a first scanning signal; and a storage capacitor including a first electrode and a second electrode, the first electrode being connected to the gate of the driving thin-film transistor.

[0029] Each of the plurality of pixels may further include a compensating thin-film transistor configured to connect the drain of a driving thin-film transistor to a gate in response to a first scan signal.

[0030] Each of the plurality of pixels may further include a gate initialization thin-film transistor configured to apply a first initialization voltage to the gate of a driving thin-film transistor in response to a second scan signal.

[0031] Each of the plurality of pixels may further include: a first emission control thin-film transistor configured to connect a first node to the source of a driving thin-film transistor in response to an emission control signal; and a second emission control thin-film transistor configured to connect the drain of a driving thin-film transistor to the anode of a light-emitting element in response to an emission control signal.

[0032] Each of the plurality of pixels may further include an anode-initialized thin-film transistor configured to apply a second initialization voltage to the anode of the light-emitting element in response to a third scan signal.

[0033] These general and specific aspects can be achieved by using systems, methods, computer programs, or a combination of systems, methods, and computer programs.

[0034] It will be understood that the foregoing general description and the following detailed description are illustrative and explanatory, and are intended to provide further illustration of the claimed invention. Attached Figure Description

[0035] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and, together with the description, serve to illustrate the inventive concept.

[0036] Figure 1 This is a block diagram of a display device constructed according to an embodiment based on the principles of the present invention.

[0037] Figure 2 This is a view of multiple pixels and multiple normally cut-off thin-film transistors according to an embodiment.

[0038] Figure 3 It is an equivalent circuit diagram of each of the plurality of pixels according to the embodiment.

[0039] Figure 4 This is a view of a semiconductor pattern of each of a plurality of pixels according to an embodiment.

[0040] Figure 5 It is an equivalent circuit diagram of each of a plurality of pixels according to another embodiment.

[0041] Figure 6 It is an equivalent circuit diagram of each of a plurality of pixels according to another embodiment.

[0042] Figure 7 It is an equivalent circuit diagram of each of a plurality of pixels according to another embodiment.

[0043] Figure 8 This is a cross-sectional view of a display device according to an embodiment. Detailed Implementation

[0044] In the following description, numerous specific details are set forth for illustrative purposes in order to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms and are non-limiting examples of apparatus or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent, however, that various embodiments may be practiced without these specific details or using one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various embodiments may be different, but are not necessarily exclusive. For example, particular shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment without departing from the inventive concept.

[0045] Unless otherwise specified, the illustrated embodiments are to be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0046] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, scale, commonalities between illustrated elements, and / or any other characteristics, properties, or characteristics of the elements. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. A particular process sequence may be performed differently than is described when embodiments can be implemented differently. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals denote the same elements.

[0047] When a component or layer is referred to as being "on," "connected to," or "coupled to" another component or layer, it can be directly on, connected to, or coupled to the other component or layer, or an intermediary component or layer may be present. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another component or layer, an intermediary component or layer is not present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediary component. Furthermore, the DR1, DR2, and DR3 axes are not limited to the three axes of a Cartesian coordinate system, such as the x-axis, y-axis, and z-axis, and can be interpreted in a broader sense. For example, the DR1, DR2, and DR3 axes can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0048] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0049] Spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes and thus describe the relationship of one element to another(s) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to cover different orientations of the apparatus in use, operation, and / or manufacture. For example, if the apparatus in the drawings is flipped, an element described as “below” or “under” other elements or features will then be oriented “above” other elements or features. Therefore, the term “below” can include both above and below orientations. Furthermore, the apparatus may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments and is not restrictive. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprising,” “including,” and variations thereof specify the presence of said features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to explain the inherent biases in measurements, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0051] This document describes various embodiments with reference to cross-sectional views and / or exploded views, which are schematic diagrams of idealized embodiments and / or intermediate structures. Therefore, variations in shape are expected as a result of, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments disclosed herein are not necessarily to be interpreted as limited to the shape of the specific areas shown, but rather include shape deviations caused, for example, by manufacturing processes. In this way, the areas shown in the figures can be schematic in nature, and the shapes of these areas may not reflect the actual shape of the areas of the device, and are therefore not necessarily intended to be limiting.

[0052] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense.

[0053] Figure 1 This is a block diagram of a display device according to an embodiment. The display device may be an organic light-emitting display device 100, which includes a light-emitting element, such as an organic light-emitting diode, whose brightness is changed by an electric current. The following mainly describes the case where the display device is an organic light-emitting display device 100.

[0054] refer to Figure 1 The organic light-emitting display device 100, which serves as a display device, includes a display unit 110, a gate driver 120, a data driver 130, a timing controller 140, and a voltage generator 150.

[0055] The display unit 110 includes pixels PX, which are arranged in the i-th row and j-th column. ij .although Figure 1 For ease of understanding, only one pixel (PX) is shown. ij However, m×n pixels PX can be arranged, for example, in a matrix configuration. Here, i is a natural number equal to or greater than 1 and equal to or less than m (i.e., an integer value). j is a natural number equal to or greater than 1 and equal to or less than n (i.e., an integer value).

[0056] For ease of description only, for reference only. Figure 1 The pixel PX is described as including seven transistors and one capacitor. However, the embodiments described herein are not limited to this, and the pixel PX may employ another pixel circuit, such as a pixel circuit including two transistors and one capacitor.

[0057] Pixel PX is connected to the first scan lines SL1_1 to SL1_m, the second scan lines SL2_1 to SL2_m+1, the transmit control lines EML_1 to EML_m, and the data lines DL_1 to DL_n. Pixel PX is also connected to the power lines PL_1 to PL_n, the first voltage lines VL1_1 to VL1_m, and the second voltage lines VL2_1 to VL2_m. As an example, such as... Figure 1 As shown, pixels PX are arranged in the i-th row and j-th column. ij It can be connected to the first scan line SL1_i, the second scan line SL2_i, the transmit control line EML_i, the data line DL_j, the power line PL_j, the first voltage line VL1_i, the second voltage line VL2_i, and the second scan line SL2_i+1. This applies to pixel PX. ij The second scan line SL2_i+1 can be represented by the third scan line.

[0058] As another example, pixel PX ijIt can be connected to one or more of the following: first scan line SL1_i, second scan line SL2_i, transmit control line EML_i, data line DL_j, power line PL_j, first voltage line VL1_i, second voltage line VL2_i, and second scan line SL2_i+1. As an example, pixel PX... ij It can be connected to the first scan line SL1_i, the data line DL_j, and the power line PL_j.

[0059] Data lines DL_1 to DL_n and power lines PL_1 to PL_n can extend along the first direction DR1 and connect to pixels PX in the same column. First scan lines SL1_1 to SL1_m, second scan lines SL2_1 to SL2_m+1, transmit control lines EML_1 to EML_m, first voltage lines VL1_1 to VL1_m, and second voltage lines VL2_1 to VL2_m can extend along the second direction DR2 and connect to pixels PX in the same row.

[0060] Each of the first scan lines SL1_1 to SL1_m is configured to transmit first scan signals GW_1 to GW_m output from gate driver 120 to pixels PX in the same row. Each of the second scan lines SL2_1 to SL2_m is configured to transmit second scan signals GI_1 to GI_m output from gate driver 120 to pixels PX in the same row. Each of the second scan lines SL2_2 to SL2_m+1 is configured to transmit third scan signals GB_1 to GB_m output from gate driver 120 to pixels PX in the same row. The second scan signal GI_i and the third scan signal GB_i-1 can be the same signal transmitted through the second scan line SL2_i.

[0061] Each of the transmit control lines EML_1 to EML_m is configured to transmit the transmit control signals EM_1 to EM_m output from the gate driver 120 to the pixel PX in the same row. Each of the data lines DL_1 to DL_n is configured to transmit the data voltages Dm_1 to Dm_n output from the data driver 130 to the pixel PX in the same column. Pixel PX arranged in the i-th row and j-th column. ij It is configured to receive the first to third scan signals GW_i, GI_i and GB_i, the data voltage Dm_j and the transmit control signal EM_i.

[0062] Each of the power lines PL_1 to PL_n is configured to transmit the first drive voltage ELVDD output from the voltage generator 150 to a pixel PX in the same column. Each of the first voltage lines VL1_1 to VL1_m is configured to transmit the first initialization voltage VINT1 output from the voltage generator 150 to a pixel PX in the same row. Each of the second voltage lines VL2_1 to VL2_m is configured to transmit the second initialization voltage VINT2 output from the voltage generator 150 to a pixel PX in the same row.

[0063] As another example, the first driving voltage ELVDD can be transmitted to the pixel PX in the same row via a power line extending in the second direction DR2. As another example, the first initialization voltage VINT1 can be transmitted to the pixel PX in the same column via a first voltage line extending in the first direction DR1. As another example, the second initialization voltage VINT2 can be transmitted to the pixel PX in the same column via a second voltage line extending in the first direction DR1.

[0064] Pixel PX ij It includes a light-emitting element and a driving thin-film transistor (TFT). The driving TFT is configured to control the magnitude of the current flowing through the light-emitting element based on the data voltage Dm_j. The data voltage Dm_j is output from the data driver 130 and transmitted to pixel PX via data line DL_j. ij Reception. The light-emitting element can be, for example, an organic light-emitting diode (OLED). Because the light-emitting element emits light corresponding to the magnitude of the current received from the driving thin-film transistor, the pixel PX... ij It can display grayscale corresponding to the data voltage Dm_j. Pixel PX can correspond to a portion (e.g., a subpixel) of a unit pixel that can display full color. ij It may further include at least one switching thin-film transistor and at least one capacitor. The pixel PX is described in more detail below. ij .

[0065] Voltage generator 150 can generate voltage for driving pixels PX ij The required voltage. As an example, voltage generator 150 can be configured to generate a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2. The level of the first driving voltage ELVDD can be greater than the level of the second driving voltage ELVSS. The level of the second initialization voltage VINT2 can be greater than the level of the first initialization voltage VINT1. The level of the second initialization voltage VINT2 can be greater than the level of the second driving voltage ELVSS. The difference between the second initialization voltage VINT2 and the second driving voltage ELVSS can be less than the threshold voltage required for the light-emitting element of pixel PX to emit light.

[0066] Voltage generator 150 can generate voltages used to control pixels PX. ij The first gate voltage VGH and the second gate voltage VGL of the switching thin-film transistor are provided to the gate driver 120. When the first gate voltage VGH is applied to the gate of the switching thin-film transistor, the switching thin-film transistor is turned off, and when the second gate voltage VGL is applied to the gate of the switching thin-film transistor, the switching thin-film transistor can be turned on. The first gate voltage VGH can be represented by the off voltage, and the second gate voltage VGL can be represented by the on voltage. Pixel PX ij The switching thin-film transistor can be a p-type metal-oxide-semiconductor field-effect transistor (MOSFET), and the level of the first gate voltage VGH can be greater than the level of the second gate voltage VGL. The voltage generator 150 can generate a gamma reference voltage and provide it to the data driver 130.

[0067] The timing controller 140 can control the display unit 110 by controlling the timing of the gate driver 120 and the data driver 130. The pixels PX of the display unit 110 can receive a new data voltage Dm each frame and emit light corresponding to the data voltage Dm to display an image corresponding to the image source data RGB of a frame.

[0068] In an embodiment, a frame period may include a gate initialization period, a data writing and anode initialization period, and a light emission period. During the gate initialization period, a first initialization voltage VINT1 may be applied to pixel PX synchronously with a second scan signal GI. During the data writing and anode initialization period, a data voltage Dm may be applied to pixel PX synchronously with a first scan signal GW, and a second initialization voltage VINT2 may be applied to pixel PX synchronously with a third scan signal GB. During the light emission period, pixel PX of display unit 110 emits light.

[0069] Timing controller 140 is configured to receive image source data RGB and control signal CONT from an external source. Timing controller 140 can be configured to convert the image source data RGB into image data DATA based on the characteristics of display unit 110 and pixel PX. Timing controller 140 can be configured to provide the image data DATA to data driver 130.

[0070] The control signal CONT may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. The timing controller 140 can control the operating timing of the gate driver 120 and the data driver 130 using the control signal CONT. The timing controller 140 can determine the frame period by counting the data enable signal DE during the horizontal scan period. In this case, the externally supplied vertical synchronization signal Vsync and horizontal synchronization signal Hsync can be omitted. The image source data RGB includes the brightness information of the pixel PX. The brightness can have a predetermined number of gray levels, for example, 1024 (=2). 10 ), 256 (=2 8 ) or 64 (=2 6 ).

[0071] The timing controller 140 can generate control signals including a gate timing control signal GDC for controlling the operating timing of the gate driver 120 and a data timing control signal DDC for controlling the operating timing of the data driver 130.

[0072] The gate timing control signal GDC may include a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE) signal. GSP is supplied to gate driver 120 to generate a first scan signal at the start of a scan period. GSC is a clock signal commonly input to gate driver 120 and is used to shift GSP. The GOE signal is configured to control the output of gate driver 120.

[0073] The Data Timing Control (DDC) signal may include a Source Start Pulse (SSP), a Source Sample Clock (SSC), and a Source Output Enable (SOE) signal. The SSP controls the data sampling start point of the data driver 130 and is provided to the data driver 130 at the beginning of the scan period. The SSC is a clock signal that controls the sampling operation of data within the data driver 130 based on the rising or falling edge of a clock signal. The SOE signal is configured to control the output of the data driver 130. Depending on the data transmission method, the SSP supplied to the data driver 130 may be omitted.

[0074] The gate driver 120 is configured to sequentially generate first scan signals GW_1 to GW_m, second scan signals GI_1 to GI_m, and third scan signals GB_1 to GB_m in response to a gate timing control signal GDC supplied from the timing controller 140 by using a first gate voltage VGH and a second gate voltage VGL provided from the voltage generator 150.

[0075] Data driver 130 samples and latches image data DATA in response to data timing control signals DDC supplied from timing controller 140 to convert it into data for a parallel data system. When converting the image data into data for the parallel data system, data driver 130 converts the image data DATA into a gamma reference voltage, thereby converting the image data DATA into a data voltage in analog form. Data driver 130 provides data voltages Dm_1 to Dm_n to pixel PX via data lines DL_1 to DL_n. Pixel PX receives data voltages Dm_1 to Dm_n in response to first scan signals GW_1 to GW_m.

[0076] Figure 2 This is a view of multiple pixels and multiple normally cut-off thin-film transistors (AFTs) according to an embodiment.

[0077] refer to Figure 2 The display unit 110 of the organic light-emitting display device 100 includes pixels PX, for example, pixels PX arranged in the i-th row and j-th column. ij Pixels PX can be arranged in a first direction DR1 and a second direction DR2 that is substantially orthogonal to the first direction DR1. As an example, pixels PX can be arranged in a matrix configuration.

[0078] In this embodiment, multiple normally-off thin-film transistors (AFTs) can be alternately arranged between pixels PX arranged in the first direction DR1. Pixels PX in the same column can be physically connected to each other through multiple normally-off thin-film transistors (AFTs). As an example, such as Figure 2 As shown, multiple constant-cut-off thin-film transistors (AFTs) can be alternately arranged between pixels PX arranged in the j-th column.

[0079] Each pixel PX can include a first node N1 and a second node N2. In this case, the first node N1 can be the first driving voltage ELVDD (see...). Figure 1 The node to which the first initialization voltage VINT1 is applied. The second node N2 can be the node to which the first initialization voltage VINT1 is applied (see...). Figure 1 The node to which the initial voltage VINT1 is selectively applied, or the node to which the initial voltage VINT1 is always applied. This is described in more detail below.

[0080] Multiple normally cut-off thin-film transistors (AFTs) can be arranged between two adjacent pixels PX. Each of the multiple normally cut-off thin-film transistors (AFTs) can connect the first node N1 of one of the two adjacent pixels PX to the second node N2 of the other pixel PX.

[0081] As an example, pixel PX in row (i-2) and column j.(i-2)j The pixel PX in the (i-1)th row and the jth column (i-1)j Pixel PX in row i and column j ij The pixel PX in the (i+1)th row and the jth column (i+1)j and the pixel PX in row (i+2) and column j. (i+2)j It can be arranged on the first direction DR1. Pixel PX (i-2)j Pixel PX (i-1)j Pixel PX ij Pixel PX (i+1)j and pixel PX (i+2)j Each can include a first node N1 and a second node N2.

[0082] Multiple normally cut-off thin-film transistors (AFTs) can be alternately arranged in a pixel (PX). (i-2)j Pixel PX (i-1)j Pixel PX ij Pixel PX (i+1)j and pixel PX (i+2)j Between. One of multiple constant-cut-off thin-film transistors (AFTs) can be arranged in pixel PX. (i-2)j With pixel PX (i-1)j Between. Another of the multiple normally cut-off thin-film transistors (AFTs) can be arranged in pixel PX. (i-1)j With pixel PX ij Between. Another of the multiple normally cut-off thin-film transistors (AFTs) can be arranged in pixel PX. ij With pixel PX (i+1)j Between. Another of the multiple normally cut-off thin-film transistors (AFTs) can be arranged in pixel PX. (i+1)j With pixel PX (i+2)j between.

[0083] like Figure 2 As shown, pixel PX (i-2)j The first node N1 is connected to pixel PX via a normally cut-off thin-film transistor AFT. (i-1)j The second node N2. Pixel PX (i-1)j The first node N1 is connected to pixel PX via a normally cut-off thin-film transistor AFT. ij The second node N2. Pixel PX ij The first node N1 is connected to pixel PX via a normally cut-off thin-film transistor AFT. (i+1)j The second node N2. Pixel PX (i+1)j The first node N1 is connected to pixel PX via a normally cut-off thin-film transistor AFT. (i+2)j The second node N2.

[0084] In an embodiment, the normally-off thin-film transistor AFT may include a first electrode E1, a second electrode E2, and a gate electrode G. The first electrode E1 is connected to a first node N1, and the second electrode E2 is connected to a second node N2. A cutoff voltage TFV can be applied to the gate electrode G of the normally-off thin-film transistor AFT. When the cutoff voltage TFV is applied to the gate electrode G, the normally-off thin-film transistor AFT can always be off. Here, "normally" can mean that the normally-off thin-film transistor AFT is off when the organic light-emitting display device 100 is turned on. When the organic light-emitting display device 100 is operating, the first electrode E1 of the normally-off thin-film transistor AFT can be electrically insulated from the second electrode E2.

[0085] Because the Always-on Cut-off (AFT) thin-film transistor can always be cut off, it can physically connect adjacent pixels PX, but electrically insulate adjacent pixels PX from each other. As an example, the AFT can physically connect the first node N1 of one of two adjacent pixels PX to the second node N2 of the other pixel PX, but can electrically insulate the first node N1 of one of two adjacent pixels PX from the second node N2 of the other pixel PX.

[0086] although Figure 2 The diagram illustrates a normally-off thin-film transistor (AFT) comprising a single thin-film transistor, but an AFT may include at least two thin-film transistors connected in series with each other. A cutoff voltage may be applied jointly to the gate electrodes of the at least two thin-film transistors connected in series with each other. In the case where the normally-off thin-film transistor AFT connected between a first node N1 and a second node N2 comprises multiple thin-film transistors connected in series with each other, the amount of leakage current flowing through the normally-off thin-film transistor AFT between the first node N1 and the second node N2 can be reduced or even further, and voltages with a high potential difference can be applied to the first node N1 and the second node N2 respectively. As an example, a first drive voltage ELVDD may be applied to the first node N1, and a first initialization voltage VINT1 may be applied to the second node N2. Even in this case, the first node N1 may be sufficiently electrically insulated from the second node N2.

[0087] Figure 3 It is an equivalent circuit diagram of each of the plurality of pixels according to the embodiment.

[0088] Figure 3 The pixel PX in the i-th row and j-th column is shown. ij (Hereinafter referred to as the first pixel) and the pixel PX in the (i+1)th row and jth column. (i+1)j (Hereinafter referred to as the second pixel). First pixel PX ij Second pixel PX(i+1)j They are adjacent to each other and arranged in the same column, and can be connected to the same data line DL_j.

[0089] In an embodiment, a normally cut-off thin-film transistor (AFT) can be disposed on a first pixel PX disposed on a first direction DR1. ij With the second pixel PX (i+1)j Between. First pixel PX ij Second pixel PX (i+1)j Each node can include a first node N1 and a second node N2. In this case, the first node N1 can be the node to which the first drive voltage ELVDD is applied. The second node N2 can be the node to which the first initialization voltage VINT1 is selectively applied.

[0090] In an embodiment, the normally-off thin-film transistor AFT may include a first electrode E1, a second electrode E2, and a gate electrode G. The first electrode E1 is connected to a first node N1, and the second electrode E2 is connected to a second node N2. A cutoff voltage TFV can be applied to the gate electrode G of the normally-off thin-film transistor AFT. When the cutoff voltage TFV is applied to the gate electrode G, the normally-off thin-film transistor AFT can always be turned off.

[0091] The constant cutoff thin-film transistor AFT can convert the first pixel PX ij The first node N1 is connected to the second pixel PX (i+1)j The second node N2. Since the always-off thin-film transistor AFT can always be off, the always-off thin-film transistor AFT can turn the first pixel PX... ij The first node N1 is physically connected to the second pixel PX (i+1)j The second node N2. The normally cut-off thin-film transistor AFT connects the first pixel PX. ij Physically connected to the second pixel PX (i+1)j However, the first pixel PX ij The second pixel PX can be connected via a normally cut-off thin-film transistor AFT. (i+1)j Electrical insulation.

[0092] although Figure 3 The diagram shows a normally cut-off thin-film transistor (AFT) comprising a single thin-film transistor, but an AFT may comprise at least two thin-film transistors connected in series with each other.

[0093] refer to Figure 3 The first pixel PX ijConnected to the first to third scan lines GWL_i, GIL_i, and GBL_i, the data line DL_j, and the transmit control line EML_i, the first to third scan lines GWL_i, GIL_i, and GBL_i transmit the first to third scan signals GW_i, GI_i, and GB_i, respectively. The data line DL_j transmits the data voltage Dm_j, and the transmit control line EML_i transmits the transmit control signal EM_i. First pixel PX ij Connected to power line PL_j, first voltage line VL1_i, and second voltage line VL2_i, power line PL_j transmits the first driving voltage ELVDD, first voltage line VL1_i transmits the first initialization voltage VINT1, and second voltage line VL2_i transmits the second initialization voltage VINT2. First pixel PX ij Connected to the common electrode to which the second driving voltage ELVSS is applied. First pixel PX ij Can be with Figure 1 First pixel PX ij Correspondingly.

[0094] The first scan line GGL_i and Figure 1 The first scan line SL1_i corresponds to the second scan line GIL_i. Figure 1 The second scan line SL2_i corresponds to the third scan line GBL_i. Figure 1 The second scan line SL2_i+1 corresponds to this.

[0095] Second pixel PX (i+1)j Connected to the first to third scan lines GWL_i+1, GIL_i+1, and GBL_i+1, the data line DL_j, and the transmit control line EML_i+1, the first to third scan lines GWL_i+1, GIL_i+1, and GBL_i+1 transmit the first to third scan signals GW_i+1, GI_i+1, and GB_i+1, respectively. The data line DL_j transmits the data voltage Dm_j, and the transmit control line EML_i+1 transmits the transmit control signal EM_i+1. The second pixel PX (i+1)j Connected to power line PL_j, first voltage line VL1_i+1, and second voltage line VL2_i+1, power line PL_j transmits the first driving voltage ELVDD, first voltage line VL1_i+1 transmits the first initialization voltage VINT1, and second voltage line VL2_i+1 transmits the second initialization voltage VINT2. Second pixel PX (i+1)j Connected to the common electrode to which the second drive voltage ELVSS is applied. The second scan line GIL_i+1 is... Figure 1 This corresponds to the second scan line SL2_i+1. For the first pixel PX... ijThe second scan line GIL_i+1 can be represented by the third scan line GBL_i.

[0096] In the following text, the first pixel PX ij Second pixel PX (i+1)j The components included are described. Because the first pixel PX ij The equivalent circuit diagram also applies to the second pixel PX. (i+1)j Therefore, for the first pixel PX used as a reference ij Describe it.

[0097] First pixel PX ij It includes a light-emitting element (OLED), first to seventh thin-film transistors (T1, T2, T3, T4, T5, T6, and T7), and a storage capacitor Cst. The light-emitting element (OLED) can be an organic light-emitting diode having an anode and a cathode. The cathode can be a common electrode to which a second driving voltage ELVSS is applied.

[0098] The first thin-film transistor T1 can be a driving transistor in which the magnitude of the drain current is determined according to the gate-source voltage, and the second to seventh thin-film transistors T2, T3, T4, T5, T6, and T7 can be switching transistors that are turned on / off according to the gate-source voltage (basically the gate voltage). The third thin-film transistor T3 includes a first compensation thin-film transistor T3a and a second compensation thin-film transistor T3b connected in series with each other. The fourth thin-film transistor T4 includes a first gate initialization thin-film transistor T4a and a second gate initialization thin-film transistor T4b connected in series with each other.

[0099] The first thin-film transistor T1 can be represented by a driving thin-film transistor, the second thin-film transistor T2 can be represented by a scanning thin-film transistor, the third thin-film transistor T3 can be represented by a compensation thin-film transistor, the fourth thin-film transistor T4 can be represented by a gate initialization thin-film transistor, the fifth thin-film transistor T5 can be represented by a first emitter control thin-film transistor, the sixth thin-film transistor T6 can be represented by a second emitter control thin-film transistor, and the seventh thin-film transistor T7 can be represented by an anode initialization thin-film transistor.

[0100] A storage capacitor Cst is connected between the power line PL_j and the gate of the driving thin-film transistor T1. The storage capacitor Cst may include a top electrode CE2 and a bottom electrode CE1, with the top electrode CE2 connected to the power line PL_j and the bottom electrode CE1 connected to the gate of the driving thin-film transistor T1.

[0101] The driving thin-film transistor T1 can control the magnitude of the driving current Id flowing from the power line PL_j to the light-emitting element OLED. The driving thin-film transistor T1 may include a gate, a source S, and a drain D. The gate is connected to the bottom electrode CE1 of the storage capacitor Cst, the source S is connected to the power line PL_j through a first emitter control thin-film transistor T5, and the drain D is connected to the light-emitting element OLED through a second emitter control thin-film transistor T6.

[0102] The driving thin-film transistor T1 can output a driving current Id to the light-emitting element OLED based on the gate-source voltage. The magnitude of the driving current Id is determined based on the difference between the gate-source voltage and the threshold voltage of the driving thin-film transistor T1. The light-emitting element OLED can receive the driving current Id from the driving thin-film transistor T1 and emit light with a brightness corresponding to the magnitude of the driving current Id.

[0103] The scanning thin-film transistor T2 is configured to transmit a data voltage Dm_j to the source S of the driving thin-film transistor T1 in response to a first scan signal GW_i. The scanning thin-film transistor T2 may include a gate, a source S, and a drain D, with the gate connected to the first scan line GWL_i, the source S connected to the data line DL_j, and the drain D connected to the source S of the driving thin-film transistor T1.

[0104] A first compensation thin-film transistor T3a and a second compensation thin-film transistor T3b are connected between the drain D and gate of the driving thin-film transistor T1, and the drain D of the driving thin-film transistor T1 is connected to the gate in response to a first scan signal GW_i. The first compensation thin-film transistor T3a may include a gate, a source S, and a drain D. The gate is connected to the first scan line GWL_i, the source S is connected to the second compensation thin-film transistor T3b, and the drain D is connected to the gate of the driving thin-film transistor T1. The second compensation thin-film transistor T3b may include a gate, a source S, and a drain D. The gate is connected to the first scan line GWL_i, the source S is connected to the drain D of the driving thin-film transistor T1, and the drain D is connected to the source S of the first compensation thin-film transistor T3a. Although... Figure 3 The diagram shows that the compensation thin-film transistor T3 includes two thin-film transistors T3a and T3b connected in series, but the compensation thin-film transistor T3 may include a single thin-film transistor.

[0105] In response to the second scan signal GI_i, the gate-initialized thin-film transistor T4 applies a first initialization voltage VINT1 to the gate of the driving thin-film transistor T1. The gate-initialized thin-film transistor T4 may include a gate, a source, and a drain. The gate is connected to the second scan line GIL_i, the source is connected to the gate of the driving thin-film transistor T1, and the drain is connected to the first voltage line VL1_i.

[0106] like Figure 3 As shown, the gate-initialized thin-film transistor T4 may include a first gate-initialized thin-film transistor T4a and a second gate-initialized thin-film transistor T4b connected in series between the gate of the driving thin-film transistor T1 and the first voltage line VL1_i. The node between the first gate-initialized thin-film transistor T4a and the second gate-initialized thin-film transistor T4b is represented by a second node N2. The first gate-initialized thin-film transistor T4a may include a gate, a source S, and a drain D. The gate is connected to the second scan line GIL_i, the source S is connected to the gate of the driving thin-film transistor T1, and the drain D is connected to the second node N2. The second gate-initialized thin-film transistor T4b may include a gate, a source S, and a drain D. The gate is connected to the second scan line GIL_i, the source S is connected to the second node N2, and the drain D is connected to the first voltage line VL1_i. The second node N2 may be either the source or the drain of the gate-initialized thin-film transistor T4.

[0107] When the second gate initialization thin-film transistor T4b is turned on in response to the second scan signal GI_i, the first initialization voltage VINT1 can be applied to the second node N2. The first initialization voltage VINT1 can be selectively applied to the second node N2.

[0108] although Figure 3 The diagram illustrates a gate-initialized thin-film transistor T4 comprising two thin-film transistors T4a and T4b connected in series, but the gate-initialized thin-film transistor T4 may include three or more thin-film transistors connected in series. In this case, a second node N2 may be arranged among the multiple gate-initialized thin-film transistors T4. The second node N2 may be the source or drain of the gate-initialized thin-film transistor T4.

[0109] As another example, the gate-initialized thin-film transistor T4 may include a thin-film transistor. This is described in more detail below.

[0110] When the gate initialization thin-film transistor T4 is turned off in response to the second scan signal GI_i+1, the second pixel PX (i+1)j The second node N2 can be in a floating state. Because the second pixel PX (i+1)j The second node N2 is positioned between the always-off thin-film transistor AFT and the off-gate initialization thin-film transistor T4, so the second pixel PX (i+1)j The second node N2 can be in a floating state.

[0111] The anode initialization thin-film transistor T7 is configured to apply a second initialization voltage VINT2 to the light-emitting element OLED in response to a third scan signal GB_i. The anode initialization thin-film transistor T7 may include a gate, a source S, and a drain D. The gate is connected to the third scan line GBL_i, the source S is connected to the anode of the light-emitting element OLED, and the drain D is connected to the second voltage line VL2_i.

[0112] The first emitter control thin-film transistor T5 can be configured to connect the power line PL_j to the source S of the driving thin-film transistor T1 in response to the emitter control signal EM_i. The node between the first emitter control thin-film transistor T5 and the power line PL_j is represented by a first node N1. The first emitter control thin-film transistor T5 may include a gate, a source S, and a drain D. The gate is connected to the emitter control line EML_i, the source S is connected to the first node N1, and the drain D is connected to the source S of the driving thin-film transistor T1. Because the first node N1 is connected to the power line PL_j, a first drive voltage ELVDD can be applied to the first node N1.

[0113] The second emission control thin-film transistor T6 can connect the drain D of the driving thin-film transistor T1 to the anode of the light-emitting element OLED in response to the emission control signal EM_i. The second emission control thin-film transistor T6 may include a gate, a source S, and a drain D. The gate is connected to the emission control line EML_i, the source S is connected to the drain D of the driving thin-film transistor T1, and the drain D is connected to the anode of the light-emitting element OLED.

[0114] The second scan signal GI_i can be substantially synchronized with the first scan signal GW_i-1 in the previous row. The third scan signal GB_i can be substantially synchronized with the first scan signal GW_i. According to another example, the third scan signal GB_i can be substantially synchronized with the first scan signal GW_i+1 in the next row.

[0115] The specific operation process of a pixel of the organic light-emitting display device according to the embodiment is described in detail below.

[0116] First, when a high-level transmit control signal EM_i is received, the first transmit control thin-film transistor T5 and the second transmit control thin-film transistor T6 are turned off, driving thin-film transistor T1 to stop outputting the drive current Id, and the light-emitting element OLED stops emitting light.

[0117] Then, during the gate initialization period in which the second scan signal GI_i is received at a low level, the gate initialization thin-film transistor T4 is turned on, and the first initialization voltage VINT1 is applied to the gate of the driving thin-film transistor T1, i.e., the bottom electrode CE1 of the storage capacitor Cst. The difference ELVDD-VINT1 between the first driving voltage ELVDD and the first initialization voltage VINT1 is stored in the storage capacitor Cst.

[0118] Then, during the data writing period when the first scan signal GW_i is low, scan TFT T2 and compensation TFT T3 are turned on, and the data voltage Dm_j is received by the source S of drive TFT T1. Drive TFT T1 is diode-connected and forward biased by compensation TFT T3. The gate voltage of drive TFT T1 rises from the first initialization voltage VINT1. When the gate voltage of drive TFT T1 becomes the data compensation voltage Dm_j-|Vth|, which is lower than the threshold voltage Vth of drive TFT T1 from the data voltage Dm_j, drive TFT T1 is turned off, and the rise of the gate voltage of drive TFT T1 stops. Therefore, the difference ELVDD – Dm_j+|Vth| between the first drive voltage ELVDD and the data compensation voltage Dm_j-|Vth| is stored in the storage capacitor Cst.

[0119] Additionally, during the anode initialization period when the third scan signal GB_i is received at a low level, the anode initialization thin-film transistor T7 is turned on, and the second initialization voltage VINT2 is applied to the anode of the OLED. Because the OLED does not fully emit light by applying the second initialization voltage VINT2 to its anode, the phenomenon of the OLED subtly emitting light to correspond to black grayscale during the next frame can be eliminated.

[0120] The level of the second initialization voltage VINT2 can be greater than the level of the first initialization voltage VINT1, and lower than the threshold voltage of the OLED, which is greater than the second driving voltage ELVSS. Because the OLED has a relatively large size, it has a considerable capacitance. Furthermore, because the level of the first initialization voltage VINT1 is too low, the OLED begins to emit light only after a considerable delay in the next frame. Conversely, according to this embodiment, the anode of the OLED is initialized using a second initialization voltage VINT2 with a level greater than that of the first initialization voltage VINT1, and therefore, the OLED can begin to emit light in a short time in the next frame. That is, the light emission delay problem can be solved.

[0121] The first scan signal GW_i can be synchronized with the third scan signal GB_i. In this case, the data writing period can coincide with the anode initialization period.

[0122] First, when a low-level transmit control signal EM_i is received, the first transmit control thin-film transistor T5 and the second transmit control thin-film transistor T6 are turned on, and the thin-film transistor T1 is driven to output a drive current Id. The light-emitting element OLED can emit light with a brightness corresponding to the magnitude of the drive current Id. The drive current Id corresponds to the voltage stored in the storage capacitor Cst (i.e., the voltage ELVDD-Dm_j obtained by subtracting the threshold voltage |Vth| of the driving thin-film transistor T1 from the source-gate voltage ELVDD–Dm_j+|Vth|).

[0123] Figure 4 This is a view of a semiconductor pattern of each of a plurality of pixels according to an embodiment.

[0124] refer to Figure 4 The display unit 110 of the organic light-emitting display device 100 includes a semiconductor pattern A.

[0125] Semiconductor pattern A can extend continuously in the first direction DR1. Semiconductor pattern A can extend continuously in the first direction DR1 to form a single unit. Although Figure 4 The semiconductor pattern A shown extends partially along the second direction DR2, but reference... Figure 2 Because semiconductor pattern A is used to form a column of pixels PX and normally cut-off thin-film transistors AFT connected therebetween, semiconductor pattern A generally extends in the first direction DR1. That is, although semiconductor pattern A includes a portion extending in the second direction DR2, semiconductor pattern A generally extends in the first direction DR1.

[0126] Semiconductor pattern A may include multiple pixel regions A ij and A (i+1)j and alternately arranged in multiple pixel regions A ij and A (i+1)j Multiple transistor regions A between AFT .

[0127] Multiple pixel regions A ij and A (i+1)j Each of them can be included in multiple pixels (PX). ij and PX (i+1)j In, and multiple transistor regions A AFT Each of these can be included in multiple normally cut-off thin-film transistors (AFTs). As an example, the first pixel region A... ijIt can be included in the first pixel PX ij In the middle. Second pixel region A (i+1)j It can be included in the second pixel PX (i+1)j In the middle. Transistor region A AFT It can be included in a normally cut-off thin-film transistor (AFT).

[0128] Transistor region A AFT The first pixel region A can be ij The first node N1 is physically connected to the second pixel region A (i+1)j The second node N2.

[0129] As a comparative example, the semiconductor pattern may not extend continuously in the first direction and may have an island shape. The semiconductor patterns included in multiple pixels may not be connected to each other. After the semiconductor pattern is formed, electrostatic discharge (ESD) may occur from the outside due to subsequent processing. When the semiconductor patterns are not connected to each other, the ESD may be isolated inside the semiconductor pattern. Therefore, the semiconductor pattern affected by ESD is damaged, and the damaged semiconductor pattern results in defective pixels.

[0130] However, according to the embodiment, when the semiconductor pattern A extends continuously in the first direction DR1, electrostatic discharge occurring from the outside can be distributed in the first direction DR1 without being isolated. Therefore, since the electrostatic discharge can be distributed inside the semiconductor pattern A in the first direction DR1, damage to the semiconductor pattern A can be prevented.

[0131] Figure 5 This is an equivalent circuit diagram for each of a plurality of pixels according to another embodiment. Figure 5 In, with Figure 3 Those figures with the same reference numerals denote the same components, and therefore their repeated descriptions are omitted.

[0132] refer to Figure 5 The normally cut-off thin-film transistor AFT can be arranged on the first pixel PX arranged in the first direction DR1. ij With the second pixel PX (i+1)j Between. First pixel PX ij Second pixel PX (i+1)j Each of these can include a first node N1 and a second node N2. In this case, a first drive voltage ELVDD can be applied to the first node N1. A first initialization voltage VINT1 can be selectively applied to the second node N2.

[0133] The normally-off thin-film transistor (AFT) may include a first electrode E1, a second electrode E2, and a gate electrode G. The first electrode E1 is connected to a first node N1, and the second electrode E2 is connected to a second node N2. A first driving voltage ELVDD, which serves as the cutoff voltage TFV, can be applied to the gate electrode G of the normally-off thin-film transistor AFT. When the first driving voltage ELVDD is applied to the gate electrode G, the normally-off thin-film transistor AFT is turned off.

[0134] In one embodiment, the gate electrode G of the normally cut-off thin-film transistor AFT can be connected to the first electrode E1. The first electrode E1 is connected to the power line PL_j, and a first drive voltage ELVDD can be applied to both the first electrode E1 and the gate electrode G.

[0135] Because the always-off thin-film transistor AFT can always be off, the first pixel PX ij Physically connected to the second pixel PX via a normally cut-off thin-film transistor AFT. (i+1)j However, the first pixel PX ij The second pixel PX can be connected via a normally cut-off thin-film transistor AFT. (i+1)j Electrical insulation.

[0136] Figure 6 This is an equivalent circuit diagram for each of a plurality of pixels according to another embodiment. Figure 6 In, with Figure 3 The same reference numerals in the figures denote the same components, and therefore, for ease of explanation of this figure, repeated descriptions are omitted.

[0137] refer to Figure 6 The gate-initialized thin-film transistor T4 may include a thin-film transistor. The gate-initialized thin-film transistor T4 is configured to apply a first initialization voltage VINT1 to the gate of the driving thin-film transistor T1 in response to a second scan signal GI_i. The gate-initialized thin-film transistor T4 may include a gate, a source S, and a drain D. The gate is connected to the second scan line GIL_i, the source S is connected to the gate of the driving thin-film transistor T1, and the drain D is connected to the first voltage line VL1_i.

[0138] The second node N2 can be a node connected to the first voltage line VL1_i. The first initialization voltage VINT1 can be applied to the second node N2. The first initialization voltage VINT1 can be applied to the second node N2 regardless of whether the gate initialization thin-film transistor T4 is on / off.

[0139] although Figure 6The diagram illustrates a normally-off thin-film transistor (AFT) comprising a single thin-film transistor, but an AFT may include at least two thin-film transistors connected in series with each other. A cutoff voltage may be applied to the gate electrodes of the at least two thin-film transistors connected in series with each other.

[0140] Although the first pixel PX is used as a reference ij A description is provided, but the description also applies to the second pixel PX. (i+1) j.

[0141] Figure 7 This is an equivalent circuit diagram for each of a plurality of pixels according to another embodiment. Figure 7 In, with Figure 3 The same reference numerals in the figures denote the same components, and therefore, for ease of explanation of this figure, repeated descriptions are omitted.

[0142] refer to Figure 7 The gate-initialized thin-film transistor T4 may include a thin-film transistor. The gate-initialized thin-film transistor T4 is configured to apply a first initialization voltage VINT1 to the gate of the driving thin-film transistor T1 in response to a second scan signal GI_i. The gate-initialized thin-film transistor T4 may include a gate, a source S, and a drain D. The gate is connected to the second scan line GIL_i, the source S is connected to the gate of the driving thin-film transistor T1, and the drain D is connected to the first voltage line VL1_i.

[0143] The second node N2 can be arranged between the gate initialization thin-film transistor T4 and the driving thin-film transistor T1. The second node N2 can be the source S of the gate initialization thin-film transistor T4 and the gate of the driving thin-film transistor T1. When the gate initialization thin-film transistor T4 is turned on in response to the second scan signal GI_i, the first initialization voltage VINT1 can be applied to the second node N2. The first initialization voltage VINT1 can be selectively applied to the second node N2.

[0144] although Figure 7 The diagram illustrates a normally-off thin-film transistor (AFT) comprising a single thin-film transistor, but an AFT may include at least two thin-film transistors connected in series with each other. A cutoff voltage may be applied to the gate electrodes of the at least two thin-film transistors connected in series with each other.

[0145] Although the first pixel PX is used as a reference ij A description is provided, but the description also applies to the second pixel PX. (i+1) j.

[0146] Figure 8 This is a cross-sectional view of a display device according to an embodiment. In the embodiment, Figure 8The first pixel PX in the display device is shown. ij The cross-section is shown, and for clarity, some components may be omitted. The multiple layers stacked in the display device are described in detail below.

[0147] refer to Figure 8 The display device may include a substrate 101, a buffer layer 111, a pixel circuit layer PCL, a display element layer DEL, and a thin film encapsulation layer TFE.

[0148] Substrate 101 may comprise glass or polymeric resin, such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate (CAP). Substrate 101 comprising polymeric resin may be flexible, rollable, or bendable. Substrate 101 may have a multilayer structure comprising a base layer and a barrier layer (not shown), the base layer comprising polymeric resin.

[0149] The buffer layer 111 may include inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide, and may include a single layer or multiple layers containing inorganic insulating materials.

[0150] The pixel circuit layer PCL can be disposed on the buffer layer 111. The pixel circuit layer PCL may include a thin-film transistor (TFT), an inorganic insulating layer IIL, a first planarization layer 115, and a second planarization layer 116. The TFT is included in the pixel circuit, and the inorganic insulating layer IIL is disposed on / below the element of the TFT. The inorganic insulating layer IIL may include a first gate insulating layer 112, a second gate insulating layer 113, and an interlayer insulating layer 114.

[0151] A thin-film transistor (TFT) may include a semiconductor layer A. Semiconductor layer A may include polycrystalline silicon. Alternatively, semiconductor layer A may include amorphous silicon, oxide semiconductor, or organic semiconductor. Semiconductor layer A may include a channel region, a drain region, and a source region, with the drain and source regions disposed on opposite sides of the channel region. The gate electrode G may overlap with the channel region.

[0152] The gate electrode G may comprise a low-resistance metallic material. The gate electrode G may comprise a conductive material comprising at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may comprise a single layer or multiple layers comprising the aforementioned materials.

[0153] The first gate insulating layer 112 between semiconductor layer A and gate electrode G may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x Zinc oxide (ZnO) x It can be ZnO and / or ZnO2.

[0154] The second gate insulating layer 113 may cover the gate electrode G. Similar to the first gate insulating layer 112, the second gate insulating layer 113 may include an inorganic insulating material, such as silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x Zinc oxide (ZnO) x It can be ZnO and / or ZnO2.

[0155] The top electrode CE2 of the storage capacitor Cst can be disposed on the second gate insulating layer 113. The top electrode CE2 can overlap with the gate electrode G below it. In this case, the overlapping gate electrode G and the top electrode CE2, together with the second gate insulating layer 113 between them, can constitute the storage capacitor Cst of the pixel circuit. That is, the gate electrode G can serve as the bottom electrode CE1 of the storage capacitor Cst. As described above, the storage capacitor Cst can overlap with the thin-film transistor TFT. In an embodiment, the storage capacitor Cst may not overlap with the thin-film transistor TFT.

[0156] The top electrode CE2 may comprise a single layer or multiple layers of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu).

[0157] Interlayer insulating layer 114 may cover the top electrode CE2. Interlayer insulating layer 114 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x Zinc oxide (ZnO) x The inorganic insulating layer 114 may be ZnO and / or ZnO2. The interlayer insulating layer 114 may include a single layer or multiple layers containing these inorganic insulating materials.

[0158] The drain electrode D and the source electrode S can be disposed on the interlayer insulating layer 114. The drain electrode D and the source electrode S can comprise materials with excellent conductivity. The drain electrode D and the source electrode S can comprise conductive materials comprising at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and have a single-layer or multi-layer structure comprising the aforementioned materials. In an embodiment, the drain electrode D and the source electrode S can have a Ti / Al / Ti multilayer structure.

[0159] The first planarization layer 115 may cover the drain electrode D and the source electrode S. The first planarization layer 115 may include an organic insulating layer. The first planarization layer 115 may include an organic insulating material, such as a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof.

[0160] The connection electrode CML can be disposed on the first planarization layer 115. In this case, the connection electrode CML can be connected to the drain electrode D or the source electrode S through the contact holes of the first planarization layer 115. The connection electrode CML can include a material with excellent conductivity. The connection electrode CML can include a conductive material comprising at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and can comprise a single layer or multiple layers comprising the above materials. In an embodiment, the connection electrode CML can have a Ti / Al / Ti multilayer structure.

[0161] The second planarization layer 116 may cover the connection electrode CML. The second planarization layer 116 may include an organic insulating layer. The second planarization layer 116 may include an organic insulating material, such as a general polymer such as polymethyl methacrylate (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof.

[0162] The display element layer DEL can be disposed on the pixel circuit layer PCL. The display element layer DEL can include display elements DE. The display element DE can be an organic light-emitting diode (OLED). The pixel electrode 211 of the display element DE can be electrically connected to the connection electrode CML through the contact holes of the second planarization layer 116. Although Figure 8 The image shows that the pixel electrode 211 of the display element DE is electrically connected to the thin-film transistor TFT via the connection electrode CML. However, in some embodiments, the connection electrode CML may be omitted, and the pixel electrode 211 of the display element DE may be directly connected to the thin-film transistor TFT.

[0163] Pixel electrode 211 may include a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, pixel electrode 211 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In another embodiment, pixel electrode 211 may further include a layer comprising ITO, IZO, ZnO, or In2O3 on / below the reflective layer.

[0164] A pixel defining layer 118 may be disposed on the pixel electrode 211, and the pixel defining layer 118 includes an opening 118OP exposing a central portion of the pixel electrode 211. The pixel defining layer 118 may include an organic insulating material and / or an inorganic insulating material. The opening 118OP may define an emission region EA (hereinafter referred to as the emission region) of light emitted from the display element DE. As an example, the width of the opening 118OP may correspond to the width of the emission region EA of the display element DE.

[0165] Spacers 119 may be disposed on the pixel defining layer 118. Spacers 119 are designed to prevent damage to the substrate 101 during the manufacturing process of the display device. When manufacturing the display panel, a mask may be used. Deposition material is deposited on the substrate 101 when the mask enters the interior of the opening 118OP of the pixel defining layer 118 or is in close contact with the pixel defining layer 118. In this case, spacers 119 can prevent defects in the substrate 101, such as damage or breakage of a portion of the substrate 101 due to the mask.

[0166] The spacer 119 may include an organic insulating material, such as polyimide. Alternatively, the spacer 119 may include an inorganic insulating material such as silicon nitride or silicon oxide, or may include both organic and inorganic insulating materials.

[0167] In one embodiment, the spacer 119 may comprise a different material from the pixel defining layer 118. Alternatively, in another embodiment, the spacer 119 may comprise the same material as the pixel defining layer 118. In this case, the pixel defining layer 118 and the spacer 119 can be formed simultaneously during a masking process using a halftone mask or the like.

[0168] Intermediate layer 212 may be disposed on pixel defining layer 118. Intermediate layer 212 may include emitting layer 212b disposed in opening 118OP of pixel defining layer 118. Emitting layer 212b may include a polymer or low molecular weight organic material that emits light of a preset color.

[0169] The first functional layer 212a and the second functional layer 212c can be disposed below and above the emitter layer 212b, respectively. The first functional layer 212a may include, for example, a hole transport layer (HTL), or may include an HTL and a hole injection layer (HIL). The second functional layer 212c is disposed on the emitter layer 212b and may be omitted. The second functional layer 212c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). Like the counter electrode 213 described below, the first functional layer 212a and / or the second functional layer 212c may be a common layer that completely covers the substrate 101.

[0170] The counter electrode 213 may comprise a conductive material having a low work function. As an example, the counter electrode 213 may comprise a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or any alloy thereof. Alternatively, the counter electrode 213 may further comprise a layer comprising ITO, IZO, ZnO, or In2O3 on top of the (semi-)transparent layer comprising the aforementioned materials.

[0171] In an embodiment, a capping layer (not shown) may be further disposed on the counter electrode 213. The capping layer may include lithium fluoride (LiF), inorganic materials, and / or organic materials.

[0172] The thin-film encapsulation layer TFE can be disposed on the counter electrode 213. In an embodiment, the thin-film encapsulation layer TFE includes at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 8 The thin-film encapsulation layer TFE shown includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 stacked sequentially.

[0173] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise at least one inorganic material selected from alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may comprise a polymeric material. The polymeric material may comprise acrylic resins, epoxy resins, polyimides, and polyethylene. In an embodiment, the organic encapsulation layer 320 may comprise acrylates.

[0174] Although not shown, a touch electrode layer may be disposed on a thin-film encapsulation layer TFE. An optical functional layer may be disposed on the touch electrode layer. The touch electrode layer may obtain coordinate information corresponding to external inputs such as touch events. The optical functional layer may reduce the reflectivity of light incident on the display device from the outside (external light) and / or increase the color purity of light emitted from the display device. In embodiments, the optical functional layer may include a retarder and / or a polarizer. The retarder may include a film-type retarder or a liquid crystal-type retarder. The retarder may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may include a film-type polarizer or a liquid crystal-type polarizer. A film-type polarizer may include a stretchable synthetic resin film, while a liquid crystal-type polarizer may include liquid crystal arranged in a predetermined arrangement. Each of the retarder and polarizer may further include a protective film.

[0175] In another embodiment, the optical functional layer may include a black matrix and color filters. The color filters can be arranged to take into account the colors of light emitted from the pixels of the display device, respectively. Each of the color filters may include a red, green, or blue pigment or dye. Alternatively, in addition to pigments or dyes, each of the color filters may further include quantum dots. Alternatively, some of the color filters may not include pigments or dyes and may include scattering particles such as titanium dioxide.

[0176] In another embodiment, the optical functional layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, can interfere destructively, and thus reduce the reflectivity of external light.

[0177] The adhesive component can be disposed between the touch electrode layer and the optical functional layer. Adhesive components known in the art can be used without limitation. The adhesive component can be a pressure-sensitive adhesive (PSA).

[0178] According to various embodiments, because the semiconductor pattern extending continuously in the first direction is formed as a single unit, defective pixel problems, such as damage to the semiconductor pattern due to external electrostatic discharge, can be solved. Therefore, defects in the display device can be prevented.

[0179] Although only the display device has been described so far, this disclosure is not limited thereto. By way of example, the method of manufacturing the display device also falls within the scope of this disclosure.

[0180] Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display device, comprising: Including the first pixel of the first node; The second pixel that is adjacent to the first pixel and includes the second node; as well as A normally off thin-film transistor including a first electrode, a second electrode, and a gate electrode, wherein the first electrode is connected to a first node of a first pixel, the second electrode is connected to a second node of a second pixel, and a cutoff voltage is applied to the gate electrode.

2. The display device according to claim 1, wherein, The normally cut-off thin-film transistor further includes a semiconductor pattern connecting the first node to the second node.

3. The display device according to claim 2, wherein, The first pixel further includes: First light-emitting element; The first driving thin-film transistor is configured to control the current flowing through the first light-emitting element according to the first gate-source voltage; A first emitter control thin-film transistor is configured to connect the first node to the source of the first driving thin-film transistor in response to an emitter control signal; and A first gate-initialized thin-film transistor is configured to apply a first initialization voltage to the gate of the first driving thin-film transistor in response to a first scan signal. The driving voltage is applied to the first node.

4. The display device according to claim 3, wherein, The cutoff voltage is the driving voltage.

5. The display device according to claim 3, wherein, The second pixel further includes: Second light-emitting element; The second driving thin-film transistor is configured to control the current flowing through the second light-emitting element according to the second gate-source voltage; and The second gate initialization thin-film transistor is configured to apply the first initialization voltage to the gate of the second driving thin-film transistor in response to a second scan signal. When the second gate initialization thin-film transistor is turned on in response to the second scan signal, the first initialization voltage is applied to the second node.

6. The display device according to claim 5, wherein, The second gate initialization thin-film transistor includes a plurality of thin-film transistors connected in series with each other, and The second node is arranged between the plurality of thin-film transistors.

7. The display device according to claim 6, wherein, When the plurality of thin-film transistors are turned off in response to the second scan signal, the second node is in a floating state.

8. The display device according to claim 5, wherein, The first pixel further includes: An anode-initialized thin-film transistor is configured to apply a second initialization voltage to the anode of the first light-emitting element in response to the second scan signal.

9. The display device according to claim 8, wherein, The first pixel further includes: A storage capacitor including a top electrode and a bottom electrode, the driving voltage being applied to the top electrode, and the bottom electrode being connected to the gate of the first driving thin-film transistor; A scanning thin-film transistor is configured to transmit a data voltage to the source of the first driving thin-film transistor in response to a third scanning signal; A compensation thin-film transistor, configured to operate in response to the third scan signal, is connected between the drain and the gate of the first driving thin-film transistor; and A second emission control thin-film transistor is configured to connect the drain of the first driving thin-film transistor to the anode of the first light-emitting element in response to the emission control signal.

10. The display device according to claim 3, wherein, The second pixel further includes: Second light-emitting element; The second driving thin-film transistor is configured to control the current flowing through the second light-emitting element according to the second gate-source voltage; and The second gate initialization thin-film transistor is configured to apply the first initialization voltage to the gate of the second driving thin-film transistor in response to a second scan signal. The second node is the source or drain of the second gate-initialized thin-film transistor.

11. The display device according to claim 1, further comprising: The data line extending in the first direction, Wherein, the first pixel is adjacent to the second pixel in the first direction.

12. The display device according to any one of claims 1 to 11, wherein, The first pixel is electrically insulated from the second pixel by the normally cut-off thin-film transistor.

13. The display device according to claim 1, wherein, The gate electrode of the normally cut-off thin-film transistor is connected to the first electrode, and the cut-off voltage is applied to the first electrode.

14. A display device, comprising: Multiple pixels, each arranged in a first direction and including a light-emitting element, a first node and a second node, a driving voltage is applied to the first node and a first initialization voltage is selectively applied to the second node; as well as Multiple normally-off thin-film transistors are alternately arranged with the multiple pixels in the first direction. Each of the plurality of normally cut-off thin-film transistors physically connects the first node of the first pixel of two adjacent pixels in the plurality of pixels to the second node of the second pixel.

15. The display device according to claim 14, further comprising: A semiconductor pattern extending continuously in the first direction as a single unit. The semiconductor pattern includes multiple pixel regions and multiple transistor regions, wherein the multiple pixel regions are respectively included in the multiple pixels, and the multiple transistor regions are respectively included in the multiple normally cut-off thin-film transistors.

16. The display device according to claim 14, wherein, Each of the plurality of pixels further includes: A driving thin-film transistor is configured to control the current flowing through the light-emitting element according to the gate-source voltage; A scanning thin-film transistor is configured to transmit a data voltage to the driving thin-film transistor in response to a first scan signal; and A storage capacitor including a first electrode and a second electrode, wherein the first electrode is connected to the gate of the driving thin-film transistor.

17. The display device according to claim 16, wherein, Each of the plurality of pixels further includes: A compensation thin-film transistor is configured to connect the drain of the driving thin-film transistor to the gate in response to the first scan signal.

18. The display device according to claim 17, wherein, Each of the plurality of pixels further includes: A gate-initialized thin-film transistor is configured to apply the first initialization voltage to the gate of the driving thin-film transistor in response to a second scan signal.

19. The display device according to claim 18, wherein, Each of the plurality of pixels further includes: A first emit control thin-film transistor is configured to connect the first node to the source of the driving thin-film transistor in response to an emit control signal; and A second emission control thin-film transistor is configured to connect the drain of the driving thin-film transistor to the anode of the light-emitting element in response to the emission control signal.

20. The display device according to claim 19, wherein, Each of the plurality of pixels further includes: An anode-initialized thin-film transistor is configured to apply a second initialization voltage to the anode of the light-emitting element in response to a third scan signal.

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