Organic light emitting display device

Abstract

An organic light emitting display device includes a first transistor including a first active region and a first gate electrode disposed on the first active region, a third transistor including a third lower gate electrode disposed on the first gate electrode, a third active region disposed on the third lower gate electrode, and a third upper gate electrode disposed on the third active region, and a fourth transistor including a fourth active region disposed in the same layer as the first active region and a fourth gate electrode disposed on the fourth active region. The first transistor is a first type transistor, and the fourth transistor is a second type transistor different from the first type transistor.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to organic light-emitting display devices. More specifically, the present invention relates to organic light-emitting display devices having improved transmittance of external light. Background Technology

[0002] Display devices used in computer monitors, televisions, and mobile phones may include organic light-emitting displays (“OLEDs”) that emit their own light and liquid crystal displays (“LCDs”) that require a separate light source.

[0003] When external light passes through the first part of the organic light-emitting display device, leakage current may occur. Therefore, the brightness of the first part may deteriorate. As a result, the display quality of the organic light-emitting display device may deteriorate.

[0004] On the other hand, when external light does not pass through the second part of the organic light-emitting display device, the sensitivity of the sensor may deteriorate. Therefore, the sensor capability of the second part may be degraded. Summary of the Invention

[0005] Some embodiments provide an organic light-emitting display device that has improved transmittance by providing shielding only for specific portions of the organic light-emitting display device.

[0006] An organic light-emitting display device according to an embodiment includes: a first transistor including a first active region and a first gate electrode disposed on the first active region; a third transistor including a third lower gate electrode disposed on the first gate electrode, a third active region disposed on the third lower gate electrode, and a third upper gate electrode disposed on the third active region; and a fourth transistor including a fourth active region disposed in the same layer as the first active region and a fourth gate electrode disposed on the fourth active region, wherein the first transistor is a first type of transistor, and the fourth transistor is a second type of transistor different from the first type of transistor.

[0007] According to an embodiment, the organic light-emitting display device may further include a seventh transistor, which includes a seventh active region disposed in the same layer as the first active region and a seventh gate electrode disposed on the seventh active region.

[0008] According to an embodiment, the organic light-emitting display device may further include a gate initialization signal line, which is disposed in the same layer as the first gate electrode, the fourth gate electrode and the seventh gate electrode and receives a gate initialization signal, wherein the gate initialization signal line may include the fourth gate electrode and the seventh gate electrode.

[0009] According to an embodiment, the third active region may include an oxide semiconductor.

[0010] According to an embodiment, the third transistor may be an NMOS transistor.

[0011] According to an embodiment, each of the first active region, the fourth active region, and the seventh active region may include polycrystalline silicon.

[0012] According to an embodiment, the seventh transistor may be a transistor of the second type.

[0013] According to an embodiment, each of the fourth and seventh transistors may be an NMOS transistor.

[0014] According to an embodiment, the organic light-emitting display device may further include: a second transistor, including a second active region disposed in the same layer as the first active region and a second gate electrode disposed on the second active region; a fifth transistor, including a fifth active region disposed in the same layer as the first active region and a fifth gate electrode disposed on the fifth active region; and a sixth transistor, including a sixth active region disposed in the same layer as the first active region and a sixth gate electrode disposed on the sixth active region.

[0015] According to an embodiment, the third active region may include an oxide semiconductor.

[0016] According to an embodiment, the third transistor may be an NMOS transistor.

[0017] According to an embodiment, each of the first active region, the second active region, the fourth active region, the fifth active region, the sixth active region, and the seventh active region may include polycrystalline silicon.

[0018] According to an embodiment, each of the fourth and seventh transistors may be an NMOS transistor.

[0019] According to an embodiment, each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor may be a PMOS transistor.

[0020] According to an embodiment, the organic light-emitting display device may further include a storage capacitor and a boost capacitor. The storage capacitor includes a first storage electrode connected to a first gate electrode and a second storage electrode disposed on the first storage electrode. The boost capacitor includes a first boost electrode connected to a second gate electrode and a second boost electrode disposed on the first boost electrode.

[0021] According to an embodiment, the fourth active region may include an overlapping region that overlaps with the fourth gate electrode in a plan view, a first impurity region adjacent to the overlapping region, and a second impurity region adjacent to the first impurity region, wherein the first impurity concentration of the first impurity region may be less than the second impurity concentration of the second impurity region.

[0022] According to an embodiment, the organic light-emitting display device may further include a shielding pattern disposed on a third upper gate electrode and covering a third active region.

[0023] According to an embodiment, the shielding pattern may not cover the fourth active region in the plan view.

[0024] According to an embodiment, the organic light-emitting display device may further include a high-power voltage line for transmitting a high power voltage to a first transistor, wherein the high-power voltage line may include a shielding pattern.

[0025] The shielding pattern can be disposed on an oxide semiconductor. The shielding pattern may not be disposed on polysilicon. The third active region of the third transistor may include an oxide semiconductor. The fourth active region of the fourth transistor may include polysilicon. Therefore, the area where the shielding pattern is disposed can be effectively minimized. Therefore, the organic light-emitting display device has improved transmittance.

[0026] It should be understood that both the foregoing general description and the following specific description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0027] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the inventive concept.

[0028] Figure 1 This is a block diagram illustrating an organic light-emitting display device according to an embodiment.

[0029] Figure 2 This is a circuit diagram illustrating pixels according to an embodiment.

[0030] Figure 3 It is used for driving in high-frequency drive mode. Figure 2 A time sequence diagram of pixels.

[0031] Figure 4 It is used for driving in low-frequency drive mode. Figure 2 A time sequence diagram of pixels.

[0032] Figure 5 This is a layout diagram illustrating adjacent pixels according to an embodiment.

[0033] Figure 6 yes Figure 5 A magnified layout of one pixel.

[0034] Figures 7 to 15 It is for each layer of diagrams Figure 6 The layout diagram of the components shown.

[0035] Figure 16 It is along Figure 6 The cross-sectional view taken from line I-I'.

[0036] Figure 17 It is along Figure 6 The cross-sectional view taken by line I-I' is used to describe the impurity region included in the fourth active region.

[0037] Figure 18 and Figure 19 It is used to describe Figure 17 The diagram shows the formation of impurity regions. Detailed Implementation

[0038] It will be understood that when an element is referred to as being "on" another element, the element may be directly "on" the other element, or an intermediary element may exist between the element and the other element. Conversely, when an element is referred to as being "directly" "on" another element, no intermediary element exists. Furthermore, relative terms such as "below" or "bottom" and "above" or "top" may be used herein to describe the relationship between one element and another as illustrated in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to cover different orientations of the device. For example, if the device in one of the drawings is flipped, an element described as being "below" the other element will be oriented to be "above" the other element. Thus, depending on the specific orientation of the drawing, the exemplary term "below" may cover both "below" and "above" orientations. Similarly, if the device in one of the drawings is flipped, an element described as being "below" or "under" the other element will be oriented to be "above" the other element. Thus, the exemplary terms "below" and "under" may cover both "above" and "below" orientations.

[0039] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, without departing from the teachings herein, “first element,” “first component,” “first area,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second area, second layer, or second part.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to include the plural forms that include “at least one” unless the context clearly indicates otherwise. “At least one” should not be construed as limited to “a”. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the items listed. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0041] The exemplary, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0042] Figure 1 This is a block diagram illustrating an organic light-emitting display device according to an embodiment.

[0043] refer to Figure 1 An organic light-emitting display device according to an embodiment of the present invention may include a display unit 10 comprising a plurality of pixels PX, a scan driver 20, a data driver 30, an emission control driver 40, and a control unit 50.

[0044] The display unit 10 may include a plurality of pixels PX placed at the intersections of multiple scan lines SL0 to SLn+1, multiple data lines DL1 to DLm, and multiple emission control lines EL1 to ELn. Here, "n" and "m" are natural numbers. Therefore, the pixels PX can be arranged in a matrix form. The scan lines SL0 to SLn+1 and the emission control lines EL1 to ELn can extend in a first direction D1, which is the row direction, and the data lines DL1 to DLm and the high power voltage line ELVDDL can extend in a second direction D2, which is the column direction.

[0045] Each pixel PX can be connected to three scan lines SL0 to SLn+1. The scan driver 20 can transmit three scan signals to each pixel PX through scan lines SL0 to SLn+1. In other words, the scan driver 20 can sequentially supply scan signals to scan lines SL1 to SLn, previous scan lines SL0 to SLn-1, and subsequent scan lines SL2 to SLn+1.

[0046] Each pixel PX can be connected to one of the data lines DL1 to DLm. The data driver 30 can transmit the data signal DATA to each pixel PX via the data lines DL1 to DLm. When a scan signal is supplied to scan lines SL1 to SLn, the data signal DATA can be supplied to each pixel PX selected by the scan signal.

[0047] Each pixel PX can be connected to one of the transmission control lines EL1 to ELn. The transmission control driver 40 can transmit transmission control signals to each pixel PX via the transmission control lines EL1 to ELn. The transmission control signals can control the transmission time of each pixel PX. Depending on the internal structure of each pixel PX, the transmission control driver 40 can be omitted.

[0048] The control unit 50 can convert multiple image signals IR, IG, and IB transmitted from an external source into multiple image data signals DR, DG, and DB, and can transmit the converted image data signals DR, DG, and DB to the data driver 30. Additionally, the control unit 50 can receive a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK, and can generate control signals for controlling the scan driver 20, the data driver 30, and the transmit control driver 40. In other words, the control unit 50 can respectively transmit a scan drive control signal SCS for controlling the scan driver 20, a data drive control signal DCS for controlling the data driver 30, and a transmit drive control signal ECS for controlling the transmit control driver 40.

[0049] Each pixel PX can receive a high power voltage ELVDD and a low power voltage ELVSS from an external power supply. The high power voltage ELVDD can be a predetermined high-level voltage, and the low power voltage ELVSS can be a voltage lower than the high power voltage ELVDD or can be ground. The high power voltage ELVDD can be supplied to each pixel PX via the high power voltage line ELVDDL. Each pixel PX can receive an initialization voltage VINT from an external power supply. Each pixel PX can also receive a diode initialization voltage AINT from an external power supply.

[0050] Each pixel PX can be supplied to the organic light-emitting diode OLED according to the data signal DATA transmitted via data lines DL1 to DLm (see...). Figure 2 It emits light with a predetermined brightness by driving the current of the light source.

[0051] Figure 2 This is a circuit diagram illustrating pixels according to an embodiment.

[0052] refer to Figure 2Each pixel PX may include transistors T1, T2, T3, T4, T5, T6 and T7, storage capacitor CST, boost capacitor CBT and organic light-emitting diode OLED. Figure 2 The illustration shows a configuration in which transistors T1, T2, T3, T4, T5, T6 and T7, storage capacitor CST, boost capacitor CBT, and organic light-emitting diode (OLED) are all provided, but the invention is not limited thereto.

[0053] The first transistor T1 may include a first terminal (e.g., a source terminal) for receiving a high power voltage ELVDD, a second terminal (e.g., a drain terminal) for transmitting the supplied high power voltage ELVDD to an organic light-emitting diode (OLED), and a gate terminal for receiving a voltage used to turn the first transistor T1 on or off. The first transistor T1 may generate a drive current based on the voltage difference between the gate terminal and the first terminal.

[0054] The second transistor T2 may include a first terminal (e.g., a source terminal) for receiving a data signal DATA, a second terminal (e.g., a drain terminal) for transmitting the data signal DATA to the first terminal of the first transistor T1, and a gate terminal for receiving a gate signal GW. The gate signal GW may determine an on-state in which the data signal DATA is transmitted or an off-state in which the data signal DATA is not transmitted.

[0055] The third transistor T3 may include a first terminal (e.g., a source terminal) connected to the gate terminal of the first transistor T1, a second terminal (e.g., a drain terminal) connected to the second terminal of the first transistor T1, an upper gate terminal for receiving the gate switching signal GC, and a lower gate terminal for receiving the gate switching signal GC.

[0056] The fourth transistor T4 may include a first terminal (e.g., a source terminal) for receiving the initialization voltage VINT, a second terminal (e.g., a drain terminal) connected to the first terminal of the third transistor T3, and a gate terminal for receiving the gate initialization signal GI.

[0057] The fifth transistor T5 may include a first terminal (e.g., a source terminal) that receives a high power voltage ELVDD, a second terminal (e.g., a drain terminal) that is connected to the first terminal of the first transistor T1, and a gate terminal that receives a transmit control signal EM.

[0058] The sixth transistor T6 may include a first terminal (e.g., a source terminal) connected to the second terminal of the first transistor T1, a second terminal (e.g., a drain terminal) connected to the first terminal of the organic light-emitting diode OLED, and a gate terminal for receiving the emission control signal EM.

[0059] The seventh transistor T7 may include a first terminal (e.g., a source terminal) connected to the second terminal of the sixth transistor T6, a second terminal (e.g., a drain terminal) connected to an external power supply that provides the diode initialization voltage AINT, and a gate terminal that receives the diode initialization signal GB.

[0060] An organic light-emitting diode (OLED) may include a first terminal (e.g., an anode terminal) connected to a second terminal of a sixth transistor T6 to receive a drive current and a second terminal (e.g., a cathode terminal) to receive a low power voltage ELVSS.

[0061] The storage capacitor CST may include a first terminal receiving a high power voltage ELVDD and a second terminal connected to the gate terminal of the first transistor T1. The storage capacitor CST can maintain the voltage level of the gate terminal of the first transistor T1 during the off period of the gate signal GW.

[0062] The boost capacitor CBT may include a connection to the gate signal line 1220 (see [link]). Figure 8 The first terminal of the transistor T1 and the second terminal connected to the gate terminal of the first transistor T1. The boost capacitor CBT can maintain the voltage level of the gate terminal of the first transistor T1 during the off period of the gate initialization signal GI.

[0063] Each of transistors T1, T2, T3, T4, T5, T6, and T7 can be an NMOS transistor or a PMOS transistor. An NMOS transistor can be turned on when the signal supplied to its gate terminal has a positive voltage level and can be turned off when the signal supplied to its gate terminal has a negative voltage level. A PMOS transistor can be turned on when the signal supplied to its gate terminal has a negative voltage level and can be turned off when the signal supplied to its gate terminal has a positive voltage level.

[0064] In recent years, there has been a need for display devices that can display a predetermined standby screen when the display device is not in use. For example, display devices that support always-on display modes have been developed. A always-on display mode can be a low-power mode that displays a standby screen. A always-on display mode can display a standby screen including a time image (i.e., an image indicating the current time), a date image, and a weather image when the display device is in standby mode. The always-on display mode can minimize power consumption by driving at a low frequency. For example, a mode used to display the active screen of a display device can be called a high-frequency driving mode, and a always-on display mode can be called a low-frequency driving mode.

[0065] Figure 3 It is used for driving in high-frequency drive mode. Figure 2 A time sequence diagram of pixels.

[0066] refer to Figure 2 and Figure 3Each of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be a transistor of type 1. The first type of transistor can be a PMOS transistor. Each of the third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be a transistor of type 2, different from the first type of transistor. The second type of transistor can be an NMOS transistor. A frame can begin at a first time point t1 and end at a seventh time point t7. In high-frequency drive mode, this frame can be continuously repeated in the next frame.

[0067] From the second time point t2 to the third time point t3, the gate initialization signal GI and the diode initialization signal GB can have positive voltage levels. Therefore, the fourth transistor T4 and the seventh transistor T7 can be turned on. When the fourth transistor T4 is turned on, the initialization voltage VINT can be provided to the first terminal of the third transistor T3, the second terminal of the boost capacitor CBT, the gate terminal of the first transistor T1, and the second terminal of the storage capacitor CST. When the seventh transistor T7 is turned on, current can flow out to the external power supply supplying the diode initialization voltage AINT. This current can be the residual current after the driving current flows through the organic light-emitting diode OLED to emit light. In other words, the organic light-emitting diode OLED can be initialized.

[0068] From time point t4 to time point t5, the gate signal GW can have a negative voltage level, and the gate switching signal GC can have a positive voltage level. Therefore, the second transistor T2 and the third transistor T3 can be turned on. When the second transistor T2 is turned on, the data signal DATA can be provided to the first terminal of the first transistor T1. When the third transistor T3 is turned on, the initialization voltage VINT can be provided to the second terminal of the first transistor T1.

[0069] From time point t6 to time point t7, the transmit control signal EM can have a negative voltage level. Therefore, the fifth transistor T5 and the sixth transistor T6 can be turned on. When the fifth transistor T5 is turned on, a high power voltage ELVDD can be provided to the first transistor T1. Therefore, the data signal DATA can be transmitted based on the voltage difference between the first and second terminals of the first transistor T1. When the sixth transistor T6 is turned on, the transmitted data signal DATA can be supplied to the organic light-emitting diode (OLED). Therefore, the OLED can emit light with a predetermined brightness depending on the data signal DATA.

[0070] The time taken for a frame can be controlled by the length from the third time point t3 to the fourth time point t4 and the length from the fifth time point t5 to the sixth time point t6. When a frame is completed, the next frame can be repeated in the same way as the previous frame.

[0071] Figure 4 It is used for driving in low-frequency drive mode. Figure 2 A time sequence diagram of pixels.

[0072] refer to Figure 2 , Figure 3 and Figure 4 A frame from the first time point t1' in low-frequency drive mode to the seventh time point t7' in low-frequency drive mode can continue in the same manner as a frame in high-frequency drive mode. However, the second frame in low-frequency drive mode may not continue from the first frame in low-frequency drive mode. That is, the signal pattern in the second frame in low-frequency drive mode is different from the signal pattern in the first frame in low-frequency drive mode.

[0073] In low-frequency drive mode, the second frame may not have a time point where the gate initialization signal GI and the diode initialization signal GB have a positive voltage level. Therefore, the fourth transistor T4 and the seventh transistor T7 can be turned off in the second frame. When the fourth transistor T4 is continuously turned off, the first terminal of the third transistor T3, the second terminal of the boost capacitor CBT, the gate terminal of the first transistor T1, and the second terminal of the storage capacitor CST may not receive the initialization voltage VINT. When the seventh transistor T7 is continuously turned off, the residual current may not flow out to the external power supply that supplies the diode initialization voltage AINT. In other words, the organic light-emitting diode (OLED) may not be initialized.

[0074] From time point t8' in the low-frequency drive mode to time point t9' in the low-frequency drive mode, the gate signal GW can have a negative voltage level. On the other hand, the gate switching signal GC can still not have a positive voltage level. Therefore, the second transistor T2 can be turned on, and the third transistor T3 can remain off. When the second transistor T2 is turned on, the data signal DATA can be provided to the first terminal of the first transistor T1. However, when the third transistor T3 is turned off, the initialization voltage VINT can not be provided to the second terminal of the first transistor T1.

[0075] From the tenth time point t10' to the eleventh time point t11' in the low-frequency drive mode, the transmit control signal EM can have a negative voltage level. Therefore, the fifth transistor T5 and the sixth transistor T6 can be turned on. When the fifth transistor T5 is turned on, a high power voltage ELVDD can be provided to the first transistor T1. Therefore, the data signal DATA can be transmitted based on the voltage difference between the first terminal and the second terminal of the first transistor T1. When the sixth transistor T6 is turned on, the transmitted data signal DATA can be supplied to the organic light-emitting diode (OLED). Therefore, the OLED can emit light with a predetermined brightness depending on the transmitted data signal DATA. Keeping the gate initialization signal GI, the diode initialization signal GB, and the gate switching signal GC constant can be referred to as self-scanning.

[0076] In low-frequency drive mode, a frame can begin at a first time point t1' and end at a seventh time point t7', and the next frame can begin at a seventh time point t7' and end at an eleventh time point t11'. For example, when driving the low-frequency drive mode at 10 Hz, the third to tenth frames can be repeated in the same way as the second frame, and the eleventh frame can be repeated in the same way as the first frame.

[0077] Figure 5 This is a layout diagram illustrating adjacent pixels according to an embodiment.

[0078] refer to Figure 5 A pixel PX and a first pixel PX1 adjacent to pixel PX in the first direction D1 may have a shape that is symmetrical about the vertical axis between the pixel PX and the first pixel PX1 and extends in the second direction D2.

[0079] Figure 6 yes Figure 5 A magnified layout of one pixel.

[0080] refer to Figure 6 The fourth transistor T4 and the seventh transistor T7 can be placed in the same row in the first direction D1. The third transistor T3 and the sixth transistor T6 can be placed in the same column as the fourth transistor T4 in the second direction D2. The fifth transistor T5 can be placed in the same row as the sixth transistor T6 in the first direction D1. The second transistor T2 can be placed in the same column as the fifth transistor T5 in the second direction D2. The first transistor T1 can be placed between the row in which the fifth transistor T5 and the sixth transistor T6 are placed and the row in which the third transistor T3 is placed. The first transistor T1 can be placed between the column in which the second transistor T2 and the fifth transistor T5 are placed and the column in which the seventh transistor T7 is placed.

[0081] Figures 7 to 15 It is for each layer of diagrams Figure 6 The layout diagram of the components shown. Figure 16 It is along Figure 6 The cross-sectional view taken from line I-I'.

[0082] refer to Figures 6 to 16 The organic light-emitting display device may include a substrate SUB, a buffer layer BF, a first active layer 1100, a first gate insulating layer GIL1, a first gate layer 1200, a first interlayer insulating layer ILD1, a second gate layer 1300, a second interlayer insulating layer ILD2, a second active layer 1400, a second gate insulating layer GIL2, a third gate layer 1500, a third interlayer insulating layer ILD3, a first connecting layer 1800, a first through-hole insulating layer VIA1, a second connecting layer 2000, and a second through-hole insulating layer VIA2.

[0083] The substrate SUB can include a glass substrate, a quartz substrate, or a plastic substrate, etc. In an embodiment, the substrate SUB can include a plastic substrate, and therefore, the organic light-emitting display device can have flexible properties. In this case, the substrate SUB can have a structure in which at least one organic film and at least one barrier layer are alternately stacked. For example, the organic film can include or be formed using an organic material such as polyimide, and the barrier layer can include or be formed using an inorganic material.

[0084] A buffer layer BF can be disposed on the substrate SUB. The buffer layer BF can prevent metal atoms or impurities from diffusing from the substrate SUB into the first active layer 1100. Furthermore, during the crystallization process for forming the first active layer 1100, the buffer layer BF can control the heat supply rate. That is, the buffer layer BF can control the heat supply from the substrate SUB to the first active layer 1100. Therefore, the first active layer 1100 can be formed uniformly.

[0085] The first active layer 1100 can be disposed on the buffer layer BF. In the first active layer 1100, a first active region A1, a second active region A2, a fourth active region A4, a fifth active region A5, a sixth active region A6, and a seventh active region A7 can be formed. The first active layer 1100 may include a first portion 1110, a second portion 1120, and a third portion 1130. The first portion 1110 may include the fourth active region A4. The second portion 1120 may include the seventh active region A7. The third portion 1130 may include the first active region A1, the second active region A2, the fifth active region A5, and the sixth active region A6. The first portion 1110 and the second portion 1120 may be spaced apart from each other in the first direction D1. The first active region A1, the second active region A2, the fifth active region A5, and the sixth active region A6 may be spaced apart from each other, but may be connected to form the same third portion 1130.

[0086] In this embodiment, each of the first active region A1, the second active region A2, the fifth active region A5, and the sixth active region A6 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon, etc. More specifically, each of the first active region A1, the second active region A2, the fifth active region A5, and the sixth active region A6 may include PMOS polycrystalline silicon.

[0087] In this embodiment, each of the fourth active region A4 and the seventh active region A7 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon, etc. More specifically, each of the fourth active region A4 and the seventh active region A7 may include NMOS polycrystalline silicon.

[0088] A first gate insulating layer (GIL1) may be disposed on the first active layer 1100. The first gate insulating layer (GIL1) may be used to insulate the first active layer 1100 from the first gate layer 1200. The first gate insulating layer (GIL1) may include an insulating material. For example, the first gate insulating layer (GIL1) may include silicon oxide, silicon nitride, titanium oxide, or tantalum oxide, etc.

[0089] A first gate layer 1200 may be disposed on a first gate insulating layer GIL1. In the first gate layer 1200, a first gate electrode G1, a second gate electrode G2, a fourth gate electrode G4, a fifth gate electrode G5, a sixth gate electrode G6, a seventh gate electrode G7, a first storage electrode SE1, and a first boost electrode BE1 may be formed. The first gate layer 1200 may include a gate initialization signal line 1210, a gate signal line 1220, an isolated structure 1230, and a light emission control signal line 1240. The gate initialization signal line 1210 may include the fourth gate electrode G4 and the seventh gate electrode G7. In other words, the fourth gate electrode G4 and the seventh gate electrode G7 may be connected to each other as the gate initialization signal line 1210. The gate signal line 1220 may include the second gate electrode G2 and the first boost electrode BE1. In other words, the second gate electrode G2 and the first boost electrode BE1 may be connected to each other as the gate signal line 1220. The isolated structure 1230 may include the first gate electrode G1 and the first storage electrode SE1. In other words, the first gate electrode G1 and the first storage electrode SE1 can be connected to each other as an isolated structure 1230. The light emission control signal line 1240 may include a fifth gate electrode G5 and a sixth gate electrode G6. In other words, the fifth gate electrode G5 and the sixth gate electrode G6 can be connected to each other as a light emission control signal line 1240.

[0090] In this embodiment, the first gate layer 1200 may include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the first gate layer 1200 may include silver, silver-containing alloys, molybdenum, molybdenum-containing alloys, aluminum, aluminum-containing alloys, aluminum nitride, tungsten, tungsten nitride, copper, nickel, chromium, chromium nitride, titanium, tantalum, platinum, scandium, indium tin oxide, or indium zinc oxide.

[0091] In an embodiment, the first gate electrode G1 may receive a signal for turning the first transistor T1 on and / or off.

[0092] In an embodiment, the second gate electrode G2 can receive a gate signal GW for turning on and / or turning off the second transistor T2 via the gate signal line 1220.

[0093] In an embodiment, the fourth gate electrode G4 can receive a gate initialization signal GI for turning on and / or turning off the fourth transistor T4 via the gate initialization signal line 1210.

[0094] In an embodiment, the fifth gate electrode G5 can receive an emission control signal EM for turning on and / or turning off the fifth transistor T5 via the light emission control signal line 1240.

[0095] In an embodiment, the sixth gate electrode G6 can receive an emission control signal EM for turning the sixth transistor T6 on and / or off via the light emission control signal line 1240.

[0096] In an embodiment, the seventh gate electrode G7 can receive a gate initialization signal GI for turning on and / or turning off the seventh transistor T7 via the gate initialization signal line 1210.

[0097] A first interlayer insulating layer (ILD1) can be disposed on the first gate layer 1200. The first interlayer insulating layer (ILD1) can be used to insulate the first gate layer 1200 from the second gate layer 1300. The first interlayer insulating layer (ILD1) may include an insulating material. For example, the first interlayer insulating layer (ILD1) may include silicon oxide, silicon nitride, titanium oxide, or tantalum oxide, etc.

[0098] The second gate layer 1300 can be disposed on the first interlayer insulating layer ILD1. A third lower gate electrode GD3 and a second storage electrode SE2 can be formed in the second gate layer 1300. The second gate layer 1300 may include a lower gate switch signal line 1310 and an overlay structure 1320. The lower gate switch signal line 1310 may include the third lower gate electrode GD3. The overlay structure 1320 may include the second storage electrode SE2.

[0099] In this embodiment, the second gate layer 1300 may include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the second gate layer 1300 may include silver, silver-containing alloys, molybdenum, molybdenum-containing alloys, aluminum, aluminum-containing alloys, aluminum nitride, tungsten, tungsten nitride, copper, nickel, chromium, chromium nitride, titanium, tantalum, platinum, scandium, indium tin oxide, or indium zinc oxide.

[0100] In an embodiment, the third lower gate electrode GD3 can receive a gate switching signal GC for turning on and / or turning off the third transistor T3 via the lower gate switch signal line 1310. The third upper gate electrode GU3 (to be discussed later) Figure 11 (As described in the text) can be connected to the upper gate switch signal line 1520 (see description). Figure 11 The gate switching signal GC is received. If the gate switching signal GC is not provided to the third lower gate electrode GD3, impurities may degrade the characteristics of the third active region A3.

[0101] A second interlayer insulating layer (ILD2) can be disposed on the second gate layer 1300. The second interlayer insulating layer (ILD2) can be used to insulate the second gate layer 1300 from the second active layer 1400. The second interlayer insulating layer (ILD2) may include an insulating material. For example, the second interlayer insulating layer (ILD2) may include silicon oxide, silicon nitride, titanium oxide, or tantalum oxide, etc.

[0102] The second active layer 1400 can be disposed on the second interlayer insulating layer ILD2. A third active region A3 and a second boost electrode BE2 can be formed in the second active layer 1400. The third active region A3 and the second boost electrode BE2 can be spaced apart from each other, but can be formed as the same structure.

[0103] In this embodiment, the third active region A3 may include an oxide semiconductor. For example, the third active region A3 may include one or a combination of oxides of zinc, indium, gallium, tin, titanium, and phosphorus. Specifically, the third active region A3 may include at least one of zinc oxide, zinc tin oxide, zinc indium oxide, indium oxide, titanium oxide, indium gallium zinc oxide (“IGZO”), and indium tin zinc oxide (“ITZO”). More specifically, the third active region A3 may include an NMOS oxide semiconductor.

[0104] A second gate insulating layer GIL2 may be disposed on the second active layer 1400. The second gate insulating layer GIL2 can be used to insulate the second active layer 1400 from the third gate layer 1500. The second gate insulating layer GIL2 may include an insulating material. For example, the second gate insulating layer GIL2 may include silicon oxide, silicon nitride, titanium oxide, or tantalum oxide, etc.

[0105] The third gate layer 1500 may be disposed on the second gate insulating layer GIL2. The third gate layer 1500 may include an initialization voltage line 1510 and an upper gate switch signal line 1520. The upper gate switch signal line 1520 may include a third upper gate electrode GU3.

[0106] In this embodiment, the upper gate switch signal line 1520 may overlap with the lower gate switch signal line 1310 in a plan view (i.e., viewed from a direction perpendicular to the plane defined by the first direction D1 and the second direction D2). Specifically, the upper gate switch signal line 1520 and the lower gate switch signal line 1310 may receive the gate switch signal GC. In other words, the upper gate switch signal line 1520 and the lower gate switch signal line 1310 may be separated from the same line. Therefore, the third upper gate electrode GU3 and the third lower gate electrode GD3 may be connected to each other via the upper gate switch signal line 1520 and the lower gate switch signal line 1310, respectively.

[0107] In this embodiment, the initialization voltage line 1510 may be spaced apart from the upper gate switch signal line 1520 in the second direction D2 and may extend in the first direction D1. A third upper gate electrode GU3 is placed within the upper gate switch signal line 1520. A portion of the initialization voltage line 1510 may overlap with a second portion 1120 of the first active layer 1100 in a plan view. Another portion of the initialization voltage line 1510 may overlap with a first portion 1110 of the first active layer 1100 in a plan view.

[0108] In this embodiment, the third gate layer 1500 may include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the third gate layer 1500 may include silver, silver-containing alloys, molybdenum, molybdenum-containing alloys, aluminum, aluminum-containing alloys, aluminum nitride, tungsten, tungsten nitride, copper, nickel, chromium, chromium nitride, titanium, tantalum, platinum, scandium, indium tin oxide, or indium zinc oxide.

[0109] In this embodiment, the third upper gate electrode GU3 can receive a gate switching signal GC for turning on and / or turning off the third transistor T3 via the upper gate switching signal line 1520. The third upper gate electrode GU3 and the third lower gate electrode GD3 can be connected to the upper gate switching signal line 1520 and the lower gate switching signal line 1310, respectively, to receive the gate switching signal GC. Therefore, since the gate switching signal GC is provided to the third lower gate electrode GD3, impurities can prevent the characteristics of the third active region A3 from deteriorating. In other words, the third transistor T3 can be referred to as having a dual-gate electrode comprising the third upper gate electrode GU3 and the third lower gate electrode GD3.

[0110] A third interlayer insulating layer (ILD3) can be disposed on the third gate layer 1500. The third interlayer insulating layer (ILD3) can be used to insulate the third gate layer 1500 from the first interconnect layer 1800. The third interlayer insulating layer (ILD3) may include an insulating material. For example, the third interlayer insulating layer (ILD3) may include silicon oxide, silicon nitride, titanium oxide, or tantalum oxide, etc.

[0111] The first contact hole 1630 can penetrate the third interlayer insulating layer ILD3 and the second gate insulating layer GIL2 to expose the second active layer 1400.

[0112] The second contact hole 1716 can penetrate the third interlayer insulating layer ILD3, the second gate insulating layer GIL2, the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the first gate insulating layer GIL1 to expose the third portion 1130 of the first active layer 1100.

[0113] The third contact hole 1713 can penetrate the third interlayer insulating layer ILD3, the second gate insulating layer GIL2, the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the first gate insulating layer GIL1 to expose the first portion 1110 of the first active layer 1100.

[0114] The fourth contact hole 1620 can penetrate the third interlayer insulating layer ILD3 and the second gate insulating layer GIL2 to expose the second active layer 1400.

[0115] The fifth contact hole 1715 can penetrate the third interlayer insulating layer ILD3, the second gate insulating layer GIL2, the second interlayer insulating layer ILD2 and the first interlayer insulating layer ILD1 to expose the isolated structure 1230 of the first gate layer 1200.

[0116] The sixth contact hole 1712 can penetrate the third interlayer insulating layer ILD3, the second gate insulating layer GIL2, the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1 and the first gate insulating layer GIL1 to expose the second portion 1120 of the first active layer 1100.

[0117] The first connecting layer 1800 may be disposed on the third interlayer insulating layer ILD3. The first connecting layer 1800 may include a first connecting pattern 1850, a second connecting pattern 1840, and a third connecting pattern 1820.

[0118] In this embodiment, the first connection pattern 1850 may be arranged in the same column as the third transistor T3 and the sixth transistor T6 in the second direction D2, and may be placed between the third transistor T3 and the sixth transistor T6. A portion of the first connection pattern 1850 may overlap with the third portion 1130 of the first active layer 1100 in a plan view. Another portion of the first connection pattern 1850 may overlap with the second active layer 1400. The first connection pattern 1850 may fill the first contact hole 1630 and the second contact hole 1716. The first connection pattern 1850 can transmit and receive signals by electrically connecting the third portion 1130 of the first active layer 1100 to the second active layer 1400.

[0119] In one embodiment, a portion of the second connection pattern 1840 may overlap with a first portion 1110 of the first active layer 1100 in a plan view. The second connection pattern 1840 may fill the third contact hole 1713, the fourth contact hole 1620, and the fifth contact hole 1715. Therefore, the second connection pattern 1840 can transmit and receive signals by electrically connecting the first portion 1110 of the first active layer 1100 to the third portion 1130 of the first active layer 1100.

[0120] In an embodiment, in a plan view, a first portion of the third connection pattern 1820 may overlap with the gate initialization signal line 1210, a second portion of the third connection pattern 1820 may overlap with the second portion 1120 of the first active layer 1100, and a third portion of the third connection pattern 1820 may overlap with the initialization voltage line 1510. The third connection pattern 1820 may fill the sixth contact hole 1712.

[0121] A first via insulating layer VIA1 may be disposed on the first interconnect layer 1800. The first via insulating layer VIA1 can be used to insulate the first interconnect layer 1800 from the second interconnect layer 2000. The first via insulating layer VIA1 may include an organic insulating material. For example, the first via insulating layer VIA1 may include photoresist, polyacrylic resin, polyimide resin, or acrylic resin, etc.

[0122] The second connection layer 2000 may be disposed on the first through-hole insulating layer VIA1. The second connection layer 2000 may include a data signal line 2010 for transmitting data signal DATA, a high power voltage line 2020 for transmitting high power voltage ELVDD, and a fourth connection pattern 2030.

[0123] In an embodiment, the fourth connection pattern 2030 can transmit and receive signals by electrically connecting the first connection pattern 1850 and the second connection pattern 1840.

[0124] In an embodiment, in the high power voltage line 2020, the shielding pattern SD can be configured to cover the third upper gate electrode GU3, the third active region A3, and the third lower gate electrode GD3. In a plan view, the shielding pattern SD can completely overlap with the third upper gate electrode GU3, the third active region A3, and the third lower gate electrode GD3. When the third active region A3 comprises oxide semiconductor, it may be desirable for the shielding pattern SD to block the transmission of external light. However, when the shielding pattern SD is disposed in a wide area of ​​the pixel PX, the transmittance of external light may be reduced. Therefore, the sensitivity of the infrared sensor and / or fingerprint recognition sensor of the pixel PX may be reduced. Therefore, shielding the active region is desirable only when the active region of the transistor comprises oxide semiconductor. In other words, shielding the active region is not required when the active region of the transistor comprises polysilicon. More specifically, it is desirable to minimize the shielding area. In the organic light-emitting display device according to an embodiment of the present invention, only the third transistor T3 comprises oxide semiconductor, thereby minimizing the shielding area.

[0125] In this embodiment, the shielding pattern SD may not cover the fourth active region A4. More specifically, the shielding pattern SD may shield the third active region A3, but may not shield the fourth active region A4. Therefore, by reducing the area of ​​the shielding pattern SD, the transmittance of the organic light-emitting display device can be improved.

[0126] A second via insulating layer VIA2 can be disposed on the second interconnect layer 2000. The second via insulating layer VIA2 can be used to insulate the second interconnect layer 2000 from the organic light-emitting diode (OLED). The second via insulating layer VIA2 can include an organic insulating material. For example, the second via insulating layer VIA2 can include photoresist, polyacrylic resin, polyimide resin, or acrylic resin, etc.

[0127] Figure 17 It is along Figure 6 The cross-sectional view taken by line I-I' is used to describe the impurity region included in the fourth active region. Figure 18 and Figure 19 It is used to describe Figure 17 The diagram shows the formation of impurity regions.

[0128] refer to Figure 17 The fourth active region A4 may include an overlapping region AA, a first impurity region AA1, and a second impurity region AA2.

[0129] In this embodiment, the overlapping region AA may be the region in a plan view where the first portion 1110 of the first active layer 1100 and the gate initialization signal line 1210 of the first gate layer 1200 overlap. The first impurity region AA1 may be adjacent to the overlapping region AA. The second impurity region AA2 may be adjacent to the first impurity region AA1. In other words, the first impurity region AA1 may be located between the overlapping region AA and the second impurity region AA2.

[0130] refer to Figures 17 to 19 An organic light-emitting display device may include a first pixel PX1 adjacent to pixel PX in a first direction D1, a second pixel PX2 adjacent to pixel PX in a second direction D2, and a third pixel PX3 adjacent to the second pixel PX2 in the first direction D1. The first pixel PX1 is symmetrical to pixel PX in the first direction D1. The third pixel PX3 is symmetrical to the second pixel PX2 in the first direction D1.

[0131] In this embodiment, pixels PX, PX1, PX2, and PX3 may be in a state where the fabrication of the first active layer 1100, the first gate insulating layer GIL1, and the first gate layer 1200 has been completed. A first mask MASK10 may cover the point in each of pixels PX, PX1, PX2, and PX3 where the fourth transistor T4 and the seventh transistor T7 are placed. The first mask MASK10 may include sub-masks MASK11 to MASK13. To fabricate an organic light-emitting display device, a first process may be performed to dope a first impurity into the area not covered by the first mask MASK10. Therefore, each of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be a PMOS transistor.

[0132] Following the first process, a second process can be performed using a second mask 20 that covers the entire area of ​​the first gate layer 1200 and the region opposite the first mask 10. In the second process, a second impurity can be doped in the region not covered by the second mask 20. Through the second process, each of the fourth transistor T4 and the seventh transistor T7 can be an NMOS transistor.

[0133] In the second process of doping with a second impurity, the amount of photosensitive material surrounding the gate initialization signal line 1210 of the first gate layer 1200 can be controlled. Therefore, the concentration of the first impurity in the first impurity region AA1 and the concentration of the second impurity in the second impurity region AA2 can be controlled. The concentration of the first impurity in the first impurity region AA1 is less than the concentration of the second impurity in the second impurity region AA2. Therefore, the concentration of the first impurity in the first impurity region AA1 can have a value between a high concentration of the second impurity in the second impurity region AA2 and a low concentration of the impurity in the overlapping region AA. In other words, a lightly doped drain region can be formed to reduce the electric field strength at the boundary between the channel region of the fourth active region A4 and the source / drain region of the fourth active region A4.

[0134] Although specific embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. An organic light-emitting display device, comprising: The first transistor includes a first active region and a first gate electrode disposed on the first active region; The third transistor includes a third lower gate electrode disposed on the first gate electrode, a third active region disposed on the third lower gate electrode, and a third upper gate electrode disposed on the third active region; The fourth transistor includes a fourth active region disposed in the same layer as the first active region and a fourth gate electrode disposed on the fourth active region; and The shielding pattern covers the third active region, including the oxide semiconductor, but does not cover the fourth active region, including the polysilicon. Wherein the first transistor is a first type of transistor, and The fourth transistor is a second type of transistor, which is different from the first type of transistor.

2. The organic light-emitting display device according to claim 1, further comprising: The seventh transistor includes a seventh active region disposed in the same layer as the first active region and a seventh gate electrode disposed on the seventh active region.

3. The organic light-emitting display device according to claim 2, further comprising: The second transistor includes a second active region disposed in the same layer as the first active region and a second gate electrode disposed on the second active region. The fifth transistor includes a fifth active region disposed in the same layer as the first active region and a fifth gate electrode disposed on the fifth active region; as well as The sixth transistor includes a sixth active region disposed in the same layer as the first active region and a sixth gate electrode disposed on the sixth active region.

4. The organic light-emitting display device according to claim 1, wherein, The third transistor is an NMOS transistor.

5. The organic light-emitting display device according to claim 3, wherein, Each of the first active region, the second active region, the fourth active region, the fifth active region, the sixth active region, and the seventh active region comprises polycrystalline silicon.

6. The organic light-emitting display device according to claim 5, wherein, Each of the fourth and seventh transistors is an NMOS transistor.

7. The organic light-emitting display device according to claim 6, wherein, Each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor is a PMOS transistor.

8. The organic light-emitting display device according to any one of claims 1 to 7, wherein, The shielding pattern is disposed on the third upper gate electrode.

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