Stacked memory and reset method for memory dies of stacked memory

Abstract

The application discloses a stacked memory and a reset method of a memory die thereof, comprising: a plurality of memory dies; each memory die is provided with a reset circuit and has independent fuse information, the fuse information is obtained by fusing a group of fuses in a plurality of groups of fuses arranged in the memory die according to a fuse arrangement combination mode, and the fuse arrangement combination mode used by the memory die is determined according to a manufacturing process of the stacked memory in sequence; and each memory die is selected and controlled by a signal containing the fuse information. That is, the memory dies in the stacked memory of the application can be selected and controlled in a horizontal direction, and when the memory dies need to be taken down for reuse, the fuse information on the reset circuit can be reset, so that the remaining unused fuse groups in the memory dies can be used, thereby achieving the purpose that the memory dies can be reused, and improving the utilization of the chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and more specifically to a stacked memory and a method for resetting the memory die of the stacked memory. Background Technology

[0002] In the current manufacturing scheme of stacked memory, memory dies including memory arrays and control dies including peripheral circuits are fabricated separately. Multiple memory dies and control dies are then stacked and packaged, and the stacked dies are electrically connected to each other through through silicon vias (TSVs).

[0003] However, stacked dies can only be used in designated locations, thus reducing the usability of the dies and negatively impacting the final product yield. Summary of the Invention

[0004] The purpose of this application is to address the shortcomings of the prior art by proposing a stacked memory and a method for resetting the memory die thereon, which is achieved through the following technical solution.

[0005] The first aspect of this application proposes a stacked memory, comprising:

[0006] Multiple memory dies, and each memory die is equipped with a reset circuit;

[0007] Each of the memory dies has independent fuse information. The fuse information is obtained by fusing one set of fuses from multiple sets of fuses in the memory die according to a fuse arrangement and combination method. The fuse arrangement and combination method used by each memory die is determined sequentially according to the manufacturing process of the stacked memory.

[0008] Each of the aforementioned memory dies can be individually selected and controlled by a signal containing fuse information.

[0009] A second aspect of this application proposes a method for resetting the storage die of a stacked memory, the method comprising:

[0010] The fuse information of the storage die is reset by a reset circuit in the storage die so that the storage die can be reused.

[0011] The memory die has independent fuse information, which is obtained by fusing one set of fuses from multiple sets of fuses in the memory die according to a certain fuse arrangement and combination method. The fuse arrangement and combination method used by the memory die is determined sequentially according to the manufacturing process of the stacked memory. The memory die is individually selected and controlled by a signal containing fuse information.

[0012] A third aspect of this application provides an electronic device including a stacked memory as described in the first aspect above.

[0013] The stacked memory and the method for resetting the memory die of the stacked memory described above have the following beneficial effects:

[0014] This application, based on the removal of logic dies, sequentially determines a fuse arrangement for each memory die during the manufacturing process of a stacked memory. This causes the fuses in the memory die to be blown according to the determined fuse arrangement, obtaining an independent fuse information. Therefore, each memory die can be individually selected and controlled by a signal containing the fuse information. In other words, the memory dies in the stacked memory can be distinguished, selected, and controlled horizontally. Based on this, by setting a reset circuit in each memory die, when a memory die needs to be removed for reuse, the reset circuit can reset its fuse information, allowing the remaining unused fuse groups in the memory die to be used. This achieves the goal of reusing the memory die, improving chip reusability, thereby increasing the final product yield and reducing costs. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0016] Figure 1 This application illustrates a schematic diagram of a stacked memory structure in a related art.

[0017] Figure 2 This is a schematic diagram illustrating the structure of a stacked memory according to an exemplary embodiment of this application;

[0018] Figure 3 This is a schematic diagram illustrating the resetting of a stacked memory die according to an exemplary embodiment of this application. Detailed Implementation

[0019] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0020] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0021] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0022] See Figure 1 The stacked memory in the prior art shown includes memory dies and logic dies that are sequentially stacked in a vertical direction. The dies are electrically connected to each other through through-silicon vias. The memory dies include a memory array to provide memory processing functions, and the logic dies include a control peripheral circuit to provide standard memory access coordination functions, such as page table translation, address mapping, and write combination.

[0023] For example Figure 1 As shown, the stacked memory also includes processing units and a packaging substrate stacked with the die.

[0024] The processing unit is either a programmable processing unit or a reprogrammable processing unit. In some embodiments, the reprogrammable processing unit includes logic circuitry that can be dynamically programmed to perform various functions or execute certain instructions. In one embodiment, the reprogrammable processing unit may be configured to execute instructions that include memory processing functions controlling the memory die. The reprogrammable processing unit may include, but is not limited to, field-programmable gate arrays, application-specific integrated circuits, programmable array logic, and other similar devices. The package substrate may be configured to communicate with other components or dies and externally throughout the system.

[0025] In terms of storage, Figure 1 Each memory die is divided into n memory partitions, each partition includes several memory banks, and each partition is stacked on top of each other in a vertical direction through through-silicon vias. Each stacked group of partitions can be called a vault. The processing unit can independently access each vault through the logic die for read and write operations.

[0026] Because stacked memory dies are divided into storage partitions along the vertical direction, individual dies cannot be identified. As a result, stacked dies can only be used in designated locations, and individual dies cannot be reused. This reduces the usability of the dies and negatively impacts the final product yield.

[0027] It should be noted that the above Figure 1 The example shown only depicts one logic die, but the actual product does not limit the number of logic dies.

[0028] To address the aforementioned technical issues, after removing the logic dies, during the manufacturing process of the stacked memory, a specific fuse arrangement is determined for each memory die. The fuses in the memory die are then blown according to this predetermined arrangement, generating an independent fuse information. This allows each memory die to be individually selected and controlled by a signal containing the fuse information. In other words, the memory dies in the stacked memory can be distinguished, selected, and controlled horizontally. Based on this, by incorporating a reset circuit into each memory die, when a die needs to be removed for reuse, the reset circuit can reset its fuse information. This allows the remaining unused fuse groups on the memory die to be used, thereby achieving the goal of reusing the memory dies, improving chip reusability, increasing final product yield, and reducing costs.

[0029] See Figure 2 This application illustrates a stacked memory according to an exemplary embodiment, comprising: n memory dies, each memory die having a reset circuit.

[0030] Each memory die has independent fuse information, which is obtained by fusing one set of fuses from multiple sets of fuses on the memory die according to a specific fuse arrangement. The fuse arrangement used for each memory die is determined sequentially according to the manufacturing process of the stacked memory, and each memory die can be individually selected and controlled by a signal containing the fuse information. For example, this signal can be generated and controlled by a processing unit.

[0031] In practice, in order to enable the memory die to be reused, at least two sets of fuses must be installed in the memory die. One set of fuses is used when the memory die is used for the first time, and the other set of fuses can be used when it is used again.

[0032] Furthermore, to ensure the uniqueness of the fuse information for each memory die, the number of fuses in each group of fuses on the memory die can be determined based on the number of memory dies. For example, if there are 4 memory dies, then each group of fuses on each memory die needs at least 2 fuses, meaning there are four possible fuse combinations: 00, 01, 10, and 11. Each memory die corresponds to one fuse combination, where 0 indicates no fuse and 1 indicates fuse.

[0033] For example, starting from the first memory die at the top, the second memory die, the third memory die, ... the nth memory die are stacked together in sequence along the vertical direction. Thus, according to the stacking order, a circuit breaker arrangement 1 is determined for the first memory die, and circuit breaker information 1 is obtained. A circuit breaker arrangement 2 is determined for the second memory die, and circuit breaker information 2 is obtained. And so on, a circuit breaker arrangement n is determined for the nth memory die, and circuit breaker information 3 is obtained.

[0034] Furthermore, since the storage die is selected based on the fuse information, the fuse information needs to be recorded on both the storage die and the external controller for mutual verification and future lookup.

[0035] It should be noted that the fuse information for each storage die is obtained by melting the fuse in the storage die during the stacking process.

[0036] In some embodiments, each memory die may also include a selection section electrically connected to a reset circuit.

[0037] For example Figure 2 As shown, the stacked memory also includes a processing unit and a packaging substrate, with the processing unit electrically connected to a reset circuit.

[0038] The processing unit can be configured to execute instructions that include storage processing functions that control the memory die, as well as instructions that generate and control the fuse information for resetting the memory die.

[0039] Therefore, a fuse may be included in the reset circuit.

[0040] When the memory die needs to be removed for reuse, the selection section in the memory die receives a reset command and blows the fuse in the reset circuit based on the reset command to reset the fuse information of the memory die, so that the memory die can be reused.

[0041] When a memory die is reused, the unused fuse group in the memory die needs to be used to obtain independent fuse information again.

[0042] In some embodiments, the fuse involved in the above embodiments may be an electric fuse or a metal fuse, and this application does not specifically limit it.

[0043] In some embodiments, each memory die includes a memory array and peripheral drive circuitry.

[0044] Based on the above description, the memory dies in the stacked memory proposed in this application can be selected and controlled horizontally. Therefore, by providing a reset circuit in each memory die, when a memory die needs to be removed for reuse, the reset circuit can reset the fuse information on it, allowing the remaining unused fuse groups in the memory die to be used. This achieves the goal of reusing the memory die, improving chip utilization, thereby increasing the final product yield and reducing costs.

[0045] In some embodiments, to enable communication between n memory dies, through-silicon vias (TSVs) can be provided at the same location on each of the n memory dies. These TSVs are used to electrically connect the n memory dies.

[0046] In some embodiments, the stacked memory may further include a switch selection circuit. Figure 2 (Not shown in the image), the switch selection circuit is electrically connected to each memory die to send a signal to the corresponding memory die based on the fuse information of the memory die contained in the signal.

[0047] The signal can be generated by the processing unit according to actual needs and sent to the switch selection circuit, or it can be generated by the processing unit according to the control command generated by the external controller and sent to the switch selection circuit.

[0048] The signal can be a row active command or a column active command.

[0049] For example, the switch selection circuit can be constructed using a pass-gate structure or a logic circuit.

[0050] Based on the above Figure 2 The stacked memory structure shown below will be described in detail below with specific embodiments to illustrate the reset process of the memory die of the stacked memory.

[0051] The method for resetting the storage die of the stacked memory includes the following steps:

[0052] Step 301: Reset the fuse information of the storage die by resetting the reset circuit in the storage die so that the storage die can be reused.

[0053] Each memory die includes a memory array and peripheral drive circuitry, and each memory die is a valid die that has passed testing.

[0054] Based on the above Figure 2 In the illustrated embodiment, the storage die has independent fuse information, which is obtained by fusing one set of fuses from multiple sets of fuses provided in the storage die according to a fuse arrangement and combination method. The fuse arrangement and combination method used by the storage die is determined sequentially according to the manufacturing process of the stacked memory.

[0055] Each memory die can be individually selected and controlled by a signal containing fuse information. During the fabrication of the stacked memory, the fuse information can be recorded on the memory die and an external controller for mutual verification and future lookup.

[0056] Specifically, the reset process can be as follows: the selection unit in the memory die receives a reset command, and based on the reset command, the selection unit blows the fuse contained in the reset circuit to reset the fuse information of the memory die, so that the memory die can be removed for reuse to manufacture the next stack.

[0057] For example, a reset command can be generated by the processing unit based on an instruction from an external controller and sent to the storage die.

[0058] like Figure 3 The diagram shown illustrates the reset of a memory die. In computers, data storage and identification are performed according to specific rules. Therefore, the memory die has a fuse information decoding section. The fuse information is recorded on the memory die in the form of data decoded by the decoding section. During reset, the fuse information decoding section in the selection unit translates the fuse information in the reset command into a specific data form and determines whether it is the fuse information of this memory die. If it is, the selection unit blows the fuse included in the reset circuit to reset the fuse information of the memory die.

[0059] This application also proposes an electronic device, which includes the features described above. Figure 2 The stacked memory.

[0060] For example, the stacked memory can be any one of dynamic random access memory (DRAM), thyristor random access memory (TRAM), static random access memory (SRAM), and non-volatile memory (such as read-only memory, flash memory, ferroelectric random access memory, magnetoresistive random access memory, etc.).

[0061] In some embodiments, the electronic device may include a smartphone, computer, tablet, wearable smart device, artificial intelligence device, or power bank.

[0062] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0063] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A stacked memory comprising a plurality of memory dies, characterized in that, Each of the plurality of memory dies is provided with a reset circuit; Each of the memory dies has independent fuse information. The fuse information is obtained by fusing one set of fuses from multiple sets of fuses provided in the memory die according to a fuse arrangement and combination method. The fuse arrangement and combination method used by each memory die is determined sequentially according to the manufacturing process of the stacked memory. The number of fuses in each set of fuses is determined according to the number of multiple memory dies. Each of the aforementioned memory dies is individually selected and controlled by a signal containing fuse information; Each of the memory dies is further provided with a selection section, and the reset circuit is electrically connected to the selection section. The selection section is used to receive a reset command and, based on the reset command, blow the unused fuse group included in the reset circuit when it is necessary to remove the memory die for reuse.

2. The memory according to claim 1, characterized in that, The fuse is an electric fuse and / or a metal fuse.

3. The memory according to claim 1, characterized in that, The reset circuit includes a fuse.

4. A method for resetting a storage die in a stacked memory, characterized in that, The method includes: The fuse information of the storage die is reset by a reset circuit in the storage die so that the storage die can be reused. The memory die has independent fuse information, which is obtained by fusing one group of fuses from multiple sets of fuses on the memory die according to a specific fuse arrangement. The fuse arrangement used by the memory die is determined sequentially according to the manufacturing process of the stacked memory. The memory die is individually selected and controlled by a signal containing fuse information. The number of fuses in each set is determined according to the number of memory dies. The step of resetting the fuse information of the storage die through a reset circuit in the storage die includes: The selection section in the storage die receives a reset command; The selection unit melts the fuse contained in the reset circuit based on the reset command, thereby resetting the fuse information of the memory die.

5. An electronic device comprising a stacked memory as described in any one of claims 1 to 3.

6. The electronic device according to claim 5 includes a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, and power bank.

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