Display substrate and its preparation method, display device

Abstract

A display substrate includes a display area and a peripheral area surrounding the display area. A scan driving circuit is disposed in the peripheral area. The display area has multiple sub-pixels and multiple first signal lines connected to the scan driving circuit and extending along a first direction. The display area includes a substrate and a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on the substrate. The third conductive layer includes multiple first signal lines and first and second electrodes of multiple transistors. An insulating layer between the third conductive layer and the first conductive layer has a first via, and the first signal lines contact the control electrode of the transistors exposed through the first via in the first conductive layer.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display substrates are different from traditional liquid crystal display (LCD) substrates, possessing advantages such as active light emission, good temperature characteristics, low power consumption, fast response, flexibility, ultra-thinness, and low cost. Therefore, OLED display substrates have become one of the important developments in next-generation display devices and are receiving increasing attention. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, a method for fabricating the same, and a display device.

[0005] On one hand, this disclosure provides a display substrate, including: a display area and a peripheral area surrounding the display area, the peripheral area being provided with a scan driving circuit, the display area being provided with a plurality of sub-pixels and a plurality of first signal lines connected to the scan driving circuit and extending along a first direction. At least one of the plurality of sub-pixels includes: a light-emitting element and a driving circuit for driving the light-emitting element to emit light, the driving circuit including a plurality of transistors and a storage capacitor. The display area includes: a substrate and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially disposed on the substrate. The semiconductor layer includes: an active layer of a plurality of transistors; the first conductive layer includes: a control electrode of a plurality of transistors and a first electrode of a storage capacitor; the second conductive layer includes: a second electrode of the storage capacitor; the third conductive layer includes: a plurality of first signal lines and a first electrode and a second electrode of a plurality of transistors; an insulating layer between the third conductive layer and the first conductive layer is provided with a first via, the first signal lines contacting the control electrode of the transistor exposed by the first conductive layer through the first via.

[0006] On the other hand, this disclosure provides a display device including a display substrate as described above.

[0007] On the other hand, this disclosure provides a method for fabricating a display substrate, for fabricating the display substrate as described above, comprising: providing a substrate; and sequentially forming a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer on the substrate in a display area. The semiconductor layer includes an active layer of a plurality of transistors; the first conductive layer includes a control electrode of the plurality of transistors and a first electrode of a storage capacitor; the second conductive layer includes a second electrode of the storage capacitor; the third conductive layer includes a plurality of first signal lines and a first electrode and a second electrode of the plurality of transistors; an insulating layer between the third conductive layer and the first conductive layer is provided with a first via, and the first signal lines contact the control electrode of the transistor exposed by the first conductive layer through the first via.

[0008] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0009] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0010] Figure 1 This is a schematic diagram of the structure of a display substrate according to at least one embodiment of the present disclosure;

[0011] Figure 2 This is a schematic diagram of the structure of a scanning drive circuit according to at least one embodiment of the present disclosure;

[0012] Figure 3 This is an equivalent circuit diagram of a shift register unit according to at least one embodiment of the present disclosure;

[0013] Figure 4 for Figure 3 The provided timing diagram for the shift register unit;

[0014] Figure 5 This is an equivalent circuit diagram of the driving circuit for a sub-pixel according to at least one embodiment of the present disclosure;

[0015] Figure 6 for Figure 5 The provided timing diagram of the driver circuit is shown.

[0016] Figure 7 This is a top view of a sub-pixel of a display substrate according to at least one embodiment of the present disclosure;

[0017] Figure 8 for Figure 7 A cross-sectional view along the QQ direction;

[0018] Figure 9This is a top view of a display substrate after the semiconductor layer has been formed in at least one embodiment of this disclosure;

[0019] Figure 10 This is a top view of a display substrate after the first conductive layer has been formed in at least one embodiment of this disclosure;

[0020] Figure 11 This is a top view of a display substrate after the second conductive layer has been formed in at least one embodiment of this disclosure;

[0021] Figure 12 This is a top view of a display substrate after the third conductive layer has been formed in at least one embodiment of the present disclosure;

[0022] Figure 13 This is a top view of a display substrate after the fourth conductive layer has been formed in at least one embodiment of this disclosure;

[0023] Figure 14 This is a top view of a plurality of sub-pixels of a display substrate according to at least one embodiment of the present disclosure;

[0024] Figure 15 This is a simulation schematic diagram of the gate driving of a display substrate according to at least one embodiment of the present disclosure;

[0025] Figure 16 include Figure 16 (a) and Figure 16 (b) shows a schematic diagram of the gate drive delay;

[0026] Figure 17 This is a schematic flowchart of a method for preparing a display substrate according to at least one embodiment of the present disclosure;

[0027] Figure 18 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0028] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0029] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique technical solution as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other technical solutions to form another unique technical solution as defined by the claims. Therefore, it should be understood that any feature shown or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, one or more modifications and changes may be made within the scope of the appended claims.

[0030] Furthermore, in describing representative embodiments, the specification may have presented a method or process as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0031] The embodiments will now be described with reference to the accompanying drawings. These embodiments can be implemented in several different forms. Those skilled in the art will readily understand that the methods and content can be varied in different forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited to the content described in the following embodiments.

[0032] In the accompanying drawings, the size of each component, the thickness of a layer, or the area are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of each part in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0033] The ordinal numbers such as "first," "second," and "third" used in this disclosure are provided to avoid confusion among the constituent elements, not to limit the quantity. In this disclosure, "multiple" can refer to two or more numbers.

[0034] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "above" or "below" another element, that element may be located "directly" above or below the other element, or there may be intermediate elements. The positional relationships of the constituent elements vary appropriately depending on the direction in which each constituent element is described. Therefore, the terminology used is not limited to those described in the specification and may be appropriately replaced as appropriate.

[0035] In this disclosure, terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. An “electrical connection” includes situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the “component having some electrical function” as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of “components having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0036] In this disclosure, "parallel" means that the angle formed by two straight lines is greater than or equal to -10° and less than 10°, or may include the angle being greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" means that the angle formed by two straight lines is greater than or equal to 80° and less than 100°, or may include the angle being greater than or equal to 85° and less than 95°.

[0037] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0038] In this disclosure, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0039] Those skilled in the art will understand that the transistors used in all embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Exemplarily, the thin-film transistors used in the embodiments of this disclosure can be oxide semiconductor transistors. Since the source and drain electrodes of the switching transistors used here are symmetrical, their source and drain electrodes can be interchanged. In the embodiments of this disclosure, the control electrode can be the gate electrode. To distinguish the two electrodes of the transistor other than the gate electrode, one electrode is called the first electrode, and the other electrode is called the second electrode. The first electrode can be either the source electrode or the drain electrode, and the second electrode can be either the drain electrode or the source electrode.

[0040] With the widespread application and development of display technology, the market demand for medium and large-sized OLED display substrates is gradually emerging. As the resolution of OLED display substrates increases, the scanning time of each row of sub-pixels in the OLED display substrate becomes shorter, and the data signal writing time continues to decrease. As the size of OLED display substrates increases, the length of the horizontally arranged gate lines within the OLED display substrate gradually increases, which can easily lead to more severe gate delay, resulting in insufficient charging of sub-pixels; moreover, with the increase of refresh rate, the trend of insufficient charging becomes more and more obvious.

[0041] This disclosure provides a display substrate and its preparation method, as well as a display device, which can improve the resolution and refresh rate of the display substrate.

[0042] This disclosure provides at least one embodiment of a display substrate, including: a display area and a peripheral area surrounding the display area. A scan driving circuit is disposed in the peripheral area. The display area has a plurality of sub-pixels and a plurality of first signal lines connected to the scan driving circuit and extending along a first direction. At least one of the plurality of sub-pixels includes: a light-emitting element and a driving circuit for driving the light-emitting element to emit light; the driving circuit includes a plurality of transistors and a storage capacitor. The display area includes: a substrate and a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on the substrate. The semiconductor layer includes: an active layer of a plurality of transistors. The first conductive layer includes: a control electrode of a plurality of transistors and a first electrode of a storage capacitor. The second conductive layer includes: a second electrode of a storage capacitor. The third conductive layer includes: a plurality of first signal lines and a first electrode and a second electrode of a plurality of transistors. A first via is disposed in an insulating layer between the third conductive layer and the first conductive layer, and the first signal lines contact the control electrode of the transistors exposed by the first via in the first conductive layer.

[0043] The display substrate provided in this embodiment has the first signal line used to connect the control electrode of the transistor and the scanning drive circuit disposed on the same layer as the first and second electrodes of the transistor. The connection between the first signal line and the control electrode of the transistor is realized through the first via disposed on the insulating layer between the third conductive layer and the first conductive layer. This can greatly reduce the impedance of the first signal line, thereby reducing the gate drive delay of the sub-pixel drive circuit and increasing the effective charging time, which in turn can improve the resolution and refresh rate of the display substrate.

[0044] In some exemplary embodiments, the display area further includes a fourth conductive layer disposed on the side of the third conductive layer away from the substrate. The fourth conductive layer includes a plurality of second signal lines extending along a second direction perpendicular to the first direction. An insulating layer between the fourth and third conductive layers is provided with a second via, and the second signal lines contact a first or second electrode of a transistor exposed by the third conductive layer through the second via. In this exemplary embodiment, by placing the second signal lines perpendicular to the extension direction of the first signal lines in the fourth conductive layer, direct intersection between the second and first signal lines can be avoided.

[0045] In some exemplary embodiments, the third conductive layer may include a three-layer stacked structure formed of titanium (Ti), aluminum (Al), and titanium. That is, the third conductive layer may include a titanium layer, an aluminum layer, and a titanium layer stacked sequentially. However, this embodiment is not limited to this. In some examples, the third conductive layer may be a single-layer metal structure. In this exemplary embodiment, using a metal material with low resistivity to form the third conductive layer can reduce the resistance of the first signal line.

[0046] In some exemplary embodiments, the orthographic projection of the first signal line on the substrate may at least partially overlap with the orthographic projection of the control electrode of the transistor connected to the first signal line on the substrate. In some examples, the orthographic projection of the first signal line on the substrate may cover the orthographic projection of the control electrode of the transistor connected to the first signal line on the substrate. However, this embodiment is not limited in this respect.

[0047] In some exemplary embodiments, a plurality of first vias may be provided along the extension direction of the first signal line, and the orthogonal projection of the first signal line on the substrate may cover the orthogonal projection of the first vias on the substrate.

[0048] In some exemplary embodiments, the first signal line may include a scan line. The scan driving circuit may include multiple cascaded shift register units, wherein the i-th level shift register unit can provide a scan signal to the sub-pixel of the i-th row through the scan line, where i is an integer greater than 0.

[0049] In some exemplary embodiments, the first signal line may include a scan line and a reset signal line. The scan driving circuit may include multiple cascaded shift register units. The i-th level shift register unit can provide a scan signal to the i-th row sub-pixel through the scan line, and the i-th level shift register unit can provide a reset signal to the (i+1)-th row sub-pixel through the reset signal line, where i is an integer greater than 0.

[0050] In some exemplary embodiments, the shift register unit may include: a first transistor to an eighth transistor, a first capacitor, and a second capacitor. The control electrode of the first transistor is connected to a first clock signal terminal, the first terminal of the first transistor is connected to a first voltage terminal, and the second terminal of the first transistor is connected to a first control node. The control electrode of the second transistor is connected to a second control node, the first terminal of the second transistor is connected to the first clock signal, and the second terminal of the second transistor is connected to the first control node. The control electrode of the third transistor is connected to the first clock signal terminal, the first terminal of the third transistor is connected to an input signal terminal, and the second terminal of the third transistor is connected to a second control node. The control electrode of the fourth transistor is connected to the first control node, the first terminal of the fourth transistor is connected to a second voltage terminal, and the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor. The control electrode of the fifth transistor is connected to a second clock signal terminal, and the second terminal of the fifth transistor is connected to the second control node. The control electrode of the sixth transistor is connected to the first voltage terminal, the first terminal of the sixth transistor is connected to the second control node, and the second terminal of the sixth transistor is connected to the third control node. The control electrode of the seventh transistor is connected to the third control node, the first terminal of the seventh transistor is connected to an output terminal, and the second terminal of the seventh transistor is connected to a second clock signal terminal. The control electrode of the eighth transistor is connected to the first control node, the first electrode of the eighth transistor is connected to the second voltage terminal, and the second electrode of the eighth transistor is connected to the output terminal. The first electrode of the first capacitor is connected to the output terminal, and the second electrode of the first capacitor is connected to the third control node. The first electrode of the second capacitor is connected to the second voltage terminal, and the second electrode of the second capacitor is connected to the first control node. However, this embodiment is not limited to this.

[0051] In some exemplary embodiments, a light-emitting driving circuit may also be provided in the peripheral area. The display area may also be provided with a plurality of light-emitting control lines connected to the light-emitting driving circuit and extending along a first direction. The light-emitting driving circuit can provide light-emitting control signals to the sub-pixels through the light-emitting control lines. The first conductive layer may further include a plurality of light-emitting control lines. The light-emitting control lines and the control electrode of at least one transistor in the driving circuit of a row of sub-pixels may be an integral structure. However, this embodiment is not limited to this.

[0052] In some exemplary embodiments, the second signal line may include a data line, a first power line, and an initial signal line. In some examples, each column of sub-pixels may be connected to the same data line and the same first power line. In some examples, each row of sub-pixels may be connected to the same initial signal line. However, this embodiment is not limited in this respect.

[0053] In some exemplary embodiments, the display area may further include: a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The first insulating layer may be disposed between the semiconductor layer and the first conductive layer; the second insulating layer may be disposed between the first conductive layer and the second conductive layer; the third insulating layer may be disposed between the second conductive layer and the third conductive layer; and the fourth insulating layer may be disposed between the third conductive layer and the fourth conductive layer.

[0054] In some exemplary embodiments, for at least one sub-pixel, the driving circuit may include a plurality of transistors: a first switching transistor to a sixth switching transistor, and a driving transistor. The control electrode of the first switching transistor is connected to a scan line, the first electrode of the first switching transistor is connected to a data line, and the second electrode of the first switching transistor is connected to the first electrode of the driving transistor. The control electrode of the second switching transistor is connected to a scan line, the first electrode of the second switching transistor is connected to the control electrode of the driving transistor, and the second electrode of the second switching transistor is connected to the second electrode of the driving transistor. The control electrode of the third switching transistor is connected to a light emission control line, the first electrode of the third switching transistor is connected to a first power supply line, and the second electrode of the third switching transistor is connected to the first electrode of the driving transistor. The control electrode of the fourth switching transistor is connected to a light emission control line, the first electrode of the fourth switching transistor is connected to the second electrode of the driving transistor, and the second electrode of the fourth switching transistor is connected to the first electrode of the light-emitting element. The control electrode of the fifth switching transistor is connected to a reset signal line, the first electrode of the fifth switching transistor is connected to an initial signal line, and the second electrode of the fifth switching transistor is connected to the first electrode of the second switching transistor. The control electrode of the sixth switching transistor is connected to a reset signal line, the first electrode of the sixth switching transistor is connected to the initial signal line, and the second electrode of the sixth switching transistor is connected to the first electrode of the light-emitting element. The first electrode of the storage capacitor is connected to the control electrode of the driving transistor, and the second electrode of the storage capacitor is connected to the first power supply line. In this exemplary embodiment, the driving circuit of the sub-pixel can be a 7T1C (including 7 transistors and 1 capacitor) structure. However, this embodiment is not limited to this. In some examples, the driving circuit of the sub-pixel can be a 2T1C or 3T1C structure, etc.

[0055] In some exemplary embodiments, the reset signal lines connected to the control electrodes of the fifth and sixth switching transistors can be located on opposite sides of the scan lines connected to the control electrodes of the first and second switching transistors, respectively. In some examples, the distance between the reset signal line connected to the control electrode of the sixth switching transistor and the scan line can be greater than the distance between the reset signal line connected to the control electrode of the fifth switching transistor and the scan line. However, this embodiment is not limited to this.

[0056] In some exemplary embodiments, the second electrodes of storage capacitors in adjacent sub-pixels located in the same row can be in direct contact. In some examples, the second electrodes of storage capacitors in adjacent sub-pixels located in the same row can be a single, integrated structure. However, this embodiment is not limited to this.

[0057] In some exemplary embodiments, the first electrode of the storage capacitor and the control electrode of the driving transistor can be an integral structure. The second electrode of the storage capacitor can have a hollowed-out region, and the orthographic projection of the control electrode of the driving transistor on the substrate can cover the orthographic projection of the hollowed-out region on the substrate. The first electrode of the second switching transistor can be connected to the control electrode of the driving transistor through the hollowed-out region.

[0058] In some exemplary embodiments, the display area may further include: a fifth conductive layer, a fifth insulating layer disposed between the fourth conductive layer and the fifth conductive layer, an organic light-emitting layer of a light-emitting element disposed on the side of the fifth conductive layer away from the substrate, and a second electrode. The fifth conductive layer may include a first electrode of the light-emitting element. The second electrode of the light-emitting element may be disposed on the side of the organic light-emitting layer away from the substrate. In some examples, the first electrode of the light-emitting element may be the anode of the light-emitting element, and the second electrode of the light-emitting element may be the cathode of the light-emitting element.

[0059] The following examples illustrate the display substrate provided in the embodiments of this disclosure.

[0060] Figure 1 This is a schematic diagram of the structure of a display substrate according to at least one embodiment of the present disclosure. Figure 1 As shown, the display substrate of this exemplary embodiment may include: a display area AA and a peripheral area located around the display area AA. The display area AA may be provided with a plurality of sub-pixels P arranged in a regular manner along a first direction (e.g., Figure 1 Multiple first signal lines (including scan lines and reset signal lines) extending in the X direction and multiple light emission control lines along the second direction (such as...) Figure 1 Multiple second signal lines (including data lines, first power lines, and initial signal lines) extending in the Y direction. The first and second directions can be located in the same plane, and the first direction can be perpendicular to the second direction. In this example, each first signal line can extend in the X direction, and the multiple first signal lines can be arranged sequentially in the Y direction; each second signal line can extend in the Y direction, and the multiple second signal lines can be arranged sequentially in the X direction.

[0061] like Figure 1As shown, M rows of scan lines G1 to GM are arranged along the Y direction, and N columns of data lines D1 to DN are arranged along the X direction in a manner that keeps them insulated from the scan lines. Here, M and N are both integers greater than 0. Sub-pixels P can be distributed at the intersections of the M rows of scan lines and the N columns of data lines, and multiple sub-pixels P are arranged according to a matrix rule. In some examples, three sub-pixels emitting different colors of light (e.g., red, green, blue) or four sub-pixels emitting different colors of light (e.g., red, green, blue, white) can form a pixel unit. However, this embodiment is not limited to this.

[0062] To facilitate the distinction between scan lines and sub-pixel rows, in Figure 1 Sometimes, rows are sequentially named from top to bottom as row 1, row 2, ..., row M. Similarly, to easily distinguish between data lines and sub-pixel columns, in... Figure 1 Sometimes, columns are named sequentially from left to right as column 1, column 2, ..., column N.

[0063] In this exemplary embodiment, the peripheral area may be provided with a timing controller 10, a data driving circuit 11, a scanning driving circuit 12, and a light-emitting driving circuit 13. The scanning driving circuit 12 and the light-emitting driving circuit 13 may be respectively disposed on opposite sides of the display area AA (e.g., left and right sides), while the timing controller 10 and the data driving circuit 11 may be disposed on one side of the display area AA. However, this embodiment is not limited in this respect.

[0064] In this exemplary embodiment, the data driving circuit 11 can provide data signals to the sub-pixels via data lines. The scan driving circuit 12 can provide scan signals to the sub-pixels via scan lines and reset signals via reset signal lines. The light-emitting driving circuit 13 can provide light-emitting control signals to the sub-pixels via light-emitting control lines. The timing controller 10 can provide driving signals to the data driving circuit 11, the scan driving circuit 12, and the light-emitting driving circuit 13. The operation of the scan driving circuit 12, the data driving circuit 11, and the light-emitting control circuit 13 can be controlled by the timing controller 10. The timing controller 10 can provide the data driving circuit 11 with grayscale data specifying the grayscale level to be displayed in the sub-pixels. The data driving circuit 11 can provide a data signal corresponding to the potential of the grayscale data of the sub-pixels to the sub-pixels of the row selected by the scan driving circuit 12 via data lines.

[0065] Figure 2 This is a schematic diagram of the structure of a scanning drive circuit according to at least one embodiment of the present disclosure. Figure 2As shown, the scan driving circuit of this exemplary embodiment may include multiple cascaded shift register units. The signal input terminal INPUT(1) of the first-stage shift register unit is connected to the initial signal terminal STV, and the output terminal GP(i) of the i-th-stage shift register unit is connected to the signal input terminal INPUT(i+1) of the (i+1)-th-stage shift register unit. The output terminal GP(i) of the i-th-stage shift register unit can provide a scan signal to the sub-pixel of the i-th row via a scan line, and a reset signal to the sub-pixel of the (i+1)-th row via a reset signal line. Here, i is an integer greater than 0.

[0066] Figure 3 This is an equivalent circuit diagram of any stage shift register unit of the scan drive circuit according to at least one embodiment of the present disclosure. Figure 3 As shown, the shift register unit of this exemplary embodiment may include: a first transistor M1 to an eighth transistor M8, a first capacitor C1, and a second capacitor C2.

[0067] In this exemplary embodiment, the control electrode of the first transistor M1 is connected to the first clock signal terminal CLK1, the first terminal of the first transistor M1 is connected to the first voltage terminal VGL, and the second terminal of the first transistor M1 is connected to the first control node P1. The control electrode of the second transistor M2 is connected to the second control node P2, the first terminal of the second transistor M2 is connected to the first clock signal terminal CLK1, and the second terminal of the second transistor M2 is connected to the first control node P1. The control electrode of the third transistor M3 is connected to the first clock signal terminal CLK1, the first terminal of the third transistor M3 is connected to the signal input terminal INPUT, and the second terminal of the third transistor M3 is connected to the second control node P2. The control electrode of the fourth transistor M4 is connected to the first control node P1, the first terminal of the fourth transistor M4 is connected to the second voltage terminal VGH, and the second terminal of the fourth transistor M4 is connected to the first terminal of the fifth transistor M5. The control electrode of the fifth transistor M5 is connected to the second clock signal terminal CLK2, and the second terminal of the fifth transistor M5 is connected to the second control node P2. The control electrode of the sixth transistor M6 is connected to the first voltage terminal VGL, the first electrode of the sixth transistor M6 is connected to the second control node P2, and the second electrode of the sixth transistor M6 is connected to the third control node P3. The control electrode of the seventh transistor M7 is connected to the third control node P3, the first electrode of the seventh transistor M7 is connected to the second clock signal terminal CLK2, and the second electrode of the seventh transistor M7 is connected to the output terminal GP. The control electrode of the eighth transistor M8 is connected to the first control node P1, the first electrode of the eighth transistor M8 is connected to the second voltage terminal VGH, and the second electrode of the eighth transistor M8 is connected to the output terminal GP. The first electrode of the first capacitor C1 is connected to the output terminal GP, and the second electrode of the first capacitor C1 is connected to the third control node P3. The first electrode of the second capacitor C2 is connected to the second voltage terminal VGH, and the second electrode of the second capacitor C2 is connected to the first control node P1.

[0068] The following example uses P-type thin-film transistors, from M1 to M8. Figure 3 The operation of the shift register unit shown is illustrated by way of example. The operation of the first-stage shift register unit is used as an example for explanation. Figure 4 for Figure 3 The provided timing diagram for the shift register unit is shown below. Figure 3 and Figure 4 As shown, the shift register unit of this exemplary embodiment may include eight transistor units (M1 to M8), two capacitor units (C1 and C2), three input terminals (INPUT, CLK1, CLK2), one output terminal (GP), and two voltage terminals (VGL, VGH). The first voltage terminal VGL can continuously provide a low-level signal, and the second voltage terminal VGH can continuously provide a high-level signal.

[0069] In input phase S11, the input signal of the first clock signal terminal CLK1 is low, turning on the first transistor M1 and the third transistor M3. With the first transistor M1 on and the input signal of the first voltage terminal VGL low, the potential of the first control node P1 is pulled low. With the third transistor M3 on and the input signal of the signal input terminal INPUT low, the potential of the second control node P2 is pulled low, causing the second transistor M2 to turn on, further ensuring that the potential of the first control node P1 is pulled low. Because the potential of the first control node P1 is pulled low, the fourth transistor M4 and the eighth transistor M8 turn on. With the eighth transistor M8 on and the input signal of the second voltage terminal VGH high, the potential of the output terminal GP is pulled high. With the input signal of the second clock signal terminal CLK2 high, the fifth transistor M5 is turned off. When the input signal of the first voltage terminal VGL is low, the sixth transistor M6 is turned on. The potential of the third control node P3 is pulled low by the potential of the second control node P2, which turns on the seventh transistor M7, further ensuring that the potential of the output terminal GP is pulled high.

[0070] In the output stage S12, the input signal of the first clock signal terminal CLK1 is high, the first transistor M1 and the third transistor M3 are off, the potential of the second control node P2 remains low, the second transistor M2 is on, and the potential of the first control node P1 remains high. Furthermore, the second capacitor C2 further ensures that the first control node P2 remains high. Since the potential of the first control node P2 remains high, the fourth transistor M4 and the eighth transistor M8 are off. The input signal of the second clock signal terminal CLK2 is low, and the fifth transistor M5 is on. The input signal of the first voltage terminal VGL is low, the sixth transistor M6 is on, and the potential of the third control node P3 is further pulled low by the second control node P2, causing the seventh transistor M7 to turn on. The potential of the output terminal GP is pulled low by the input signal of the second clock signal terminal CLK2.

[0071] During the reset phase S13, the input signal of the first clock signal terminal CLK1 is low, the first transistor M1 and the third transistor M3 are turned on, and the potential of the first control node P1 is pulled low by the input signal of the first voltage terminal VGL; the input signal of the signal input terminal INPUT is high, the potential of the second control node P2 is pulled high, causing the second transistor M2 to turn off. Since the potential of the first control node P1 is pulled low, the fourth transistor M4 and the eighth transistor M8 are turned on. With the eighth transistor M8 turned on and the input signal of the second voltage terminal VGH high, the potential of the output terminal GP can remain high. The input signal of the second clock signal terminal CLK2 is high, and the fifth transistor M5 is turned off. The input signal of the first voltage terminal VGL is low, the sixth transistor M6 is turned on, and the potential of the third control node P3 is pulled high by the second control node P2, causing the seventh transistor M7 to turn off.

[0072] During the first hold phase S14, the input signal of the first clock signal terminal CLK1 is high, the first switching transistor M4 and the third switching transistor M3 are off, the input signal of the signal input terminal INPUT is high, the potential of the second control node P2 remains high, the second transistor M2 is off, and the potential of the first control node P1 remains low. Because the potential of the first control node P1 remains low, the fourth transistor M4 and the eighth transistor M8 are turned on, and the potential of the output terminal GP remains high. The input signal of the second clock signal terminal CLK2 is low, and the fifth transistor M5 is turned on. The potential of the first voltage terminal VGL is low, the sixth transistor M6 is turned on, the potential of the third control node P3 remains high, and the seventh transistor M7 is off.

[0073] During the second hold phase S15, the input signal of the first clock signal terminal CLK1 is low, the first transistor M1 and the third transistor M3 are turned on, the input signal of the signal input terminal INPUT is high, the potential of the second control node P2 remains high, the second transistor M2 is turned off, and the potential of the first control node P1 remains low. Since the potential of the first control node P1 remains low, the fourth transistor M4 and the eighth transistor M7 are turned on, and the potential of the output terminal GP remains high. The input signal of the second clock signal terminal CLK2 is high, and the fifth transistor M5 is turned off. The potential of the first voltage terminal VGL is low, the sixth transistor M6 is turned on, the potential of the third control node P3 remains high, and the seventh transistor M7 is turned off.

[0074] After the second hold phase, the first and second hold phases can be repeated until the input signal at the signal input terminal INPUT is low, and then the input phase can be restarted.

[0075] In this exemplary embodiment, at least one sub-pixel may include a light-emitting element and a driving circuit for driving the light-emitting element to emit light. The driving circuit may include multiple transistors and a storage capacitor. In this example, the driving circuit of the sub-pixel may be a 7T1C structure (i.e., including seven transistors and one capacitor). However, this embodiment is not limited to this. In some examples, the driving circuit of the sub-pixel may be a 2T1C or 3T1C structure, etc.

[0076] Figure 5 This is an equivalent circuit diagram of a driving circuit according to at least one embodiment of the present disclosure. Figure 5 As shown, the driving circuit of this exemplary embodiment may include: a first switching transistor T1 to a sixth switching transistor T6, a driving transistor DTFT, and a storage capacitor Cst.

[0077] In this exemplary embodiment, the control electrode of the driving transistor DTFT is connected to the first node N1, the first electrode of the driving transistor T3 is connected to the second node N2, and the second electrode of the driving transistor T3 is connected to the third node N3. The control electrode of the first switching transistor T1 is connected to the scan line G, the first electrode of the first switching transistor T1 is connected to the data line D, and the second electrode of the first switching transistor T1 is connected to the second node N2. The control electrode of the second switching transistor T2 is connected to the scan line G, the first electrode of the second switching transistor T2 is connected to the first node N1, and the second electrode of the second switching transistor T2 is connected to the third node N3. The control electrode of the third switching transistor T3 is connected to the light emission control line EM, the first electrode of the third switching transistor T3 is connected to the first power supply line VDD, and the second electrode of the third switching transistor T3 is connected to the second node N2. The control electrode of the fourth switching transistor T4 is connected to the light emission control line EM, the first electrode of the fourth switching transistor T4 is connected to the third node N3, and the second electrode of the fourth switching transistor T4 is connected to the anode of the light-emitting element EL. The control electrode of the fifth switching transistor T5 is connected to the reset signal line RST, the first electrode of the fifth switching transistor T5 is connected to the initial signal line Vint, and the second electrode of the fifth switching transistor T5 is connected to the first node N1. The control electrode of the sixth switching transistor T6 is connected to the reset signal line RST, the first electrode of the sixth switching transistor T6 is connected to the initial signal line Vint, and the second electrode of the sixth switching transistor T6 is connected to the anode of the light-emitting element EL. The first electrode of the storage capacitor Cst is connected to the first node N1, and the second electrode of the storage capacitor Cst is connected to the first power supply line VDD. The cathode of the light-emitting element EL is connected to the second power supply line VSS.

[0078] The following example uses P-type thin-film transistors as an example, where the first switching transistor T1 to the sixth switching transistor T6 and the driving transistor DTFT are all P-type thin-film transistors. Figure 5 The operation of the provided drive circuit is illustrated by example. Figure 6 for Figure 5 The provided timing diagram for the driver circuit is shown below. Figure 5 As shown, the driving circuit involved in this exemplary embodiment may include: six switching transistors (T1 to T6), one driving transistor (DTFT), one capacitor cell (Cst), five signal input terminals (D, G, EM, RST, and Vint), and two power supply terminals (VDD and VSS). Exemplarily, the first power supply line VDD can continuously provide a high-level signal, and the second power supply line VSS can continuously provide a low-level signal.

[0079] During the reset phase S21, a high-level signal is input to the scan line G, turning off the first switching transistor T1 and the second switching transistor T2. A high-level signal is input to the light emission control line EM, turning off the third switching transistor T3 and the fourth switching transistor T4. A low-level signal is input to the reset signal line RST, turning on the fifth switching transistor T5 and the sixth switching transistor T6, providing the signal input to the initial signal line Vint to the first node N1 and the fourth node N4 to reset the first node N1 and the fourth node N4, thereby eliminating the influence of the previous frame signal.

[0080] During the writing phase S22, the reset signal line RST receives a high-level signal, and the fifth switching transistor T5 and the sixth switching transistor T6 are turned off. The light emission control line EM receives a high-level signal, and the third switching transistor T3 and the fourth switching transistor T4 are turned off. The scan line G receives a low-level signal, and the first switching transistor T1 and the second switching transistor T2 are turned on. The first switching transistor M1 is turned on, providing the data signal input to the data line DATA to the second node N2. At this time, the potential Vn2 of the second node N2 is equal to Vdata, where Vdata is the voltage value of the data signal. The second switching transistor M2 is turned on, connecting the first node N1 and the third node N3, that is, connecting the control electrode of the driving transistor DTFT to the second electrode, so as to write the data signal transmitted to the second node N2 and the threshold voltage Vth (i.e., the compensation signal) of the driving transistor DTFT (i.e., the data signal) to the first node N1, and simultaneously charging the storage capacitor Cst. At this time, the potential Vn1 of the first node N1 is equal to Vdata - Vth. The data signal can be written to the control electrode of the driving transistor DTFT and the threshold voltage of the driving transistor DTFT can be compensated through the writing stage S21, so as to eliminate the influence of the threshold voltage of the driving transistor DTFT on the driving current during the light emission stage.

[0081] During the light-emitting stage S23, the reset signal line RST receives a high-level signal, and the fifth switching transistor T5 and the sixth switching transistor T6 are turned off. The scan line G receives a high-level signal, and the first switching transistor T1 and the second switching transistor T2 are turned off. The light-emitting control line EM receives a low-level signal, and the third switching transistor T3 and the fourth switching transistor T4 are turned on. The third switching transistor T3 is turned on, providing the signal input from the first power line VDD to the second node N2. At this time, Vn2 = Vvdd. The driving transistor DTFT is turned on under the action of the signal (i.e., the data signal and the compensation signal) from the first node N1, and outputs a driving current under the action of the signal provided by the first power line VDD to drive the light-emitting element EL to emit light. The potential of the first node N1 is kept constant at Vdata-Vth under the action of the storage capacitor Cst. Therefore, the source-gate voltage of the driving transistor DTFT can be:

[0082] Vsg=Vn2-Vn1=Vvdd-Vdata+Vth.

[0083] Based on the following transistor IV curve equation:

[0084] I = K(Vsg - Vth) 2 =K(Vvdd-Vdata) 2 ;

[0085] Wherein, K is a fixed constant related to the process parameters and geometry of the driving transistor DTFT.

[0086] Therefore, the driving current is independent of the threshold voltage of the driving transistor DTFT, eliminating the influence of the threshold voltage on the light-emitting element EL, thereby improving display uniformity and luminous efficiency.

[0087] Figure 7 This is a top view of a sub-pixel of a display substrate according to at least one embodiment of the present disclosure. Figure 8 for Figure 7 A cross-sectional view along the QQ direction. (See diagram below.) Figure 7 and Figure 8As shown, the display area of ​​the display substrate provided in this exemplary embodiment may include: a substrate 30, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate 30. The first insulating layer 32 may be disposed between the semiconductor layer and the first conductive layer; the second insulating layer 34 may be disposed between the first and second conductive layers; the third insulating layer 36 may be disposed between the second and third conductive layers; the fourth insulating layer 38 may be disposed between the third and fourth conductive layers; and the fifth insulating layer 40 may be disposed between the fourth and fifth conductive layers. The fifth conductive layer may include an anode 41 of a light-emitting element, and an organic light-emitting layer 43 and a cathode 44 of the light-emitting element are also disposed on the fifth conductive layer.

[0088] Figure 9 This is a top view of a display substrate after the semiconductor layer has been formed, according to at least one embodiment of this disclosure. Figures 7 to 9 As shown, the fifth switching transistor T5, the second switching transistor T2, the first switching transistor T1, the driving transistor DTFT, the third switching transistor T3, the fourth switching transistor T4, and the sixth switching transistor T6 can move along the path shown in the figure. Figure 9 The semiconductor layer shown is formed. Figure 9 As shown, the semiconductor layer can have a bent or folded shape. The semiconductor layer may include: an active layer 210 of a first switching transistor T1, an active layer 220 of a second switching transistor T2, an active layer 230 of a third switching transistor T3, an active layer 240 of a fourth switching transistor T4, an active layer 250 of a fifth switching transistor T5, an active layer 260 of a sixth switching transistor T6, and an active layer 270 of a driving transistor DTFT.

[0089] In this exemplary embodiment, the active layer material may include, for example, polysilicon or a metal oxide. In some examples, the active layer may include a channel region, a first doped region, and a second doped region. The channel region may be undoped and have semiconductor properties. The first and second doped regions may be located on opposite sides of the channel region and are doped with impurities, thus becoming conductive. The impurities may vary depending on the type of transistor.

[0090] In this exemplary embodiment, the first or second doped region of the active layer can be interpreted as the source or drain electrode of a transistor. For example, the source electrode of a driving transistor may correspond to the first doped region, which is doped with impurities, surrounding the channel region of the active layer; the drain electrode of a driving transistor may correspond to the second doped region, which is doped with impurities, surrounding the channel region of the active layer. Additionally, portions of the active layer between transistors can be interpreted as doped wiring, which can be used to electrically connect transistors.

[0091] Figure 10This is a top view of a display substrate after the first conductive layer has been formed, according to at least one embodiment of this disclosure. Figures 7 to 10 As shown, the first conductive layer may include: a light-emitting control line EM, a control electrode 211 of a first switching transistor T1, control electrodes 221a and 221b of a second switching transistor T2, a control electrode 231 of a third switching transistor T3, a control electrode 241 of a fourth switching transistor T4, control electrodes 251a and 251b of a fifth switching transistor T5, a control electrode 261 of a sixth switching transistor T6, a control electrode 271 of a driving transistor DTFT, and a first electrode 281 of a storage capacitor Cst.

[0092] In this exemplary embodiment, the control electrode 271 of the driving transistor DTFT and the first electrode 281 of the storage capacitor Cst can be an integral structure. The light-emitting control line EM, the control electrode 231 of the third switching transistor T3, and the control electrode 241 of the fourth switching transistor T4 can be an integral structure. The control electrodes 221a and 221b of the second switching transistor T2 can be an integral structure. The control electrodes 251a and 251b of the fifth switching transistor T5 can be an integral structure.

[0093] Figure 11 This is a top view of a display substrate after the second conductive layer has been formed in at least one embodiment of this disclosure. Figures 7 to 11 As shown, the second conductive layer may include a second electrode 282 of the storage capacitor Cst. In this exemplary embodiment, the second electrode 282 of the storage capacitor Cst may have a hollow region H. The orthographic projection of the control electrode 271 of the driving transistor DTFT onto the substrate 30 may cover the orthographic projection of the hollow region H onto the substrate 30. In some examples, the orthographic projection of the hollow region H onto the substrate 30 may be circular or polygonal. However, this embodiment is not limited to this.

[0094] Figure 12 This is a top view of a display substrate after the formation of the third conductive layer in at least one embodiment of this disclosure. Figures 7 to 12 As shown, the third conductive layer may include: scan line G, reset signal lines RSTa and RSTb, first electrode 212 of first switching transistor T1, first electrode 222 of second switching transistor T2, first electrode 232 of third switching transistor T3, second electrode 243 of fourth switching transistor T4, first electrode 252 of fifth switching transistor T5, and first electrode 262 of sixth switching transistor T6.

[0095] In this exemplary embodiment, the scan line G may be parallel to the reset signal lines RSTa and RSTb, and the distance between the scan line G and the reset signal line RSTa may be less than the distance between the scan line G and the reset signal line RSTb.

[0096] In this exemplary embodiment, the scan line G can be connected to the control electrode 211 of the first switching transistor T1 through the first via K2 in the third insulating layer 36 and the second insulating layer 34. The scan line G can be connected to the control electrodes 221a and 221b of the second switching transistor T1 through the first via K3 in the third insulating layer 36 and the second insulating layer 34. The reset signal line RSTa can be connected to the control electrodes 251a and 251b of the fifth switching transistor T5 through the first via K10 in the third insulating layer 36 and the second insulating layer 34. The reset signal line RSTb can be connected to the control electrode 261 of the sixth switching transistor T6 through the first via K11 in the third insulating layer 36 and the second insulating layer 34.

[0097] In this exemplary embodiment, the orthogonal projection of the scan line G onto the substrate 30 can cover the orthogonal projection of the control electrode 211 of the first switching transistor T1 onto the substrate 30, and can partially overlap with the orthogonal projections of the control electrodes 221a and 221b of the second switching transistor T2 onto the substrate 30. The orthogonal projection of the reset signal line RSTa onto the substrate 30 can partially overlap with the orthogonal projections of the control electrodes 251a and 251b of the fifth switching transistor T5 onto the substrate 30. The orthogonal projection of the reset signal line RSTb onto the substrate 30 can cover the orthogonal projection of the control electrode 261 of the sixth switching transistor T6 onto the substrate 30.

[0098] In this exemplary embodiment, the orthogonal projection of scan line G on substrate 30 can cover the orthogonal projections of first vias K2 and K3 on substrate 30. The orthogonal projection of reset signal line RSTa on substrate 30 can cover the orthogonal projection of first via K10 on substrate 30. The orthogonal projection of reset signal line RSTb on substrate 30 can cover the orthogonal projection of first via K11 on substrate 30.

[0099] In this exemplary embodiment, the first electrode 212 of the first switching transistor T1 can be connected to the first doped region 210b of the active layer 210 of the first switching transistor T1 through a third via K1 in the third insulating layer 36, the second insulating layer 34, and the first insulating layer 32. The first electrode 222 of the second switching transistor T2 can be connected to the first doped region 220b of the active layer 220 of the second switching transistor T2 through a third via K4 in the third insulating layer 36, the second insulating layer 34, and the first insulating layer 32, and can also be connected to the control electrode 271 of the driving transistor DTFT through a first via K5 in the third insulating layer 36 and the second insulating layer 34. The first electrode 232 of the third switching transistor T3 can be connected to the first doped region 230b of the active layer 230 of the third switching transistor T3 through a third via K7 in the third insulating layer 36, the second insulating layer 34, and the first insulating layer 32, and can also be connected to the second electrode 282 of the storage capacitor Cst through a fourth via K6 in the third insulating layer 36. The second terminal 243 of the fourth switching transistor T4 can be connected to the second doped region 240c of the active layer 240 of the fourth switching transistor T4 through the third via K8 in the third insulating layer 36, the second insulating layer 34, and the first insulating layer 32. The first terminal 252 of the fifth switching transistor T5 can be connected to the first doped region 250b of the active layer 250 of the fifth switching transistor T5 through the third via K9 in the third insulating layer 36, the second insulating layer 34, and the first insulating layer 32. The first terminal 262 of the sixth switching transistor T6 can be connected to the first doped region 260b of the active layer 260 of the sixth switching transistor T6 through the third via K12 in the third insulating layer 36, the second insulating layer 34, and the first insulating layer 32.

[0100] Figure 13 This is a top view of at least one embodiment of the present disclosure in which a fourth conductive layer is formed. Figures 7 to 13 As shown, the fourth conductive layer may include: a connecting electrode 291, a data line D, a first power line VDD, and an initial signal line Vint. The data line D, the first power line VDD, and the initial signal line Vint extend in parallel directions, all parallel to the second direction. The width of the first power line VDD along the first direction may be greater than the width of the initial signal line Vint along the first direction, and the width of the initial signal line Vint along the first direction may be greater than the width of the first power line VDD along the first direction.

[0101] In this exemplary embodiment, the data line D can be connected to the first terminal 212 of the first switching transistor T1 through the second via K14 in the fourth insulating layer 38. The first power line VDD can be connected to the first terminal 232 of the third switching transistor T3 through the second vias K17, K18, and K19 in the fourth insulating layer 38. In this exemplary embodiment, by providing multiple second vias in the fourth insulating layer 38 to connect the first terminal 232 of the third switching transistor T3 and the first power line VDD, a stable power signal can be ensured. The initial signal line Vint can be connected to the first terminal 252 of the fifth switching transistor T5 through the second via K15 in the fourth insulating layer 38, and to the first terminal 262 of the sixth switching transistor T6 through the second via K16 in the fourth insulating layer 38.

[0102] In this exemplary embodiment, the connection electrode 291 can be connected to the second electrode 243 of the fourth switching transistor T4 through the second via K20 in the fourth insulating layer 38. The connection electrode 291 can also be connected to the anode 41 of the light-emitting element through the fifth via K21 in the fifth insulating layer 40.

[0103] In this exemplary embodiment, the storage capacitor Cst may include a first electrode 281 and a second electrode 282, with a second insulating layer 34 between them. The first electrode 281 of the storage capacitor Cst may also serve as the control electrode of the driving transistor DTFT. In this example, the control electrode 271 of the driving transistor DTFT and the first electrode 281 of the storage capacitor Cst may be an integral structure.

[0104] In this exemplary embodiment, the driving transistor DTFT may include an active layer 270 and a control electrode 271. The active layer 270 of the driving transistor DTFT may include a first doped region 270b, a second doped region 270c, and a channel region 270a connecting the first doped region 270b and the second doped region 270c. The control electrode 271 may also serve as the first electrode 281 of the storage capacitor Cst. The orthographic projection of the channel region 270a of the active layer 270 of the driving transistor DTFT onto the substrate 30 may overlap with the orthographic projection of the control electrode 271 onto the substrate 30. The first doped region 270b and the second doped region 270c extend in two directions relative to the channel region 270a. The first doped region 270b of the driving transistor DTFT is connected to the second doped region 210c of the active layer 210 of the first switching transistor T1. The second doped region 270c of the driving transistor DTFT is connected to the second doped region 220c of the active layer 220 of the second switching transistor T2 and the first doped region 240b of the active layer 240 of the fourth switching transistor T4.

[0105] In this exemplary embodiment, the first switching transistor T1 may include an active layer 210, a control electrode 211, and a first electrode 212. The active layer 210 of the first switching transistor T1 may include a first doped region 210b, a second doped region 210c, and a channel region 210a connecting the first doped region 210b and the second doped region 210c. The second doped region 210c of the first switching transistor T1 may be connected to the first doped region 270b of the active layer 270 of the driving transistor DTFT. The first doped region 210b of the first switching transistor T1 may be connected to the first electrode 212 of the first switching transistor T1 through a third via K1 in the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. The first electrode 212 of the first switching transistor T1 may be connected to the data line D through a second via K14 in the fourth insulating layer 38. The control electrode 211 of the first switching transistor T1 may be connected to the scan line G through a first via K2 in the second insulating layer 34 and the third insulating layer 36.

[0106] In this exemplary embodiment, the second switching transistor T2 may include an active layer 220, control electrodes 221a and 221b, and a first electrode 222. The active layer 220 may include channel regions 220a1, 220a2, and 220a3, a first doped region 220b, and a second doped region 220c. Channel region 220a1 corresponds to control electrode 221a, channel region 220a3 corresponds to control electrode 221b, and channel region 220a2 is located between 220a1 and 220a3. The first doped region 220b of the second switching transistor T2 may be connected to the second doped region 250c of the fifth switching transistor T5. The first doped region 220b may be connected to the first electrode 222 of the second switching transistor T2 through a third via K4 in the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. The first electrode 222 of the second switching transistor T2 can be connected to the control electrode 271 of the driving transistor DTFT through the first via K5 in the third insulating layer 36 and the second insulating layer 34. The control electrodes 221a and 221b of the second switching transistor T2 can be connected to the scan line G through the first via K3 in the second insulating layer 34 and the third insulating layer 36. In this example, the second switching transistor T2, by providing dual control electrodes, can be used to prevent and reduce leakage current.

[0107] In this exemplary embodiment, the third switching transistor T3 may include an active layer 230, a control electrode 231, and a first electrode 232. The active layer 230 may include a channel region 230a, a first doped region 230b, and a second doped region 230c. The first doped region 230b of the third switching transistor T3 can be connected to the first electrode 232 through a third via K7 in the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. The first electrode 232 of the third switching transistor T3 can be connected to the first power line VDD through second vias K17, K18, and K19 in the fourth insulating layer 38. The first electrode 232 of the third switching transistor T3 can also be connected to the second electrode 282 of the storage capacitor Cst through a fourth via K6 in the third insulating layer 36. The control electrode 231 of the third switching transistor T3 and the light-emitting control line EM can be an integral structure.

[0108] In this exemplary embodiment, the fourth switching transistor T4 may include an active layer 240, a control electrode 241, and a second electrode 243. The active layer 240 of the fourth switching transistor T4 may include a channel region 240a, a first doped region 240b, and a second doped region 240c. The first doped region 240b of the fourth switching transistor T4 may be connected to the second doped region 270c of the driving transistor DTFT and the second doped region 220c of the second switching transistor T2, respectively. The second doped region 240c of the fourth switching transistor T4 may be connected to the second electrode 243 of the fourth switching transistor T4 through a third via K8 in the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. The second electrode 243 of the fourth switching transistor T4 may be connected to the connection electrode 291 through a second via K20 in the fourth insulating layer 38. The connection electrode 291 may be connected to the anode 41 of the light-emitting element through a fifth via K21 in the fifth insulating layer 40.

[0109] In this exemplary embodiment, the fifth switching transistor T5 may include an active layer 250, control electrodes 251a and 251b, and a first electrode 252. The active layer 250 may include channel regions 250a1, 250a2, and 220a3, a first doped region 250b, and a second doped region 250c. Channel region 250a1 corresponds to control electrode 251a, channel region 250a3 corresponds to control electrode 251b, and channel region 250a2 is located between 250a1 and 250a3. The first doped region 250b may be connected to the first doped region 220b of the second switching transistor T2. The first doped region 250b of the fifth switching transistor T5 may be connected to the second electrode 252 through a third via K9 in the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. The control electrodes 251a and 251b of the fifth switching transistor T5 can be connected to the reset signal line RSTa through the first via K10 in the second insulating layer 34 and the third insulating layer 36. In this example, the fifth switching transistor T5, by providing dual control electrodes, can be used to prevent and reduce leakage current.

[0110] In this exemplary embodiment, the sixth switching transistor T6 may include an active layer 260, a control electrode 261, and a first electrode 262. The active layer 260 may include a channel region 260a, a first doped region 260b, and a second doped region 260c. The first doped region 260b of the sixth switching transistor T6 can be connected to the first electrode 262 via a third via K12 in the first insulating layer 32, the second insulating layer 34, and the third insulating layer 36. The first electrode 262 of the sixth switching transistor T6 can be connected to the initial signal line Vint via a second via K16 in the fourth insulating layer 38. The second doped region 260c of the sixth switching transistor T6 can be connected to the second doped region 240c of the fourth switching transistor T4. The control electrode 261 of the sixth switching transistor T6 can be connected to the reset signal line RSTb via a first via K11 in the second insulating layer 34 and the third insulating layer 36.

[0111] Figure 14 This is a top view of a plurality of sub-pixels in a display substrate according to at least one embodiment of the present disclosure. Figure 14 As shown, a row of sub-pixels can be connected to the reset signal lines RSTa and RSTb of the same row, as well as the scan line G of the same row. A column of sub-pixels can be connected to the data line D of the same column, as well as the first wire VDD of the same column. The first electrode 252 of the fifth switching transistor T5 of multiple sub-pixels can be a single integrated structure, connected to the initial signal line Vint through the second via K15. The first electrode 262 of the sixth switching transistor T6 of multiple sub-pixels can be a single integrated structure, connected to the initial signal line Vint through the second via K16. In this example, each row of sub-pixels can share one initial signal line Vint. However, this embodiment is not limited to this.

[0112] In this exemplary embodiment, the second electrodes 282 of the storage capacitors Cst of the multiple sub-pixels can be an integral structure. However, this embodiment is not limited to this. In some examples, the second electrodes of the storage capacitors Cst of the multiple sub-pixels can be independent structures in direct contact. By setting the second electrodes of the storage capacitors of the multiple sub-pixels in direct contact, a stable power signal can be transmitted between the multiple sub-pixels.

[0113] The following reference Figures 7 to 14 The fabrication process of the display substrate in this exemplary embodiment is illustrated by example. The "patterning process" mentioned in this embodiment includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are known and mature fabrication processes. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without limitation. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using deposition or other processes.

[0114] The fabrication process of the display substrate in this exemplary embodiment may include the following steps.

[0115] Step 100: Provide a substrate, deposit a semiconductor thin film on the substrate, and process the semiconductor thin film using a patterning process to form a semiconductor layer, such as... Figure 9 As shown.

[0116] In this exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. A rigid substrate may include one or more of glass and metal foil. A flexible substrate may include one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0117] In this exemplary embodiment, the semiconductor layer may be made of polycrystalline silicon or metal oxide, and the present disclosure does not limit this to any particular material.

[0118] Step 200: Deposit a first insulating thin film on the semiconductor layer, process the first insulating thin film using a patterning process to form a first insulating layer, deposit a first conductive thin film on the first insulating layer, and process the first conductive thin film using a patterning process to form a first conductive layer, such as... Figure 10 As shown.

[0119] In this exemplary embodiment, the first conductive layer may include: a light-emitting control line EM, a control electrode 211 of a first switching transistor T1, control electrodes 221a and 221b of a second switching transistor T2, a control electrode 231 of a third switching transistor T3, a control electrode 241 of a fourth switching transistor T4, control electrodes 251a and 251b of a fifth switching transistor T5, a control electrode 261 of a sixth switching transistor T6, a control electrode 271 of a driving transistor DTFT, and a first electrode 281 of a storage capacitor Cst.

[0120] In this exemplary embodiment, the first conductive film can be a metallic material, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), or an alloy of the above metals, such as aluminum-niobium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a multilayer stacked structure, such as Mo / Cu / Mo or Mo / Al / Mo, or a stacked structure formed of metal and transparent conductive material, such as ITO / Ag / ITO. The first insulating film can be a silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a high dielectric constant (High k) material, such as aluminum oxide (AlOx), hafnium oxide (HfOx), or tantalum oxide (TaOx). It can be a single layer, multiple layers, or a composite layer. Typically, the first insulating layer 32 can be referred to as a gate insulating (GI) layer.

[0121] Step 300: Deposit a second insulating film on the first conductive layer, process the second insulating film using a patterning process to form a second insulating layer, deposit a second conductive film on the second insulating layer, and process the second conductive film using a patterning process to form a second conductive layer, such as... Figure 11 As shown.

[0122] In this exemplary embodiment, the second conductive layer may include a second electrode 282 of the storage capacitor Cst.

[0123] In this exemplary embodiment, the second conductive film can be a metallic material, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), or an alloy of the above metals, such as aluminum-niobium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a multilayer stacked structure, such as Mo / Cu / Mo or Mo / Al / Mo, or a stacked structure formed of metal and transparent conductive material, such as ITO / Ag / ITO. The second insulating film can be a silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a high dielectric constant (High k) material, such as aluminum oxide (AlOx), hafnium oxide (HfOx), or tantalum oxide (TaOx). It can be a single layer, multiple layers, or a composite layer. Typically, the second insulating layer 34 can be referred to as a gate insulating (GI) layer.

[0124] Step 400: Deposit a third insulating film on the second conductive layer, process the third insulating film using a patterning process to form a third insulating layer, deposit a third conductive film on the third insulating layer, and process the third conductive film using a patterning process to form a third conductive layer, such as... Figure 12 As shown.

[0125] In this exemplary embodiment, the third conductive layer may include: a scan line G, reset signal lines RSTa and RSTb, a first electrode 212 of a first switching transistor T1, a first electrode 222 of a second switching transistor T2, a first electrode 232 of a third switching transistor T3, a second electrode 243 of a fourth switching transistor T4, a first electrode 252 of a fifth switching transistor T5, and a first electrode 262 of a sixth switching transistor T6.

[0126] In this exemplary embodiment, the third conductive film can be a metallic material, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or an alloy of the above metals, such as aluminum-niobium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a multilayer stacked structure, such as Ti / Al / Ti, or a stacked structure formed by metals and transparent conductive materials, such as ITO / Ag / ITO. The third insulating film can be a silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a high dielectric constant (High k) material, such as aluminum oxide (AlOx), hafnium oxide (HfOx), or tantalum oxide (TaOx). It can be a single layer, multiple layers, or a composite layer. Typically, the third insulating layer 36 can be referred to as an interlayer insulating layer.

[0127] Step 500: A fourth insulating film is deposited on the third conductive layer. A patterning process is used to process the fourth insulating film to form a fourth insulating layer. A fourth conductive film is deposited on the fourth insulating layer. A patterning process is used to process the fourth conductive film to form a fourth conductive layer. Figure 13 As shown.

[0128] In this exemplary embodiment, the fourth conductive layer may include: a connection electrode 291, a data line D, a first power line VDD, and an initial signal line Vint.

[0129] In this exemplary embodiment, the fourth conductive film can be a metallic material, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), or an alloy of the above metals, such as aluminum-niobium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a multilayer stacked structure, such as Mo / Cu / Mo or Mo / Al / Mo, or a stacked structure formed of metal and transparent conductive material, such as ITO / Ag / ITO. The fourth insulating film can be a silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or a high dielectric constant (High k) material, such as aluminum oxide (AlOx), hafnium oxide (HfOx), or tantalum oxide (TaOx). It can be a single layer, multiple layers, or a composite layer.

[0130] Step 600: A fifth insulating layer is formed on the fourth conductive layer. A fifth conductive thin film is deposited on the fifth insulating layer. The fifth conductive thin film is processed using a patterning process to form the fifth conductive layer. A pixel definition film is coated on the fifth conductive layer. A pixel definition layer 42 pattern is formed by mask exposure and development, defining the opening region of the anode 41 of the light-emitting element. An organic light-emitting layer 43 is formed in the opening region. A sixth conductive thin film is deposited on the organic light-emitting layer. The sixth conductive thin film is processed using a patterning process to form the cathode 44 of the light-emitting element, as shown below. Figure 8 As shown.

[0131] In this exemplary embodiment, the fifth insulating layer may include an inorganic insulating layer and an organic insulating layer stacked together. The material of the inorganic insulating layer may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc.; the material of the organic insulating layer may include polyimide, acrylic, or polyethylene terephthalate, etc.

[0132] In this exemplary embodiment, the pixel definition film may be made of materials such as polyimide, acrylic, or polyethylene terephthalate.

[0133] In this exemplary embodiment, the organic light-emitting layer 43 may primarily include an emitting material layer (EML). In some examples, the organic light-emitting layer may include a hole injection layer, a hole transport layer, an emitting material layer, an electron transport layer, and an electron injection layer arranged sequentially to improve the efficiency of electron and hole injection into the emitting layer.

[0134] In some examples, the anode 41 of the light-emitting element may be made of at least one transparent conductive material selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). The cathode 44 of the light-emitting element may be made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. However, this embodiment is not limited in this respect.

[0135] In the display substrate provided in this exemplary embodiment, a scan line G (for providing scan signals to sub-pixels) and a reset signal line (for providing reset signals to sub-pixels), which are connected to the scan driving circuit and extend along a first direction, are disposed in a third conductive layer. The signals transmitted by the scan line and reset signal line are transmitted back to the first conductive layer via a perforation method, thereby achieving connection with the control electrode of the transistor disposed in the first conductive layer. By disposing the scan line and reset signal line in the same layer as the first and second electrodes of the transistor, this exemplary embodiment reduces the impedance of the scan line and reset signal line extending along the first direction, thereby reducing the gate drive delay time, increasing the charging rate of the display substrate, and consequently improving the resolution and refresh rate of the display substrate. Furthermore, by disposing the first power line VDD, data line D, and initial signal line Vint extending along a second direction in a fourth conductive layer, direct intersection with the scan line and reset signal line can be avoided.

[0136] Figure 15 This is a simulation schematic diagram of the gate driving of a display substrate according to at least one embodiment of the present disclosure. Figure 15 As shown, the first signal line within the display area of ​​the display substrate used to transmit signals provided by the scan driving circuit to the sub-pixels can be represented by a simulation circuit including resistors and capacitors. In this example, a circuit including four resistors R and three capacitors C can be used to simulate the first signal line transmitting signals within the display area. The four resistors are connected in series from the output terminal GP of the shift register unit, and one end of a capacitor C is connected between two adjacent resistors, with the other end of the capacitor C grounded. However, this embodiment is not limited to this. In some examples, the simulation circuit for the first signal line within the display area may include five resistors R and four capacitors C.

[0137] In one example, when the first signal line in the display area is disposed in the same layer as the control electrode of the transistor, and the material of the control electrode layer can be, for example, Mo / Al / Mo, the simulated total resistance of the first signal line in the display area is 54.32 kΩ and the total capacitance is 175.95 pF. When the first signal line in the display area is disposed in the same layer as the first and second electrodes of the transistor, and the material of this layer can be, for example, Ti / Al / Ti, the simulated total resistance of the first signal line in the display area is 4.12 kΩ and the total capacitance is 161.49 pF. Therefore, this exemplary embodiment, by disposing the first signal line in the same layer as the first and second electrodes of the transistor, can significantly reduce the resistance on the first signal line and significantly reduce the impedance of the gate electrode layer.

[0138] Figure 16 include Figure 16 (a) and Figure 16 (b) shows a schematic diagram of the gate drive delay. Figure 16 (a) shows a schematic diagram of the gate drive delay when the first signal line and the control electrode of the transistor are set on the same layer. Figure 16 (b) shows a schematic diagram of the gate drive delay when the first signal line is set on the same layer as the first and second poles of the transistor. Figure 16 (a) and Figure 16 (b) for in Figure 15 The diagram shows simulated gate drive delays under the conditions of a first power supply terminal VGH = 7V and a second power supply terminal VGL = -7V for the shift register unit shown. Figure 16 As shown in (a), when the first signal line is disposed on the same layer as the control electrode of the transistor, the falling edge duration Tr1 = 2.3 microseconds (μs), the rising edge duration Tf1 = 2.38 μs, and the signal delay duration is 4.68 μs. Figure 16As shown in (b), when the first signal line is disposed on the same layer as the first and second electrodes of the transistor, the falling edge duration of the signal transmitted by the first signal line is Tr2 = 0.27 μs, the rising edge duration is Tf2 = 0.26 μs, and the signal delay duration is 0.53 μs. For a display substrate with a resolution of 2560*1920 and a refresh rate of 60Hz, the scanning time of one frame is 1 / 60Hz = 16.67ms, and the scanning time of one line is 16.67ms / 1920 = 8.6µs. The effective charging time of the sub-pixel in the display substrate where the first signal line is disposed on the same layer as the control electrode of the transistor is 8.6 - 4.68 = 3.92μs, while the effective charging time of the sub-pixel in the display substrate where the first signal line is disposed on the same layer as the first and second electrodes of the transistor can be 8.6 - 0.53 = 8.07μs. It can be seen that the display substrate provided in this embodiment can greatly extend the effective charging time by disposing the first signal line on the same layer as the first and second electrodes of the transistor, thereby meeting the high resolution requirements.

[0139] In some examples, the driving circuit of the sub-pixel is simulated under the conditions of VGH = 7V, VGL = -7V, and data voltage Vb = 2.56V. Based on the simulation results of the sub-pixel driving circuit and the formula for calculating the charging rate, the charging ratio of the display substrate in this exemplary embodiment can be obtained. The formula for calculating the charging ratio is:

[0140]

[0141] Among them, VG Light_on VData represents the potential of the first node N1 in the driving circuit when the light-emitting element is lit, i.e., the voltage of the control electrode of the driving transistor DTFT; Vinit represents the voltage value provided by the initial signal line Vint; VData represents the voltage value provided by the initial signal line Vint. Light_on Vth represents the data voltage value provided by the data line D when the light-emitting element is lit, and Vth represents the threshold voltage of the driving transistor DTFT.

[0142] Taking a pixel comprising RGB sub-pixels as an example, when the first signal line of a display substrate with a resolution of 2560*1920 and a refresh rate of 60Hz is arranged on the same layer as the gate electrode, according to simulation results, the charging rates of the R, G, and B sub-pixels are 71.2%, 70.3%, and 68%, respectively. Since the charging rates are all less than 75%, it indicates that the charging rate of the display substrate with the first signal line arranged on the same layer as the gate electrode is insufficient at 60Hz and cannot meet product requirements. According to simulation results, when the first signal line of a display substrate with a resolution of 2560*1920 and a refresh rate of 60Hz is arranged on the same layer as the source and drain electrodes, the charging rates of the R, G, and B sub-pixels are 85%, 85%, and 84%, respectively. The charging rates are all greater than 75%, indicating that the display substrate provided in this exemplary embodiment has a sufficient charging rate at 60Hz. Furthermore, simulations were performed on a display substrate with a resolution of 2560*1920 and a refresh rate of 90Hz. The simulation results show that the charging rates of the R, G, and B sub-pixels of the display substrate provided in this exemplary embodiment are 78.9%, 79.4%, and 78.1%, respectively, all exceeding 75%. This indicates that the display substrate provided in this embodiment has a relatively sufficient charging rate at 90Hz. Therefore, it is evident that the display substrate provided in this embodiment can improve the refresh rate.

[0143] Figure 17 This is a schematic flowchart illustrating a method for fabricating a display substrate according to at least one embodiment of this disclosure. Figure 17 As shown, at least one embodiment of this disclosure provides a method for fabricating a display substrate, used to fabricate the display substrate as described above, comprising the following steps: Step S1, providing a substrate; Step S2, in a display area, sequentially forming a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer on the substrate. The semiconductor layer may include: an active layer of multiple transistors. The first conductive layer may include: control electrodes of multiple transistors and a first electrode of a storage capacitor. The second conductive layer may include: a second electrode of a storage capacitor. The third conductive layer may include: multiple first signal lines and first and second electrodes of multiple transistors. An insulating layer between the third conductive layer and the first conductive layer may be provided with a first via, allowing the first signal lines to contact the control electrodes of the transistors exposed by the first conductive layer through the first via.

[0144] In some exemplary embodiments, the above-described fabrication method further includes forming a fourth conductive layer on the side of the third conductive layer away from the substrate. The fourth conductive layer may include a plurality of second signal lines extending along a second direction perpendicular to the first direction. An insulating layer between the fourth conductive layer and the third conductive layer may have a second via, and the second signal lines may contact a first or second electrode of a transistor exposed by the third conductive layer through the second via.

[0145] In some exemplary embodiments, forming a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially on a substrate may include: forming a semiconductor layer and a first insulating layer sequentially on the substrate; forming a first conductive layer and a second insulating layer sequentially on the first insulating layer; forming a second conductive layer and a third insulating layer sequentially on the second insulating layer; forming a third conductive layer and a fourth insulating layer sequentially on the third insulating layer; and forming a fourth conductive layer on the fourth insulating layer.

[0146] In some exemplary embodiments, after forming the fourth conductive layer, the preparation method of this embodiment may further include: forming a fifth insulating layer on the fourth conductive layer; sequentially forming a fifth conductive layer, an organic light-emitting layer of the light-emitting element, and a second electrode on the fifth insulating layer; the fifth conductive layer includes a first electrode of the light-emitting element.

[0147] The fabrication process of the display substrate provided in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0148] Figure 18 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 18 As shown, at least one embodiment of this disclosure provides a display device 91, including a display substrate 910. The display substrate 910 can be the display substrate provided in the foregoing embodiments, and its implementation principle and effect are similar, so it will not be described again here. In some examples, the display substrate 910 can be an OLED display substrate. In some examples, the display device 91 can be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; this embodiment is not limited to this.

[0149] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized by, The display device comprises: a display region and a peripheral region located at the periphery of the display region, the peripheral region being provided with a scan driving circuit, and the display region being provided with a plurality of sub-pixels and a plurality of first signal lines connected with the scan driving circuit and extending along a first direction; at least one of the plurality of sub-pixels comprises a light-emitting element and a driving circuit for driving the light-emitting element to emit light, and the driving circuit comprises a plurality of transistors and a storage capacitor; the display region comprises a substrate and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer sequentially arranged on the substrate; the semiconductor layer comprises an active layer of a plurality of transistors; the first conductive layer comprises control electrodes of a plurality of transistors, first electrodes of a storage capacitor and a plurality of light-emitting control lines; the second conductive layer comprises second electrodes of the storage capacitor; the third conductive layer comprises a plurality of first signal lines and first electrodes and second electrodes of a plurality of transistors; an insulating layer between the third conductive layer and the first conductive layer is provided with a first via, and the first signal line contacts the control electrode of the transistor exposed by the first via of the first conductive layer; the first signal line comprises a scan line and a reset signal line; the material of the third conductive layer is different from that of the first conductive layer, and the third conductive layer comprises a three-layer stacked structure of titanium, aluminum and titanium; a projection of the first signal line on the substrate at least partially overlaps with a projection of the control electrode of the transistor connected with the first signal line on the substrate.

2. The display substrate of claim 1, wherein, The display region further comprises a fourth conductive layer arranged on a side of the third conductive layer away from the substrate; the fourth conductive layer comprises a plurality of second signal lines extending along a second direction perpendicular to the first direction; an insulating layer between the fourth conductive layer and the third conductive layer is provided with a second via, and the second signal line contacts the first electrode or the second electrode of the transistor exposed by the second via of the third conductive layer. 3.The display substrate of claim 1, wherein, A plurality of first vias are arranged along the extension direction of the first signal line, and a projection of the first signal line on the substrate covers a projection of the first via on the substrate.

4. The display substrate of claim 1, wherein, The scan driving circuit comprises a plurality of cascaded shift register units, and an i-th shift register unit provides a scan signal to sub-pixels in an i-th row through the scan line, where i is an integer greater than 0.

5. The display substrate of claim 4, wherein, The i-th shift register unit provides a reset signal to sub-pixels in an i+1-th row through the reset signal line. 6.The display substrate of claim 4 or 5, wherein, The shift register unit comprises a first transistor to an eighth transistor, a first capacitor and a second capacitor; The control electrode of the first transistor is connected with the first clock signal end, the first electrode of the first transistor is connected with the first voltage end, and the second electrode of the first transistor is connected with the first control node; the control electrode of the second transistor is connected with the second control node, the first electrode of the second transistor is connected with the first clock signal, and the second electrode of the second transistor is connected with the first control node; the control electrode of the third transistor is connected with the first clock signal end, the first electrode of the third transistor is connected with the input signal end, and the second electrode of the third transistor is connected with the second control node; the control electrode of the fourth transistor is connected with the first control node, the first electrode of the fourth transistor is connected with the second voltage end, and the second electrode of the fourth transistor is connected with the first electrode of the fifth transistor; the control electrode of the fifth transistor is connected with the second clock signal end, and the second electrode of the fifth transistor is connected with the second control node; the control electrode of the sixth transistor is connected with the first voltage end, the first electrode of the sixth transistor is connected with the second control node, and the second electrode of the sixth transistor is connected with the third control node; the control electrode of the seventh transistor is connected with the third control node, the first electrode of the seventh transistor is connected with the output end, and the second electrode of the seventh transistor is connected with the second clock signal end; the control electrode of the eighth transistor is connected with the first control node, the first electrode of the eighth transistor is connected with the second voltage end, and the second electrode of the eighth transistor is connected with the output end. The first electrode of the first capacitor is connected with the output end, and the second electrode of the first capacitor is connected with the third control node; the first electrode of the second capacitor is connected with the second voltage end, and the second electrode of the second capacitor is connected with the first control node. 7.The display substrate of claim 4 or 5, wherein, The peripheral region is further provided with a light-emitting driving circuit, and the display region is further provided with a plurality of light-emitting control lines connected with the light-emitting driving circuit and extending along the first direction, and the light-emitting driving circuit provides a light-emitting control signal to the sub-pixels through the light-emitting control lines. The light-emitting control line is integrated with the control electrode of at least one transistor in the driving circuit of a row of sub-pixels. 8.The display substrate of claim 2, wherein, The second signal line includes a data line, a first power line, and an initial signal line. 9.The display substrate of claim 8, wherein, The display region further includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. The first insulating layer is arranged between the semiconductor layer and the first conductive layer, the second insulating layer is arranged between the first conductive layer and the second conductive layer, the third insulating layer is arranged between the second conductive layer and the third conductive layer, and the fourth insulating layer is arranged between the third conductive layer and the fourth conductive layer. 10.The display substrate of claim 8, wherein, For at least one sub-pixel, the plurality of transistors of the driving circuit includes first to sixth switching transistors and a driving transistor. The control electrode of the first switch transistor is connected with a scan line, the first electrode of the first switch transistor is connected with a data line, and the second electrode of the first switch transistor is connected with the first electrode of the drive transistor; the control electrode of the second switch transistor is connected with the scan line, the first electrode of the second switch transistor is connected with the control electrode of the drive transistor, and the second electrode of the second switch transistor is connected with the second electrode of the drive transistor; the control electrode of the third switch transistor is connected with a light-emitting control line, the first electrode of the third switch transistor is connected with a first power supply line, and the second electrode of the third switch transistor is connected with the first electrode of the drive transistor; the control electrode of the fourth switch transistor is connected with the light-emitting control line, the first electrode of the fourth switch transistor is connected with the second electrode of the drive transistor, and the second electrode of the fourth switch transistor is connected with the first electrode of the light-emitting element; the control electrode of the fifth switch transistor is connected with a reset signal line, the first electrode of the fifth switch transistor is connected with an initial signal line, and the second electrode of the fifth switch transistor is connected with the first electrode of the second switch transistor; the control electrode of the sixth switch transistor is connected with the reset signal line, the first electrode of the sixth switch transistor is connected with the initial signal line, and the second electrode of the sixth switch transistor is connected with the first electrode of the light-emitting element. The first electrode of the storage capacitor is connected with the control electrode of the drive transistor, and the second electrode of the storage capacitor is connected with the first power supply line. 11.The display substrate of claim 10, wherein, The reset signal line connected with the control electrode of the fifth switch transistor and the reset signal line connected with the control electrode of the sixth switch transistor are respectively located on both sides of the scan line connected with the control electrodes of the first switch transistor and the second switch transistor. 12.The display substrate of claim 10, wherein, The second electrodes of the storage capacitors in the adjacent sub-pixels in the same row directly contact. 13.The display substrate of claim 10, wherein, The first electrode of the storage capacitor is in an integral structure with the control electrode of the drive transistor. The second electrode of the storage capacitor has a hollow region, the orthographic projection of the control electrode of the drive transistor on the substrate covers the orthographic projection of the hollow region on the substrate, and the first electrode of the second switch transistor is connected with the control electrode of the drive transistor through the hollow region. 14.The display substrate of claim 10, wherein, The display region further comprises a fifth conductive layer, a fifth insulating layer arranged between the fourth conductive layer and the fifth conductive layer, an organic light-emitting layer of the light-emitting element and a second electrode arranged on the side of the fifth conductive layer away from the substrate. The fifth conductive layer comprises the first electrode of the light-emitting element. The second electrode of the light-emitting element is arranged on the side of the organic light-emitting layer away from the substrate.

15. A display device comprising: The display substrate comprises the display substrate according to any one of claims 1 to 14.

16. A method for manufacturing a display substrate, comprising: The display substrate is prepared by the preparation method comprising: providing a substrate; forming, on the substrate, a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer in sequence in a display region; The semiconductor layer includes active layers of a plurality of transistors; the first conductive layer includes control electrodes of the plurality of transistors and first electrodes of storage capacitors; the second conductive layer includes second electrodes of the storage capacitors; the third conductive layer includes a plurality of first signal lines and first electrodes and second electrodes of the plurality of transistors; the insulating layer between the third conductive layer and the first conductive layer is provided with a first via hole, and the first signal lines contact the control electrodes of the transistors exposed by the first conductive layer through the first via hole.

17. The method of claim 16, wherein the method further comprises, The preparation method further includes: forming a fourth conductive layer on the side of the third conductive layer away from the substrate, the fourth conductive layer including a plurality of second signal lines extending along a second direction perpendicular to the first direction, the insulating layer between the fourth conductive layer and the third conductive layer being provided with a second via hole, and the second signal lines contacting the first electrodes or the second electrodes of the transistors exposed by the third conductive layer through the second via hole.

18. The method of claim 17, wherein, The preparation method further includes: forming a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer on the substrate in sequence, including: forming a semiconductor layer and a first insulating layer on the substrate in sequence; forming a first conductive layer and a second insulating layer on the first insulating layer in sequence; forming a second conductive layer and a third insulating layer on the second insulating layer in sequence; forming a third conductive layer and a fourth insulating layer on the third insulating layer in sequence; forming a fourth conductive layer on the fourth insulating layer; after forming the fourth conductive layer, the preparation method further includes: forming a fifth insulating layer on the fourth conductive layer; forming a fifth conductive layer, an organic light-emitting layer of a light-emitting element, and a second electrode on the fifth insulating layer in sequence; wherein the fifth conductive layer includes a first electrode of the light-emitting element.

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