Memory with programmable refresh order and interleaving time

Abstract

This document discloses a memory having a programmable refresh order and interleaved timing. In one embodiment, the memory device includes a first bank and a second bank. The memory device is configured to, in response to a refresh command, perform a first refresh operation on the first bank at a first time and a second refresh operation on the second bank at a second time after the first time. The memory device is further configured to, in response to a read or write command, perform a read or write operation on the first bank, the second bank, or both the first bank and the second bank after the first refresh has begun and after the second refresh has been completed.

Description

Technical Field

[0001] This disclosure relates to memory systems, apparatuses, and associated methods. In particular, this disclosure relates to memory apparatuses having programmable refresh order and programmable refresh interleaving time. Background Technology

[0002] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Memory devices are often provided as internal semiconductor integrated circuits in computers or other electronic devices and / or as external removable devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory, including static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), as well as other types of memory, may require an external power source to maintain its data. In contrast, non-volatile memory can retain its stored data even without external power. Non-volatile memory can be used in a wide variety of technologies, including flash memory (e.g., NAND and NOR), phase-change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), as well as other types of memory. Typically, among other metrics, improvements to memory devices may include increasing memory cell density, increasing read / write speeds or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs. Summary of the Invention

[0003] This disclosure provides a method comprising: receiving a refresh command; in response to the refresh command: performing a first refresh operation on a first memory bank of a memory device at a first time, and performing a second refresh operation on a second memory bank of the memory device at a second time after the first time; receiving a read command or a write command after receiving the refresh command; and in response to the read command or the write command, performing a read or write operation on the first memory bank after the first refresh operation on the first memory bank is started and before the second refresh operation on the second memory bank is completed.

[0004] Another aspect of this disclosure provides an apparatus comprising: a memory array including a first memory bank group and a second memory bank group; and logic coupled to a command / address bus and the memory array, wherein the logic is configured to: perform a first refresh operation on the first memory bank group at a first time in response to a refresh command received via the command / address bus, and perform a second refresh operation on the second memory bank group at a second time after the first time; and perform a read or write operation on the first memory bank group, the second memory bank group, or both the first memory bank group and the second memory bank group in response to a read or write command received via the command / address bus, after the first refresh has begun and before the second refresh operation has been completed.

[0005] Another aspect of this disclosure provides a system comprising: a memory controller; and a memory device communicating with the memory controller, wherein the memory device includes a first memory bank and a second memory bank, and wherein: the memory controller is configured to issue a refresh command to the memory device, the refresh command instructing the memory device to refresh both the first memory bank and the second memory bank; in response to the refresh command, the memory device is configured to: perform a first refresh operation on the first memory bank at a first time; and perform a second refresh operation on the second memory bank at a second time after the first time; and the memory device is further configured to perform a read or write operation on the first memory bank, the second memory bank, or both the first memory bank and the second memory bank after the first refresh operation begins and before the second refresh operation is completed. Attached Figure Description

[0006] Many aspects of this disclosure can be better understood by referring to the following figures. The components in the figures are not necessarily scaled. Rather, the focus is on clearly illustrating the principles of this disclosure. The figures should not be used to limit this disclosure to the specific embodiments depicted, but are merely for explanation and understanding.

[0007] Figure 1 A block diagram illustrating various embodiments of a memory system configured according to the present technology.

[0008] Figure 2 This is a timing diagram of the default response of a memory device according to various embodiments of the present technology to receiving a command to refresh all memory banks.

[0009] Figure 3 and 4 This is a timing diagram of a memory device according to various embodiments of the present technology for receiving a programmable response to a command to refresh all memory banks.

[0010] Figure 5A flowchart illustrating a programmable refresh routine for a memory device and / or memory system configured according to various embodiments of the present technology.

[0011] Figure 6 A schematic diagram of a system comprising a memory device configured according to various embodiments of the present technology. Detailed Implementation

[0012] Memory devices, such as DRAM devices, utilize refresh operations to prevent data corruption by factors such as charge leakage or other effects that degrade data over time. Typically, a memory device performs a refresh operation in response to receiving a refresh command (e.g., from a memory controller). One such refresh command is a refresh all banks command (REFab). In response to receiving the refresh all banks command (REFab), the memory device continues to perform several refresh operations to refresh all banks of its memory array within a time period (tRFC1). Memory devices often interleave these refresh operations to reduce the peak power consumed by the memory device, meaning that the memory banks of the memory device are refreshed at different points in time during the time period (tRFC1). Furthermore, the memory device locks the memory array so that the memory banks of the memory device are inaccessible for reading or writing data during the time period (tRFC1). Therefore, each time the refresh all banks command (REFab) is issued, the total time that the memory array of the memory device is available for reading and writing data is reduced, even if several banks of the memory array are idle (e.g., not currently accessed) and are not the target of refresh operations for at least a portion of the time period (tRFC1).

[0013] To address this issue and increase the total time that the memory array of a memory device can be used for reading and writing data, the memory system and apparatus of this technology can execute commands (e.g., precharge, write, read, and / or other commands) on selected memory banks and / or selected memory groups in the memory array that are idle and not currently subject to a refresh operation, while the memory device performs a refresh operation on other memory banks and / or other memory groups in the memory array in response to receiving a refresh all memory bank command REFab. In some embodiments, the memory system and apparatus can be programmed to refresh the memory banks and / or memory groups in the memory array in the order (refresh order). Such capabilities provide flexibility regarding the time that a particular memory bank and / or memory group remains or becomes accessible after receiving a refresh all memory bank command REFab. For example, the memory device of this technology can be selectively programmed to perform a refresh operation (e.g., start and / or execute) on a second memory group after performing a refresh operation (e.g., start and / or execute) on a first memory group in response to receiving a refresh all memory bank command REFab. In this example, during the period following the memory device receiving the refresh all memory bank command REFab, the second memory bank group remains accessible for reading and writing data while the memory device performs a refresh operation on the first memory bank group, and continues until the memory device performs a refresh operation to refresh the second memory bank group. Alternatively, after the memory device completes a refresh operation on the first memory bank group and while the memory device performs a refresh operation on the second memory bank group, the first memory bank group may become accessible for reading and writing data. In some embodiments, the memory device may be selectively reprogrammed to perform a refresh operation on the first memory bank group after performing a refresh operation on the second memory bank group in response to receiving the refresh all memory bank command REFab. In such examples, during the period following the memory device receiving the refresh all memory bank command REFab, the first memory bank group remains accessible for reading and writing data, and / or the second memory bank group becomes accessible for reading and writing data after the memory device performs a refresh operation on the second memory bank group.

[0014] In these and other embodiments, the memory systems and apparatus of this technology can selectively program time periods (interleaving times) between refresh operations on banks and / or groups of banks. This capability provides flexibility regarding the time and / or duration for which a particular bank and / or group of banks remains or becomes accessible after receiving a refresh all-banks command REFab. For example, a memory apparatus of this technology can be selectively programmed to perform a refresh operation (e.g., start and / or execute) on a second bank group for a specified time period after a refresh operation (e.g., start and / or execute) is performed on a first bank group in response to receiving a refresh all-banks command REFab. In this example, the time period for which the second bank group remains accessible for reading or writing data after receiving the refresh all-banks command REFab may depend at least in part on the specified time period. In other words, as the duration of the specified time period increases, the second bank group may remain accessible for reading or writing data for a longer period after the memory apparatus receives the refresh all-banks command REFab. Alternatively, as the duration of the specified time period decreases, the second bank group can remain accessible for reading or writing data for a shorter period of time after the memory device receives the refresh command REFab for all banks, and / or the memory device can perform a refresh operation on the second bank group more quickly, making the second bank group accessible for reading or writing data more quickly after the refresh.

[0015] Those skilled in the art will understand that the technology may have additional embodiments, and that the technology may be described without further reference. Figures 1 to 6 The embodiments described herein are practiced in several details. In the embodiments described below, memory devices and systems are primarily described in the context of means incorporating DRAM storage media. However, memory devices configured according to other embodiments of the present technology may include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive, and other storage media, including non-volatile, flash (e.g., "NAND" and / or "NOR") storage media.

[0016] As used herein, the term "refresh" refers to various maintenance operations that can be performed on one or more memory cells of a memory device configured according to various embodiments of the present technology. In some embodiments, the term "refresh" may refer to a maintenance operation performed on one or more memory cells to maintain their data. For example, in the context of DRAM and other memory devices, the term "refresh" may refer to reading data from one or more memory cells and rewriting the data to one or more memory cells to increase the charge stored on one or more memory cells to improve charge leakage and prevent data loss. In these and other embodiments, the term "refresh" may refer to reading data from one or more memory cells and rewriting the data to one or more memory cells in the opposite or other data state (e.g., from high to low or from low to high) to improve hysteresis offset, material depolarization, imprinting, and / or wear effects, etc. In these and other embodiments, the term "refresh" may refer to other maintenance operations, such as reading data from one or more memory cells and rewriting the data to one or more memory cells at another / other memory location. The term "refresh operation" refers to one or more operations (e.g., one or more automatic refresh operations, one or more self-refresh operations, and / or one or more row hammer refresh operations) that refresh one or more memory cells of a memory device during the process.

[0017] In the embodiments described below, for clarity and understanding, the memory devices and systems are described primarily in the context of programming the refresh order and refresh interleaving time of memory bank groups, wherein each memory bank group comprises multiple individual memory banks. However, this disclosure is not limited thereto. Those skilled in the art will recognize that all or subgroups of the techniques disclosed herein can be implemented in the context of programming the interleaving order and / or interleaving time of memory regions (e.g., individual memory banks, subgroups of individual memory banks, memory rows, memory columns, memory cells, logical memory banks, multiple memory bank groups, memory dies, memory devices, memory systems, etc.) rather than memory bank groups, and such implementations are within the scope of this technology.

[0018] Furthermore, in the embodiments described below, for clarity and understanding, the memory device and system are described primarily in the context of refreshing each bank of the memory device in response to receiving the refresh all banks command REFab. However, this disclosure is not limited thereto. Those skilled in the art will recognize that all or a subgroup of the techniques disclosed herein may be implemented in the context of refreshing a subgroup of the memory devices of the memory device in response to receiving one or more refresh commands instead of the refresh all banks command REFab, and such implementations are within the scope of this technology.

[0019] Figure 1The block diagram illustrates a memory system 190 configured according to various embodiments of the present technology. The memory system 190 may include a memory device 100 (e.g., a single memory die, multiple memory dies, etc.) that can be connected to any of a plurality of electronic devices, or components thereof, capable of using the memory for temporary or permanent storage of information. For example, the memory device 100 may be operatively connected to a memory controller 101 (e.g., via interface 119) and / or a host device 108 (e.g., via interface 116 and / or via memory controller 101 and interface 117). The host device 108 operatively connected to the memory device 100 may be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet, digital reader, digital media player, etc.), or some components thereof (e.g., a central processing unit, coprocessor, dedicated memory controller, etc.). The host device 108 may be a networked device (e.g., a switch, router, etc.) or a recorder of digital images, audio and / or video, a vehicle, a home appliance, a toy, or any of many other products. In one embodiment, the host device 108 may be directly connected to the memory device 100, but in other embodiments, the host device 108 may be indirectly connected to the memory device 100 (e.g., via a network connection or via an intermediary device, such as a memory controller 101).

[0020] The memory device 100 can receive multiple signals (e.g., from the memory controller 101 and / or from the host device 108). In this regard, the memory device 100 may employ multiple external terminals, including command terminals and address terminals respectively coupled to the command bus and address bus to receive command signal CMD and address signal ADDR (e.g., from the memory controller 101 and / or from the host device 108). The memory device may further include: a chip select terminal for receiving a chip select signal CS; a clock terminal for receiving clock signals CK and CKF; a data clock terminal for receiving data clock signals WCK and WCKF; data terminals DQ, RDQS, DBI, and DMI; and power supply terminals VDD, VSS, and VDDQ.

[0021] Power supply potentials VDD and VSS can be supplied to the power supply terminals of memory device 100. These power supply potentials VDD and VSS can be supplied to internal voltage generator circuit 170. Internal voltage generator circuit 170 can generate various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS. Internal potential VPP can be used in line decoder 140, internal potentials VOD and VARY can be used in sense amplifiers included in memory array 150 of memory device 100, and internal potential VPERI can be used in many other circuit blocks.

[0022] A power supply potential VDDQ can also be supplied to the power supply terminals. The power supply potential VDDQ can be supplied to the input / output (IO) circuit 160 together with the power supply potential VSS. In an embodiment of this technology, the power supply potential VDDQ can be the same potential as the power supply potential VDD. In another embodiment of this technology, the power supply potential VDDQ can be a different potential than the power supply potential VDD. However, a dedicated power supply potential VDDQ can be used in the IO circuit 160 so that power supply noise generated by the IO circuit 160 does not propagate to other circuit blocks.

[0023] External clock signals and complementary external clock signals can be supplied to the clock terminal and data clock terminal. External clock signals CK, CKF, WCK, and WCKF can be supplied to the clock input circuit 120. CK and CKF signals can be complementary, and WCK and WCKF signals can also be complementary. Complementary clock signals can have opposite clock levels and simultaneously transition between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and vice versa.

[0024] The clock input circuit 120 includes an input buffer that can receive external clock signals. For example, when enabled by the CKE signal from the command decoder 115, the input buffer can receive CK and CKF signals as well as WCK and WCKF signals. The clock input circuit 120 can receive external clock signals to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to the internal clock circuit 130. The internal clock circuit 130 can provide various phase and frequency controlled internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from the command decoder 115. For example, the internal clock circuit 130 may include a clock path (in... Figure 1(Not shown), the clock path receives the internal clock signal ICLK and provides various clock signals (not shown) to the command decoder 115. The internal clock circuit 130 may further provide input / output (IO) clock signals. The IO clock signals may be supplied to the IO circuit 160 and may be used as timing signals to determine the output timing for reading data and the input timing for writing data. Multiple clock frequencies may be provided for the IO clock signals so that data can be output from and input to the memory device 100 at different data rates. Higher clock frequencies are desirable when high memory speed is desired. Lower clock frequencies are desirable when lower power consumption is desired. The internal clock signal ICLK may also be supplied to the timing generator 135, and thus various internal clock signals may be generated that can be used by the command decoder 115, the column decoder 145, and / or other components of the memory device 100.

[0025] Memory device 100 may include an array of memory cells, such as memory array 150. The memory cells of memory array 150 may be arranged in multiple memory bank regions, and each memory region may include multiple word lines (WLs), multiple bit lines (BLs), and multiple memory cells arranged at the intersections of word lines and bit lines. In some embodiments, a memory region may be one or more memory banks or another arrangement of memory cells (e.g., half a memory bank, a subarray within a memory bank, etc.). In these and other embodiments, the memory regions of memory array 150 may be arranged in one or more groups (e.g., one or more groups of memory banks, one or more logical memory columns, or dies, etc.). The memory cells in memory array 150 may include any of a variety of different memory media types, including capacitor, magnetoresistive, ferroelectric, phase-change, etc. The selection of word lines WLs may be performed by row decoder 140, and the selection of bit lines BLs may be performed by column decoder 145. A sense amplifier (SAMP) may be provided for a corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which may in turn be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmit gate (TG) that can be used as a switch. The memory array 150 may also include board lines and corresponding circuitry for managing its operation.

[0026] Address signals and bank address signals can be supplied to the command and address terminals from outside the memory device 100 (e.g., from the memory controller 101 and / or from the host device 108). The address signals and bank address signals supplied to the address terminals are transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 can receive the address signals and supply the decoded row address signal (XADD) to the row decoder 140 and the decoded column address signal (YADD) to the column decoder 145. The address decoder 110 can also extract the bank address signal (BADD) and supply it to both the row decoder 140 and the column decoder 145.

[0027] Command signals CMD, address signals ADDR, and chip select signals CS can be supplied to command and address terminals (e.g., from memory controller 101 and / or host device 108). The command signals can represent various memory commands (e.g., access commands, which may include read commands, write commands, and refresh commands). The select signal CS can be used to select memory device 100 to respond to commands and addresses provided to the command and address terminals. When an active CS signal is provided to memory device 100, commands and addresses can be decoded and memory operations can be performed. The command signal CMD can be provided as an internal command signal ICMD to command decoder 115 via command / address input circuitry 105. Command decoder 115 may include circuitry for decoding the internal command signal ICMD to generate various internal signals and commands for performing memory operations (e.g., row command signals for selecting word lines and column command signals for selecting bit lines). The internal command signals may also include outputting and inputting activation commands to command decoder 115, such as clock command CMDCK (not shown).

[0028] Command decoder 115 may further include one or more registers 118 for tracking various counts or values ​​(e.g., counts of refresh commands received by memory device 100 or self-refresh operations performed by memory device 100) and / or for storing various operating conditions of memory device 100 for performing certain functions, features, and modes (refresh mode, test mode, etc.). Therefore, in some embodiments, register 118 (or a subgroup of register 118) may be referred to as a mode register. As described in more detail below, memory device 100 can be placed in refresh mode by programming certain bits of register 118. Once memory device 100 is placed in refresh mode, memory device 100 can use certain address bits received in the address signal ADDR to determine the order in which the banks of memory array 150 are refreshed in response to receiving the refresh all banks command REFab (refresh order) and / or to determine one or more time periods (one or more interleaved times) between refresh operations on the banks after receiving the refresh all banks command REFab. Alternatively, the refresh order and / or one or more interleaving times can be specified by programming certain bits of register 118. In other words, the refresh order and / or one or more interleaving times can be programmed using register 118 of memory device 100 and / or by using certain address bits of the address signal ADDR received by memory device 100.

[0029] When a read command is issued and row and column addresses are supplied in a timely manner along with the read command, read data can be read from memory cells in memory array 150 specified by these row and column addresses. The read command can be received by command decoder 115, which can provide internal commands to I / O circuitry 160 to enable read data to be output from data terminals DQ, RDQS, DBI, and DMI via read / write (RW) amplifier 155 and I / O circuitry 160 according to the RDQS clock signal. Read data can be provided at a time defined by read latency information RL, which can be programmed into memory device 100, for example, in mode register 118. The read latency information RL can be defined based on the clock cycle of the CK clock signal. For example, the read latency information RL can be the number of clock cycles of the CK signal when the associated read data is provided after memory device 100 receives a read command.

[0030] When a write command is issued and the row and column addresses are supplied in a timely manner along with the command, write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command can be received by a command decoder 115, which can provide an internal command to the I / O circuit 160 so that the write data can be received by the data receiver in the I / O circuit 160 and supplied to the memory array 150 via the I / O circuit 160 and the RW amplifier 155. The write data can be written to the memory cells specified by the row and column addresses. The write data can be supplied to the data terminals at a time defined by the write latency information WL. The write latency information WL can be programmed in the memory device 100, for example, in the mode register 118. The write latency information WL can be defined according to the clock cycle of the CK clock signal. For example, the write latency information WL can be the number of clock cycles of the CK signal when the associated write data is received after the memory device 100 receives the write command.

[0031] Memory array 150 can be refreshed or maintained as described herein to prevent data loss due to charge leakage or imprinting effects. As described herein, a refresh operation can be initiated by memory system 190 (e.g., by host device 108, memory controller 101, and / or memory device 100) and may include accessing one or more rows (e.g., WLs) and discharging the cells of the accessed rows to the corresponding SAMP. When a row is opened (e.g., when the accessed WL is activated), the SAMP can compare the voltage generated from the discharged cells with a reference. The SAMP can then write back the logic value (e.g., charge the cell) to the nominal value of a given logic state. In some cases, this write-back process can increase the charge of the cell to improve the discharge problem discussed above. In other cases, the write-back process can reverse the data state of the cell (e.g., from high to low or from low to high) to improve hysteresis offset, material depolarization, etc. Other refresh schemes or methods may also be employed.

[0032] In one method, memory device 100 may be configured to simultaneously refresh the same row of memory cells in each bank of memory array 150. In another method, memory device 100 may be configured to sequentially refresh the same row of memory cells in each bank of memory array 150. In yet another method, memory device 100 may further include circuitry (e.g., one or more registers, latches, embedded memories, counters, etc.) configured to track row (e.g., word line) addresses, each corresponding to one bank of memory in memory array 150. In this method, memory device 100 is not limited to refreshing the same row in each bank of memory array 150 before refreshing another row in one bank.

[0033] Regardless of the refresh method, memory device 100 can be configured to refresh memory cells in memory array 150 within a given refresh rate, or time window referred to as tREF (e.g., 32ms, 28ms, 25ms, 23ms, 21ms, 18ms, 16ms, 8ms, etc.). In these embodiments, memory system 190 (e.g., memory controller 101, host device 108, and / or memory device 100) can be configured to supply refresh commands to memory device 100 according to a specified minimum tREFI rhythm. For example, memory system 190 can be configured to supply one or more refresh commands to memory device 100 at least every 7.8μs, such that approximately 4000 refresh commands are supplied to memory device 100 within a 32ms time window.

[0034] As in Figure 1 As shown, memory device 100 includes a central logic circuitry system 125. The central logic circuitry system 125 includes one or more array timers 127. In some embodiments, the array timers 127 include a central array timer shared among the memory banks of memory array 150 and activated when memory device 100 receives a refresh command. Alternatively, array timers 127 may include array timers dedicated to individual memory banks, multiple memory banks, memory subgroups within individual memory banks, etc. As discussed in more detail below, memory device 100 may utilize the central array timer of central logic circuitry system 125 and / or other array timers 127 to determine when to perform a refresh operation and / or when to perform other operations (e.g., row hammer refresh (RHR) operation) after receiving a refresh command.

[0035] As explained above, an example of a refresh command is the refresh all memory bank command REFab. In response to receiving the refresh all memory bank command REFab, memory device 100 may continue to perform several refresh operations to refresh all memory banks of its memory array 150. Figure 2 Timing diagram 210 shows the default response of memory device 100 to receiving the REFab command to refresh all memory banks. For clarity and understanding, the memory array 150 of memory device 100 is shown with respect to... Figure 2 (and below) Figure 3 and 4 The memory array 150 of the memory device 100 is described as comprising four memory bank groups B0-B3, each of which includes a plurality of memory banks. In other embodiments, the memory array 150 of the memory device 100 may include more or fewer memory bank groups.

[0036] refer to Figure 2In response to receiving a refresh command REFab for all memory banks, memory device 100 locks memory bank groups B0-B3 (e.g., memory device 100 prevents memory bank groups B0-B3 from being accessed and / or made available for other operations) and continues to refresh each memory bank of memory array 150 during the time period tRFC1. Specifically, memory device 100 first performs interleaved refresh operations on memory bank groups B0-B3 (e.g., using...). Figure 1 The array timer 127 of the central logic circuit system 125 (e.g., to reduce the peak power consumed by the memory device 100 while refreshing the banks of the memory array 150). For example, the memory device 100 performs a refresh operation on bank group B3 (e.g., one or more auto-refresh operations and / or one or more RHR operations), and then performs a refresh operation on bank group B1 (e.g., one or more auto-refresh operations and / or one or more RHR operations) at time t1 after the memory device 100 has performed a refresh operation on bank group B3. Similarly, the memory device 100 performs a refresh operation on bank group B2 (e.g., one or more auto-refresh operations and / or one or more RHR operations) at time t1 after the memory device 100 has performed a refresh operation on bank group B2, and performs a refresh operation on bank group B0 (e.g., one or more auto-refresh operations and / or one or more RHR operations) at time t1 after the memory device 100 has performed a refresh operation on bank group B2. The time t1 is equal, which makes the interleaving of refresh operations on memory groups B0-B3 consistent.

[0037] Because the refresh operations for memory groups B0-B3 are interleaved, there exist time periods tRFC1 during which memory groups B0-B3 are not updated shortly after receiving the refresh command REFab for all memory groups. For example, memory groups B0-B2 are not refreshed for at least time t1 after receiving the refresh command REFab for all memory groups. Indeed, as in Figure 2As shown, after receiving the refresh all memory bank command REFab, memory bank group B2 is not refreshed for at least twice the time t1, and memory bank group B0 is not refreshed for at least three times the time t1. Therefore, for a portion of the time period tRFC1 after receiving the refresh all memory bank command REFab, memory bank groups B0-B2 remain idle (e.g., not currently used for reading or writing data because memory array 150 is locked) and are not the object of refresh operations. Depending at least in part on the duration of time t1, memory device 100 may have sufficient time to receive and execute one or more access (e.g., precharge, read, and / or write) and / or other commands on memory bank groups B0, B1, and / or B2 before memory device 100 performs refresh operations on memory bank groups B0, B1, and / or B2 in response to receiving the refresh all memory bank command REFab. Therefore, depending at least in part on the duration of time t1, locking the entire memory array 150 in response to receiving the refresh command REFab for all memory banks could constitute a waste of the total time available for reading and writing data for memory banks B0, B1, and / or B2.

[0038] In addition, such as in Figure 2 As shown, memory device 100 can perform two RHR pump operations on the memory rows (word lines) of the memory banks B0-B3 after completing an auto-refresh operation on memory banks B0-B3. These RHR operations are not interleaved, meaning that an RHR operation can be performed on any one of the memory banks B0-B3 during the time period tRFC1 after all memory banks B0-B3 have been auto-refreshed. In some embodiments, memory device 100 may use central logic circuitry system 125 ( Figure 1 The array timer 127 (e.g., the central array timer) is used to indicate when sufficient time has elapsed since receiving the refresh command REFab for memory device 100 to refresh the memory by an automatic refresh operation. Figure 2 All memory banks B0-B3 are configured such that memory device 100 can continue to perform RHR operations on memory banks B0-B3 before the time period tRFC1 expires.

[0039] Because it is possible to Figure 2 Any memory bank group B0-B3 performs an RHR operation, and because the RHR operation is not performed until all memory bank groups B0-B3 have been refreshed by an automatic refresh operation, the memory device 100 keeps all memory bank groups B0-B3 locked for the entire duration of time period tRFC1. Figure 2As shown, there is a time period after refreshing memory banks B1-B3 during which memory banks B1-B3 remain idle and are not the target of refresh or RHR operations. Therefore, depending at least in part on the time period required for memory device 100 to refresh individual memory banks via one or more auto-refresh operations, locking the entire memory array 150 for the remaining tRFC1 duration after refreshing memory banks B1, B2, and / or B3 via one or more auto-refresh operations but before executing the RHR pump can constitute a waste of the total time that memory banks B1, B2, and / or B3 remain available for reading and writing data and / or other operations. In other words, after refreshing memory banks B1, B2, and / or B3 via one or more auto-refresh operations and delaying the RHR operation on memory banks B1, B2, and / or B3 until memory device 100 completes refreshing memory bank B0, locking the entire memory array 150 for the remaining tRFC1 duration may constitute a waste of the total time that memory banks B1, B2, and / or B3 remain available for reading and writing data or for other operations.

[0040] To address these issues, memory device 100 can, upon receiving (e.g., a single) refresh command, receive and execute other commands (e.g., precharge, write, read, and / or other commands) on a group of memory banks in memory array 150 that are idle at the time the refresh command is executed and are not currently undergoing a refresh operation. For example, Figure 3 and 4 Timing diagrams 310 and 410 are shown for a memory device 100 according to various embodiments of the present technology, respectively, to receive a programmable response to the REFab command to refresh all memory banks.

[0041] First refer to Figure 3 Similar to Figure 2 In the default response illustrated in timing diagram 210, memory device 100 (e.g., logic coupled to the command / address bus) may, in response to the refresh all bank command REFab, lock bank groups B0-B3 and continue performing refresh operations (e.g., auto-refresh and / or RHR operations) on each bank of memory array 150. However, unlike the default response, memory device 100 (e.g., logic) may (1) interleave RHR operations such that an RHR operation is performed on a bank group shortly after memory device 100 has completed an auto-refresh operation on a single bank group, and (2) once memory device 100 has completed an RHR operation on a bank group, the bank group is unlocked for other commands.

[0042] For reference Figure 3In a specific example, memory device 100 (e.g., logic) may perform a refresh operation (e.g., an auto-refresh operation and / or one or more RHR operations) on memory group B3 in response to receiving a refresh all memory command REFab. In the illustrated embodiment, memory device 100 performs both an auto-refresh operation and an RHR operation on memory groups B0-B3. Specifically, shortly after memory device 100 completes refreshing memory group B3 via the auto-refresh command, memory device 100 may perform an RHR operation on memory group B3 without first waiting for memory device 100 to complete auto-refresh operations on other memory groups B0-B2. In some embodiments, memory device 100 (e.g., logic) may start and utilize central logic circuitry 125 ( Figure 1 ) array timer 127 ( Figure 1 The memory device 100 determines when to perform an RHR operation on memory bank group B3. When the memory device 100 receives the refresh all memory bank command REFab and / or when the memory device 100 performs a refresh operation on memory bank group B3, the memory device 100 may start array timer 127. After the memory device 100 completes the RHR operation on memory bank group B3, the memory device 100 (e.g., logically) may unlock memory bank group B3 and execute various commands CMD B3 (e.g., precharge, read, write, and / or other commands) on memory bank group B3 without first waiting for the memory device 100 to complete refreshing other memory bank groups B0-B2. Therefore, in this example, in conjunction with the above regarding... Figure 2 Unlike the time period tRFC1 discussed, memory bank B3 is only unavailable during the time period tRFCB3. In other words, unlike the execution of memory device 100... Figure 2 Compared to the default response described herein, when memory device 100 executes... Figure 3 When the programmable response is described, memory group B3 can be used for faster reading and writing of data (or for other operations) and for a longer total amount of time.

[0043] Continuing with the above example, the memory device 100 (e.g., logic) also performs a refresh operation on memory group B1 during an interleaved time S1 (e.g., while the memory device 100 is performing a refresh operation on memory group B3) after performing a refresh operation on memory group B3 (e.g., startup and / or execution). Shortly after the memory device 100 completes an automatic refresh of memory group B1, the memory device 100 may perform an RHR operation on memory group B1. In some embodiments, the memory device 100 (e.g., logic) may start and utilize the central logic circuitry system 125 ( Figure 1 ) array timer 127 ( Figure 1(For example, array timer 127 of the central logic circuitry 125, which may be the same as or different from array timer 127 used for memory bank group B3) determines when to perform an RHR operation on memory bank group B1. Memory device 100 may start array timer 127 when it receives a refresh all memory bank command REFab, when it performs a refresh operation on memory bank group B3, and / or when it performs a refresh operation on memory bank B1. After memory device 100 completes the RHR operation on memory bank group B1, memory device 100 (e.g., logic) may unlock memory bank group B1 and execute various commands CMD B3 or B1 (e.g., precharge, read, write, and / or other commands) on one or both of memory bank groups B3 and / or B1. Therefore, in this example, memory bank group B1 is unavailable during the time period tRFCB1.

[0044] Memory device 100 can refresh memory banks B2 and B0 in a manner similar to memory banks B3 and B1, making memory banks B2 and B0 unavailable during time periods tRFCB2 and tRFCB0, respectively. For example, one or more array timers 127 (e.g., array timers 127 dedicated to memory banks B2 or B0 and / or array timers 127 shared among all or subgroups of memory banks B0-B3) can be used to determine when to perform an RHR operation on memory banks B2 and B0. Memory device 100 can unlock memory bank B2 after time period TRFCB2 has elapsed and can execute various commands CMD B3, B1, or B2 (e.g., precharge, read, write, and / or other commands) on any one or more of memory banks B3, B1, and / or B2. After the time period TRFCB0 has elapsed, the memory device can unlock memory bank B0 and execute various commands CMD All BK (e.g., precharge, read, write and / or other commands) on any one or more of memory banks B0-B3.

[0045] In some embodiments, the order of memory bank groups B0-B3 can be programmably refreshed in response to a refresh all memory bank REFab command. For example, one or more mode registers 118 of memory device 100 ( Figure 1 One or more bits of the mode register 118 can be programmed to set the refresh order of memory banks B0-B3 in response to the REFab command. Table 1 below illustrates one possibility for programming the mode register 118 to set the refresh order of memory banks B0-B3:

[0046] MR bit Refresh order 0 B0, B1, B2, B3 1 B1, B2, B3, B0 2 B2, B3, B0, B1 3 B3, B0, B1, B2 4 B3, B2, B1, B0 5 B2, B1, B0, B3 6 B1, B0, B3, B2 7 B3, B1, B2, B0 8 B2, B0, B3, B1 9 B1, B3, B0, B2

[0047] Table 1

[0048] Table 1 above illustrates only 10 of the 24 possible refresh orders for memory banks B0-B3. Therefore, those skilled in the art will recognize that refresh orders other than those shown in Table 1 are also possible, and that one or more bits of mode register 118 may be used in addition to or in lieu of one or more of the refresh orders included in Table 1 above, and / or programmed into memory device 100 by using more than one mode register 118.

[0049] Referring to Table 1 above as an example, memory device 100 can be programmed to assert mode register 118 by bit 7. Figure 3 The refresh order described herein refreshes memory banks B0-B3. In this way, memory device 100 can be programmed such that memory bank B3 becomes the first memory bank group to become available after receiving the refresh all memory bank command REFab. In other words, the ability to program the refresh order of memory banks B0-B3 provides the flexibility to program memory device 100 to prioritize specific memory bank groups. For example, by programming mode register 118 such that bit 0 instead of bit 7 is asserted, memory device 100 can be programmed to refresh memory bank B0 first in response to receiving the refresh all memory bank command REFab, such that memory bank B0 is the first memory bank to become available (e.g., for reading or writing data) after receiving the refresh all memory bank command REFab, and / or ... Figure 2 It becomes available faster under the default response described in the document.

[0050] Alternatively, the command signal CMD received by the memory device 100 may be used. Figure 1 One or more bits of the REFab command can be programmed to specify the order in which memory banks B0-B3 are refreshed in response to the REFab command. For example, one or more bits of the REFab command can be programmed to specify the order in which memory banks B0-B3 are refreshed. Table 2 below shows an example of using two bits of the REFab command to program the order. Figure 3 Possible refresh order of memory banks B0-B3:

[0051] Command address bit 6 value Command address bit 7 value Refresh order 0 0 B0, B3, B1, B2 0 1 B1, B2, B0, B3 1 0 B2, B0, B3, B1 1 1 B3, B1, B2, B0

[0052] Table 2

[0053] Table 2 above illustrates only four of the 24 possible refresh orders for memory banks B0-B3. Therefore, those skilled in the art will recognize that other refresh orders besides those shown in Table 2 are also possible, and that one or more bits of the refresh all memory banks command REFab can be used to program the memory device 100 in addition to or in lieu of one or more of the refresh orders included in Table 2 above.

[0054] Referring to Table 2 above as an example, the memory device 100 can be programmed to assert both command address bit 6 and command address bit 7 by receiving the refresh all memory bank command REFab in the memory device 100. Figure 3 The order in which memory banks B0-B3 are refreshed is described. In this way, memory device 100 can be programmed such that memory bank B3 becomes the first memory bank group to become available after receiving the refresh all memory bank command REFab. As another example, by not declaring command address bit 6 or command address bit 7 when issuing the refresh all memory bank command REFab, memory device 100 can be programmed to refresh memory bank B0 first in response to receiving the refresh all memory bank command REFab, such that memory bank B0 is the first memory bank to become available (e.g., for reading or writing data) after receiving the refresh all memory bank command REFab, and / or such that memory bank B0 becomes available before... Figure 2 It becomes available faster under the default response described in the document.

[0055] In some embodiments, mode register 118 ( Figure 1 The bits of both the mode register 118 and the command signal CMD can be used to program the refresh order of memory banks B0-B3. For example, memory device 100 can be configured to preferentially select the refresh order specified in the mode register 118 instead of the refresh order specified in the refresh all memory bank command REFab (or vice versa). As a specific example, unless and / or until the bits of mode register 118 are programmed (at which point memory device 100 can be configured to refresh memory banks B0-B3 in the order specified in mode register 118), memory device 100 may refresh memory banks B0-B3 in the order specified in the refresh all memory bank command REFab received by memory device 100.

[0056] Refer again Figure 3After receiving the refresh command REFab for all memory banks, the time periods tRFC0, tRFC1, and tRFC2 during which memory banks B0, B1, and B2 are unavailable, respectively, depend at least in part on the interleaving times S1, S2, and / or S3 between refresh operations on memory banks B0, B1, and / or B2. In other words, shortening the duration of interleaving times S1, S2, and / or S3 reduces the time memory banks B0, B1, and / or B2 are locked after receiving the refresh command REFab, while increasing the interleaving times S1, S2, and / or S3 increases the time memory banks B0, B1, and / or B2 are locked after receiving the refresh command REFab.

[0057] In some embodiments, the lengths of the interleaving times S1, S2, and / or S3 can be programmed. For example, one or more mode registers 118 of the memory device 100 ( Figure 1 One or more bits of the mode register 118 can be programmed to set the interleaving times S1, S2, and / or S3. Table 3 below illustrates one possibility for programming the mode register 118 to set the interleaving times S1, S2, and S3:

[0058] MR bit Interleaving length (ns) 0 5 1 10 2 15 3 20 4 25 5 30

[0059] Table 3

[0060] Table 3 above illustrates only six possible interleaving lengths. Those skilled in the art will recognize that other interleaving lengths besides those shown in Table 3 above are also possible, and that one or more bits of one or more mode registers may be used to program into the memory device 100 in addition to or in lieu of one or more of the interleaving lengths included in Table 3 above.

[0061] Referring to Table 3 above as an example, memory device 100 can be programmed to enable bit 3 of assertion mode register 118 to... Figure 3 The refresh operations of memory bank groups B0-B3 are interleaved or offset by 20ns (e.g., S1, S2, and S3 are set to equal 20ns). In this way, memory device 100 (e.g., logic) can refresh memory bank group B0-B3 20ns after performing a refresh operation on memory bank group B3. Figure 3 The memory device 100 performs a refresh operation on memory bank B1. Similarly, the memory device 100 may perform a refresh operation on memory bank B2 20 ns after performing a refresh operation on memory bank B1, and the memory device 100 may perform a refresh operation on memory bank B0 20 ns after performing a refresh operation on memory bank B2.

[0062] As discussed above, the time periods tRFC1, tRFC2, and tRFC0 represent the duration for which memory groups B1, B2, and B0 remain locked after receiving the refresh all memory command REFab. In other words, tRFC1, tRFC2, and tRFC0 represent the amount of time elapsed before memory groups B1, B2, and B3 become available for reading or writing data or for other operations after receiving the refresh all memory command REFab. Reducing the interleaving times S1, S2, and / or S3 reduces the time periods tRFC1, tRFC2, and tRFC0, and therefore makes memory groups B1, B2, and / or B3 available faster after receiving the refresh all memory command REFab. Continuing with the example in Table 3, bits 0, 1, or 2 of assertion mode register 118 set the interleaving times S1, S2, and S3 to 5ns, 10ns, or 15ns, respectively. Upon receiving the REFab command to refresh all memory banks, memory banks B1, B2, and B3 become available for reading or writing data for other operations much faster than bit 3 of assertion mode register 118. On the other hand, bits 4 or 5 of assertion mode register 118 set the interleaving times S1, S2, and S3 to 25ns or 30ns, respectively, and add time periods tRFC1, tRFC2, and tRFC0. This prevents memory banks B1, B2, and B3 from becoming available after being refreshed until a later time point compared to the time point at which memory banks B1, B2, and B0 become available after being refreshed via bit 3 of assertion mode register 118. In other words, the ability to program the interleaving times S1, S2, and S3 between refresh operations of memory bank groups B0-B3 provides flexibility in accelerating or delaying the point in time when a particular memory bank group of the memory array 150 becomes available after the REFab refresh command for all memory banks has been received.

[0063] In some embodiments, more than one mode register 118 may be used, allowing the interleaving times S1, S2, and / or S3 to be independently programmable. In these embodiments, the interleaving times S1, S2, and / or S3 may be programmed to be equal to or different from each other. Independently programming the interleaving times S1, S2, and / or S3 provides greater granularity in setting the point in time when a particular bank becomes available after being refreshed in response to receiving the refresh all-banks command REFab. In these and other embodiments, one or more bits of the command signal CMD (e.g., the refresh all-banks command REFab) received by the memory device 100 may be used to program the interleaving times (e.g., in a manner similar to how one or more bits of the command signal CMD can be programmed to set the refresh order, as discussed above).

[0064] Each of the interleaving times S1, S2, and S3 described above is measured from the point in time when a refresh operation is performed on a bank group in memory array 150. For example, interleaving time S1 is described above as being measured from the point in time when a refresh operation is performed on bank group B3, and interleaving time S2 is described above as being measured from the point in time when a refresh operation is performed on bank group B1. In other embodiments, the interleaving times may be measured from other points in time. For example, one or more of the interleaving times may be measured from the point in time when the memory device 100 receives the refresh command REFab for all banks or from the point in time when the memory device 100 performs a refresh operation on the first bank group in the refresh order (e.g., bank group B3).

[0065] Now for reference Figure 4 The programmable response illustrated in timing diagram 410 is similar to that described above. Figure 3 The programmable response discussed is that the memory device 100 (e.g., logic) does not lock the entire memory array 150 in response to receiving the refresh command REFab for all memory banks. Instead, the memory device 100 (e.g., logic) locks the first group of memory banks in the programmed refresh order (e.g., ...). Figure 4 The remaining memory bank group (B3) is locked, and this is at least partially dependent on the interleaving times S1, S2, and / or S3. For example, if the length of the interleaving time S1 is long enough to receive and execute commands (e.g., precharge, read, write, or other commands) on memory bank group B1 before the memory device 100 (e.g., logic) performs a refresh operation on memory bank group B1, the memory device 100 (e.g., logic) may make memory bank group B1 available for a period of time after receiving the refresh command REFab for reading or writing data or for other operations. In some embodiments, the memory device 100 (e.g., logic) may subsequently lock memory bank group B1 for a period of time before performing a refresh operation on memory bank group B1 (e.g., to provide sufficient tolerance for precharging memory bank group B1 before performing a refresh operation). On the other hand, if the length of the interleaving time S1 is too short to receive and execute the command for the memory bank B1 before the memory device 100 (e.g., logic) performs a refresh operation on the memory bank B1, then the memory device 100 (e.g., logic) may lock the memory bank B1 immediately after receiving the refresh command REFab for all memory banks or shortly thereafter.

[0066] Similarly, memory device 100 (e.g., logic) may make memory bank groups B2 and / or B0 available for a period of time after receiving the refresh all memory bank command REFab, depending on the interleaving times S1, S2, and / or S3, to read or write data or for other operations. For example, if the length of the interleaving times S1 and / or S2 is long enough to receive and execute commands (e.g., precharge, read, write, or other commands) on memory bank group B2 before memory device 100 performs a refresh operation on memory bank group B2, memory device 100 may make memory bank group B2 available for the period of time during which the refresh all memory bank command REFab is received. Otherwise, memory device 100 may lock memory bank group B2 immediately upon receiving the refresh all memory bank command REFab or for a short period after receiving the refresh all memory bank command REFab. As another example, if the lengths of the interleaving times S1, S2, and / or S3 are sufficiently long to receive and execute commands (e.g., precharge, read, write, or other commands) on memory bank B0 before memory device 100 performs a refresh operation on memory bank B0, memory device 100 may use memory bank B0 for the period during which the refresh command REFab is received. Otherwise, memory device 100 may lock memory bank B0 immediately upon receiving the refresh command REFab or for a short period after receiving the refresh command REFab.

[0067] As discussed above, one or both of the refresh order and interleaving time can be programmed. This provides flexibility in receiving and executing commands (e.g., precharge, read, write, or other commands) on a specific memory group of memory array 150 after receiving the refresh command REFab for all memory banks and before performing refresh operations on one or more of memory groups B0-B3. For example, to provide sufficient time after receiving the refresh command REFab for all memory banks to receive and execute commands (e.g., precharge, read, write, or other commands) on memory group B0, the refresh order of memory device 100 can be programmed such that memory device 100 (e.g., logic) performs a refresh operation on each of the other memory groups B1-B3 before memory device 100 (e.g., makes memory group B0 the last in the refresh order) performs a refresh operation on memory group B0. Alternatively, the interleaving times S1, S2, and / or S3 can be programmed to adjust (e.g., delay) the timing of the memory device 100 (e.g., logic) performing a refresh operation on memory bank group B0. In this way, the memory device 100 (e.g., logic) can receive and execute commands on idle memory bank groups that are not currently being refreshed, after receiving the refresh command REFab for all memory banks and / or while performing refresh operations on other memory bank groups of the memory device 100.

[0068] Figure 5 This is a flowchart illustrating a programmable refresh routine 580 configured according to various embodiments of the present technology for a memory device and / or memory system. In some embodiments, routine 580 may be executed at least partially by the memory device, a memory controller operatively connected to the memory device, and / or a host device operatively connected to the memory controller and / or the memory device. For example, one or more steps of routine 580 may be implemented at least partially by components of the memory device, such as a command decoder, a central logic circuit system, one or more array timers, one or more mode registers, a row decoder, a column decoder, a memory array, a memory row, a memory bank, a memory bank group, and / or logic connected to a command / address bus. In these and other embodiments, all or subgroups of the steps of routine 580 may be executed by other components of the memory device, components of the memory controller, components of the host device, and / or other components of the memory system containing the memory device.

[0069] Routine 580 may begin at block 581 or block 582. At block 581, routine 580 programs the refresh order of the memory bank groups of the memory device and / or programs one or more interleaving lengths between refresh operations on the memory bank groups. For example, routine 580 may program one or more bits of one or more mode registers to set the order in which routine 580 refreshes the memory bank groups in response to receiving a refresh command (e.g., refresh all memory bank command REFab). In these and other embodiments, routine 580 may program one or more bits of one or more mode registers to set the time length between refresh operations on memory bank groups that are immediately adjacent to each other in the refresh order. The time lengths may be programmed to be equal and to offset the refresh operations uniformly from each other, or one or more of the time lengths may be programmed to be different from the other programmed time lengths.

[0070] At block 582, routine 580 receives a refresh command (e.g., a single refresh command, a sequence of refresh commands, or a series of refresh commands). For example, routine 580 may receive a refresh all memory bank command REFab instructing routine 580 to refresh each bank group of the memory device. In some embodiments, one or more command address bits of the refresh command are used to specify the refresh order of the refresh commands and / or one or more interleaving lengths. In these embodiments, routine 580 monitors one or more command address bits to determine the specified refresh order and / or interleaving length and thus programs the refresh order and / or interleaving length before proceeding to block 583 (block 582a).

[0071] At block 583, routine 580 executes the refresh command received at block 582 according to the refresh order and / or interleaving length programmed in blocks 581 and / or 582a. If the refresh command received at block 582 is a refresh all memory bank command REFab, routine 580 continues to refresh each memory bank group of the memory device. In some embodiments, routine 580 locks all or subgroups of memory banks in response to receiving a refresh command. For example, routine 580 may lock the first memory bank group specified in the refresh order in response to receiving a refresh command and may continue to perform refresh operations (e.g., one or more auto-refresh operations and / or one or more RHR operations) on the first memory bank group. In some embodiments, routine 580 may simultaneously receive and execute one or more commands (e.g., precharge, read, write, and / or other commands) on one or more other memory bank groups of the memory device (block 583a), such as the second memory bank group specified in the refresh order or another memory bank group of the memory device. One or more commands may be storage group-specific commands (e.g., access commands) and / or other non-array-specific commands.

[0072] In cases where a refresh operation includes both an auto-refresh operation and a Refresh-Reset (RHR) operation, routine 580 may perform the auto-refresh operation before (or vice versa) the RHR operation. Specifically, after performing an auto-refresh operation on the first bank group specified in the refresh sequence, routine 580 may continue to perform one or more RHR operations on the first bank group without first waiting for routine 580 to refresh other bank groups of the memory device. In some embodiments, routine 580 uses an array timer of the memory device to determine the timing of the RHR operations. The array timer may be dedicated to the first bank group and / or shared among all or subgroups of bank groups of the memory device. Once routine 580 has completed performing refresh operations (e.g., auto-refresh and / or RHR operations) on the first bank group, routine 580 may unlock the first bank group for reading or writing data or other operations.

[0073] Continuing with the example above, routine 580 may lock the second memory bank. For example, routine 580 may lock the second memory bank for a period of time before performing a refresh operation on the second memory bank (e.g., pre-charging the second memory bank for the refresh operation). Alternatively, routine 580 may lock the second memory bank when a refresh command is received at block 582. In some embodiments, whether routine 580 locks the second memory bank when receiving a refresh command at block 582 or at some later time may depend at least in part on the programmed length of the interleaving time between (1) receiving the refresh command at block 582 or at the time when a refresh operation is performed on the first memory bank and (2) the time when a refresh operation is performed on the second memory bank or at the time of the refresh operation performed on the second memory bank.

[0074] Routine 580 may continue to perform refresh operations (e.g., one or more automatic refresh operations and / or one or more RHR operations) on the second bank group after one or more interleaving times specified in the programmed interleaving lengths have elapsed. Routine 580 may perform refresh operations on the second bank group simultaneously with routine 580 performing refresh operations on the first bank group. Alternatively or concurrently, routine 580 may perform refresh operations simultaneously with receiving and / or executing one or more commands (e.g., precharge, read, write, and / or other commands) (block 583a) on one or more other bank groups of the memory device (e.g., the first or third bank group specified in the refresh sequence). The one or more commands may be bank group-specific commands (e.g., access commands) and / or other non-array-specific commands.

[0075] In a specific instance, after performing an automatic refresh operation on the second bank group, routine 580 may continue to perform one or more RHR operations on the second bank group without first waiting for routine 580 to refresh other bank groups of the memory device. In some embodiments, routine 580 uses an array timer of the memory device to determine the timing of the RHR operations. The array timer may be dedicated to the second bank group and / or shared among all or subgroups of bank groups of the memory device. Once routine 580 has completed performing RHR operations on the second bank group, routine 580 may unlock the second bank group to read or write data or perform other operations.

[0076] Routine 580 may continue to execute the refresh command received at block 582 by performing refresh operations (e.g., one or more automatic refresh operations and / or one or more row hammer refresh operations) on one or more other (e.g., remaining) memory banks of the memory device consistent with the above discussion. Routine 580 may also simultaneously receive and execute other commands (e.g., precharge, read, write, and / or other commands) on unlocked memory banks (e.g., the first or second memory bank or other memory banks that are not currently the object of a refresh operation).

[0077] Although the steps of Example 580 are discussed and explained in a specific order, Figure 5 The method described in routine 580 is not limited thereto. In other embodiments, the method may be performed in different procedures. In these and other embodiments, any step of routine 580 may be performed before, during, and / or after any other step of routine 580. Furthermore, those skilled in the art will readily recognize that the described method may be modified, yet remains within these and other embodiments of the present technology. For example, in some embodiments, it may be omitted and / or repeated. Figure 5 The steps of routine 580 described herein. In these and other embodiments, steps of routine 580 may be combined to form one or more other routines of the memory device.

[0078] Figure 6 This is a schematic diagram of a system including a memory device according to an embodiment of the present technology. (See above reference) Figures 1 to 5 Any of the aforementioned memory devices can be incorporated into any of a large number of larger and / or more complex systems, a representative example being... Figure 6 The system 690 is shown schematically in the diagram. System 690 may include a semiconductor device assembly 600, a power supply 692, a driver 694, a processor 696, and / or other subsystems and components 698. The semiconductor device assembly 600 may include components similar to those described above. Figure 1-5 The described memory devices share generally similar features and therefore may include various features related to memory content authentication. The resulting system 690 can perform any of a wide range of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative system 690 may include, but is not limited to, handheld devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. Components of system 690 may be housed in a single unit or distributed over multiple interconnected units (e.g., via a communication network). Components of system 690 may also include remote devices and any of a wide variety of computer-readable media.

[0079] End

[0080] The detailed description of embodiments of this technology above is not intended to be exhaustive or to limit the technology to the precise forms disclosed above. Although specific embodiments and examples of this technology have been described above for illustrative purposes, those skilled in the art will recognize that various equivalent modifications can be made within the scope of this technology. For example, when steps are presented and / or discussed in a given order, alternative embodiments may perform the steps in a different order. Furthermore, various embodiments described herein may be combined to provide further embodiments.

[0081] Based on the foregoing, it will be understood that specific embodiments of the present technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the present technology. To a certain extent, any material incorporated herein by reference that conflicts with this disclosure shall be superseded by this disclosure. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. Furthermore, unless the word “or” is clearly limited to referring only to a single item excluding other items when referring to a list of two or more items, its use in this list shall be construed as including (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. Furthermore, as used herein, the term “and / or” in phrases such as “A and / or B” refers to only A, only B, and both A and B. In addition, the terms “including,” “containing,” “having,” and “with” are used throughout the document to mean that at least some of the described features are included, without excluding any large number of the same features and / or other features of additional types.

[0082] Based on the foregoing, it will also be understood that various modifications can be made without departing from the technology. For example, the various components of the technology can be further divided into sub-components, or the various components and functions of the technology can be combined and / or integrated. Furthermore, although advantages associated with certain embodiments of the technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments are required to exhibit these advantages falling within the scope of this technology. Therefore, this disclosure and related technologies may encompass other embodiments not explicitly shown or described herein.

Claims

1. A method for performing memory operations, comprising: Receive refresh command; In response to the refresh command: Perform a first refresh operation on the first bank of the memory device at the first moment, and A second refresh operation is performed on the second memory bank group of the memory device at a second time after the first time. After receiving the refresh command, receive a read command or a write command; and In response to the read command or the write command, a read or write operation is performed on the first storage group after the first refresh operation is started on the first storage group and before the second refresh operation is completed on the second storage group.

2. The method of claim 1, further comprising, in response to the refresh command, offsetting the second time from the first time by an interleaved time, the interleaved time being programmed into one or more mode registers of the memory device.

3. The method of claim 1, further comprising, in response to the refresh command, performing the first refresh operation and the second refresh operation in accordance with the order specified in one or more mode registers programmed into the memory device and / or by one or more command address bits of the refresh command.

4. The method according to claim 1, wherein: The first refresh operation and the second refresh operation each include a row hammer refresh (RHR) operation; and The method further includes using one or more array timers of the memory device to initiate the RHR operation of the first refresh operation and the RHR operation of the second refresh operation at different times.

5. The method of claim 1, wherein the read or write operation is a first read or write operation, and wherein the method further includes performing a second read or write operation on the second memory bank during the first refresh operation.

6. The method of claim 1, wherein performing the read or write operation comprises performing the read or write operation on the first memory bank during the second refresh operation.

7. A memory device comprising: A memory array comprising a first memory bank group and a second memory bank group; and Logic, coupled to the command / address bus and the memory array, wherein the logic is configured to: In response to a refresh command received via the command / address bus, a first refresh operation is performed on the first memory bank group at a first time, and a second refresh operation is performed on the second memory bank group at a second time after the first time. In response to a read or write command received via the command / address bus, a read or write operation is performed on the first memory bank, the second memory bank, or both the first memory bank and the second memory bank after the first refresh is started and before the second refresh operation is completed.

8. The memory device of claim 7, further comprising one or more mode registers, wherein: One or more bits of the one or more mode registers are programmable to define the interleaving time between the first time and the second time; and In response to the refresh command, the logic is further configured to: Read one or more bits of the one or more mode registers to determine the interleaving time, and The second time is offset from the first time by the interleaved time.

9. The memory device of claim 7, further comprising one or more mode registers, wherein: One or more bits of the one or more mode registers are programmable to define the order in which the first bank group and the second bank group are refreshed in response to the refresh command; and In response to the refresh command, the logic is further configured to: Read the one or more bits of the one or more mode registers to determine the order, and The first refresh operation and the second refresh operation are performed in the order stated.

10. The memory device according to claim 7, wherein: The refresh command contains multiple command address bits; One or more of the plurality of command address bits specify the order in which the first memory group and the second memory group are refreshed in response to the refresh command; and In response to the refresh command, the logic is further configured to: Read the one or more command address bits to determine the order, and The first refresh operation and the second refresh operation are performed in the order stated.

11. The memory device of claim 7, wherein the logic is configured to perform the read or write operation on the second memory bank during the first refresh operation.

12. The memory device of claim 11, further comprising one or more array timers, wherein: The first refresh operation includes a row hammer refresh RHR operation; and The logic is further configured to initiate the RHR operation using one or more array timers in response to the refresh command.

13. The memory device according to claim 12, wherein: The RHR operation is the first RHR operation; The second refresh operation includes a second RHR operation; and The logic is further configured to initiate the second RHR operation using one or more array timers in response to the refresh command.

14. The memory device of claim 13, wherein the logic is configured to: The first RHR operation is initiated using the first array timer of the one or more array timers; and The second RHR operation is initiated using a second array timer, which is different from the first array timer.

15. The memory device of claim 7, wherein the logic is configured to perform the read or write operation on the first memory bank during the second refresh operation.

16. The memory device of claim 7, wherein the refresh command is a refresh all memory bank command (REFab).

17. The memory device of claim 7, wherein the device is a single memory die.

18. A memory system comprising: Memory controller; and A memory device that communicates with the memory controller, wherein the memory device includes a first memory bank and a second memory bank, and in: The memory controller is configured to issue a refresh command to the memory device, the refresh command instructing the memory device to refresh both the first memory bank group and the second memory bank group. In response to the refresh command, the memory device is configured to: Perform a first refresh operation on the first storage group at the first time; and A second refresh operation is performed on the second storage group at a second time after the first time. The memory device is further configured to perform a read or write operation on the first memory bank, the second memory bank, or both the first memory bank and the second memory bank after the first refresh operation begins and before the second refresh operation is completed.

19. The memory system of claim 18, wherein: The memory device further includes one or more mode registers; The memory controller is further configured to program one or more bits of the one or more mode registers to set the interleaving time between the first time and the second time; and In response to the refresh command, the memory device is further configured to offset the second time from the first time by the interleaved time.

20. The memory system of claim 18, wherein: The memory controller is further configured to: Programming one or more bits of one or more mode registers of the memory device to set the order in which the first bank group and the second bank group are refreshed in response to the refresh command, or The order of one or more command address bits of the refresh command is set by programming; and In response to the refresh command, the memory device is further configured to: Reading one or more bits of the one or more mode registers and / or reading one or more command address bits of the refresh command to determine the order, and The first refresh operation and the second refresh operation are performed in the order stated.

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