Display substrate, method for preparing same, and display device

Abstract

A display substrate, a method for manufacturing the same, and a display device. The manufacturing method includes: providing a substrate, on which a plurality of pixel driving circuits are formed, the plurality of pixel driving circuits including a first pixel driving circuit and a second pixel driving circuit; forming a first insulating layer on the substrate; forming a first wiring layer on the first insulating layer, the first wiring layer including a first connecting wiring, the first connecting wiring being formed to be electrically connected to the first pixel driving circuit through the first insulating layer; forming and patterning a second insulating layer on the first wiring layer; forming a second wiring layer on the second insulating layer, the second wiring layer including a second connecting wiring, the second connecting wiring being formed to be electrically connected to the second pixel driving circuit through the first insulating layer and the second insulating layer; and forming and patterning a third insulating layer on the second wiring layer; the third insulating layer and the second insulating layer are patterned using the same mask.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate, a method for manufacturing the same, and a display device. Background Art

[0002] Currently, display screens for electronic devices are developing towards larger and full-screen designs to provide users with a better visual experience. Taking electronic products such as mobile phones and tablet computers as examples, since these electronic devices need to incorporate components such as cameras and light sensors, and these components usually occupy the display area of the display screen, it is difficult to achieve a full-screen design for the display screen. In order to improve the light transmittance of the area where the camera is located in the display screen and ensure the photographing effect of the camera, only the light-emitting devices of the pixel circuit are retained in the area where the camera is located. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a method for manufacturing a display substrate. The manufacturing method includes: providing a substrate, wherein a plurality of pixel driving circuits are formed on the substrate, and the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit; forming a first insulating layer on the substrate, wherein the first insulating layer is formed to partially expose the plurality of pixel driving circuits; forming a first wiring layer on the first insulating layer, wherein the first wiring layer includes a first connection wiring, and the first connection wiring is formed to be electrically connected to the first pixel driving circuit through the first insulating layer; forming and patterning a second insulating layer on the first wiring layer; forming a second wiring layer on the second insulating layer, wherein the second wiring layer includes a second connection wiring, and the second connection wiring is formed to be electrically connected to the second pixel driving circuit through the first insulating layer and the second insulating layer; and forming and patterning a third insulating layer on the second wiring layer; wherein the third insulating layer and the second insulating layer are patterned using the same mask.

[0004] For example, the manufacturing method provided by at least one embodiment of the present disclosure further includes: forming a plurality of light-emitting devices on the third insulating layer, wherein each of the plurality of light-emitting devices includes a first electrode, the plurality of light-emitting devices include a first light-emitting device and a second light-emitting device, the first electrode of the first light-emitting device is electrically connected to the first connection wiring through the second insulating layer and the third insulating layer, and the first electrode of the second light-emitting device is electrically connected to the second connection wiring through the third insulating layer.

[0005] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the first insulating layer on the substrate includes: forming a first via and a second via in the first insulating layer, wherein the first via partially exposes the first pixel driving circuit, and the second via partially exposes the second pixel driving circuit.

[0006] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the first wiring layer on the first insulating layer includes: forming the first end of the first connection wiring to be electrically connected to the first pixel driving circuit through a first via hole in the first insulating layer, wherein the second end of the first connection wiring is formed to be used for electrically connecting the first light-emitting device.

[0007] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the second insulating layer includes: forming a third via hole and a fourth via hole in the second insulating layer, wherein the third via hole exposes the second end of the first connection wiring, and the orthographic projection of the fourth via hole on the substrate overlaps with the orthographic projection of the second end of the second connection wiring on the substrate.

[0008] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the second insulating layer further includes: forming a fifth via hole and a sixth via hole in the second insulating layer, wherein the orthographic projection of the fifth via hole on the substrate overlaps with the orthographic projection of the first via hole, and the fifth via hole exposes the first end of the first connection wiring, and the sixth via hole corresponds to the second via hole.

[0009] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the second wiring layer includes: forming the first end of the second connection wiring to be electrically connected to the second pixel driving circuit through a second via hole in the first insulating layer and the sixth via hole in the second insulating layer, wherein the second end of the second connection wiring is formed to be used for connecting the second light-emitting device.

[0010] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the third insulating layer includes: forming a seventh via hole and an eighth via hole in the third insulating layer, wherein the orthographic projection of the seventh via hole on the substrate overlaps with the orthographic projections of the first via hole in the first insulating layer and the fifth via hole in the second insulating layer on the substrate, and the seventh via hole exposes the first end of the first connection wiring, and the orthographic projection of the eighth via hole on the substrate overlaps with the orthographic projections of the second via hole in the first insulating layer and the sixth via hole in the second insulating layer on the substrate, and the eighth via hole exposes the first end of the second connection wiring.

[0011] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the third insulating layer further includes: forming a ninth via and a tenth via in the third insulating layer, wherein a positive projection of the ninth via on the substrate overlaps with a third via of the second insulating layer, and the ninth via exposes a second end of the first connection trace; a positive projection of the tenth via on the substrate overlaps with a fourth via of the second insulating layer, and the tenth via exposes a second end of the second connection trace.

[0012] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming a first electrode of the plurality of light-emitting devices includes: forming the first electrode of the first light-emitting device to be connected to the second end of the first connection trace through the third via of the second insulating layer and the ninth via of the third insulating layer; forming the first electrode of the second light-emitting device to be connected to the second end of the second connection trace through the tenth via of the third insulating layer.

[0013] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, while forming the first electrodes of the plurality of light-emitting devices, a first protective layer and a second protective layer are also formed. The first protective layer covers a seventh via of the third insulating layer and a fifth via of the second insulating layer, and the second protective layer covers an eighth via of the third insulating layer.

[0014] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the first trace layer further includes: forming a first cushion layer at a second via of the first insulating layer, wherein the first cushion layer at least partially covers the second via and is electrically connected to the second pixel driving circuit, and a sixth via of the second insulating layer at least partially exposes the first cushion layer to allow the second connection trace to be electrically connected to the second pixel driving circuit through the first cushion layer.

[0015] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the first trace layer further includes: forming a second cushion layer on the first insulating layer, wherein the second cushion layer is electrically connected to the second end of the second connection trace, and a fourth via of the second insulating layer at least partially exposes the second cushion layer.

[0016] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the second trace layer further includes: forming a third cushion layer at a fifth via of the second insulating layer, wherein the third cushion layer at least partially overlaps with the fifth via of the second insulating layer, thereby being electrically connected to the first end of the first connection trace, and a seventh via of the third insulating layer at least partially exposes the third cushion layer to allow electrical connection to the first connection trace through the third cushion layer.

[0017] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the second wiring layer further includes: forming a fourth cushion layer on the second insulating layer, wherein the fourth cushion layer at least partially overlaps with the third vias of the second insulating layer and covers the second end of the first connection trace, and the ninth vias of the third insulating layer at least partially expose the fourth cushion layer.

[0018] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the plurality of light-emitting devices further includes: after forming the first electrodes of the plurality of light-emitting devices, forming a pixel defining layer on the first electrodes of the plurality of light-emitting devices and on a side of the third insulating layer away from the substrate, wherein the pixel defining layer is formed to include a plurality of first pixel openings, wherein the plurality of first pixel openings correspond to the plurality of light-emitting devices one by one to form the light-emitting regions of the plurality of light-emitting devices, forming the first light-emitting layers of the plurality of light-emitting devices in the first pixel openings, and forming the second electrodes of the plurality of light-emitting devices on a side of the first light-emitting layers and the pixel defining layer away from the substrate.

[0019] For example, in the manufacturing method provided by at least one embodiment of the present disclosure, forming the first wiring layer further includes: forming a first dummy trace, wherein the first dummy trace is connected to the second end of the first connection trace, forming the second wiring layer further includes: forming a second dummy trace, wherein the second dummy trace is connected to the second end of the second connection trace, wherein an extending direction of the first dummy trace intersects with an extending direction of the first connection trace, and an extending direction of the second dummy trace intersects with an extending direction of the second connection trace.

[0020] At least one embodiment of the present disclosure further provides a display substrate, which has a first side for display and a second side opposite to the first side, and includes a substrate, a first insulating layer disposed on the substrate, a first connection trace located in a first display area and a second display area, a second insulating layer disposed on a side of the first insulating layer away from the substrate, a second connection trace located in the first display area and the second display area, and a third insulating layer disposed on a side of the second insulating layer away from the substrate. The substrate includes: a display area, the display area including a first display area and at least a part of a second display area surrounding the first display area, wherein the first display area includes a first sub-pixel array, and the first display area allows light from the first side of the display substrate to be at least partially transmitted to the second side of the display substrate, the first sub-pixel array includes a plurality of light-emitting devices arranged in an array, the plurality of light-emitting devices include a first light-emitting device and a second light-emitting device, the second display area includes a first pixel driving circuit array, the first pixel driving circuit array includes a plurality of first pixel driving circuit units, and the plurality of first pixel driving circuit units include a first pixel driving circuit and a second pixel driving circuit; the first insulating layer includes a first via and a second via, the first via and the second via respectively expose the first pixel driving circuit and the second pixel driving circuit, the first connection trace is located on a side of the first insulating layer away from the substrate, a first end of the first connection trace is formed to be electrically connected to the first pixel driving circuit through the first via, a second end of the first connection trace is electrically connected to the first light-emitting device, the second insulating layer includes a plurality of vias, wherein the plurality of vias of the second insulating layer are formed to electrically connect the first light-emitting device, the second light-emitting device, the first pixel driving circuit, and the second pixel driving circuit, the second connection trace is located on a side of the second insulating layer away from the substrate, a first end of the second connection trace is formed to be electrically connected to the second pixel driving circuit through the second via and a via in the second insulating layer for connecting the second pixel driving circuit, a second end of the second connection trace is electrically connected to the second light-emitting device, the third insulating layer includes a plurality of vias, wherein the plurality of vias of the third insulating layer correspond to the plurality of vias of the second insulating layer one by one to form a plurality of vias penetrating through the second insulating layer and the third insulating layer.

[0021] For example, in the display substrate provided by at least one embodiment of the present disclosure, each of the plurality of light-emitting devices includes a first electrode, the first electrode of the first light-emitting device is connected to the second end of the first connection trace through the vias of the second insulating layer and the third insulating layer, and the first electrode of the second light-emitting device is connected to the second end of the second connection trace through the vias of the third insulating layer.

[0022] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of vias in the second insulating layer include a third via, a fourth via, a fifth via, and a sixth via. Among them, the third via and the fourth via are located in the first display area, the third via exposes the second end of the first connection trace, the orthographic projection of the fourth via on the substrate overlaps with the orthographic projection of the second end of the second connection trace on the substrate, the fifth via and the sixth via are located in the second display area, the orthographic projection of the fifth via on the substrate overlaps with the orthographic projection of the first via in the first insulating layer, and the fifth via exposes the first end of the first connection trace, and the orthographic projection of the sixth via on the substrate overlaps with the orthographic projection of the second via in the first insulating layer.

[0023] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first end of the second connection trace is electrically connected to the second pixel driving circuit through the second via in the first insulating layer and the sixth via in the second insulating layer, and the second end of the second connection trace is used to be electrically connected to the second light-emitting device.

[0024] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of vias in the third insulating layer include a seventh via, an eighth via, a ninth via, and a tenth via. Among them, the seventh via and the eighth via are located in the second display area, the orthographic projection of the ninth via on the substrate overlaps with the orthographic projection of the third via in the second insulating layer, and the ninth via exposes the second end of the first connection trace, the orthographic projection of the tenth via on the substrate overlaps with the orthographic projection of the fourth via in the second insulating layer, and the tenth via exposes the second end of the second connection trace. The ninth via and the tenth via are located in the first display area. The orthographic projection of the seventh via on the substrate overlaps with the orthographic projections of the first via in the first insulating layer and the fifth via in the second insulating layer on the substrate, and the seventh via exposes the first end of the first connection trace. The orthographic projection of the eighth via on the substrate overlaps with the orthographic projections of the second via in the first insulating layer and the sixth via in the second insulating layer on the substrate, and the eighth via exposes the first end of the second connection trace.

[0025] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first electrode of the first light-emitting device is connected to the second end of the first connection trace through the third via in the second insulating layer and the ninth via in the third insulating layer, and the first electrode of the second light-emitting device is connected to the second end of the second connection trace through the tenth via in the third insulating layer.

[0026] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first light-emitting device further includes a first protective layer, and the second light-emitting device further includes a second protective layer. The first protective layer covers the seventh via hole of the third insulating layer and the fifth via hole of the second insulating layer, and the second protective layer covers the eighth via hole of the third insulating layer.

[0027] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a first cushion layer and a second cushion layer. The first cushion layer at least partially covers the second via hole of the first insulating layer and is electrically connected to the second pixel driving circuit. The sixth via hole of the second insulating layer at least partially exposes the first cushion layer to allow the second connection trace to be electrically connected to the second pixel driving circuit through the first cushion layer. The second cushion layer is electrically connected to the second end of the second connection trace, and the fourth via hole of the second insulating layer at least partially exposes the second cushion layer.

[0028] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a third cushion layer and a fourth cushion layer. Wherein, the third cushion layer at least partially overlaps with the fifth via hole of the second insulating layer to be electrically connected to the first end of the first connection trace. The seventh via hole of the third insulating layer at least partially exposes the third cushion layer. The fourth cushion layer at least partially overlaps with the third via hole of the second insulating layer and is electrically connected to the second end of the first connection trace. The ninth via hole of the third insulating layer at least partially exposes the fourth cushion layer.

[0029] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a pixel defining layer disposed on the first electrode of the plurality of light-emitting devices and on the side of the third insulating layer away from the substrate. Wherein, the pixel defining layer includes a plurality of first pixel openings. The plurality of first pixel openings correspond to the plurality of light-emitting devices one by one to form the light-emitting regions of the plurality of light-emitting devices. The plurality of light-emitting devices further include a first light-emitting layer and a second electrode. The second electrode is located on the side of the pixel defining layer away from the substrate, and the first light-emitting layer is located in the first pixel opening and between the first electrode and the second electrode.

[0030] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a first virtual trace and a second virtual trace located in the first display area, wherein the first virtual trace is connected to the second end of the first connection trace, and the second virtual trace is connected to the second end of the second connection trace. The first virtual trace and the first connection trace are disposed on the same layer and integrally formed, and the second virtual trace and the second connection trace are disposed on the same layer and integrally formed. The extending direction of the first virtual trace intersects with the extending direction of the first connection trace, and the extending direction of the second virtual trace intersects with the extending direction of the second connection trace.

[0031] At least one embodiment of the present disclosure further provides a display device, which includes any one of the above-mentioned display substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0033] Figure 1A A schematic plan view of a display substrate;

[0034] Figure 1B Along Figure 1A A schematic cross-sectional view taken along the center line B-B';

[0035] Figure 1C A partially enlarged schematic view of a display substrate;

[0036] Figure 2A A schematic plan view of the trace arrangement in the display area of a display substrate;

[0037] Figure 2B A partially enlarged schematic view of the peripheral display area of a display substrate;

[0038] Figure 2C A partially enlarged schematic view of the light-transmitting display area of a display substrate;

[0039] Figure 3A Along Figure 2A A schematic cross-sectional view taken along the center line B1-B2;

[0040] Figure 3B Along Figure 2B A schematic cross-sectional view taken along the center line B3-B4;

[0041] Figure 4A A schematic plan view of a display substrate provided by at least one embodiment of the present disclosure;

[0042] Figure 4BA schematic plan view of the wiring layout in the display area of a display substrate provided by at least one embodiment of the present disclosure;

[0043] Figure 5A A cross-sectional view of a display substrate provided by at least one embodiment of the present disclosure along Figure 4B the center lines B5 - B6 and the line B7 - B8;

[0044] Figure 5B A cross-sectional view of a display substrate provided by at least another embodiment of the present disclosure along Figure 4B the center lines B5 - B6 and the line B7 - B8;

[0045] Figure 6A A cross-sectional view of a display substrate provided by at least yet another embodiment of the present disclosure along Figure 4B the center lines B5 - B6 and the line B7 - B8;

[0046] Figure 6B A cross-sectional view of a display substrate provided by at least yet another embodiment of the present disclosure along Figure 4B the center lines B5 - B6 and the line B7 - B8;

[0047] Figure 7 A partially enlarged schematic view of the second display area of a display substrate provided by at least one embodiment of the present disclosure;

[0048] Figures 8A - 8M A process diagram of the manufacturing method of the Figure 5A display substrate shown provided by some embodiments of the present disclosure;

[0049] Figures 9A - 9F A process diagram of the manufacturing method of the Figure 5B display substrate shown provided by some embodiments of the present disclosure;

[0050] Figures 10A - 10H A process diagram of the manufacturing method of the Figure 6A display substrate shown provided by some embodiments of the present disclosure; and

[0051] Figure 11 A schematic diagram of a display device provided by at least one embodiment of the present disclosure. Detailed Description of the Embodiments

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0053] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate a quantitative limitation, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents. For the convenience of description, in some drawings, "up", "down", "front" and "back" are given. In the embodiment of the present disclosure, the vertical direction is the direction from top to bottom, the vertical direction is the direction of gravity, the horizontal direction is the direction perpendicular to the vertical direction, and the horizontal direction from right to left is the direction from front to back.

[0054] In order to maximize the screen-to-body ratio of mobile display products, technologies such as bangs screen, water drop screen, and in-screen hole have emerged one after another. This type of technology can be used to install sensors (such as image sensors, infrared sensors, distance sensors) and other components by partially digging holes in the display area. This part of the display area is designed as a light-transmitting display area, and a camera is placed under it to reduce the screen-to-body ratio problem caused by the camera occupying the frame. As a result, the light-transmitting display area can facilitate the installation of components such as sensors while realizing the display function, so that these sensors can perform functions such as imaging, infrared sensing, distance sensing, etc. through the light-transmitting display area without basically affecting the display function of the light-transmitting display area, thereby helping to realize electronic devices with full screens.

[0055] For example, Figure 1A A schematic plan view of a display substrate; Figure 1B For along Figure 1A Schematic diagram of the cross section along the midline B-B'; Figure 1C It is a partially enlarged schematic diagram of a display substrate.

[0056] like Figure 1A As shown, the display substrate 1 includes a base substrate 14. The base substrate 14 includes a display area and a peripheral area 40 surrounding the display area. The display area includes a light-transmitting display area 10, a peripheral display area 20 and a main display area 30 (e.g., a normal display area) in parallel. The peripheral display area 20 surrounds (e.g., at least partially surrounds) the light-transmitting display area 10. Figure 1A In the embodiment, the light-transmitting display area 10, the peripheral display area 20 and the main display area 30 form a rectangular or approximately rectangular display area as a whole to display a complete (rectangular) picture.

[0057] For example, Figure 1BAs shown, the light-transmissive display area 10 allows incident light from the display side S1 of the display substrate 1 to pass through this area and reach the non-display side S2 of the display substrate 1. A sensor 192 may also be disposed on the non-display side S2 of the display substrate 1 to receive the transmitted light, thereby implementing corresponding functions (such as imaging, infrared sensing, distance sensing, etc.). The sensor 192 is disposed (by means of double-sided tape or the like) on the non-display side S2 of the display substrate 1. The orthographic projection of the sensor 192 on the substrate 14 at least partially overlaps with the light-transmissive display area 10 and is configured to receive and process light from the display side S1 of the display substrate 1. Thus, while the light-transmissive display area 10 realizes display, it also provides convenience for the setting of the sensor 192.

[0058] The sensor 192 is an image sensor, an infrared sensor, a distance sensor, etc. The sensor 192 may be implemented in the form of a chip, for example. The sensor 192 is disposed on the non-display side S2 of the display substrate.

[0059] As Figure 1C As shown, the light-transmissive display area 10 includes a plurality of light-emitting devices 11 arranged in an array (the white squares in the light-transmissive display area 10). The peripheral display area 20 includes a plurality of pixel circuit units D arranged in an array (the gray squares in the peripheral display area 20). The peripheral display area 20 further includes a plurality of pixel units P arranged in an array. The pixel units P and the pixel circuit units D are alternately arranged. The main display area 30 surrounds the peripheral display area 20. The main display area 30 includes a plurality of pixel units C arranged in an array (the white squares in the main display area 30).

[0060] The pixel circuit units D in the peripheral display area 20 are used to drive the plurality of light-emitting devices 11 in the light-transmissive display area 10 one by one respectively. That is, the pixel circuits for the light-transmissive display area 10 are disposed in the peripheral display area 20, such that the pixel circuits and the light-emitting devices of each sub-pixel unit are separated from each other in position. Incident light from the display side S1 can pass through the blank areas between adjacent light-emitting devices 11 to ensure the light transmissivity of the light-transmissive display area 10. The light-emitting devices and the pixel circuits of the pixel units P in the peripheral display area 20 are located in the same pixel area and are not separated from each other in position. The light-emitting devices and the pixel circuits of the pixel units C in the main display area 30 are located in the same pixel area and are not separated from each other in position. The density of the array arrangement of the second pixel units C in the main display area 30 is greater than the density of the array arrangement of the pixel units P in the peripheral display area 20, and the density of the array arrangement of the pixel units P in the peripheral display area 20 is the same as the arrangement density of the light-emitting devices 11 in the light-transmissive display area 10, such that the light-transmissive display area 10 and the peripheral display area 20 have the same resolution. The resolution of the main display area 30 is greater than that of the light-transmissive display area 10 and the peripheral display area 20.

[0061] Figure 2AIt is a plan view of the wiring arrangement in the display area of a display substrate.

[0062] As Figure 2A shown, the multiple light-emitting devices 11 in the light-transmitting display area 10 include a first light-emitting device 114 and a second light-emitting device 115. Correspondingly, the multiple pixel circuit units D in the peripheral display area 20 include a first pixel circuit D10 and a second pixel circuit D20, which are respectively used to receive drive signals to drive the first light-emitting device 114 and the second light-emitting device 115 to emit light. The first light-emitting device 114 and the first pixel circuit D10 are correspondingly connected in the first direction X0, thereby functionally forming a sub-pixel in the light-transmitting display area 10. The second light-emitting device 115 and the second pixel circuit D20 are correspondingly connected in the first direction X0, thereby functionally forming a sub-pixel in the light-transmitting display area 10.

[0063] The display substrate 1000 further includes multiple first connection traces 101 ( Figure 2A the traces with darker color and larger line width in Figure 2A ) and multiple second connection traces 102 (

[0064] the traces with lighter color and smaller line width in

[0065] ) The multiple first connection traces 101 and the multiple second connection traces 102 generally extend along the first direction X0. The multiple first connection traces 101 and the multiple second connection traces 102 are arranged in parallel side by side in the first direction X0, and the orthographic projections of the multiple first connection traces 101 and the multiple second connection traces 102 on the substrate 14 do not cross to avoid signal crosstalk between them. The multiple first connection traces 101 and the multiple second connection traces 102 connect the pixel circuits in the peripheral display area 20 and the light-emitting devices in the light-transmitting display area 10. The multiple first connection traces 101 are electrically connected to the multiple first pixel circuits D10 and the multiple first light-emitting devices 114 in one-to-one correspondence. The multiple second connection traces 102 are connected to the multiple second pixel circuits D20 and the multiple second light-emitting devices 115 in one-to-one correspondence, and the second pixel circuit D20 is configured to drive the second light-emitting device 115 to emit light through the second connection trace 102. Figure 2AThe routing patterns of the first connection trace 101 and the second connection trace 102 shown are only examples. The first connection trace 101 and the second connection trace 102 can also both be straight traces, that is, shapes without chamfers.

[0066] Figure 3A is a cross-sectional view along Figure 2A the center line B1 - B2; Figure 3B is a cross-sectional view along Figure 2B the center line B3 - B4.

[0067] As shown in Figure 3A and 3B, the display substrate 1 further includes a first planarization layer 144, a second planarization layer 145, a third planarization layer 146, a first trace layer 151, and a second trace layer 152.

[0068] The first planarization layer 144 is located on the side of the first pixel circuit D10 ( Figure 3A shown) and the second pixel circuit D20 ( Figure 3B shown) away from the substrate 14 to provide a planarized surface. The second planarization layer 145 is located on the side of the first planarization layer 144 away from the substrate 14 to provide a planarized surface. The third planarization layer 146 is located on the side of the second planarization layer 145 away from the substrate 14 to provide a planarized surface. The first trace layer 151 is located between the first planarization layer 144 and the second planarization layer 145 ( Figure 3A shown). The second trace layer 152 is located on the side of the second planarization layer 145 away from the substrate 14 ( Figure 3B shown). The first light-emitting device 114 or the second light-emitting device 115 is located on the side of the third planarization layer 146 away from the substrate 14. The first electrode 111 (anode) of the first light-emitting device 114 or the second light-emitting device 115 is located on the side of the third planarization layer 146 away from the substrate 14.

[0069] For example, the materials of the first trace layer 151 and the second trace layer 152 can include transparent conductive materials, such as transparent metal oxides like indium tin oxide (ITO), indium zinc oxide (IZO), etc. The materials of the metal trace layer can include metal materials or their alloy materials such as silver (Ag), aluminum (Al), molybdenum (Mo), or titanium (Ti).

[0070] As shown in Figure 3A and Figure 3B shown, the first connection trace 101 is located in the first trace layer 151. The second connection trace 102 is located in the second trace layer 152. The first connection trace 101 and the second connection trace 102 are located in different film layers respectively to reduce crosstalk between signals.

[0071] As shown in Figure 3A andFigure 3B As shown, the display substrate 1 further includes a first pixel circuit connection hole DH11 and a second pixel circuit connection hole DH12. As Figure 3A shown, the first pixel circuit connection hole DH11 penetrates through the first planarization layer 144. The first connection trace 101 located in the first trace layer 151 is electrically connected to the first pixel circuit D10 through the first pixel circuit connection hole DH11. As Figure 3B shown, the second pixel circuit connection hole DH12 penetrates through the first planarization layer 144 and the second planarization layer 145. The second connection trace 102 located in the second trace layer 152 is electrically connected to the second pixel circuit D20 through the second pixel circuit connection hole DH12.

[0072] As Figure 3A and Figure 3B shown, the display substrate 1 further includes a first electrode connection hole PH11 and a second electrode connection hole PH12. As Figure 3A shown, the first electrode connection hole PH11 penetrates through the second planarization layer 145 and the third planarization layer 146. The first connection trace 101 located in the first trace layer 151 is electrically connected to the first electrode 111 of the first light-emitting device 114 through the first electrode connection hole PH11. As Figure 3B shown, the second electrode connection hole PH12 penetrates through the third planarization layer 146. The second connection trace 102 located in the second trace layer 152 is electrically connected to the first electrode 111 of the second light-emitting device 115 through the second electrode connection hole PH12.

[0073] As Figure 3A and Figure 3B shown, the display substrate 1 further includes a pixel defining layer 147. The pixel defining layer 147 is located on the side of the first electrodes 111 of the first light-emitting device 114 and the second light-emitting device 115 away from the substrate 14, and includes a plurality of first pixel openings 147A. The plurality of first pixel openings 147A correspond one-to-one to the first light-emitting device 114 and the second light-emitting device 115 to form the light-emitting regions 116 of the first light-emitting device 114 and the second light-emitting device 115. Each of the plurality of light-emitting devices 11 further includes a first light-emitting layer 112 and a second electrode 113 (for example, a cathode). The second electrode 113 is located on the side of the pixel defining layer 147 away from the substrate 14. The light-emitting layer 112 is located in the first pixel opening 147A and between the first electrode 111 and the second electrode 113; the portion of the light-emitting layer 112 directly sandwiched between the first electrode 111 and the second electrode 113 will emit light after being powered on, and thus the region occupied by this portion corresponds to the above-mentioned light-emitting region 116.

[0074] The display substrate 1 further includes a first gate insulating layer 0141, a second gate insulating layer 142, an interlayer insulating layer 143, and a packaging layer 148. Both the first pixel circuit D10 and the second pixel circuit D20 include a thin-film transistor 12 and a storage capacitor 13. The thin-film transistor 12 includes an active layer 121, a gate 122, and source-drain electrodes (a source electrode 123 and a drain electrode 124). The storage capacitor 13 includes a first capacitor plate 131 and a second capacitor plate 132. The active layer 121 is disposed on the substrate 14, the first gate insulating layer 0141 is disposed on a side of the active layer 121 away from the substrate 14, the gate 122 and the first capacitor plate 131 are disposed on the same layer on a side of the first gate insulating layer 0141 away from the substrate 14, and the second gate insulating layer 142 is disposed on a side of the gate 122 and the first capacitor plate away from the substrate 14. The second capacitor plate 132 is disposed on a side of the second gate insulating layer 142 away from the substrate 14, and the interlayer insulating layer 143 is disposed on a side of the second capacitor plate 132 away from the substrate 14. The source electrode 123 and the drain electrode 124 are disposed on a side of the interlayer insulating layer 143 away from the substrate 14 and are electrically connected to the active layer 121 through vias in the first gate insulating layer 0141, the second gate insulating layer 142, and the interlayer insulating layer 143. The first wiring layer 151 is electrically connected to one of the source-drain electrodes through a first pixel circuit connection via DH11 in the first planarization layer 144 (electrically connected to the drain electrode 124 as shown in Figure 3A ). The second wiring layer 152 is electrically connected to one of the source-drain electrodes through a second pixel circuit connection via DH12 in the first planarization layer 144 and the second planarization layer 145 (electrically connected to the drain electrode 124 as shown in Figure 3B ). The packaging layer 148 is located on a side of the second electrode 113 away from the substrate 140. The packaging layer 148 seals the first light-emitting device 114 and the second light-emitting device 115, thereby reducing or preventing deterioration of the light-emitting device 11 caused by moisture and / or oxygen included in the environment.

[0075] It should be noted that the first pixel circuit D10 and the second pixel circuit D20 can be 2T1C (i.e., 2 transistors and 1 capacitor) type pixel circuits. The two transistors are respectively a data writing transistor and a driving transistor, and the one capacitor is a signal storage capacitor. The pixel circuit can generate a driving current for driving the light-emitting element to emit light according to the received scan signal and data signal. The light-emitting element generates lights of different intensities according to the magnitude of the driving current. For example, the pixel circuit can also be other types of pixel circuits. For example, it can further have functions such as compensation, reset, and sensing, and thus can include more than 2 thin-film transistors.

[0076] Such as Figure 3A and Figure 3BAs shown, when the first connection trace 101 is located between the first planarization layer 144 and the second planarization layer 145, and the second connection trace 102 is located between the second planarization layer 145 and the third planarization layer 146, the first trace layer 151 where the first connection trace 101 is located needs to be formed by patterning with a photomask to form a connection for the first pixel circuit D10 and the first light-emitting device 114. The second planarization layer 145 needs to be formed by patterning with a photomask to form the second pixel circuit connection hole DH12 and the part of the first electrode connection hole PH11 in the second planarization layer 145. The second trace layer 152 where the second connection trace 102 is located needs to be formed by patterning with a photomask to form a connection for the second pixel circuit D20 and the second light-emitting device 115. The third planarization layer 146 needs to be formed by patterning with a photomask to form the second electrode connection hole PH12 and the first electrode connection hole PH11. Therefore, a total of 4 photomasks are required to complete the preparation of the first connection trace 101, the second planarization layer 145, the second trace layer 152, and the second connection trace 102, resulting in a relatively high cost.

[0077] Figure 2B is a partial enlarged schematic view of the peripheral display area of a display substrate; Figure 2C is a partial enlarged schematic view of the transmissive display area of a display substrate.

[0078] As Figure 2B and Figure 2C shown, the first connection trace 101 connects the first pixel circuit connection hole DH11 in the peripheral display area and the first electrode connection hole PH11 in the transmissive display area, and the second connection trace 102 connects the second pixel circuit connection hole DH12 in the peripheral display area and the second electrode connection hole PH12 in the transmissive display area. In the peripheral display area, the first pixel circuit connection hole DH11 and the second pixel circuit connection hole DH12 are separated by the pixel unit P in the peripheral display area, such that the distribution of the first connection trace 101 and the second connection trace 102 is non-uniform, which may cause phenomena such as etching patterns.

[0079] At least one embodiment of the present disclosure provides a display substrate, which has a first side for display and a second side opposite to the first side, and includes a substrate, a first insulating layer disposed on the substrate, a first connection trace located in a first display area and a second display area, a second insulating layer disposed on a side of the first insulating layer away from the substrate, a second connection trace located in the first display area and the second display area, and a third insulating layer disposed on a side of the second insulating layer away from the substrate. The substrate includes a display area, the display area includes a first display area and a second display area at least partially surrounding the first display area, the first display area includes a first sub-pixel array, and the first display area allows light from the first side of the display substrate to at least partially transmit to the second side of the display substrate. The first sub-pixel array includes a plurality of light-emitting devices arranged in an array, the plurality of light-emitting devices includes a first light-emitting device and a second light-emitting device, the second display area includes a first pixel driving circuit array, the first pixel driving circuit array includes a plurality of first pixel driving circuit units, and the plurality of first pixel driving circuit units includes a first pixel driving circuit and a second pixel driving circuit. The first insulating layer includes a first via and a second via, and the first via and the second via expose the first pixel driving circuit and the second pixel driving circuit respectively. The first connection trace is located on a side of the first insulating layer away from the substrate, a first end of the first connection trace is formed to be connected to the first pixel driving circuit through the first via, and a second end of the first connection trace is connected to the first light-emitting device. The second insulating layer includes a plurality of vias, and the plurality of vias of the second insulating layer are formed for connecting the first light-emitting device, the second light-emitting device, the first pixel driving circuit, and the second pixel driving circuit. The second connection trace is located on a side of the second insulating layer away from the substrate, a first end of the second connection trace is formed to be connected to the second pixel driving circuit through the second via and the via in the second insulating layer for connecting the second pixel driving circuit, and a second end of the second connection trace is connected to the second light-emitting device. The third insulating layer includes a plurality of vias, the plurality of vias of the third insulating layer correspond to the plurality of vias of the second insulating layer one by one to form a plurality of vias penetrating through the second insulating layer and the third insulating layer, and the third insulating layer and the second insulating layer have substantially the same planar pattern.

[0080] In the display substrate of the above embodiment, the third insulating layer and the second insulating layer have substantially the same planar pattern. Therefore, the third insulating layer and the second insulating layer can be formed by using the same mask for the patterning process to reduce the manufacturing cost.

[0081] At least one embodiment of the present disclosure further provides a display device including the above display substrate.

[0082] The embodiments and examples of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0083] For example,Figure 4A A schematic plan view of a display substrate provided by at least one embodiment of the present disclosure. Figure 4A As shown, the display substrate 1000 provided by at least one embodiment of the present disclosure includes a base substrate 140. The base substrate 140 includes a display area, which includes a first display area 100 (e.g., a light-transmitting display area), a second display area 200 (e.g., a low-resolution display area), and a third display area 300 (e.g., a normal display area). The second display area 200 surrounds (e.g., at least partially surrounds) the first display area 100. Figure 1A In the embodiment, the first display area 100, the second display area 200 and the third display area 300 form a rectangular or approximately rectangular display area as a whole to display a complete (rectangular) screen. For example, the display substrate 1000 may further include a peripheral area 400 surrounding the display area. For example, the first display area 100 allows incident light from the display side (e.g., the side facing the user) of the display substrate 1000 to be transmitted through the area to reach the non-display side (e.g., the side facing away from the user) of the display substrate 1000.

[0084] For example, the display substrate 1000 may be an organic light emitting diode (OLED) display substrate or a quantum dot light emitting diode (QLED) display substrate, etc. The embodiments of the present disclosure do not limit the specific type of the display substrate.

[0085] For example, a sensor (such as a Figure 1B The sensor 192 shown in the figure receives the transmitted light, thereby realizing corresponding functions (such as imaging, infrared sensing, distance sensing, etc.). The sensor is arranged on the non-display side of the display substrate 1000 (by means of double-sided adhesive tape, etc.), and the sensor can be located (or partially located) in the first display area 100. Thus, the first display area 100 facilitates the arrangement of the sensor while realizing the display. For example, the sensor is an image sensor, an infrared sensor, a distance sensor, etc., and the sensor can be realized in the form of a chip, etc.

[0086] For example, Figure 4B As shown, the first display area 100 includes a first sub-pixel array, and the first sub-pixel array includes a plurality of light-emitting devices arranged in an array (which may be Figure 1C The second display area 200 includes a first pixel driving circuit array, and the first pixel driving circuit array includes a plurality of first pixel driving circuit units (which can be used as Figure 1C(the arrangement of the pixel units D in the peripheral display area 20), the multiple first pixel driving circuit units include a first pixel driving circuit D100 and a second pixel driving circuit D200. The multiple first pixel driving circuit units in the second display area 200 are configured to respectively drive the multiple light-emitting devices in the first display area 100 in a one-to-one correspondence. That is, the pixel driving circuits for the first display area 100 are arranged in the second display area 200, so that the pixel driving circuits and the light-emitting devices of the first sub-pixels are separated from each other in position. The incident light from the display side of the display substrate 1000 can be transmitted through the blank area between adjacent light-emitting devices to ensure the light transmissibility of the first display area 100.

[0087] For example, as Figure 4B shown, the first pixel driving circuit D100, the second pixel driving circuit D200, the first light-emitting device 1140, and the second light-emitting device 1150 are located in one row (for example Figure 4B one of the two rows in). The first light-emitting device 1140 is correspondingly connected to the first pixel driving circuit D100 in the first direction X1, thereby functionally forming a sub-pixel in the first display area 100. The second light-emitting device 1150 is correspondingly connected to the second pixel driving circuit D200 in the first direction X1, thereby functionally forming a sub-pixel in the first display area 100.

[0088] For example, as Figure 4B shown, the display substrate 1000 further includes a first connection trace 1010 located in the first display area 100 and the second display area 200 ( Figure 4A the trace with a darker color and a larger line width in), and a second connection trace 1020 located in the first display area 100 and the second display area 200 ( Figure 4AThe traces with lighter color and smaller line width). The first connection trace 1010 and the second connection trace 1020 generally extend along the first direction X1. The first connection trace 1010 and the first connection trace 1010 are arranged side by side and parallel in the first direction X1. The orthographic projections of the first connection trace 1010 and the second connection trace 1020 on the substrate 140 do not cross to avoid signal crosstalk between each other. For example, the first connection trace 1010 is electrically connected to the first pixel driving circuit D100 and the first light-emitting device 1140. The first pixel driving circuit D100 is configured to drive the first light-emitting device 1140 to emit light through the first connection trace 1010. That is, the first connection trace 1010 electrically connects the first pixel driving circuit D100 and the first light-emitting device 1140 located in the same row. The second connection trace 1020 is electrically connected to the second pixel driving circuit D200 and the second light-emitting device 1150. The second pixel driving circuit D200 is configured to drive the second light-emitting device 1150 to emit light through the second connection trace 1020. That is, the second connection trace 1020 electrically connects the second pixel driving circuit D200 and the second light-emitting device 1150 located in the same row.

[0089] It should be noted that Figure 4B The trace forms of the first connection trace 1010 and the second connection trace 102 shown are only taken as an example, and the embodiments of the present disclosure are not limited thereto. The first connection trace 1010 and the second connection trace 1020 can also both be straight traces, that is, shapes without chamfers.

[0090] For example, the first connection trace 1010 and the second connection trace 1020 are transparent conductive traces.

[0091] For example, the materials of the first connection trace 1010 and the second connection trace 1020 can include transparent conductive materials, such as transparent metal oxides like indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0092] Figure 5A A cross-sectional schematic diagram of a display substrate provided by at least one embodiment of the present disclosure along Figure 4B the center lines B5 - B6 and B7 - B8. The line B5 - B6 is along the first connection trace 1010 and passes through the first light-emitting device 1140 located in the first display area 100 and the first pixel driving circuit D100 located in the second display area 200. The line B7 - B8 is along the second connection trace 1020 and passes through the second light-emitting device 1150 located in the first display area 100 and the second pixel driving circuit D200 located in the second display area 200.

[0093] For example, as Figure 5AAs shown, the display substrate 1000 further includes a first insulating layer 1440 (i.e., the first planarization layer), a second insulating layer 1450 (i.e., the second planarization layer), a third insulating layer 1460 (i.e., the third planarization layer), a first wiring layer 1510, and a second wiring layer 1520. The first insulating layer 1440 is disposed on a side of the first pixel driving circuit D100 and the second pixel driving circuit D200 away from the substrate 140 to provide a planarized surface. The second insulating layer 1450 is located on a side of the first insulating layer 1440 away from the substrate 140 to provide a planarized surface, and the third insulating layer 1460 is located on a side of the second insulating layer 1450 away from the substrate 140 to provide a planarized surface. The first wiring layer 1510 is located between the first insulating layer 1440 and the second insulating layer 1450. The second wiring layer 1520 is located between the second insulating layer 1450 and the third insulating layer 1460. The first light-emitting device 1140 and the second light-emitting device 1150 are located on a side of the third insulating layer 1460 away from the substrate 140.

[0094] For example, the materials of the first insulating layer 1440, the second insulating layer 1450, and the third insulating layer 1460 include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and may also include organic insulating materials such as polyimide, polyphthalimide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of the present disclosure do not limit this.

[0095] For example, as Figure 5A shown, the first insulating layer 1440 includes a first via hole GH1 and a second via hole GH2. The first via hole GH1 exposes the first pixel driving circuit D100 for electrical connection between the first connection trace 1010 and the first pixel driving circuit D100, and the second via hole GH2 exposes the second pixel driving circuit D200 for electrical connection between the second connection trace 1020 and the second pixel driving circuit D200.

[0096] The first connection trace 1010 is located in the first wiring layer 1510, that is, on a side of the first insulating layer 1440 away from the substrate 140. The first end 1011 of the first connection trace 1010 is formed to be electrically connected to the first pixel driving circuit D100 through the first via hole GH1, and the second end 1012 of the first connection trace 1010 is electrically connected to the first light-emitting device 1140. Thus, the first pixel driving circuit D100 drives the first light-emitting device 1140 to emit light through the first connection trace 1010.

[0097] The second insulating layer 1450 includes a plurality of vias (for example, including a third via GH3, a fourth via GH4, a fifth via GH5, and a sixth via GH6). The plurality of vias in the second insulating layer 1450 are formed for electrically connecting a first light-emitting device 1140 (for example, connected to the third via GH3), a second light-emitting device 1150 (for example, connected to the fourth via GH4), a first pixel driving circuit D100 (for example, connected to the fifth via GH5), and a second pixel driving circuit D200 (for example, connected to the sixth via GH6).

[0098] The second connection trace 1020 is located in the second trace layer 1520, that is, on the side of the second insulating layer 1450 away from the substrate 140. The first end 1021 of the second connection trace 1020 is formed to be electrically connected to the second pixel driving circuit D200 through the second via GH2 and the via in the second insulating layer 1450 for connecting the second pixel driving circuit D200 (for example, connected to the sixth via GH6). The second end 1022 of the second connection trace 1020 is electrically connected to the second light-emitting device 1150. The first connection trace 1010 and the second connection trace 1020 are located in different film layers to reduce the wiring space.

[0099] The third insulating layer 1460 includes a plurality of vias (for example, including a seventh via GH7, an eighth via GH8, a ninth via GH9, and a tenth via GH10). The plurality of vias in the third insulating layer 1460 correspond one-to-one in position to the plurality of vias in the second insulating layer 1450 (for example, the ninth via GH9 overlaps with the projection of the third via GH3 on the substrate 140, the seventh via GH7 overlaps with the projection of the fifth via GH5 on the substrate 140, the eighth via GH8 overlaps with the projection of the sixth via GH6 on the substrate 140, and the tenth via GH10 overlaps with the projection of the fourth via GH4 on the substrate 140.), so as to form a plurality of vias penetrating through the second insulating layer 1450 and the third insulating layer 1460. The second insulating layer 1450 and the third insulating layer 1460 have substantially the same planar pattern, so that the second insulating layer 1450 and the third insulating layer 1460 can be formed by using the same mask for the patterning process to reduce the manufacturing cost.

[0100] It should be noted that the "projection overlap" in the embodiments of the present disclosure includes the case of partial overlap of projections.

[0101] For example, as Figure 5A shown, each of the plurality of light-emitting devices located in the first display area 100 includes a first electrode (for example, an anode). The first light-emitting device 1140 (located in the Figure 5A left figure in) includes a first electrode 1141, and the second light-emitting device 1150 (located in the Figure 5AThe figure on the right in ) includes a first electrode 1151. The first electrode 1141 of the first light-emitting device 1140 is connected to the second end 1012 of the first connection trace 1010 through vias in the second insulating layer 1450 and the third insulating layer 1460 (for example, through the ninth via GH9 and the third via GH3). The first electrode 1151 of the second light-emitting device 1150 is connected to the second end 1022 of the second connection trace 1020 through a via in the third insulating layer 1460 (for example, the tenth via GH10). The first electrodes 1141 of the first light-emitting device 1140 and the first electrode 1151 of the second light-emitting device 1150 are arranged on the same layer and have the same material.

[0102] It should be noted that, in the embodiments of the present disclosure, "arranged on the same layer" includes that two functional layers or structural layers are formed on the same layer and with the same material in the hierarchical structure of the display substrate. That is, in the manufacturing process, these two functional layers or structural layers can be formed from the same material layer, and the required patterns and structures can be formed through the same patterning process. A patterning process, for example, includes processes such as the formation of photoresist, exposure, development, and etching.

[0103] For example, the material of the first electrode 1141 of the first light-emitting device 1140 and the first electrode 1151 of the second light-emitting device 1150 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In addition, the first electrodes 1141 of the first light-emitting device 1140 and the first electrode 1151 of the second light-emitting device 1150 may include a metal with a high reflectivity as a reflective layer, such as silver (Ag).

[0104] For example, as Figure 5AAs shown, the multiple vias of the second insulating layer 1450 include a third via GH3, a fourth via GH4, a fifth via GH5, and a sixth via GH6. The third via GH3 and the fourth via GH4 are located in the first display area 100. The fifth via GH5 and the sixth via GH6 are located in the second display area 200. The third via GH3 exposes the second end 1012 of the first connection trace 1010 for connecting the first electrode 1141 of the first light-emitting device 1140 and the first connection trace 1010. The orthographic projection of the fourth via GH4 on the substrate 140 overlaps with the orthographic projection of the second end 1022 of the second connection trace 1020 on the substrate 140 for connecting the first electrode 1151 of the second light-emitting device 1150 and the second connection trace 1020. The orthographic projection of the fifth via GH5 on the substrate 140 overlaps with the first via GH1 of the first insulating layer 1440, and the fifth via GH5 exposes the first end 1011 of the first connection trace 1010. The orthographic projection of the sixth via GH7 on the substrate 140 overlaps with the second via GH2 of the first insulating layer 1440 for electrically connecting the second pixel driving circuit D200 through the second connection trace 1020.

[0105] For example, as Figure 5A shown, the first end 1021 of the second connection trace 1020 is electrically connected to the second pixel driving circuit D200 through the second via GH2 of the first insulating layer 1440 and the sixth via GH6 in the second insulating layer 1450. The second end 1022 of the second connection trace 1020 covers the fourth via GH4 in the second insulating layer 1450 and is used to connect (e.g., through the tenth via GH10 in the third insulating layer 1460) the second light-emitting device 1150. Thus, the second pixel driving circuit D200 is configured to drive the second light-emitting device 1150 to emit light through the second connection trace 1020.

[0106] For example, as Figure 5AAs shown, the vias in the third insulating layer 1460 include a seventh via GH7, an eighth via GH8, a ninth via GH9, and a tenth via GH10. The seventh via GH7 and the eighth via GH8 are located in the second display area 200. The ninth via GH9 and the tenth via GH10 are located in the first display area 100. The orthographic projection of the ninth via GH9 on the substrate 140 overlaps with the orthographic projection of the third via GH3 in the second insulating layer 1450 on the substrate 140, and the ninth via GH9 exposes the second end 1012 of the first connection trace 1010 to allow the second end 1012 of the first connection trace 1010 to be electrically connected to the first electrode 1141 of the first light-emitting device 1140. The orthographic projection of the tenth via GH10 on the substrate 140 overlaps with the orthographic projection of the fourth via GH4 in the second insulating layer 1450 on the substrate 140, and the tenth via GH10 exposes the second end 1022 of the second connection trace 1020 to allow the second end 1022 of the second connection trace 1020 to be connected to the first electrode 1151 of the second light-emitting device 1150. The orthographic projection of the seventh via GH7 on the substrate 140 overlaps with the orthographic projection of the first via GH1 in the first insulating layer 1440 and the orthographic projection of the fifth via GH5 in the second insulating layer 1450 on the substrate 140, and the seventh via GH7 (and the fifth via GH5) exposes the first end 1011 of the first connection trace 1010. The orthographic projection of the eighth via GH8 on the substrate 140 overlaps with the orthographic projection of the second via GH2 in the first insulating layer 1440 and the orthographic projection of the sixth via GH6 in the second insulating layer 1450 on the substrate 140, and the eighth via GH8 exposes the first end 1021 of the second connection trace 1020.

[0107] For example, as Figure 5A shown, the orthographic projection of the ninth via GH9 in the second insulating layer 1450 on the substrate 140 overlaps with the orthographic projection of the third via GH3 in the first insulating layer 1440 on the substrate 140, the orthographic projection of the seventh via GH7 in the second insulating layer 1450 on the substrate 140 overlaps with the orthographic projection of the fifth via GH5 in the first insulating layer 1440 on the substrate 140, the orthographic projection of the eighth via GH8 in the second insulating layer 1450 on the substrate 140 overlaps with the orthographic projection of the sixth via GH6 in the first insulating layer 1440 on the substrate 140, and the orthographic projection of the tenth via GH10 in the second insulating layer 1450 on the substrate 140 overlaps with the orthographic projection of the fourth via GH4 in the first insulating layer 1440 on the substrate 140, thereby forming nested vias between the second insulating layer 1450 and the first insulating layer 1440, enabling the second insulating layer 1450 and the first insulating layer 1440 to be formed by a patterning process using the same mask to reduce the manufacturing cost.

[0108] For example, as Figure 5AAs shown, the first electrode 1141 of the first light-emitting device 1140 is connected to the second end 1012 of the first connection trace 1010 through the third via hole GH3 of the second insulating layer 1450 and the ninth via hole GH9 of the third insulating layer 1460. The first electrode 1151 of the second light-emitting device 1150 is connected to the second end 1022 of the second connection trace 1020 through the tenth via hole GH10 of the third insulating layer 1460.

[0109] For example, as Figure 5A shown, the first light-emitting device 1140 further includes a first protective layer 1154, and the second light-emitting device 1150 further includes a second protective layer 1155. The first protective layer 1154 covers the seventh via hole GH7 of the third insulating layer 1460, and the second protective layer 1155 covers the eighth via hole GH8 of the third insulating layer 1460. The first protective layer 1154 further covers the surface of the first end 1011 of the first connection trace 1010 on the side away from the substrate 140, and the second protective layer 1155 further covers the surface of the first end 1021 of the second connection trace 1020 on the side away from the substrate 140, thereby protecting the first connection trace 1010 and the second connection trace 1020 from being damaged in subsequent manufacturing processes, such as corrosion by etching solution.

[0110] For example, as Figure 5A shown, the display substrate 1000 further includes a pixel defining layer 1470 disposed on the side of the first electrode 1141 of the first light-emitting device 1140, the first electrode 1151 of the second light-emitting device 1150, and the third insulating layer 1460 away from the substrate 140. The pixel defining layer 1470 includes a plurality of first pixel openings 1471. The plurality of first pixel openings 1471 correspond to the first light-emitting device 1140 and the second light-emitting device 1150 one by one to form a light-emitting region 1160 of the first light-emitting device 1140 and a light-emitting region 2160 of the second light-emitting device 1150. The first light-emitting device 1140 further includes a first light-emitting layer 1142 and a second electrode 1143 (e.g., a cathode) (shown in the left figure in Figure 5A ), and the second light-emitting device 1150 further includes a first light-emitting layer 1152 and a second electrode 1153 (e.g., a cathode) (shown in the left figure in Figure 5A(the figure on the right side in the middle). The second electrode 1143 of the first light-emitting device 1140 and the second electrode 1153 of the second light-emitting device 1150 are located on the side of the pixel defining layer 1470 away from the substrate 140. The first light-emitting layer 1142 of the first light-emitting device 1140 is located in the first pixel opening 1471 and between the first electrode 1141 and the second electrode 1143. The first light-emitting layer 1152 of the second light-emitting device 1150 is located in the first pixel opening 1471 and between the first electrode 1151 and the second electrode 1153. The part of the first light-emitting layer 1142 directly sandwiched between the first electrode 1141 and the second electrode 1143 will emit light after being powered on, and thus the area occupied by this part corresponds to the light-emitting area 1160 of the first light-emitting device 1140. The part of the first light-emitting layer 1152 directly sandwiched between the first electrode 1151 and the second electrode 1153 will emit light after being powered on, and thus the area occupied by this part corresponds to the light-emitting area 2160 of the second light-emitting device 1150.

[0111] It should be noted that the second electrode 1143 of the first light-emitting device 1140 and the second electrode 1153 of the second light-emitting device 1150 are arranged in the same layer and have the same material. It is also possible to regard the second electrode 1143 of the first light-emitting device 1140 and the second electrode 1153 of the second light-emitting device 1150 as the same film layer, and Figure 5A in the first light-emitting device 1140, it is regarded as the second electrode 1143, and in the second light-emitting device 1150, it is regarded as the second electrode 1153 for distinction.

[0112] For example, the first light-emitting layer 1142 of the first light-emitting device 1140 and the second light-emitting layer 1152 of the second light-emitting device 1150 are arranged in the same layer and have the same material.

[0113] For example, the material of the pixel defining layer 1470 may include organic insulating materials such as polyimide, polyphthalimide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin, or may include inorganic insulating materials such as silicon oxide and silicon nitride. The embodiments of the present disclosure do not limit this.

[0114] For example, for an OLED, the first light-emitting layer 1142 of the first light-emitting device 1140 and the second light-emitting layer 1152 of the second light-emitting device 1150 may include small molecule organic materials or polymer molecule organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, may emit red light, green light, blue light, or may emit white light; and, according to needs, the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.

[0115] For a QLED, the light-emitting layer may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, indium arsenide quantum dots, etc. The particle size of the quantum dots is 2-20 nm.

[0116] For example, the second electrodes 1143 of the first light-emitting device 1140 and the second electrodes 1153 of the second light-emitting device 1150 may include various conductive materials. For example, the second electrodes 1143 of the first light-emitting device 1140 and the second electrodes 1153 of the second light-emitting device 1150 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc.

[0117] Embodiments of the present disclosure do not limit the pixel driving circuit of the sub-pixel (for example, the first pixel driving circuit D100 and the second pixel driving circuit D200). For example, it may be a 2T1C (i.e., 2 transistors and 1 capacitor) type pixel driving circuit. The two transistors are respectively a data writing transistor and a driving transistor, and the one capacitor is a signal storage capacitor. The pixel circuit may generate a driving current for driving the light-emitting element to emit light according to the received scan signal and data signal. The light-emitting element generates light of different intensities according to the magnitude of the driving current. The pixel driving circuit may also be other types of pixel driving circuits, for example, it may further have functions such as compensation, reset, and sensing, and thus may include more than 2 thin-film transistors.

[0118] For example, as Figure 5AAs shown, the display substrate 1000 further includes a first gate insulating layer 1410, a second gate insulating layer 1420, and an interlayer insulating layer 1430. The first pixel driving circuit D100 includes a thin film transistor 120 and a storage capacitor 130. The thin film transistor 120 includes an active layer 1220, a gate 1210, and source-drain electrodes (source electrode 1230 and drain electrode 1240). The storage capacitor 130 includes a first capacitor plate 1301 and a second capacitor plate 1302. The active layer 1220 is disposed on the substrate 140, the first gate insulating layer 1410 is disposed on a side of the active layer 1220 away from the substrate 140, the gate 1210 and the first capacitor plate 1301 are disposed on the same layer on a side of the first gate insulating layer 1410 away from the substrate 140, and the second gate insulating layer 1420 is disposed on a side of the gate 1210 and the first capacitor plate 1301 away from the substrate 140. The second capacitor plate 1302 is disposed on a side of the second gate insulating layer 1420 away from the substrate 140, and the interlayer insulating layer 1430 is disposed on a side of the second capacitor plate 1320 away from the substrate 140. The source electrode 1230 and the drain electrode 1240 are disposed on a side of the interlayer insulating layer 1430 away from the substrate 140 and are electrically connected to the active layer 1220 through vias in the first gate insulating layer 1410, the second gate insulating layer 1420, and the interlayer insulating layer 1430. The first end 1011 of the first connection trace 1010 is electrically connected to one of the source-drain electrodes through a first via GH1 in the first insulating layer 1440 (as Figure 5A shown in the left figure, electrically connected to the drain electrode 1240).

[0119] For example, the material of one or more of the first gate insulating layer 1410, the second gate insulating layer 1420, and the interlayer insulating layer 1430 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The materials of the first gate insulating layer 1410, the second gate insulating layer 1420, and the interlayer insulating layer 1430 may be the same or different.

[0120] For example, the material of the active layer 1220 may include polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide). The material of the gate 1210 may include a metal material or an alloy material, such as a single-layer or multi-layer metal structure formed by molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)). The materials of the source electrode 1230 and the drain electrode 1240 may include a metal material or an alloy material, such as a single-layer or multi-layer metal structure formed by molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)). The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0121] For example, a passivation layer may also be provided between the first insulating layer 1440 and the source electrode 1230 and the drain electrode 1240. The passivation layer may be provided to include vias to expose one of the source electrode 1230 and the drain electrode 1240, for example, to expose the drain electrode 1240. The passivation layer can protect the source electrode 1230 and the drain electrode 1240 from being corroded by water vapor. For example, the material of the passivation layer may include an organic insulating material or an inorganic insulating material. For example, a silicon nitride material, due to its high dielectric constant and good hydrophobic function, can well protect the first pixel driving circuit D100 or the second pixel driving circuit D200 from being corroded by water vapor.

[0122] For example, as Figure 5A shown, the second pixel driving circuit D200 includes a thin film transistor 220 and a storage capacitor 230. The thin film transistor 220 includes an active layer 2220, a gate electrode 2210, and source-drain electrodes (a source electrode 2230 and a drain electrode 2240). The storage capacitor 230 includes a first capacitor plate 2301 and a second capacitor plate 2302. The active layer 2220 is disposed on the substrate 240, and the gate electrode 2210 and the first capacitor plate 2301 are disposed on the same layer on the side of the first gate insulating layer 1410 away from the substrate 140. The second capacitor plate 2302 is disposed on the side of the second gate insulating layer 1420 away from the substrate 140. The source electrode 2230 and the drain electrode 2240 are disposed on the side of the interlayer insulating layer 1430 away from the substrate 140 and are electrically connected to the active layer 2220 through vias in the first gate insulating layer 1410, the second gate insulating layer 1420, and the interlayer insulating layer 1430. The first end 1021 of the second connection trace 1020 is electrically connected to one of the source-drain electrodes through a second via GH2 in the first insulating layer 1440 and the second insulating layer 1450 (as Figure 5A shown in the left figure in

[0123] For example, as Figure 5A shown, the display substrate 1000 further includes a packaging layer 1480. The packaging layer 1480 is located on the side of the first light-emitting device 1140 and the second light-emitting device 1150 away from the substrate 140. The packaging layer 1480 seals the first light-emitting device 1140 and the second light-emitting device 1150, thereby reducing or preventing the deterioration of the light-emitting devices caused by moisture and / or oxygen included in the environment. The packaging layer 1480 may be a single-layer structure or a composite layer structure, and the composite layer structure includes a structure in which an inorganic layer and an organic layer are stacked. The packaging layer 1480 includes at least one packaging sub-layer. For example, the packaging layer 1480 may include a first inorganic packaging layer, a first organic packaging layer, and a second inorganic packaging layer provided in sequence.

[0124] For example, the material of the encapsulation layer 1480 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resins. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc.; the material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to planarize the surface of the display substrate, and can also relieve the stress between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and may also include water-absorbing materials such as desiccants to absorb substances such as water and oxygen that invade the interior.

[0125] For example, other film layers, such as a buffer layer, a barrier layer, etc., may be provided between the substrate 140 and the first gate insulating layer 1410, and the embodiments of the present disclosure are not limited thereto.

[0126] For example, as Figure 5A shown, the substrate 140 may be a glass plate, a quartz plate, a metal plate, or a resin plate, etc. For example, the material of the substrate may include organic materials, such as the organic material may be a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate; for example, the substrate 140 may be a flexible substrate or a non-flexible substrate, and the embodiments of the present disclosure are not limited thereto.

[0127] For example, Figure 5B For one embodiment provided by the present disclosure at least another, along the display substrate Figure 4BSchematic cross-sectional view of the center line B5-B6 and the line B7-B8. It is shown that the display substrate 1000 further includes a first cushion layer 1511 and a second cushion layer 1512. The first cushion layer 1511 and the second cushion layer 1512 are located in the first wiring layer 1510, that is, on the same layer as the first connecting wiring 1010 and made of the same material. The first cushion layer 1511 covers (for example, partially covers) the second via hole GH2 of the first insulating layer 1440 and is electrically connected to the second pixel driving circuit D200 (for example, to the drain 2240 of the thin film transistor 220). The first cushion layer 1511 is located on the side of the second connecting wiring 1020 close to the substrate 140 and is connected to the second connecting wiring 1020 to electrically connect the second connecting wiring 1020 to the second pixel driving circuit D200 (for example, to the drain 2240 of the thin film transistor 220). The sixth via hole GH6 of the second insulating layer 1450 exposes (for example, partially exposes) the first cushion layer 1511 to allow the second connecting wiring 1020 to be electrically connected to the second pixel driving circuit through the first cushion layer 1511. The second cushion layer 1512 is located on the side of the second end 1022 of the second connecting wiring 1020 close to the substrate and is connected to the second end 1022 of the second connecting wiring 1020. The fourth via hole GH3 of the second insulating layer 1450 exposes the second cushion layer 1512. The first cushion layer 1511 can reduce the height of the nested holes formed by the first via hole GH1, the sixth via hole GH6, and the eighth via hole GH8, and the second cushion layer 1512 can reduce the height of the fourth via hole GH4 and the tenth via hole GH10, thereby improving the slope angles of the second connecting wiring 1020 and the first electrode 1151 of the second light-emitting device 1150 and preventing the second connecting wiring 1020 and the first electrode 1151 of the second light-emitting device 1150 from breaking.

[0128] For example, in other examples, the display substrate 1000 may further include one of the first cushion layer 1511 and the second cushion layer 1512, and the present disclosure is not limited thereto.

[0129] For example, as Figure 5BAs shown, the display substrate 1000 further includes a third cushion layer 1521 and a fourth cushion layer 1522. The third cushion layer 1521 and the fourth cushion layer 1522 are located in the second wiring layer 1520, that is, on the same layer as the second connection wiring 1020 and made of the same material. A part of the third cushion layer 1521 overlaps with the fifth via hole GH5 of the second insulating layer 1450, that is, the third cushion layer 1521 covers the fifth via hole GH5 to be electrically connected to the first end 1011 of the first connection wiring 1010. The third cushion layer 1521 is located on the side of the first protective layer 1154 close to the substrate 140 and is connected to the first protective layer 1154. The seventh via hole GH7 of the third insulating layer 1460 exposes at least a part of the third cushion layer 1521 to allow electrical connection to the first connection wiring 1010 through the third cushion layer 1521. A part of the fourth cushion layer 1522 overlaps with the third via hole GH3 of the second insulating layer 1450 and covers the second end 1012 of the first connection wiring 1010, and the ninth via hole GH9 of the third insulating layer 1460 exposes (for example, partially exposes) the fourth cushion layer 1522. The fourth cushion layer 1522 is located on the side of the first electrode 1141 of the first light-emitting device 1140 away from the substrate, and is connected to the part of the first electrode 1141 located in the ninth via hole GH9 to electrically connect the first electrode 1141 to the first connection wiring 1010. The third cushion layer 1521 can reduce the height of the nested holes formed by the seventh via hole GH7 and the fifth via hole GH5, and the fourth cushion layer 1522 can reduce the height of the nested holes formed by the third via hole GH3 and the ninth via hole GH9, thereby improving the slope angle of the first electrode 1141 of the first light-emitting device 1140 and preventing the first electrode 1141 of the first light-emitting device 1140 from breaking.

[0130] For example, in other examples, the display substrate 1000 may further include one of the third cushion layer 1521 and the fourth cushion layer 1522, and the present disclosure is not limited thereto.

[0131] It should be noted that the display substrate 1000 may include the first cushion layer 1511 and the third cushion layer 1521 without providing the second cushion layer 1512 and the fourth cushion layer 1522.

[0132] It should be noted that Figure 5B The difference between the illustrated embodiment and Figure 5A the illustrated embodiment is that the first cushion layer 1511, the second cushion layer 1512, the third cushion layer 1521, and the fourth cushion layer 1522 are added. Figure 5B The difference between the illustrated embodiment and Figure 5A other identical film layer structures of the illustrated embodiment will not be described in detail.

[0133] For example, Figure 6A For a display substrate provided in at least another embodiment of the present disclosure along Figure 4BSchematic cross-sectional view of the center line B5 - B6 and the line B7 - B8. Figure 6A The illustrated embodiment and Figure 5A compared with the illustrated embodiment, Figure 6A the second insulating layer 2450 in Figure 5A is the same film layer as the second insulating layer 1450 in Figure 6A However, due to different preparation methods, the structure has changed. As shown in

[0134] For example, Figure 6A the illustrated embodiment and Figure 5A compared with the illustrated embodiment, Figure 6A the third insulating layer 2460 in Figure 5A is the same film layer as the third insulating layer 1460 in Figure 6AAs shown, the third insulating layer 2460 is patterned using a gray-scale mask or a halftone mask (detailed later), so that the third insulating layer 2460 has two parts with different thicknesses. It should be noted that the thickness refers to the height perpendicular to the substrate 140. The third insulating layer 2460 has two parts with different thicknesses. For example, it includes a first part with a higher thickness and a second part with a lower thickness. The second part with a lower thickness of the third insulating layer 2460 located in the E1 region corresponds to the ninth via hole GH9 and the tenth via hole GH10. The second part with a lower thickness of the third insulating layer 2460 located in the E2 region corresponds to the seventh via hole GH7 and the eighth via hole GH8. Thus, by reducing the height of the local third insulating layer 2460, the heights of the seventh via hole GH7, the eighth via hole GH8, the ninth via hole GH9, and the tenth via hole GH10 can be reduced, the slope angles of the second connecting trace 1020 and the first electrode 1151 of the second light-emitting device 1150 can be improved, and the second connecting trace 1020 and the first electrode 1151 of the second light-emitting device 1150 can be prevented from breaking.

[0135] Figure 6B A cross-sectional schematic diagram of a display substrate provided by at least another embodiment of the present disclosure along Figure 4B the center line B5 - B6 and the line B7 - B8. Figure 6B The embodiment shown corresponds to Figure 5B the embodiment shown, that is, the first cushion layer 1511, the second cushion layer 1512, the third cushion layer 1521, and the fourth cushion layer 1522 are added. Figure 6B The film layer structures of the second insulating layer 2450 and the third insulating layer 2460 in Figure 6A are the same as the film layer structures of the second insulating layer 2450 and the third insulating layer 2460 shown in Figure 6B The embodiment shown in Figure 5B is obtained by combining with Figure 6A the embodiment shown, and will not be elaborated here in detail.

[0136] For example, Figure 7 A partial enlarged schematic diagram of the second display area of a display substrate provided by at least one embodiment of the present disclosure. As Figure 7As shown, the display substrate 1000 further includes a first virtual trace DML1 and a second virtual trace DML2 located in the first display area 100. The first virtual trace DML1 is connected to the second end 1012 of the first connection trace 1010, and the second virtual trace DML2 is connected to the second end 1022 of the second connection trace 1020. The first virtual trace DML1 and the first connection trace 1010 are disposed on the same layer and integrally formed, and the second virtual trace DML2 and the second connection trace 1020 are disposed on the same layer and integrally formed. The first virtual trace DML1 and the second virtual trace DML2 are located between two adjacent rows of the first connection trace 1010 and the second connection trace 1020 along the second direction Y1. The extending direction of the first virtual trace DML1 (e.g., the second direction Y1) intersects with the extending direction of the first connection trace 1010 (e.g., the first direction X1), and the extending direction of the second virtual trace DML2 (e.g., the second direction Y1) intersects with the extending direction of the second connection trace 1020 (e.g., the first direction X1). The arrangement of the first virtual trace DML1 and the second virtual trace DML2 can make the traces in the first display area 100 more uniform, thereby making the light transmission in the first display area 100 uniform, and at the same time, can also improve the etching uniformity of the traces in the first display area 100. At least one embodiment of the present disclosure further provides a method for manufacturing a display substrate. The manufacturing method includes: providing a substrate, on which a plurality of pixel driving circuits are formed, and the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit; forming a first insulating layer on the substrate, and the first insulating layer is formed to partially expose the plurality of pixel driving circuits respectively; forming a first trace layer on the first insulating layer, and the first trace layer includes a first connection trace, and the first connection trace is formed to be electrically connected to the first pixel driving circuit through the first insulating layer; forming and patterning a second insulating layer on the first trace layer; forming a second trace layer on the second insulating layer, and the second trace layer includes a second connection trace, and the second connection trace is formed to be electrically connected to the second pixel driving circuit through the first insulating layer and the second insulating layer; and forming and patterning a third insulating layer on the second trace layer; the third insulating layer and the second insulating layer are formed by using the same mask template for the patterning process to have substantially the same planar pattern.

[0137] In the display substrate manufactured by using the above manufacturing method, the third insulating layer and the second insulating layer are formed by using the same mask template for the patterning process to have substantially the same planar pattern, so that the manufacturing cost can be reduced.

[0138] The following will introduce in detail a method for manufacturing the above display substrate provided by at least one embodiment of the present disclosure with reference to the accompanying drawings.

[0139] Figures 8A - 8M For some embodiments of the present disclosure Figure 5A The process diagram of the method for manufacturing the display substrate shown.Figure 5A Taking the display substrate shown as an example, in combination with Figures 8A - 8M This disclosure introduces a method for manufacturing a display substrate provided by at least one embodiment.

[0140] For example, the display substrate 1000 may include a first pixel driving circuit D100 and a second pixel driving circuit D200 located in the second display area 200, a first light-emitting device 1140 and a second light-emitting device 1150 located in the first display area 100, a first connection trace 1010, a second connection trace 1020, a first gate insulating layer 1410, a second gate insulating layer 1420, an interlayer insulating layer 1430, a first insulating layer 1440, a second insulating layer 1450, a third insulating layer 1460, a pixel defining layer 1470, and a packaging layer 1480.

[0141] For example, in some embodiments, a substrate is provided.

[0142] For example, as Figure 8A shown, a substrate 140 is provided. The substrate 140 includes a display area, and the display area includes a first display area 100 (such as a transmissive display area) and a second display area 200 (such as a low-resolution display area). A plurality of pixel driving circuits are formed on the substrate 140. The plurality of pixel driving circuits include a first pixel driving circuit D100 and a second pixel driving circuit D200.

[0143] For example, the material of the substrate 140 may include an organic material. For example, the organic material may be a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate; for example, the substrate 140 may be a flexible substrate or a non-flexible substrate, and the embodiments of the present disclosure do not limit this.

[0144] For example, in the second display area 200 on the substrate 140, an active layer 1220 (a thin-film transistor 120 belonging to the first pixel driving circuit D100) and an active layer 2220 (a thin-film transistor 220 belonging to the second pixel driving circuit D200) are formed. For example, a semiconductor material layer is deposited on the substrate 140, and then a patterning process is performed on the semiconductor material layer to form the active layer 1220 and the active layer 2220. The active layer 1220 and the active layer 2220 each include a source region, a drain region, and a channel region between the source region and the drain region.

[0145] For example, the semiconductor material of the active layer 1220 and the active layer 2220 may include polysilicon or an oxide semiconductor (such as indium gallium zinc oxide), etc.

[0146] For example, after the active layer 1220 and the active layer 2220 are formed, the first gate insulating layer 1410 can be formed on the active layer 1220 and the active layer 2220 by means of deposition or the like. The material of the first gate insulating layer 1410 can include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0147] For example, after the first gate insulating layer 1410 is formed, the gate 1210 (the thin film transistor 120 belonging to the first pixel driving circuit D100), the first capacitor plate 1301 (the storage capacitor 130 belonging to the first pixel driving circuit D100), the gate 2210 (the thin film transistor 220 belonging to the second pixel driving circuit D200), and the first capacitor plate 2301 (the storage capacitor 230 belonging to the second pixel driving circuit D200) can be formed on the first gate insulating layer 1410 in the second display area 200 through a patterning process. The materials of the gate 1210, the first capacitor plate 1301, the gate 2210, and the first capacitor plate 2301 can include metal materials or alloy materials, such as a single-layer or multi-layer structure of metals formed by molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)).

[0148] In some examples, the gate 1210 can be used as a mask to dope the active layer 1220 to form the source region and the drain region of the conductive active layer 1220, and the gate 2210 can be used as a mask to dope the active layer 2220 to form the source region and the drain region of the conductive active layer 2220, while the channel region between the source region and the drain region is not doped due to the shielding effect of the gate.

[0149] For example, after the gate 1210, the first capacitor plate 1301, the gate 2210, and the first capacitor plate 2301 are formed, an insulating material can be deposited on the substrate 140 by means of deposition or the like, and the second gate insulating layer 1420 is formed on the gate 1210, the first capacitor plate 1301, the gate 2210, and the first capacitor plate 2301. The material of the second gate insulating layer 1420 can include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0150] For example, a metal material layer is deposited on the substrate 140 in the second display area 200, and the second capacitor plate 1302 is formed in the overlapping portion with the first capacitor plate 1301 and the second capacitor plate 2302 is formed in the overlapping portion with the first capacitor plate 2301 through a patterning process. The first capacitor plate 1301 and the second capacitor plate 1302 are implemented as the storage capacitor 130. The first capacitor plate 2301 and the second capacitor plate 2302 are implemented as the storage capacitor 230.

[0151] For example, after forming the second capacitor electrode plate 1302 and the second capacitor electrode plate 2302, an interlayer insulating layer 1430 can be formed by means of deposition or the like. The material of the interlayer insulating layer 1430 can include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0152] For example, vias are formed in the first gate insulating layer 1410, the second gate insulating layer 1420, and the interlayer insulating layer 1430 to expose the source region and the drain region of the active layer 1220 and the source region and the drain region of the active layer 2220.

[0153] For example, a metal material or an alloy material is deposited, and then the source electrode 1230 and the drain electrode 1240 of the thin film transistor 120, and the source electrode 2230 and the drain electrode 2240 of the thin film transistor 220 are formed in the second display region 200 through a patterning process. The source electrode 1230 and the drain electrode 1240 are electrically connected to the source region and the drain region of the active layer 1220 respectively through the vias in the first gate insulating layer 1410, the second gate insulating layer 1420, and the interlayer insulating layer 1430. The source electrode 2230 and the drain electrode 2240 are electrically connected to the source region and the drain region of the active layer 2220 respectively through the vias in the first gate insulating layer 1410, the second gate insulating layer 1420, and the interlayer insulating layer 1430.

[0154] For example, the materials of the source electrode 1230 and the drain electrode 1240 of the thin film transistor 120, and the source electrode 2230 and the drain electrode 2240 of the thin film transistor 220 can include a metal material or an alloy material, such as a single-layer or multi-layer structure of metal formed by molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a multi-metal laminate (such as a three-layer metal laminate of titanium, aluminum, and titanium (Ti / Al / Ti)).

[0155] For example, in some embodiments, a first insulating layer is formed on the substrate.

[0156] For example, as Figure 8A shown, a first insulating material layer 31 is formed on the source electrode 1230 and the drain electrode 1240 of the thin film transistor 120, and the source electrode 2230 and the drain electrode 2240 of the thin film transistor 220. The material of the first insulating material layer 31 includes inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and can also include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of the present disclosure do not limit this.

[0157] For example, as Figure 8B shown, a first insulating layer 1440 covering the first pixel driving circuit D100 and the second pixel driving circuit D200 is formed through a patterning process, and a plurality of vias are formed in the first insulating layer 1440 to partially expose the first pixel driving circuit D100 and the second pixel driving circuit D200 respectively.

[0158] For example, a first via hole GH1 and a second via hole GH2 are formed in the first insulating layer 1440. The first via hole GH1 partially exposes the first pixel driving circuit D100 (e.g., the drain 1240 of the thin film transistor 120), and the second via hole portion D exposes the second pixel driving circuit D200 (e.g., the drain 2240 of the thin film transistor 220).

[0159] For example, a first wiring layer is formed on the first insulating layer.

[0160] For example, as Figure 8C shown, a conductive material or a transparent conductive material is deposited on the first insulating layer 1440, and then the first wiring layer 1510 is formed through a patterning process. For example, the material of the first wiring layer 1510 may include a transparent conductive material, such as transparent metal oxides like indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first wiring layer 1510 includes a first connecting wiring 1010, and the first connecting wiring 1010 is formed to be electrically connected to the first pixel driving circuit D100 (e.g., the drain 1240 of the thin film transistor 120) through the first insulating layer 1440. It should be noted that the electrical connection through the first insulating layer 1440 means that the first connecting wiring 1010 realizes the electrical connection through a via hole (e.g., the first via hole GH1) in the first insulating layer 1440. The first pixel driving circuit D100 is configured to drive the first light emitting device 1140 to emit light through the first connecting wiring 1010.

[0161] For example, the first end 1011 of the first connecting wiring 1010 is formed to be electrically connected to the drain 1240 of the thin film transistor 120, which is an example of the first pixel driving circuit D100, through the first via hole GH1, and the second end 1012 of the first connecting wiring 1010 is used to be electrically connected to the first light emitting device 1140. Thus, the first pixel driving circuit D100 drives the first light emitting device 1140 to emit light through the first connecting wiring 1010.

[0162] For example, as Figure 8DAs shown, a second insulating material layer 32 is deposited on the substrate 140. The second insulating material layer 32 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may also include organic insulating materials such as polyimide, polyimide, polyamide, acrylic resin, benzocyclobutene or phenolic resin. A photoresist 50 is deposited on the second insulating material layer 32. A first mask 41 is provided to expose the photoresist 50. The first mask 41 includes a light-transmitting area and an opaque area. The first mask 41 includes a light-transmitting pattern 411 corresponding to the first end 1011 and the second end 1012 of the first connecting trace 1010, the first via hole GH2 of the first insulating layer 1440, and a portion for forming the fourth via hole GH4 later, and an opaque pattern 412 of a portion other than the light-transmitting pattern 411. The photoresist 50 is a positive photoresist. During the exposure process, the portion of the photoresist 50 corresponding to the light-transmitting pattern 411 is completely exposed, while the portion corresponding to the light-opaque pattern 412 is not exposed.

[0163] For example, Figure 8E As shown, the photoresist 50 is developed, and the completely exposed portion of the photoresist 50 is removed to form a photoresist pattern 51 ( Figure 8E ) and the photoresist pattern 52 ( Figure 8E As another example, in the above-mentioned patterning process, a negative photoresist may also be used. Then, the mask plate used is, for example, a mask plate complementary to the above-mentioned first mask plate 41, so that the above-mentioned photoresist pattern 51 ( Figure 8E ) and the photoresist pattern 52 ( Figure 8E in the figure on the right).

[0164] For example, continue as Figure 8EAs shown, the second insulating material layer 32 is etched to form a second insulating layer 1450, in which a third via hole GH3, a fourth via hole GH4, a fifth via hole GH5, and a sixth via hole GH6 are formed. The third via hole GH3 and the fourth via hole GH4 are located in the first display area 100. The fifth via hole GH5 and the sixth via hole GH6 are located in the second display area 200. The third via hole GH3 exposes the second end 1012 of the first connection trace 1010 for connecting the first electrode 1141 of the first light-emitting device 1140 and the first connection trace 1010. The orthographic projection of the fourth via hole GH4 on the substrate 140 overlaps with the orthographic projection of the second end 1022 of the second connection trace 1020 on the substrate 140 for connecting the first electrode 1151 of the second light-emitting device 1150 and the second connection trace 1020. The orthographic projection of the fifth via hole GH5 on the substrate 140 overlaps with the first via hole GH1 of the first insulating layer 1440, and the fifth via hole GH5 exposes the first end 1011 of the first connection trace 1010. The orthographic projection of the sixth via hole GH7 on the substrate 140 overlaps with the second via hole GH2 of the first insulating layer 1440 for electrically connecting the second pixel driving circuit D200 through the second connection trace 1020.

[0165] For example, as Figure 8F shown, an ashing process is performed to remove the photoresist pattern 51 ( Figure 8E in the left figure) and the photoresist pattern 52 ( Figure 8E in the right figure) to form the second insulating layer 1450. The second insulating layer 1450 can also be etched and the etching thickness can be controlled to provide a planarized surface.

[0166] For example, in some embodiments, a second trace layer is formed on the second insulating layer.

[0167] For example, as Figure 8G shown, a conductive material or a transparent conductive material is deposited on the second insulating layer 1450, and then a second trace layer 1520 is formed through a patterning process. For example, the material of the second trace layer 1520 can include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), and other transparent metal oxides. The second trace layer 1520 includes the first connection trace 1010, and the second connection trace 1020 is formed to be electrically connected to the second pixel driving circuit D200 through the first insulating layer 1440 and the second insulating layer 1450. The second pixel driving circuit D200 is configured to drive the second light-emitting device 1150 to emit light through the second connection trace 1020.

[0168] For example, the first end 1021 of the second connection trace 1020 is formed to be electrically connected to the second pixel driving circuit D200 (such as the drain 2240 of the thin film transistor 220) through the second via hole GH2 and the sixth via hole GH6 in the second insulating layer 1450. The second end 1022 of the second connection trace 1020 covers the fourth via hole GH4 in the second insulating layer 1450. The second end 1022 of the second connection trace 1020 is used to be electrically connected to the second light-emitting device 1150. The first connection trace 1010 and the second connection trace 1020 are located in different film layers to reduce the wiring space.

[0169] For example, in some embodiments, a third insulating layer is formed and patterned on the second trace layer.

[0170] For example, as Figure 8H shown, a third insulating material layer 33 is deposited on the substrate 140. The third insulating material layer 33 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., or may include organic insulating materials such as polyimide, polyphthalimide, polyamide, acrylic resin, benzocyclobutene or phenolic resin. A photoresist 60 is deposited on the third insulating material layer 33. A first mask 41 is provided to expose the photoresist 60. The first mask 41 is the same mask as the first mask 41 used in the preparation of the second insulating layer 1450 as Figure 8D shown. The photoresist 60 is a positive photoresist. The light-transmitting pattern 411 of the first mask 41 corresponds to the third via hole GH3, the fourth via hole GH4, the fifth via hole GH5, and the sixth via hole GH6. During the exposure process of the second insulating layer 1450, the portion of the photoresist 60 corresponding to the light-transmitting pattern 411 of the first mask 41 is completely exposed, while the portion corresponding to the light-blocking pattern 412 of the first mask 41 is not exposed.

[0171] For example, as Figure 8I shown, the photoresist 60 is developed, and the completely exposed portion of the photoresist 60 is removed to form a photoresist pattern 61 ( Figure 8I in the left figure) and a photoresist pattern 62 ( Figure 8I in the right figure). Also for example, in the above patterning process, a negative photoresist may also be used. Then, the mask used is, for example, a mask complementary to the above first mask 41. Thus, after exposure and development, the above photoresist pattern 61 ( Figure 8I in the left figure) and a photoresist pattern 62 ( Figure 8I in the right figure) are obtained.

[0172] For example, continuing as Figure 8IAs shown, the third insulating material layer 33 is etched to form a third insulating layer 1460, in which a seventh via hole GH7, an eighth via hole GH8, a ninth via hole GH9, and a tenth via hole GH10 are formed. The seventh via hole GH7 and the eighth via hole GH8 are located in the second display area 200. The ninth via hole GH9 and the tenth via hole GH10 are located in the first display area 100. The orthographic projection of the ninth via hole GH9 on the substrate 140 overlaps with the orthographic projection of the third via hole GH3 of the second insulating layer 1450 on the substrate 140, and the ninth via hole GH9 exposes the second end 1012 of the first connection trace 1010 to allow the second end 1012 of the first connection trace 1010 to be connected to the first electrode 1141 of the first light-emitting device 1140. The orthographic projection of the tenth via hole GH10 on the substrate 140 overlaps with the orthographic projection of the fourth via hole GH4 of the second insulating layer 1450 on the substrate 140, and the tenth via hole GH10 exposes the second end 1022 of the second connection trace 1020 to allow the second end 1022 of the second connection trace 1020 to be connected to the first electrode 1151 of the second light-emitting device 1150. The orthographic projection of the seventh via hole GH7 on the substrate 140 overlaps with the orthographic projection of the first via hole GH1 of the first insulating layer 1440 and the orthographic projection of the fifth via hole GH5 of the second insulating layer 1450 on the substrate 140, and the seventh via hole GH7 (and the fifth via hole GH5) exposes the first end 1011 of the first connection trace 1010. The orthographic projection of the eighth via hole GH8 on the substrate 140 overlaps with the orthographic projection of the second via hole GH2 of the first insulating layer 1440 and the orthographic projection of the sixth via hole GH6 of the second insulating layer 1450 on the substrate 140, and the eighth via hole GH8 exposes the first end 1021 of the second connection trace 1020.

[0173] For example, as Figure 8J shown, an ashing process is performed to remove the photoresist pattern 61 ( Figure 8I in the left figure) and the photoresist pattern 62 ( Figure 8I in the right figure). The third insulating layer 1460 can also be etched and the etching thickness can be controlled to provide a planarized surface.

[0174] For example, the third insulating layer and the second insulating layer are formed by a patterning process using the same mask to have substantially the same planar pattern. As Figure 8IAs shown, the projection of the ninth via hole GH9 in the second insulating layer 1450 overlaps with the projection of the third via hole GH3 in the first insulating layer 1440 on the substrate 140. The projection of the seventh via hole GH7 in the second insulating layer 1450 overlaps with the projection of the fifth via hole GH5 in the first insulating layer 1440 on the substrate 140. The projection of the eighth via hole GH8 in the second insulating layer 1450 overlaps with the projection of the sixth via hole GH6 in the first insulating layer 1440 on the substrate 140. The projection of the tenth via hole GH10 in the second insulating layer 1450 overlaps with the projection of the fourth via hole GH4 in the first insulating layer 1440 on the substrate 140. Thus, a nested via hole is formed between the second insulating layer 1450 and the first insulating layer 1440, enabling the second insulating layer 1450 and the first insulating layer 1440 to be formed by using the same mask for the patterning process, thereby reducing the manufacturing cost.

[0175] For example, a plurality of light-emitting devices are formed on the third insulating layer. As Figure 5A shown, the first light-emitting device 1140 includes a first electrode 1141, a first light-emitting layer 1142, and a second electrode 1143. The second light-emitting device 1150 includes a first electrode 1151, a first light-emitting layer 1152, and a second electrode 1153.

[0176] For example, as Figure 8K shown, a metal material or an alloy material is deposited, and then the first electrode 1141 of the first light-emitting device 1140 and the first electrode 1151 of the second light-emitting device 1150 are formed in the first display area 100 through a patterning process. The first electrode 1141 of the first light-emitting device 1140 is formed to be connected to the second end 1012 of the first connection trace 1010 through the third via hole GH3 in the second insulating layer 1450 and the ninth via hole GH9 in the third insulating layer 1460. The first electrode 1151 of the second light-emitting device 1150 is formed to be connected to the second end 1022 of the second connection trace 1020 through the tenth via hole GH10 in the third insulating layer 1460. For example, the materials of the first electrode 1141 of the first light-emitting device 1140 and the first electrode 1151 of the second light-emitting device 1150 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In addition, the first electrode 1141 of the first light-emitting device 1140 and the first electrode 1151 of the second light-emitting device 1150 may include a metal with a high reflectivity as a reflective layer, such as silver (Ag).

[0177] For example, while forming the first electrodes of a plurality of light-emitting devices, a first protective layer and a second protective layer are also formed. As Figure 8KAs shown, while forming the first electrode 1141 of the first light-emitting device 1140 and the first electrode 1151 of the second light-emitting device 1150, a first protective layer 1154 and a second protective layer 1155 are also formed. The first protective layer 1154 covers the seventh via hole GH7 of the third insulating layer 1460, and the second protective layer 1155 covers the eighth via hole GH8 of the third insulating layer 1460. The first protective layer 1154 also covers the surface of the first end 1011 of the first connection trace 1010 on the side away from the substrate 140, and the second protective layer 1155 also covers the surface of the first end 1021 of the second connection trace 1020 on the side away from the substrate 140, thereby protecting the first connection trace 1010 and the second connection trace 1020 from being damaged in subsequent fabrication processes, such as being corroded by an etching solution.

[0178] For example, after forming the first electrodes of a plurality of light-emitting devices, a pixel defining layer is formed on the first electrodes of the plurality of light-emitting devices and on the side of the third insulating layer away from the substrate. For example, as Figure 8L shown, a pixel defining layer 1470 is formed on the first electrode 1141 of the first light-emitting device 1140, the first electrode 1151 of the second light-emitting device 1150, and the third insulating layer 1460. The pixel defining layer 1470 is formed to include a plurality of first pixel openings 1471. The plurality of first pixel openings 1471 correspond one-to-one to the first light-emitting device 1140 and the second light-emitting device 1150 to form a light-emitting region 1160 of the first light-emitting device 1140 and a light-emitting region 2160 of the second light-emitting device 1150 (as Figure 8M shown).

[0179] For example, a first light-emitting layer of a plurality of light-emitting devices is formed in the first pixel openings, and a second electrode of the plurality of light-emitting devices is formed on the side of the first light-emitting layer and the pixel defining layer away from the substrate. As Figure 8MAs shown, a first light-emitting layer 1142 of the first light-emitting device 1140 and a first light-emitting layer 1152 of the second light-emitting device 1150 are formed in a plurality of first pixel openings 1471. A second electrode 1143 of the first light-emitting device 1140 and a second electrode 1153 of the second light-emitting device 1150 are formed on the pixel defining layer 1470, the first light-emitting layer 1142 of the first light-emitting device 1140, and the first light-emitting layer 1152 of the second light-emitting device 1150. That is, the first light-emitting layer 1142 of the first light-emitting device 1140 is formed to be located in the first pixel opening 1471 and between the first electrode 1141 and the second electrode 1143. The first light-emitting layer 1152 of the second light-emitting device 1150 is formed to be located in the first pixel opening 1471 and between the first electrode 1151 and the second electrode 1153. The portion of the first light-emitting layer 1142 directly sandwiched between the first electrode 1141 and the second electrode 1143 will emit light after being powered on, and thus the region occupied by this portion corresponds to the light-emitting region 1160 of the first light-emitting device 1140. The portion of the first light-emitting layer 1152 directly sandwiched between the first electrode 1151 and the second electrode 1153 will emit light after being powered on, and thus the region occupied by this portion corresponds to the light-emitting region 2160 of the second light-emitting device 1150.

[0180] For example, continuing as Figure 8M shown, an encapsulation layer 1480 is formed by depositing an insulating material on the second electrode 1143 of the first light-emitting device 1140 and the second electrode 1153 of the second light-emitting device 1150. The encapsulation layer 1480 seals the first light-emitting device 1140 and the second light-emitting device 1150, thereby reducing or preventing the deterioration of the light-emitting device caused by moisture and / or oxygen included in the environment. The encapsulation layer 1480 can be a single-layer structure or a composite layer structure, and the composite layer structure includes a structure in which an inorganic layer and an organic layer are stacked. The encapsulation layer 1480 includes at least one encapsulation sub-layer. For example, the encapsulation layer 1480 can include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer arranged in sequence.

[0181] For example, the material of the encapsulation layer 1480 can include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc.; the material of the organic encapsulation layer can be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to planarize the surface of the display substrate, and can relieve the stress between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and can also include a water-absorbing material such as a desiccant to absorb substances such as water and oxygen that invade the interior.

[0182] Figures 9A - 9F Provided by some embodiments of the present disclosure Figure 5BProcess diagram of the method for preparing the shown display substrate.

[0183] It should be noted that Figure 5B The difference between the shown embodiment and Figure 5A the shown embodiment lies in that: a first cushion layer 1511, a second cushion layer 1512, a third cushion layer 1521, and a fourth cushion layer 1522 are added. Figure 5B The difference between the shown embodiment and Figure 5A the preparation method of the same film layer structure in the shown embodiment will not be described in detail again.

[0184] For example, when forming the first connection trace, the first cushion layer and the second cushion layer are formed simultaneously.

[0185] Such as Figure 9A the shown embodiment corresponds to Figure 8C the shown embodiment, that is, both are used to form the first trace layer 1510.

[0186] For example, as Figure 9A shown, a conductive material or a transparent conductive material is deposited on the first insulating layer 1440, and then the first trace layer 1510 is formed through a patterning process. The first trace layer 1510 includes a first connection trace 1010, a first cushion layer 1511, and a second cushion layer 1512. The first cushion layer 1511 is formed to cover (for example, partially cover) the second via hole GH2 of the first insulating layer 1440 and is electrically connected to the second pixel driving circuit D200 (for example, to the drain 2240 of the thin film transistor 220). The first cushion layer 1511 corresponds to the second end 1022 of the second connection trace 1020 and is exposed by the sixth via hole GH6 of the second insulating layer 1450 to allow the second connection trace 1020 to be electrically connected to the second pixel driving circuit through the first cushion layer 1511. The fourth via hole GH3 of the second insulating layer 1450 exposes the second cushion layer 1512, and the second cushion layer 1512 is connected to the second end 1022 of the second connection trace 1020. The first cushion layer 1511 and the second cushion layer 1512 can reduce the height of the via holes in the second insulating layer 1450, thereby improving the slope angles of the second connection trace 1020 and the first electrode 1151 of the second light emitting device 1150 and preventing the second connection trace 1020 and the first electrode 1151 of the second light emitting device 1150 from breaking.

[0187] For example, in other examples, the display substrate 1000 may also form one of the first cushion layer 1511 and the second cushion layer 1512, and the present disclosure is not limited thereto.

[0188] For example, as Figure 9B shown, a second insulating layer 1450 is formed on the first trace layer 1510. For the detailed formation process of the second insulating layer 1450, reference can be made to Figures 8D - 8MThe manufacturing process shown. The sixth via hole GH6 of the second insulating layer 1450 exposes the first cushion layer 1511. The fourth via hole of the second insulating layer 1450 exposes the second cushion layer 1512.

[0189] For example, while forming the second connection trace, the third cushion layer and the fourth cushion layer are formed.

[0190] Such as Figure 9C The embodiment shown corresponds to Figure 8G the embodiment shown, that is, both are used to form the second trace layer 1520.

[0191] For example, as Figure 9C shown, a conductive material or a transparent conductive material is deposited on the second insulating layer 1450, and then the second trace layer 1520 is formed by a patterning process. For example, the second trace layer 1520 includes a first connection trace 1010, a third cushion layer 1521, and a fourth cushion layer 1522. A part of the third cushion layer 1521 overlaps with the fifth via hole GH5 of the second insulating layer 1450, that is, the third cushion layer 1521 covers the fifth via hole GH5 to be electrically connected to the first end 1011 of the first connection trace 1010. A part of the fourth cushion layer 1522 overlaps with the third via hole GH3 of the second insulating layer 1450 and covers the second end 1012 of the first connection trace 1010.

[0192] For example, in other examples, one of the third cushion layer 1521 and the fourth cushion layer 1522 may be formed, and the present disclosure is not limited thereto.

[0193] For example, as Figure 9D shown, a third insulating layer 1460 is formed on the second trace layer 1520. For the detailed formation process of the third insulating layer 1460, reference can be made to Figures 8H - 8J the manufacturing process shown. The seventh via hole GH7 of the third insulating layer 1460 at least partially exposes the third cushion layer 1521 to allow electrical connection to the first connection trace 1010 through the third cushion layer 1521. The ninth via hole GH9 of the third insulating layer 1460 exposes (for example, partially exposes) the fourth cushion layer 1522. The third cushion layer 1521 can reduce the height of the nested holes formed by the seventh via hole GH7 and the fifth via hole GH5, and the fourth cushion layer 1522 can reduce the height of the nested holes formed by the third via hole GH3 and the ninth via hole GH9, thereby improving the slope angle of the first electrode 1141 of the first light-emitting device 1140 and preventing the first electrode 1141 of the first light-emitting device 1140 from breaking.

[0194] For example, as Figure 9EAs shown, a first electrode 1141 of the first light-emitting device 1140, a first electrode 1151 of the second light-emitting device 1150, a first protective layer 1154, and a second protective layer 1155 are formed on the third insulating layer 1460. The detailed formation process can be referred to as Figure 8K the formation process shown. The third cushion layer 1521 is located on the side of the first protective layer 1154 close to the substrate 140 and is connected to the first protective layer 1154. The fourth cushion layer 1522 is connected to the part of the first electrode 1141 located in the ninth via hole GH9 to electrically connect the first electrode 1141 to the first connection trace 1010.

[0195] For example, as Figure 9F shown, a pixel defining layer 1470, a first light-emitting device 1140, and a second light-emitting device 1150 are formed on the substrate. The detailed formation process can be referred to Figures 8L to 8M the steps shown and will not be elaborated here.

[0196] Figures 10A - 10H The process diagram of the manufacturing method of the display substrate provided by some embodiments of the present disclosure. Figure 6A shown. Figures 10A - 10H Shows Figure 6A the manufacturing process in which the second insulating layer 2450 and the third insulating layer 2460 in

[0197] are patterned using a gray tone mask or a halftone mask. Figure 10A As shown, a second insulating material layer 32 is deposited on the substrate 140. The second insulating material layer 32 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., or may include organic insulating materials such as polyimide, polyphthalimide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin. A photoresist 170 is deposited on the second insulating material layer 32. A second mask 141 is provided to expose the photoresist 170. The second mask 141 includes a completely transparent area, a partially transparent area, and an opaque area. The second mask 141 includes a completely transparent pattern 1411, a partially transparent pattern 1413, and an opaque pattern 1412. The completely transparent pattern 1411 corresponds to the first end 1011 and the second end 1012 of the first connection trace 1010, the first via hole GH2 of the first insulating layer 1440, and the part for forming the fourth via hole GH4 later. The partially transparent pattern 1413 corresponds to Figure 6AThe portions of the second insulating layer 2450 corresponding to the E1 region and the E2 region, and the light-blocking pattern 1412 are the portions of the second mask 141 other than the light-transmitting pattern 1411 and the partial light-transmitting pattern 1413. The second mask 141 is a gray mask or a halftone mask. The photoresist 170 is a positive photoresist. Correspondingly, the light transmittance of the partial light-transmitting pattern 1413 is less than that of the completely light-transmitting pattern 1411. During the exposure process, the portions of the photoresist 170 corresponding to the completely light-transmitting pattern 1411 can be completely exposed, while the portions of the photoresist 170 corresponding to the partial light-transmitting pattern 1413 are partially exposed. The portions of the photoresist 170 corresponding to the light-blocking pattern 1412 are not exposed.

[0198] As Figure 10B shown, the photoresist 170 is developed, and the completely exposed portions of the photoresist 170 are removed, that is, the portions corresponding to the third via hole GH3, the fourth via hole GH4, the fifth via hole GH5, and the sixth via hole GH6 of the second insulating layer 2450 are removed. The partially exposed portions of the photoresist 170 are thinned, while the thickness of the unexposed portions of the photoresist 170 remains basically unchanged, for example. After development, the photoresist 170 is used to form a photoresist pattern 171 ( Figure 10B in the left figure) and a photoresist pattern 172 ( Figure 10B in the right figure). Also, for example, in the above-described patterning process, a negative photoresist can also be used. Then, the mask used is, for example, a mask complementary to the above-mentioned second mask 141. Thus, after exposure and development, the above-mentioned photoresist pattern 171 ( Figure 10B in the left figure) and a photoresist pattern 172 ( Figure 10B in the right figure) are obtained.

[0199] For example, continuing as Figure 10B shown, the second insulating material layer 32 is etched to form the second insulating layer 2450, and the third via hole GH3, the fourth via hole GH4, the fifth via hole GH5, and the sixth via hole GH6 are formed in the second insulating layer 2450.

[0200] For example, as Figure 10C shown, an ashing process is performed to remove the partially exposed portions of the photoresist pattern 171 ( Figure 10B in the left figure) and the photoresist pattern 172 ( Figure 10B in the right figure), while the un-partially exposed portions of the photoresist pattern 171 ( Figure 10B in the left figure) and the photoresist pattern 172 ( Figure 10B in the right figure) are thinned to form a photoresist pattern 173 ( Figure 10C in the left figure) and a photoresist pattern 174 ( Figure 10C(in the right figure). The remaining second insulating material layer 32 is etched and the etching thickness is controlled to form the second insulating layer 2450. The second insulating layer 2450 has two parts with different thicknesses. The second insulating layer 2450 includes a first part with a higher thickness and a second part with a lower thickness. The second part with a lower thickness of the second insulating layer 2450 located in the E1 region corresponds to the third via hole GH3 and the fourth via hole GH4, and the second part with a lower thickness of the second insulating layer 2450 located in the E2 region corresponds to the fifth via hole GH5 and the sixth via hole GH6. Thus, by reducing the height of the local second insulating layer 2450, the heights of the third via hole GH3, the fourth via hole GH4, the fifth via hole GH5, and the sixth via hole GH6 can be reduced, the slope angles of the first connection trace 1010 and the first electrode 1141 of the first light-emitting device 1140 can be improved, and the breakage of the first connection trace 1010 and the first electrode 1141 of the first light-emitting device 1140 can be prevented.

[0201] For example, as Figure 10D shown, the photoresist pattern 173 ( Figure 10C in the left figure) and the photoresist pattern 174 ( Figure 10C in the right figure) are removed. The second insulating layer 2450 can also be etched and the etching thickness can be controlled to provide a planarized surface.

[0202] For example, as Figure 10E shown, a second trace layer 1520 including a second connection trace 1020 is formed on the second insulating layer 2450. A third insulating material layer 133 is deposited on the second insulating layer 2450. The third insulating material layer 133 can include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., or can also include organic insulating materials such as polyimide, polyphthalimide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin. Photoresist 160 is deposited on the third insulating material layer 133. A second mask 141 is provided to expose the photoresist 160. The second mask 141 is the same mask as the second mask 141 used in Figure 10A preparing the second insulating layer 2450. The completely transparent pattern 1411 of the second mask 141 corresponds to the third via hole GH3, the fourth via hole GH4, the fifth via hole GH5, and the sixth via hole GH6, and the partially transparent pattern 1413 of the second mask 141 corresponds to Figure 6AThe partially transparent patterns 1413 corresponding to the E1 region and the E2 region of the third insulating layer 2460. The second mask 141 is a gray mask or a halftone mask. The photoresist 160 is a positive photoresist. Correspondingly, the light transmittance of the partially transparent pattern 1413 is less than that of the fully transparent pattern 1411. During the exposure process, the portion of the photoresist 160 corresponding to the fully transparent pattern 1411 can be fully exposed, while the portion of the photoresist 160 corresponding to the partially transparent pattern 1413 is partially exposed. The portion of the photoresist 160 corresponding to the opaque pattern 1412 is not exposed.

[0203] As Figure 10F shown, the photoresist 160 is developed, and the fully exposed portion of the photoresist 160 is removed, that is, the portions corresponding to the seventh via hole GH7, the eighth via hole GH8, the ninth via hole GH9, and the tenth via hole GH10 of the third insulating layer 2460 are removed. The partially exposed portion of the photoresist 160 is thinned, while the thickness of the unexposed portion of the photoresist 160 remains substantially unchanged, for example. After development, the photoresist 160 is formed into a photoresist pattern 161 ( Figure 10F in the left figure) and a photoresist pattern 162 ( Figure 10F in the right figure). For another example, in the above patterning process, a negative photoresist can also be used. Then, the mask used is, for example, a mask complementary to the second mask 141 described above. Thus, after exposure and development, the above photoresist pattern 161 ( Figure 10F in the left figure) and a photoresist pattern 162 ( Figure 10F in the right figure) are obtained.

[0204] For example, continuing as Figure 10F shown, the third insulating material layer 133 is etched to form the third insulating layer 2460, and the seventh via hole GH7, the eighth via hole GH8, the ninth via hole GH9, and the tenth via hole GH10 are formed in the third insulating layer 2460.

[0205] For example, as Figure 10G shown, an ashing process is performed to remove the partially exposed portions of the photoresist pattern 161 ( Figure 10F in the left figure) and the photoresist pattern 162 ( Figure 10F in the right figure), while the unpartially exposed portions of the photoresist pattern 161 ( Figure 10F in the left figure) and the photoresist pattern 162 ( Figure 10G in the right figure) are thinned to form a photoresist pattern 163 ( Figure 10C in the left figure) and a photoresist pattern 164 ( Figure 10GIn the right figure). The remaining third insulating material layer 133 is etched and the etching thickness is controlled to form the third insulating layer 2460. The third insulating layer 2460 has two parts with different thicknesses. The second insulating layer 2450 includes a first part with a higher thickness and a second part with a lower thickness. The second part with a lower thickness of the third insulating layer 2460 located in the E1 region corresponds to the ninth via hole GH9 and the tenth via hole GH10. The second part with a lower thickness of the third insulating layer 2460 located in the E2 region corresponds to the seventh via hole GH7 and the eighth via hole GH8. Thus, by reducing the height of the local third insulating layer 2460, the heights of the seventh via hole GH7, the eighth via hole GH8, the ninth via hole GH9, and the tenth via hole GH10 can be reduced, the slope angles of the second connection trace 1020 and the first electrode 1151 of the second light-emitting device 1150 can be improved, and the second connection trace 1020 and the first electrode 1151 of the second light-emitting device 1150 can be prevented from breaking.

[0206] For example, as Figure 10H shown, the photoresist pattern 163 ( Figure 10C in the left figure) and the photoresist pattern 164 ( Figure 10G in the right figure) are removed. The third insulating layer 2460 can also be etched and the etching thickness can be controlled to provide a planarized surface.

[0207] For example, Figure 6A for the preparation processes of other film layers of the display substrate shown, such as the first light-emitting device 1140, the second light-emitting device 1150, and the pixel defining layer 1470, etc., reference can be made to Figures 8K - 8M the preparation process shown, and details will not be elaborated here.

[0208] For example, Figure 6B for the preparation process of the display substrate shown, reference can be made to Figures 9A - 9F and Figures 10A - 10H the preparation process, and details will not be elaborated here.

[0209] For example, forming the first trace layer further includes: forming a first virtual trace. As Figure 7 shown, the first virtual trace DML1 is connected to the second end 1012 of the first connection trace 1010, that is, when forming the first trace layer 1510 (as Figure 8C shown), the first virtual trace DML1 is integrally formed with the first connection trace 1010. The extending direction (for example, the second direction Y1) of the first virtual trace DML1 intersects with the extending direction (for example, the first direction X1) of the first connection trace 1010.

[0210] For example, forming the second trace layer further includes: forming a second virtual trace. As Figure 7As shown, the second virtual trace DML2 is connected to the second end 1022 of the second connection trace 1020, that is, when forming the second conductive layer 1520 (such as Figure 8G shown), the second virtual trace DML2 is integrally formed with the second connection trace 1020. The extending direction of the second virtual trace DML2 (such as the second direction Y1) intersects with the extending direction of the second connection trace 1020 (such as the first direction X1). The arrangement of the first virtual trace DML1 and the second virtual trace DML2 can make the traces in the first display area 100 more uniform, thereby making the light transmission in the first display area 100 uniform, and at the same time, it can also improve the etching uniformity of the traces in the first display area 100.

[0211] Figure 11 It is a schematic diagram of a display device provided by at least one embodiment of the present disclosure. At least one embodiment of the present disclosure provides a display device 2000, and the display device 2000 may include the display substrate 1000 of any of the above embodiments.

[0212] For example, as Figure 11 shown, the display device 2000 may further include a flexible circuit board and a control chip. For example, the flexible circuit board is bonded to the bonding area of the display substrate 1000, and the control chip is mounted on the flexible circuit board, thereby being electrically connected to the display area; or, the control chip is directly bonded to the bonding area, thereby being electrically connected to the display area.

[0213] For example, the control chip may be a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include a memory, and may further include a power module, etc., and realizes the power supply and signal input / output functions through separately provided wires, signal lines, etc. For example, the control chip may further include a hardware circuit and computer-executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors such as logic chips, transistors or other discrete components; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0214] For example, the display device 2000 provided by at least one embodiment of the present disclosure may be any product or component with a display function such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. The display device 2000 may further include other components, such as a data driving circuit, a timing controller, etc., and the embodiments of the present disclosure do not limit this.

[0215] For example, as Figure 11As shown, the display device 2000 further includes a sensor 192. The sensor 192 is disposed on the non-display side of the display substrate 1000. The arrangement of the sensor 192 can refer to Figure 1B . The sensor 192 is configured to receive light (such as collimated light or quasi-collimated light) from the display side of the display substrate 1000. The orthographic projection of the sensor 192 on the substrate 140 at least partially overlaps with the first display area 100. Thus, while the first display area 100 realizes display, it also provides convenience for the arrangement of the sensor 192.

[0216] For example, the sensor 192 is an image sensor, an infrared sensor, a distance sensor, etc., and the sensor 192 can be implemented in the form of a chip, etc.

[0217] For example, the sensor 192 can be an image sensor and can be used to collect images of the external environment facing the light-collecting surface of the sensor 192. For example, it can be a CMOS image sensor or a CCD image sensor; the sensor 192 can also be an infrared sensor, a distance sensor, etc. The sensor 192 can be used to implement the cameras of mobile terminals such as mobile phones and laptops, and may further include optical devices such as lenses, mirrors or optical waveguides as needed to modulate the optical path. The embodiments of the present disclosure do not limit the type, function and arrangement of the sensor 192.

[0218] It should be noted that, for clarity and conciseness, the embodiments of the present disclosure do not show all the constituent units of the display device. To implement the substrate functions of the display device, those skilled in the art can provide and arrange other structures not shown according to specific needs, and the embodiments of the present disclosure do not limit this.

[0219] Regarding the technical effects of the display device provided in the above embodiments, reference can be made to the technical effects of the display substrate provided in the embodiments of the present disclosure, which will not be elaborated here.

[0220] The following points need to be noted:

[0221] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0222] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0223] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present disclosure, and all should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for preparing a display substrate, comprising: Providing a substrate, wherein a plurality of pixel driving circuits are formed on the substrate, and the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit; Forming a first insulating layer on the substrate, wherein the first insulating layer is formed to partially expose the plurality of pixel driving circuits; Forming a first wiring layer on the first insulating layer, wherein the first wiring layer includes a first connecting wiring, and the first connecting wiring is formed to be electrically connected to the first pixel driving circuit through the first insulating layer; Forming and patterning a second insulating layer on the first wiring layer; Forming a second wiring layer on the second insulating layer, wherein the second wiring layer includes a second connecting wiring, and the second connecting wiring is formed to be electrically connected to the second pixel driving circuit through the first insulating layer and the second insulating layer; and Forming and patterning a third insulating layer on the second wiring layer; Wherein, the third insulating layer and the second insulating layer are patterned using the same mask.

2. The preparation method according to claim 1, further comprising: Forming a plurality of light-emitting devices on the third insulating layer, Wherein, each of the plurality of light-emitting devices includes a first electrode, the plurality of light-emitting devices include a first light-emitting device and a second light-emitting device, The first electrode of the first light-emitting device is electrically connected to the first connecting wiring through the second insulating layer and the third insulating layer, The first electrode of the second light-emitting device is electrically connected to the second connecting wiring through the third insulating layer.

3. The preparation method according to claim 2, wherein Forming the first insulating layer on the substrate includes: Forming a first via hole and a second via hole in the first insulating layer, wherein the first via hole partially exposes the first pixel driving circuit, and the second via hole partially exposes the second pixel driving circuit.

4. The preparation method according to claim 3, wherein Forming the first wiring layer on the first insulating layer includes: Forming the first end of the first connecting wiring to be electrically connected to the first pixel driving circuit through the first via hole of the first insulating layer, Wherein, the second end of the first connecting wiring is formed to be used for electrically connecting the first light-emitting device.

5. The preparation method according to claim 4, wherein, Forming the second insulating layer includes: Forming a third via hole and a fourth via hole in the second insulating layer, wherein the third via hole exposes the second end of the first connecting wiring, and the orthographic projection of the fourth via hole on the substrate overlaps with the orthographic projection of the second end of the second connecting wiring on the substrate.

6. The preparation method according to claim 5, wherein, Forming the second insulating layer further includes: Forming a fifth via hole and a sixth via hole in the second insulating layer, wherein the fifth via hole overlaps with the orthographic projection of the first via hole on the substrate, and the fifth via hole exposes the first end of the first connecting wiring, and the sixth via hole corresponds to the second via hole.

7. The preparation method according to claim 6, wherein Forming the second wiring layer includes: Forming the first end of the second connecting wiring to be electrically connected to the second pixel driving circuit through the second via hole of the first insulating layer and the sixth via hole in the second insulating layer, Wherein, the second end of the second connecting wiring is formed to be used for connecting the second light-emitting device.

8. The preparation method according to claim 7, wherein, Forming the third insulating layer includes: Forming a seventh via hole and an eighth via hole in the third insulating layer, wherein, the orthographic projection of the seventh via hole on the substrate overlaps with the orthographic projections of the first via hole of the first insulating layer and the fifth via hole of the second insulating layer on the substrate, and the seventh via hole exposes the first end of the first connection trace; the orthographic projection of the eighth via hole on the substrate overlaps with the orthographic projections of the second via hole of the first insulating layer and the sixth via hole of the second insulating layer on the substrate, and the eighth via hole exposes the first end of the second connection trace.

9. The preparation method according to claim 8, wherein, Forming the third insulating layer further includes: Forming a ninth via hole and a tenth via hole in the third insulating layer, wherein, the orthographic projection of the ninth via hole overlaps with the orthographic projection of the third via hole of the second insulating layer on the substrate, and the ninth via hole exposes the second end of the first connection trace; the orthographic projection of the tenth via hole overlaps with the orthographic projection of the fourth via hole of the second insulating layer on the substrate, and the tenth via hole exposes the second end of the second connection trace.

10. The preparation method according to claim 9, wherein, Forming the first electrodes of the plurality of light-emitting devices includes: The first electrode of the first light-emitting device is formed to be connected to the second end of the first connection trace through the third via hole of the second insulating layer and the ninth via hole of the third insulating layer, The first electrode of the second light-emitting device is formed to be connected to the second end of the second connection trace through the tenth via hole of the third insulating layer.

11. The preparation method according to claim 10, wherein, While forming the first electrodes of the plurality of light-emitting devices, a first protective layer and a second protective layer are also formed, The first protective layer covers the seventh via hole of the third insulating layer and the fifth via hole of the second insulating layer, and the second protective layer covers the eighth via hole of the third insulating layer.

12. The preparation method according to claim 6, wherein, Forming the first wiring layer further includes: Forming a first cushion layer at the second via hole of the first insulating layer, wherein, the first cushion layer at least partially covers the second via hole and is electrically connected to the second pixel driving circuit, The sixth via hole of the second insulating layer at least partially exposes the first cushion layer to allow the second connection trace to be electrically connected to the second pixel driving circuit through the first cushion layer.

13. The preparation method according to claim 12, wherein Forming the first wiring layer further includes: Forming a second cushion layer on the first insulating layer, wherein, the second cushion layer is electrically connected to the second end of the second connection trace, and the fourth via hole of the second insulating layer at least partially exposes the second cushion layer.

14. The preparation method according to claim 9, wherein, Forming the second wiring layer further includes: Forming a third cushion layer at the fifth via hole of the second insulating layer, wherein, the third cushion layer at least partially overlaps with the fifth via hole of the second insulating layer, thereby being electrically connected to the first end of the first connection trace, The seventh via hole of the third insulating layer at least partially exposes the third cushion layer to allow electrical connection to the first connection trace through the third cushion layer.

15. The preparation method according to claim 14, wherein Forming the second wiring layer further includes: Forming a fourth cushion layer on the second insulating layer, Wherein, at least a part of the fourth cushion layer overlaps with the third via hole of the second insulating layer and covers the second end of the first connection trace, and at least a part of the ninth via hole of the third insulating layer exposes the fourth cushion layer.

16. The preparation method according to any one of claims 2-15, wherein, Forming the plurality of light-emitting devices further includes: After forming the first electrodes of the plurality of light-emitting devices, forming a pixel defining layer on the first electrodes of the plurality of light-emitting devices and on a side of the third insulating layer away from the substrate. Wherein, the pixel defining layer is formed to include a plurality of first pixel openings, and wherein the plurality of first pixel openings correspond to the plurality of light-emitting devices one by one to form light-emitting regions of the plurality of light-emitting devices. Forming a first light-emitting layer of the plurality of light-emitting devices in the first pixel openings. Forming second electrodes of the plurality of light-emitting devices on a side of the first light-emitting layer and the pixel defining layer away from the substrate.

17. The preparation method according to any one of claims 7-15, wherein, Forming the first trace layer further includes: Forming a first dummy trace, wherein the first dummy trace is connected to the second end of the first connection trace. Forming the second trace layer further includes: Forming a second dummy trace, wherein the second dummy trace is connected to the second end of the second connection trace. Wherein, an extending direction of the first dummy trace intersects an extending direction of the first connection trace, and an extending direction of the second dummy trace intersects an extending direction of the second connection trace.

18. A display substrate having a first side for display and a second side opposite to the first side, comprising: A substrate, comprising: A display area, the display area including a first display area and a second display area at least partially surrounding the first display area. Wherein, the first display area includes a first sub-pixel array, and the first display area allows light from the first side of the display substrate to at least partially transmit to the second side of the display substrate. The first sub-pixel array includes a plurality of light-emitting devices arranged in an array, and the plurality of light-emitting devices include a first light-emitting device and a second light-emitting device. The second display area includes a first pixel driving circuit array, the first pixel driving circuit array includes a plurality of first pixel driving circuit units, and the plurality of first pixel driving circuit units include a first pixel driving circuit and a second pixel driving circuit. A first insulating layer disposed on the substrate, wherein the first insulating layer includes a first via hole and a second via hole, and the first via hole and the second via hole expose the first pixel driving circuit and the second pixel driving circuit respectively. A first connection trace located in the first display area and the second display area, wherein the first connection trace is located on a side of the first insulating layer away from the substrate, a first end of the first connection trace is formed to be electrically connected to the first pixel driving circuit through the first via hole, and a second end of the first connection trace is electrically connected to the first light-emitting device. A second insulating layer disposed on a side of the first insulating layer away from the substrate, wherein the second insulating layer includes a plurality of vias, and wherein the plurality of vias of the second insulating layer are formed to electrically connect the first light-emitting device, the second light-emitting device, the first pixel driving circuit, and the second pixel driving circuit. A second connection trace located in the first display area and the second display area, wherein the second connection trace is located on a side of the second insulating layer away from the substrate, a first end of the second connection trace is formed to be electrically connected to the second pixel driving circuit through the second via and a via in the second insulating layer for connecting the second pixel driving circuit, a second end of the second connection trace is electrically connected to the second light-emitting device, and A third insulating layer disposed on a side of the second insulating layer away from the substrate, the third insulating layer including a plurality of vias. Wherein the plurality of vias of the third insulating layer correspond to the plurality of vias of the second insulating layer one by one to form a plurality of vias penetrating through the second insulating layer and the third insulating layer.

19. The display substrate according to claim 18, wherein Each of the plurality of light-emitting devices includes a first electrode. The first electrode of the first light-emitting device is connected to the second end of the first connection trace through the vias of the second insulating layer and the third insulating layer. The first electrode of the second light-emitting device is connected to the second end of the second connection trace through the vias of the third insulating layer.

20. The display substrate according to claim 19, wherein The plurality of vias of the second insulating layer include a third via, a fourth via, a fifth via, and a sixth via. Wherein the third via and the fourth via are located in the first display area, the third via exposes the second end of the first connection trace, and a positive projection of the fourth via on the substrate overlaps a positive projection of the second end of the second connection trace on the substrate. The fifth via and the sixth via are located in the second display area, a positive projection of the fifth via on the substrate overlaps a positive projection of the first via of the first insulating layer on the substrate, and the fifth via exposes the first end of the first connection trace, and a positive projection of the sixth via on the substrate overlaps a positive projection of the second via of the first insulating layer on the substrate.

21. The display substrate according to claim 20, wherein, The first end of the second connection trace is electrically connected to the second pixel driving circuit through the second via of the first insulating layer and the sixth via in the second insulating layer, and the second end of the second connection trace is for electrically connecting the second light-emitting device.

22. The display substrate according to claim 21, wherein, The plurality of vias of the third insulating layer include a seventh via, an eighth via, a ninth via, and a tenth via. Wherein the seventh via and the eighth via are located in the second display area, a positive projection of the ninth via on the substrate overlaps a positive projection of the third via of the second insulating layer on the substrate, and the ninth via exposes the second end of the first connection trace, and a positive projection of the tenth via on the substrate overlaps a positive projection of the fourth via of the second insulating layer on the substrate, and the tenth via exposes the second end of the second connection trace. The ninth via and the tenth via are located in the first display area. The orthographic projection of the seventh via on the substrate overlaps with the orthographic projections of the first via of the first insulating layer and the fifth via of the second insulating layer on the substrate, and the seventh via exposes the first end of the first connection trace. The orthographic projection of the eighth via on the substrate overlaps with the orthographic projections of the second via of the first insulating layer and the sixth via of the second insulating layer on the substrate, and the eighth via exposes the first end of the second connection trace.

23. The display substrate according to claim 22, wherein, The first electrode of the first light-emitting device is connected to the second end of the first connection trace through the third via of the second insulating layer and the ninth via of the third insulating layer. The first electrode of the second light-emitting device is connected to the second end of the second connection trace through the tenth via of the third insulating layer.

24. The display substrate according to claim 23, wherein The first light-emitting device further includes a first protective layer, and the second light-emitting device further includes a second protective layer. The first protective layer covers the seventh via of the third insulating layer and the fifth via of the second insulating layer, and the second protective layer covers the eighth via of the third insulating layer.

25. The display substrate according to claim 22 further includes a first cushion layer and a second cushion layer. Among them, The first cushion layer at least partially covers the second via of the first insulating layer and is electrically connected to the second pixel driving circuit. The sixth via of the second insulating layer at least partially exposes the first cushion layer to allow the second connection trace to be electrically connected to the second pixel driving circuit through the first cushion layer. The second cushion layer is electrically connected to the second end of the second connection trace, and the fourth via of the second insulating layer at least partially exposes the second cushion layer.

26. The display substrate according to claim 25 further includes a third cushion layer and a fourth cushion layer. Among them, The third cushion layer at least partially overlaps with the fifth via of the second insulating layer to be electrically connected to the first end of the first connection trace, and the seventh via of the third insulating layer at least partially exposes the third cushion layer. The fourth cushion layer at least partially overlaps with the third via of the second insulating layer and is electrically connected to the second end of the first connection trace, and the ninth via of the third insulating layer at least partially exposes the fourth cushion layer.

27. The display substrate according to any one of claims 18-26 further includes a pixel defining layer disposed on the side of the first electrodes of the plurality of light-emitting devices and the third insulating layer away from the substrate. Among them, The pixel defining layer includes a plurality of first pixel openings, wherein the plurality of first pixel openings correspond to the plurality of light-emitting devices one by one to form the light-emitting areas of the plurality of light-emitting devices. The plurality of light-emitting devices further include a first light-emitting layer and a second electrode. The second electrode is located on the side of the pixel defining layer away from the substrate, and the first light-emitting layer is located in the first pixel opening and between the first electrode and the second electrode.

28. The display substrate according to any one of claims 18-26 further includes a first virtual trace and a second virtual trace located in the first display area. Among them, The first virtual trace is connected to the second end of the first connection trace, and the second virtual trace is connected to the second end of the second connection trace. Wherein, the first virtual trace and the first connection trace are arranged on the same layer and integrally formed, the second virtual trace and the second connection trace are arranged on the same layer and integrally formed, the extending direction of the first virtual trace intersects with the extending direction of the first connection trace, and the extending direction of the second virtual trace intersects with the extending direction of the second connection trace.

29. A display device, comprising the display substrate according to any one of claims 18-28.

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