Display device

Abstract

A display device according to embodiments can include a substrate including a display area including a plurality of pixel areas each including an emission area and a non-display area at at least one side of the display area, and a pixel disposed in each of the plurality of pixel areas. The pixel can include a first electrode and a second electrode spaced apart from each other on the substrate, a plurality of light emitting elements connected between the first electrode and the second electrode, and an optical pattern disposed on the plurality of light emitting elements and overlapping at least some of the plurality of light emitting elements. In embodiments, the optical pattern is configured to extract light emitted from the plurality of light emitting elements.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to display devices. Background Technology

[0002] Light-emitting diodes (LEDs) can exhibit relatively satisfactory durability even under harsh environmental conditions, and can perform well in terms of lifespan and brightness.

[0003] To apply LEDs to lighting devices, display devices, and other applications, they need to be connected to electrodes so that a voltage from a power source can be applied to them. Various studies have been conducted regarding the arrangement of LEDs and electrodes, exploring applications for LEDs, methods to reduce the space required for electrodes, and methods for manufacturing LEDs. Summary of the Invention

[0004] Technical issues

[0005] Various embodiments of this disclosure relate to display devices with improved light output efficiency.

[0006] Technical solution

[0007] A display device according to an embodiment of the present disclosure includes: a substrate including a display area and a non-display area, the display area including a plurality of pixel areas, each of the plurality of pixel areas including an emission area, and a non-display area located at at least one side of the display area; and pixels disposed in each of the plurality of pixel areas. A pixel may include: a first electrode and a second electrode spaced apart from each other on the substrate; a plurality of light-emitting elements connected between the first electrode and the second electrode; and an optical pattern disposed on the plurality of light-emitting elements and overlapping at least some of the plurality of light-emitting elements.

[0008] In embodiments of this disclosure, the optical pattern can be configured to extract light emitted from a plurality of light-emitting elements.

[0009] In embodiments of this disclosure, the optical pattern may be a lens.

[0010] In embodiments of this disclosure, the display device may further include an encapsulation layer disposed on the first electrode, the second electrode, and the light-emitting element.

[0011] In embodiments of this disclosure, the optical pattern may be integrated with the encapsulation layer.

[0012] In embodiments of this disclosure, the encapsulation layer may be disposed on an optical pattern.

[0013] In embodiments of this disclosure, the optical pattern may include multiple sub-optical patterns. Each of the multiple sub-optical patterns may group a specific number of light-emitting elements from a plurality of light-emitting elements into a unit, and may be disposed on that unit.

[0014] In embodiments of this disclosure, the multiple sub-optical patterns may have different shapes from each other.

[0015] In embodiments of this disclosure, multiple sub-optical patterns may have the same shape.

[0016] In embodiments of this disclosure, the display device may further include an insulating layer directly disposed on the upper surface of each of the plurality of light-emitting elements. An optical pattern may be disposed on the plurality of light-emitting elements, and the insulating layer is interposed between the optical pattern and the plurality of light-emitting elements.

[0017] In embodiments of this disclosure, the display device may further include: a first contact electrode disposed on an insulating layer and electrically connected to one end of a light-emitting element; and a second contact electrode spaced apart from the first contact electrode on the insulating layer and electrically connected to the other end of a light-emitting element. An optical pattern may cover a portion of the first contact electrode and a portion of the second contact electrode.

[0018] In embodiments of this disclosure, the optical pattern may include light-diffusing particles.

[0019] A display device according to an embodiment of the present disclosure includes: a substrate including a display area and a non-display area, the display area including a plurality of pixel areas, each of the plurality of pixel areas including an emission area, and a non-display area located at at least one side of the display area; and pixels disposed in each of the plurality of pixel areas. A pixel may include: a first electrode and a second electrode spaced apart from each other on the substrate; a plurality of light-emitting elements connected between the first electrode and the second electrode; an insulating optical pattern disposed on the upper surface of each of the plurality of light-emitting elements and extracting light emitted from the plurality of light-emitting elements; a first contact electrode and a second contact electrode spaced apart from each other on the insulating optical pattern; and an encapsulation layer disposed on the first contact electrode and the second contact electrode.

[0020] A display device according to embodiments of the present disclosure may include: a substrate including a display area and a non-display area, the display area including a plurality of pixel areas, each of the plurality of pixel areas including an emission area, and a non-display area surrounding at least one side of the display area; and pixels disposed in each of the plurality of pixel areas. A pixel may include: a first electrode and a second electrode spaced apart from each other on the substrate; a plurality of light-emitting elements connected between the first electrode and the second electrode; an insulating layer disposed on the upper surface of each of the plurality of light-emitting elements; a first contact electrode and a second contact electrode spaced apart from each other on the insulating layer; an encapsulation layer disposed on the first contact electrode and the second contact electrode; and an optical layer disposed on the encapsulation layer.

[0021] In embodiments of this disclosure, the optical layer can be configured to extract light emitted from a plurality of light-emitting elements.

[0022] Beneficial effects

[0023] Embodiments of this disclosure may provide a display device in which an optical pattern is disposed on a light-emitting element to diffuse and / or scatter or focus (or converge) light emitted from the light-emitting element, thereby improving light output efficiency.

[0024] The effects of this disclosure are not limited to the foregoing, and various other effects are anticipated herein. Attached Figure Description

[0025] Figure 1a This is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure.

[0026] Figure 1b It is shown Figure 1a A schematic cross-sectional view of the light-emitting element.

[0027] Figure 2a This is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure.

[0028] Figure 2b It is shown Figure 2a A schematic cross-sectional view of the light-emitting element.

[0029] Figure 3a This is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure.

[0030] Figure 3b It is shown Figure 3a A schematic cross-sectional view of the light-emitting element.

[0031] Figure 4a This is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure.

[0032] Figure 4b It is shown Figure 4a A schematic cross-sectional view of the light-emitting element.

[0033] Figure 5 A display device according to an embodiment of the present disclosure is shown, and in particular, it is used... Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b A schematic plan view of a display device in which any of the light-emitting elements shown serves as the light source.

[0034] Figures 6a to 6e It is shown Figure 5 The circuit diagram shows various implementations of the electrical connection relationships of the components included in a pixel.

[0035] Figure 7a and Figure 7b It is shown Figure 5 The circuit diagram shows various implementations of the electrical connection relationships of the components included in a pixel.

[0036] Figure 8 It is shown schematically. Figure 5 A planar view of one pixel in the pixel diagram shown.

[0037] Figure 9 It is shown schematically. Figure 8 The pixel includes a plan view of components other than the first embankment pattern.

[0038] Figure 10 It is along Figure 8 A schematic cross-sectional view taken from line I-I'.

[0039] Figure 11 yes Figure 10 An enlarged schematic cross-sectional view of part EA.

[0040] Figure 12a and Figure 12b It shows Figure 11 Different implementations of the optical pattern shown, and are related to Figure 10 An enlarged schematic cross-sectional view corresponding to part EA.

[0041] Figure 13 It is along Figure 8 A schematic cross-sectional view taken from line II-II'.

[0042] Figure 14 It shows Figure 13 Another embodiment of the first dike pattern shown, and is related to Figure 8The schematic sectional view corresponding to line II-II'.

[0043] Figure 15 It is along Figure 8 A schematic cross-sectional view taken from line III-III'.

[0044] Figure 16 It shows Figure 10 Another embodiment of the encapsulation layer shown, and is related to Figure 8 The schematic cross-sectional view corresponding to line I-I'.

[0045] Figures 17a to 17c It is shown Figure 8 Schematic plan view of different implementations of pixels.

[0046] Figure 18 This is a schematic plan view of pixels according to an embodiment of the present disclosure.

[0047] Figure 19 It is along Figure 18 A schematic cross-sectional view taken from line IV-IV'.

[0048] Figure 20 It is along Figure 18 A schematic cross-sectional view taken by line V-V'.

[0049] Figure 21 The image shows pixels according to an embodiment of the present disclosure, and is related to... Figure 18 A schematic cross-sectional view corresponding to line IV-IV'.

[0050] Figures 22a to 22d It is shown Figure 21 Schematic cross-sectional views of different implementations of pixels. Detailed Implementation

[0051] Because this disclosure allows for various variations and multiple implementations, specific embodiments will be illustrated in the accompanying drawings and described in detail in the written description. However, this is not intended to limit this disclosure to a particular mode of practice, and it should be understood that all changes, equivalents, and substitutions that do not depart from the technical scope of this disclosure are included herein.

[0052] Throughout this disclosure, the same reference numerals denote the same parts in the various figures and embodiments. For clarity, the dimensions of elements in the figures may be enlarged. It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below may be referred to as a second element without departing from the teachings of this disclosure. Similarly, a second element may also be referred to as a first element. In this disclosure, singular forms are intended to include plural forms as well, unless the context clearly indicates otherwise.

[0053] It should also be understood that, when used in this specification, the terms "comprise," "include," "have," etc., specify the presence of the stated features, integrals, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. Furthermore, when a first portion, such as a layer, film, region, or plate, is disposed on a second portion, the first portion may not only be directly disposed on the second portion, but a third portion may also be disposed between them. Furthermore, when expressing that a first portion, such as a layer, film, region, or plate, is formed on the second portion, the surface on which the first portion is formed is not limited to the upper surface of the second portion, but may include other surfaces such as the side or lower surface of the second portion. Conversely, when a first portion, such as a layer, film, region, or plate, is below the second portion, the first portion may not only be directly below the second portion, but a third portion may also be disposed between them.

[0054] The embodiments and necessary details of this disclosure are described with reference to the accompanying drawings to provide a detailed description of the disclosure, enabling those skilled in the art to readily practice it. Furthermore, the singular form may include the plural form, unless specifically mentioned in the sentence.

[0055] Figure 1a This is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure. Figure 1b It is shown Figure 1a A schematic cross-sectional view of the light-emitting element. Figure 2a This is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure. Figure 2b It is shown Figure 2a A schematic cross-sectional view of the light-emitting element. Figure 3a This is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure. Figure 3b It is shown Figure 3a A schematic cross-sectional view of the light-emitting element. Figure 4a This is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure. Figure 4b It is shown Figure 4a A schematic cross-sectional view of the light-emitting element.

[0056] For the sake of explanation, reference will be made to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b Describes a light-emitting element (LD) manufactured by an etching method, and then refers to... Figure 4a and Figure 4b This invention describes a light-emitting element (LD) manufactured by a growth method. In embodiments of this disclosure, the type and / or shape of the light-emitting element (LD) are not limited to... Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b The implementation shown is as follows.

[0057] refer to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b The light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element (LD) may be implemented as an emitting stack formed by continuously stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0058] In embodiments of this disclosure, the light-emitting element (LD) can be formed into a shape extending in one direction. If the direction in which the light-emitting element (LD) extends is defined as the longitudinal direction, the light-emitting element (LD) can have one end and another end in the extending direction. Either the first semiconductor layer 11 or the second semiconductor layer 13 can be disposed on one end of the light-emitting element (LD), and the other of the first semiconductor layer 11 and the second semiconductor layer 13 can be disposed on the other end of the light-emitting element (LD).

[0059] The light-emitting element (LD) can have various shapes. For example, the LD can have a rod-like or bar-like shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1). In embodiments of this disclosure, the length L of the LD relative to the longitudinal direction can be greater than its diameter (D, or the width of the cross-section). The LD can include a light-emitting diode manufactured to have a small size (e.g., having a length L and / or diameter D corresponding to the micrometer or nanometer scale). In various embodiments of this disclosure, the shape of the LD can be varied to meet the requirements (or design conditions) of a lighting device or a self-emitting display device.

[0060] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For instance, the first semiconductor layer 11 may include an n-type semiconductor layer comprising any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the constituent materials of the first semiconductor layer 11 are not limited to these, and the first semiconductor layer 11 may be formed from various other materials.

[0061] The active layer 12 can be disposed on the first semiconductor layer 11 and has a single quantum well structure or a multiple quantum well structure. The position of the active layer 12 can be varied in various ways depending on the type of light-emitting element (LD). The active layer 12 can emit light with wavelengths from 400 nm to 900 nm and uses a double heterostructure. In embodiments of this disclosure, a cladding layer (not shown) doped with a conductive dopant can be formed above and / or below the active layer 12. For example, the cladding layer can be formed of an AlGaN layer or an InAlGaN layer. In embodiments, materials such as AlGaN or InAlGaN can be used to form the active layer 12, and various other materials can be used to form the active layer 12.

[0062] If a predetermined voltage or a higher electric field is applied between the opposite ends of the light-emitting element (LD), the LD emits light through the coupling of electron-hole pairs in the active layer 12. Since the light emission of the LD can be controlled based on the aforementioned principle, the LD can be used as a light source for various light-emitting devices, including pixels of display devices.

[0063] The second semiconductor layer 13 may be disposed on the active layer 12 and may include a semiconductor layer of a different type than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer comprising any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant such as Mg. However, the materials used to form the second semiconductor layer 13 are not limited to these, and the second semiconductor layer 13 may be formed from various other materials.

[0064] In embodiments of this disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different widths (or thicknesses) relative to the longitudinal direction of the light-emitting element LD. For example, the first semiconductor layer 11 may have a wider width (or thicker thickness) than the second semiconductor layer 13 relative to the longitudinal direction of the light-emitting element LD. Therefore, as... Figures 1a to 3b As shown, the active layer 12 of the light-emitting element LD can be disposed closer to the upper surface of the second semiconductor layer 13 rather than closer to the lower surface of the first semiconductor layer 11.

[0065] In embodiments of this disclosure, in addition to including a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13, the light-emitting element LD may further include an additional electrode 15 disposed on the second semiconductor layer 13. In embodiments, such as Figure 3a and Figure 3b As shown, the light-emitting element LD may also include an additional electrode 16 disposed on one end of the first semiconductor layer 11.

[0066] Although each of the supplementary electrodes 15 and 16 may be an ohmic contact electrode, this disclosure is not limited thereto, and according to embodiments, it may be a Schottky contact electrode. Furthermore, each of the supplementary electrodes 15 and 16 may comprise a metal or a metal oxide. For example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), ITO, and their oxides or alloys may be used alone or in combination with each other. However, this disclosure is not limited thereto.

[0067] The materials included in the respective auxiliary electrodes 15 and 16 may be the same or different from each other. Auxiliary electrodes 15 and 16 may be transparent or translucent. Therefore, light generated from the light-emitting element LD can pass through auxiliary electrodes 15 and 16 and can then be emitted to the outside of the light-emitting element LD. In some embodiments, where light generated from the light-emitting element LD is emitted to the outside of the light-emitting element LD through a region other than the opposite ends of the light-emitting element LD instead of passing through auxiliary electrodes 15 and 16, the auxiliary electrodes 15 and 16 may comprise an opaque metal.

[0068] In embodiments of this disclosure, the light-emitting element LD may further include an insulating layer 14. However, in some embodiments, the insulating layer 14 may be omitted, or it may be configured to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0069] The insulating layer 14 prevents the active layer 12 from short-circuiting due to contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. Furthermore, the insulating layer 14 minimizes surface defects on the light-emitting element (LD), thereby improving the LD's lifespan and efficiency. When multiple LDs are arranged in close contact with each other, the insulating layer 14 prevents unwanted short circuits between the LDs. The presence or absence of the insulating layer 14 is not limited, as long as it prevents short circuits between the active layer 12 and external conductive materials.

[0070] like Figure 1a and Figure 1b As shown, the insulating layer 14 can be shaped to surround the outer peripheral surface of the emitter stack including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15. For the sake of explanation, Figure 1a This shows that a portion of the insulating layer 14 has been removed. The first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15 included in the light-emitting element LD can be surrounded by the insulating layer 14.

[0071] Although in the above embodiments, the insulating layer 14 has been described as surrounding the entire outer peripheral surface of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13 and the additional electrode 15, this disclosure is not limited thereto.

[0072] In some implementations, such as Figure 2a and Figure 2b As shown, the insulating layer 14 may surround the respective outer peripheral surfaces of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, and may not surround the entire outer peripheral surface of the additional electrode 15 disposed on the second semiconductor layer 13, or may surround only a portion of the outer peripheral surface of the additional electrode 15 without surrounding other portions of the outer peripheral surface of the additional electrode 15. Here, the insulating layer 14 may allow at least opposite ends of the light-emitting element LD to be exposed to the outside. For example, the insulating layer 14 may allow not only the additional electrode 15 disposed at one end of the second semiconductor layer 13 to be exposed to the outside, but also one end of the first semiconductor layer 11 to be exposed to the outside. In embodiments, as Figure 3a and Figure 3bAs shown, with the additional electrodes 15 and 16 respectively disposed on opposite ends of the light-emitting element LD, the insulating layer 14 can allow at least a portion of each of the additional electrodes 15 and 16 to be exposed to the outside. Alternatively, in an embodiment, the insulating layer 14 may not be provided.

[0073] In embodiments of this disclosure, the insulating layer 14 may comprise a transparent insulating material. For example, the insulating layer 14 may comprise at least one insulating material selected from the group consisting of SiO2, Si3N4, Al2O3, and TiO2, but is not limited thereto. In other words, various materials with insulating properties can be used.

[0074] If the insulating layer 14 is disposed on the surface of the light-emitting element LD, short circuits between the active layer 12 and the first and / or second electrodes (not shown) can be prevented. Furthermore, due to the insulating layer 14, the occurrence of defects on the surface of the light-emitting element LD can be minimized, thereby improving the lifespan and efficiency of the light-emitting element LD. In the case where multiple light-emitting elements LD are arranged in close contact with each other, the insulating layer 14 can prevent undesirable short circuits between the light-emitting elements LD.

[0075] Light-emitting elements (LDs) can be used as light sources for various display devices. LDs can be manufactured using surface treatment processes. For example, LDs can be surface-treated such that when multiple LDs are mixed with a fluid solution (or solvent) and then supplied to each emitting area (e.g., the emitting area of ​​each pixel or the emitting area of ​​each sub-pixel), the LDs are uniformly distributed in the solution rather than unevenly aggregated.

[0076] Light-emitting devices, including the light-emitting elements (LDs) described above, can be used not only in display devices but also in various other devices that require a light source. For example, when multiple LDs are positioned in the emission area of ​​each pixel on a display panel, the LDs can serve as the light source for the pixels. However, the applications of LDs are not limited to the examples described above. For instance, LDs can also be used in other types of devices that require a light source (such as lighting devices).

[0077] Next, we will refer to Figure 4a and Figure 4b Describes a light-emitting element (LD) manufactured by a growth method.

[0078] The following description of the light-emitting element (LD) manufactured by the growth method will focus on the differences from the embodiments described above, and the components of the LD not separately explained in the following description may be consistent with the components of the foregoing embodiments. The same reference numerals are used to denote the same components, and similar reference numerals are used to denote similar components.

[0079] refer to Figure 4a and Figure 4b According to embodiments of the present disclosure, a light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. In some embodiments, the light-emitting element LD may include an emission pattern 10 having a core-shell structure. The emission pattern 10 may include a first semiconductor layer 11 disposed in the central portion of the light-emitting element LD, an active layer 12 surrounding at least one side of the first semiconductor layer 11, a second semiconductor layer 13 surrounding at least one side of the active layer 12, and an additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0080] The light-emitting element (LD) can be formed as a polygonal pyramid shape extending in one direction. For example, the LD can have a hexagonal pyramid shape. If the direction in which the LD extends is defined as the longitudinal direction, the LD can have one end (or lower end) and another end (or upper end) in the longitudinal direction. A portion of either the first semiconductor layer 11 or the second semiconductor layer 13 on one end (or lower end) of the LD can be exposed to the outside. A portion of the other semiconductor layer 11 or the second semiconductor layer 13 on the other end (or upper end) of the LD can be exposed to the outside. For example, a portion of the first semiconductor layer 11 on one end (or lower end) of the LD can be exposed, and a portion of the second semiconductor layer 13 on the other end (or upper end) of the LD can be exposed. In an embodiment, when the LD includes an additional electrode 15, a portion of the additional electrode 15 surrounding at least one side of the second semiconductor layer 13 on the other end (or upper end) of the LD can be exposed.

[0081] In embodiments of this disclosure, the first semiconductor layer 11 may be disposed in the core (i.e., the central (or middle) portion) of the light-emitting element LD. The light-emitting element LD may have a shape corresponding to the shape of the first semiconductor layer 11. For example, if the first semiconductor layer 11 has a hexagonal pyramid shape, then the light-emitting element LD and the emission pattern 10 may each also have a hexagonal pyramid shape.

[0082] The active layer 12 may be configured and / or formed in a shape that surrounds the outer peripheral surface of the first semiconductor layer 11 in the longitudinal direction of the light-emitting element LD. More specifically, the active layer 12 may be configured and / or formed in a shape that surrounds a region of the first semiconductor layer 11 in the longitudinal direction of the light-emitting element LD, rather than the lower end of the opposite end of the first semiconductor layer 11.

[0083] The second semiconductor layer 13 may be configured and / or formed in a shape surrounding the active layer 12 in the longitudinal direction of the light-emitting element LD, and may include a semiconductor layer of a different type than the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer.

[0084] In embodiments of this disclosure, the light-emitting element (LD) may include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The additional electrode 15 may be an ohmic contact electrode electrically connected to the second semiconductor layer 13, but this disclosure is not limited thereto.

[0085] As described above, the light-emitting element (LD) can have a hexagonal pyramid shape with its opposite ends protruding outwards, and can be implemented as an emission pattern 10 with a core-shell structure. This core-shell structure includes a first semiconductor layer 11 disposed in its central portion, an active layer 12 surrounding the first semiconductor layer 11, a second semiconductor layer 13 surrounding the active layer 12, and an additional electrode 15 surrounding the second semiconductor layer 13. The first semiconductor layer 11 can be disposed at one end (or the lower end) of the light-emitting element LD with the hexagonal pyramid shape, and the additional electrode 15 can be disposed at the other end (or the upper end) of the light-emitting element LD.

[0086] In one embodiment, the light-emitting element LD may further include an insulating layer 14 disposed on the outer peripheral surface of the emission pattern 10 having a core-shell structure. The insulating layer 14 may include a transparent insulating material.

[0087] Figure 5 A display device according to an embodiment of the present disclosure is shown, and in particular, it is used... Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b A schematic plan view of a display device in which any of the light-emitting elements shown serves as the light source.

[0088] For the sake of explanation, Figure 5 The display area DA, on which the image is displayed, schematically illustrates the structure of the display device. In some embodiments, although not shown, at least one drive circuit (e.g., a scan driver and a data driver) and / or multiple lines may also be provided in the display device.

[0089] refer to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a , Figure 4b and Figure 5 The display device according to embodiments of the present disclosure may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB (and each of the pixels PXL includes at least one light-emitting element LD), a driver (not shown) disposed on the substrate SUB and configured to drive the pixels PXL, and a line assembly (not shown) configured to connect the pixels PXL to the driver.

[0090] Based on the method of driving the light-emitting element (LD), display devices can be classified into passive matrix display devices and active matrix display devices. For example, in the case where the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor configured to control the amount of current to be supplied to the light-emitting element (LD) and a switching transistor configured to transmit data signals to the driving transistor.

[0091] Recently, active matrix display devices capable of selectively activating each pixel PXL have become mainstream, considering resolution, contrast ratio, and operating speed. However, this disclosure is not limited to this. For example, passive matrix display devices in which pixels PXL can be activated in groups can also employ components (e.g., a first electrode and a second electrode) for driving light-emitting elements LDs.

[0092] The substrate SUB may include the display area DA and the non-display area NDA.

[0093] In this implementation, the display area DA can be located in the central portion of the display device, and the non-display area NDA can be located in the peripheral portion of the display device surrounding the display area DA. The positions of the display area DA and the non-display area NDA are not limited to these and can be changed.

[0094] The display area DA can be the area where pixels PXL are set for displaying images. The non-display area NDA can be the area where drivers for driving pixels PXL are set and some of the line components for connecting pixels PXL to the drivers are set.

[0095] The display area DA can have various shapes. For example, the display area DA can be configured as a closed polygon shape including linear edges. Alternatively, the display area DA can be configured as a circular shape and / or an elliptical shape including curved edges. As another option, the display area DA can be configured as various shapes, such as semi-circular and semi-elliptical shapes including linear and curved edges.

[0096] The non-display area NDA can be located at at least one side of the display area DA. In embodiments of this disclosure, the non-display area NDA can surround the periphery (or edge) of the display area DA.

[0097] The substrate SUB may include a transparent insulating material that allows light to pass through.

[0098] The substrate SUB can be a rigid substrate. For example, a rigid substrate can be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate. The substrate SUB can also be a flexible substrate.

[0099] One region of the substrate SUB can be configured as a display area DA in which pixel PXL is disposed, and another region of the substrate SUB can be configured as a non-display area NDA. For example, the substrate SUB may include a display area DA and a non-display area NDA disposed around the display area DA, wherein the display area DA includes a plurality of pixel regions in which the corresponding pixel PXL is formed.

[0100] Pixel PXL can be disposed on substrate SUB in display area DA. In embodiments of this disclosure, pixel PXL can be arranged in display area DA in a strip or penTile arrangement structure, but this disclosure is not limited thereto.

[0101] Each of the pixels PXL may include at least one light-emitting element (LD) configured to be driven in response to a corresponding scan signal and a corresponding data signal. The LD may have a small size corresponding to the micrometer or nanometer scale and may be connected in parallel with other LDs arranged adjacent to it, but this disclosure is not limited thereto. The LD may form the light source for each pixel PXL.

[0102] Each of the pixels PXL may include at least one light source, which is driven by a predetermined signal (e.g., a scan signal and a data signal) and / or a predetermined power supply (e.g., a first driving power supply and a second driving power supply). For example, each of the pixels PXL may include Figures 1a to 4b Each of the light-emitting elements (LDs) shown in the embodiments is, for example, at least one ultra-miniature light-emitting element (LD) having a small size corresponding to the nanometer or micrometer scale. However, the types of light-emitting elements (LDs) that can be used as light sources for each of the pixels PXL in the embodiments of this disclosure are not limited to this.

[0103] In embodiments of this disclosure, the color, type, and / or number of pixels PXL are not particularly limited. For example, the color of light emitted from each pixel PXL can be changed in various ways.

[0104] The driver can provide predetermined signals and predetermined electrical voltages to each of the pixels PXL via the line assembly, and thus control the operation of the pixels PXL. For the sake of explanation, in Figure 5 In this example, the line component has been omitted.

[0105] The driver may include: a scan driver configured to provide scan signals to pixel PXL via scan lines; a transmit driver configured to provide transmit control signals to pixel PXL via transmit control lines; a data driver configured to provide data signals to pixel PXL via data lines; and a timing controller. The timing controller can control the scan driver, transmit driver, and data driver.

[0106] Figures 6a to 6e It is shown Figure 5 The circuit diagram shows various implementations of the electrical connection relationships of the components included in a pixel.

[0107] For example, Figures 6a to 6e Different embodiments of the electrical connection relationships of components included in a pixel PXL that can be used in an active display device are shown. However, the types of components included in a pixel PXL that can be applied to embodiments of this disclosure are not limited thereto.

[0108] exist Figures 6a to 6e In China, not only Figure 5 The components included in each of the pixels PXL shown, and the areas in which the components are set, are also included in the definition of the term "pixel PXL". In the implementation, Figures 6a to 6e Each pixel PXL shown can be Figure 5 Any one of the pixels PXL set in the display device. Pixels PXL can have substantially the same or similar structures to each other.

[0109] refer to Figures 1a to 4b , Figure 5 as well as Figures 6a to 6e Each pixel (PXL, hereinafter referred to as "pixel") may include an emission unit EMU configured to generate light with a brightness corresponding to the data signal. Pixel PXL may optionally also include pixel circuitry 144 configured to drive the emission unit EMU.

[0110] In an embodiment, the transmitting unit (EMU) may include a plurality of light-emitting elements (LDs) connected in parallel between a first electric field line PL1 applied by a first driving power supply VDD and a second electric field line PL2 applied by a second driving power supply VSS. For example, the transmitting unit (EMU) may include a first electrode EL1 (or "first alignment electrode") connected to the first driving power supply VDD via pixel circuit 144 and the first electric field line PL1, a second electrode EL2 (or "second alignment electrode") connected to the second driving power supply VSS via the second electric field line PL2, and a plurality of light-emitting elements (LDs) connected in parallel to each other in the same direction between the first electrode EL1 and the second electrode EL2. In embodiments of this disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0111] In embodiments of this disclosure, each of the light-emitting elements (LDs) included in the transmitting unit (EMU) may include a first terminal connected to a first driving power supply VDD via a first electrode EL1 and a second terminal connected to a second driving power supply VSS via a second electrode EL2. The first driving power supply VDD and the second driving power supply VSS may have different potentials. For example, the first driving power supply VDD may be set to a high potential power supply, and the second driving power supply VSS may be set to a low potential power supply. Here, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to be equal to or greater than the threshold voltage of the light-emitting element LD during the emission period of pixel PXL.

[0112] As described above, light-emitting elements (LDs) connected in parallel with each other between the first electrode EL1 and the second electrode EL2 in the same direction (e.g., in the forward direction) can form corresponding effective light sources, and voltages with different potentials are supplied to the first electrode EL1 and the second electrode EL2 respectively. The effective light sources can be collected to form the emission unit (EMU) of the pixel PXL.

[0113] The light-emitting element (LD) of the transmitting unit EMU can emit light with a brightness corresponding to the driving current supplied to it by the pixel circuit 144. For example, during each frame period, the pixel circuit 144 can supply the transmitting unit EMU with a driving current corresponding to the gray level of the corresponding frame data. The driving current supplied to the transmitting unit EMU can be distributed among the light-emitting elements (LDs) connected to each other in the same direction. Therefore, each of the light-emitting elements (LDs) can emit light with a brightness corresponding to the current applied to it, so that the transmitting unit EMU can emit light with a brightness corresponding to the driving current.

[0114] although Figures 6a to 6e An embodiment is shown in which the light-emitting elements (LDs) are connected to each other in the same direction between a first driving power supply VDD and a second driving power supply VSS, but this disclosure is not limited thereto. In the embodiment, in addition to including the light-emitting elements (LDs) that form a corresponding effective light source, the emitting unit (EMU) may also include at least one ineffective light source. For example, such as Figure 6d and Figure 6eAs shown, at least one reverse-emitting element LDr can also be connected between the first electrode EL1 and the second electrode EL2 of the emitting unit EMU. The reverse-emitting element LDr, together with the emitting element LD that forms an effective light source, can be connected in parallel between the first electrode EL1 and the second electrode EL2. Here, the reverse-emitting element LDr can be connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to that of the emitting element LD. Even when a predetermined driving voltage (e.g., a forward driving voltage) is applied between the first electrode EL1 and the second electrode EL2, the reverse-emitting element LDr remains disabled. Therefore, current essentially does not flow through the reverse-emitting element LDr.

[0115] Pixel circuit 144 can be connected to the scan line (e.g., the i-th scan line Si) and data line (e.g., the j-th data line Dj) of the corresponding pixel PXL. For example, if pixel PXL is located in the i-th row (i is a positive integer) and j-th column (j is a positive integer) of display area DA, then pixel circuit 144 of pixel PXL can be connected to the i-th scan line Si and j-th data line Dj of display area DA. In the implementation, as... Figure 6a and Figure 6b As shown, the pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The structure of the pixel circuit 144 is not limited to... Figure 6a and Figure 6b The implementation shown is as follows.

[0116] First, refer to Figure 6a The pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0117] The first terminal of the first transistor (T1; the switching transistor) can be connected to a data line (e.g., the j-th data line Dj), and its second terminal can be connected to the first node N1. Here, the first and second terminals of the first transistor T1 are different terminals, and for example, if the first terminal is the source electrode, the second terminal can be the drain electrode. The gate electrode of the first transistor T1 can be connected to the i-th scan line Si.

[0118] When a scan signal with a voltage (e.g., a low-level voltage) capable of turning on the first transistor T1 is provided from the i-th scan line Si, the first transistor T1 turns on to electrically connect the j-th data line Dj to the first node N1. Here, the data signal of the corresponding frame is provided to the j-th data line Dj, thereby transmitting the data signal to the first node N1. The data signal transmitted to the first node N1 can charge the storage capacitor Cst.

[0119] The first terminal of the second transistor (T2; the driving transistor) can be connected to the first driving power supply VDD, and its second terminal can be electrically connected to the first electrode EL1 of the light-emitting element LD. The gate electrode of the second transistor T2 can be connected to the first node N1. In this way, the second transistor T2 can control the amount of driving current to be supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0120] One electrode of the storage capacitor Cst can be connected to the first drive power supply VDD, and the other electrode can be connected to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to the data signal provided to the first node N1, and the charged voltage is maintained until the data signal of the subsequent frame is provided.

[0121] Figure 6a and Figure 6b Each pixel circuit 144 is shown, which includes a first transistor T1 configured to transmit a data signal to the pixel PXL, a storage capacitor Cst configured to store the data signal, and a second transistor T2 configured to provide a drive current corresponding to the data signal to the light-emitting element LD.

[0122] However, this disclosure is not limited thereto, and the structure of the pixel circuit 144 can be changed in various ways. For example, the pixel circuit 144 may also include at least one transistor element (such as a transistor element configured to compensate the threshold voltage of the second transistor T2, a transistor element configured to initialize the first node N1, and / or a transistor element configured to control the emission time of the light-emitting element LD) or other circuit elements (such as a boost capacitor for increasing the voltage of the first node N1).

[0123] Furthermore, despite Figure 6a The transistors included in the pixel circuit 144 (e.g., the first transistor T1 and the second transistor T2) are shown as being formed of P-type transistors, but this disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 may be changed to an N-type transistor.

[0124] refer to Figures 1a to 4b , Figure 5 and Figure 6b According to embodiments of this disclosure, the first transistor T1 and the second transistor T2 can be formed from N-type transistors. Aside from changes in the connection positions of some components due to the change in transistor type, Figure 6b The configuration and operation of the pixel circuit 144 shown are similar to Figure 6a The configuration and operation of the pixel circuit 144 will be explained. Therefore, the description related to it will be simplified.

[0125] In embodiments of this disclosure, Figure 6b The pixel circuit 144 shown may include a first transistor T1 and a second transistor T2 formed of N-type transistors, and a storage capacitor Cst. When the first transistor T1 and the second transistor T2 are formed of N-type transistors, the transmitter unit EMU may be connected between the first drive power supply VDD and the pixel circuit 144 to ensure the stability of the storage capacitor Cst, which is configured to be charged using a voltage corresponding to the data signal supplied to the first node N1. This disclosure is not limited thereto. In embodiments, Figure 6b The transmitting unit (EMU) shown can be connected between the pixel circuit 144 and the second driving power supply (VSS). In embodiments of this disclosure, the configuration of the pixel circuit 144 is not limited to... Figure 6a and Figure 6b The implementation shown is illustrated. For example, it can be used with... Figure 6c and Figure 6d The pixel circuit 144 is configured in the same manner as the embodiment shown.

[0126] like Figure 6c and Figure 6d As shown, pixel circuit 144 can also be connected to at least one other scan line. For example, pixel PXL, located in the i-th row of display area DA, can also be connected to scan line Si-1 (i-1) and / or scan line Si+1 (i+1). In an embodiment, pixel circuit 144 can be connected not only to the first driving power supply VDD and the second driving power supply VSS, but also to a third power supply. For example, pixel circuit 144 can also be connected to initialization power supply Vint.

[0127] The pixel circuit 144 may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0128] One electrode (e.g., the source electrode) of the first transistor (T1; the driving transistor) can be connected to the first driving power supply VDD via the fifth transistor T5, and its other electrode (e.g., the drain electrode) can be connected to one end of the light-emitting element LD via the sixth transistor T6. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the driving current flowing between the first driving power supply VDD and the second driving power supply VSS via the light-emitting element LD in response to the voltage of the first node N1. The aforementioned first transistor T1 may have the same characteristics as the reference... Figure 6a The configuration of the second transistor T2 described is the same.

[0129] A second transistor (T2; a switching transistor) can be connected between the j-th data line Dj connected to pixel PXL and the source electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the i-th scan line Si connected to pixel PXL. When a scan signal with a gate on-state voltage (e.g., a low-level voltage) is provided from the i-th scan line Si, the second transistor T2 can be turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal provided from the j-th data line Dj can be transmitted to the first transistor T1. The aforementioned second transistor T2 can have the same characteristics as the reference transistor. Figure 6a The configuration of the first transistor T1 described is the same as that described.

[0130] The third transistor T3 can be connected between the drain electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 can be connected to the i-th scan line Si. When a scan signal with a gate on-state voltage is provided from the i-th scan line Si, the third transistor T3 can be turned on to electrically connect the drain electrode of the first transistor T1 to the first node N1.

[0131] The fourth transistor T4 can be connected between the first node N1 and the initialization power line IPL to which the initialization power supply Vint will be applied. The gate electrode of the fourth transistor T4 can be connected to the previous scan line, for example, the (i-1)th scan line Si-1. When a scan signal with a gate-on voltage is provided to the (i-1)th scan line Si-1, the fourth transistor T4 can be turned on, allowing the voltage of the initialization power supply Vint to be transmitted to the first node N1. Here, the initialization power supply Vint can have a voltage equal to or less than the minimum voltage of the data signal.

[0132] The fifth transistor T5 can be connected between the first drive power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to a corresponding emitter control line, for example, the i-th emitter control line Ei. When an emitter control signal with a gate cutoff voltage is provided to the i-th emitter control line Ei, the fifth transistor T5 can be turned off, and under other conditions it can be turned on.

[0133] The sixth transistor T6 can be connected between the first transistor T1 and the first terminal of the light-emitting element LD (which is connected to the second node N2). The gate electrode of the sixth transistor T6 can be connected to the i-th emitter control line Ei. When an emitter control signal with a gate cutoff voltage is provided to the i-th emitter control line Ei, the sixth transistor T6 can be turned off, and under other conditions it can be turned on.

[0134] The seventh transistor T7 can be connected between the initialization power line IPL and the first terminal of the light-emitting element LD. The gate electrode of the seventh transistor T7 can be connected to any of the scan lines in the subsequent group, for example, to the (i+1)th scan line Si+1. When a scan signal with a gate on-state voltage is provided to the (i+1)th scan line Si+1, the seventh transistor T7 can be turned on, so that the voltage of the initialization power supply Vint can be provided to the first terminal of the light-emitting element LD.

[0135] The storage capacitor Cst can be connected between the first drive power supply VDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to both the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0136] Despite Figure 6c and Figure 6d In the pixel circuit 144, the transistors (e.g., the first transistor T1 to the seventh transistor T7) have been shown as being formed of P-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be changed to an N-type transistor.

[0137] In embodiments of this disclosure, the configuration of the pixel circuit 144 is not limited to... Figures 6a to 6d The implementation shown is illustrated. For example, it can be used with... Figure 6e The pixel circuit 144 is configured in the same manner as the embodiment shown.

[0138] like Figure 6e As shown, the pixel circuit 144 can also be connected to a control line (e.g., the i-th control line CLI) and a sensing line (e.g., the j-th sensing line SENj). For example, the pixel circuit 144 of a pixel PXL disposed in the i-th row and j-th column of the display area DA can be connected to the i-th control line CLI and the j-th sensing line SENj of the display area DA. The pixel circuit 144 described above may also include a third transistor T3 and include... Figure 6a and Figure 6b The first transistor T1 and the second transistor T2 are shown in the figure.

[0139] The third transistor T3 is connected between the second transistor T2 and the j-th sensing line SENj. For example, one electrode of the third transistor T3 can be connected to a terminal (e.g., the source electrode) of the second transistor T2, which is connected to the first electrode EL1, and the other electrode of the third transistor T3 can be connected to the j-th sensing line SENj. If the sensing line (e.g., the j-th sensing line SENj) is omitted, the other electrode of the third transistor T3 can be connected to the j-th data line Dj.

[0140] In one embodiment, the gate electrode of the third transistor T3 is connected to the i-th control line CLI. If the i-th control line CLI is omitted, the gate electrode of the third transistor T3 may be connected to the i-th scan line Si. The third transistor T3 may be turned on by a control signal that has a gate on-state voltage (e.g., a high-level voltage) during a predetermined sensing period and is provided to the i-th control line CLI, such that the j-th sensing line SENj and the second transistor T2 can be electrically connected to each other.

[0141] In this embodiment, the sensing period can be the period during which feature information (e.g., the threshold voltage of the second transistor T2) of each pixel PXL disposed in the display area DA is extracted. During the aforementioned sensing period, the second transistor T2 can be turned on by providing a predetermined reference voltage that enables the second transistor T2 to conduct via the j-th data line Dj and the first transistor T1, or by connecting each pixel PXL to a current source. Furthermore, the second transistor T2 can be connected to the j-th sensing line SENj by turning on the third transistor T3 by providing a control signal with a gate conduction voltage to the third transistor T3. Therefore, feature information of each pixel PXL, including the threshold voltage of the second transistor T2, can be extracted via the j-th sensing line SENj. The extracted feature information can be used to convert image data to compensate for feature deviations between pixels PXL.

[0142] although Figure 6e An embodiment is shown in which all of the first transistor T1 to the third transistor T3 are N-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistor T1 to the third transistor T3 can be changed to a P-type transistor. Furthermore, although... Figure 6e An embodiment is shown in which the transmitter unit EMU is connected between the pixel circuit 144 and the second driving power supply VSS, but the transmitter unit EMU can be connected between the first driving power supply VDD and the pixel circuit 144.

[0143] although Figures 6a to 6e An embodiment in which all light-emitting elements (LDs) of each emitting unit (EMU) are connected in parallel with each other is shown, but this disclosure is not limited thereto. In an embodiment, the emitting unit (EMU) may include at least one series group comprising multiple light-emitting elements (LDs) connected in parallel with each other. In other words, the emitting unit (EMU) may be formed by a series / parallel combination structure. Reference will be made below. Figure 7a and Figure 7b Describe the aforementioned configuration.

[0144] The structures applicable to the pixel PXL of this disclosure are not limited to... Figures 6a to 6eThe embodiments shown are illustrated, and the corresponding pixels PXL can have various structures. In the embodiments of this disclosure, each pixel PXL can be configured in a passive light-emitting display device, etc. In this case, the pixel circuit 144 can be omitted, and the opposite ends of the light-emitting element LD included in the emitting unit EMU can be directly connected to the scan lines Si-1, Si and Si+1, the j-th data line Dj, the predetermined control line, the first power line PL1 to be applied with the first driving power VDD and / or the second power line PL2 to be applied with the second driving power VSS.

[0145] Figure 7a and Figure 7b It is shown Figure 5 The circuit diagram illustrates various implementations of the electrical connections of components included in a single pixel. (Example) Figure 7a and Figure 7b As shown, the emission unit (EMU) of each pixel PXL can be configured to include multiple cascaded groups connected sequentially to each other. Figure 7a and Figure 7b In the following description of the implementation methods, terms related to... Figures 6a to 6e Detailed explanations of components similar to or identical to those in the implementation (e.g., detailed explanations of pixel circuit 144) are provided to avoid redundant explanations.

[0146] First, refer to Figure 7a The transmitting unit (EMU) may include multiple light-emitting elements (LDs) connected in series with each other. For example, the transmitting unit (EMU) may include a first light-emitting element LD1, a second light-emitting element LD2, a third light-emitting element LD3, and a fourth light-emitting element LD4 connected in series in the forward direction between a first driving power supply VDD and a second driving power supply VSS, thus forming an effective light source. In the following embodiments, the term "light-emitting element LD" or "multiple light-emitting elements LD" will be used to arbitrarily refer to one of the first light-emitting elements LD1 to the fourth light-emitting element LD4, or to collectively refer to the first light-emitting elements LD1 to the fourth light-emitting elements LD4.

[0147] One end of the first light-emitting element LD1 (e.g., the second semiconductor layer) can be connected to the first driving power supply VDD through the first electrode EL1, and the other end of the first light-emitting element LD1 (e.g., the first semiconductor layer) can be connected to one end of the second light-emitting element LD2 (e.g., the second semiconductor layer) through the first intermediate electrode CTE1 connected between the first series group and the second series group.

[0148] One end of the second light-emitting element LD2 can be connected to the first intermediate electrode CTE1, and the other end of the second light-emitting element LD2 (e.g., the first semiconductor layer) can be connected to one end of the third light-emitting element LD3 (e.g., the second semiconductor layer) through the second intermediate electrode CTE2 connected between the second series group and the third series group.

[0149] One end of the third light-emitting element LD3 can be connected to the second intermediate electrode CTE2, and the other end of the third light-emitting element LD3 (e.g., the first semiconductor layer) can be connected to one end of the fourth light-emitting element LD4 (e.g., the second semiconductor layer) through the third intermediate electrode CTE3 connected between the third series group and the fourth series group.

[0150] One end of the fourth light-emitting element LD4 can be connected to the third intermediate electrode CTE3, and the other end of the fourth light-emitting element LD4 (e.g., the first semiconductor layer) can be connected to the second driving power supply VSS through the second electrode EL2.

[0151] As described above, the first light-emitting element LD1 to the fourth light-emitting element LD4 can be connected in series between the first electrode EL1 and the second electrode EL2 of the emission unit EMU of the pixel PXL.

[0152] In the case of an EMU having a structure in which light-emitting elements (LDs) are connected in series with each other, compared to the case of an EMU having a structure in which light-emitting elements (LDs) are connected in parallel with each other, the voltage applied between the first electrode EL1 and the second electrode EL2 can be increased, and the amount of drive current flowing through the EMU can be reduced. Therefore, when the EMU of each pixel PXL has a series structure, the power consumption of the display device can be reduced.

[0153] In implementations, at least one series group can be arranged in the form of multiple light-emitting elements (LDs) connected in parallel with each other. In this case, the emission unit (EMU) of each pixel PXL can be formed by a series / parallel combination structure. For example, it can be as follows: Figure 7b The transmitter unit (EMU) is configured as shown in the diagram.

[0154] Next, refer to Figure 7bThe emitter unit (EMU) of the pixel PXL may include multiple series groups that are continuously connected to each other between a first driving power supply VDD and a second driving power supply VSS. Each of the series groups may include one or more light-emitting elements (LDs) connected in a forward direction between the two electrodes of the electrode pair constituting the respective series group. For example, the emitter unit (EMU) may include a first series group SET1 to a third series group SET3 that are continuously connected between the first driving power supply VDD and the second driving power supply VSS. Each of the first series group SET1 to the third series group SET3 may include two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 constituting the electrode pair of the respective series group, and multiple light-emitting elements (LDs) connected in parallel between each pair of electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 in a forward direction (i.e., in the same direction).

[0155] The first series group SET1 may include the first electrode EL1 and the second electrode EL2a of the two electrodes EL1 and EL2a, EL2b and EL3a and EL3b and EL4 constituting the electrode pair included in the transmitting unit EMU, and at least one first light-emitting element LD1 connected between the first electrode EL1 and the second electrode EL2a. For example, the first series group SET1 may include the first electrode EL1 connected to the first driving power supply VDD via the pixel circuit 144, the second electrode EL2a connected to the second driving power supply VSS, and a plurality of first light-emitting elements LD1 connected between the first electrode EL1 and the second electrode EL2a. One end (e.g., the second semiconductor layer) of each first light-emitting element LD1 may be electrically connected to the first electrode EL1 of the first series group SET1, and its other end (e.g., the first semiconductor layer) may be electrically connected to the second electrode EL2a of the first series group SET1. The first light-emitting elements LD1 may be connected in parallel between the first electrode EL1 and the second electrode EL2a, and connected between the first electrode EL1 and the second electrode EL2a in the same direction (e.g., the forward direction). In the implementation, at least one reverse light-emitting element (reference) Figure 6e The reverse light-emitting element (LDr) can also be connected to the first series group SET1. The reverse light-emitting element LDr, together with the first light-emitting element LD1 forming the effective light source, can be connected in parallel between the first electrode EL1 and the second electrode EL2a. The reverse light-emitting element LDr can be connected between the first electrode EL1 and the second electrode EL2a in the opposite direction to that of the first light-emitting element LD1. Even when a predetermined driving voltage (e.g., a forward driving voltage) is applied between the first electrode EL1 and the second electrode EL2a, the reverse light-emitting element LDr remains disabled. Therefore, current essentially does not flow through the reverse light-emitting element LDr.

[0156] The second series group SET2 may include the second electrode EL2b and the third electrode EL3a of the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 constituting the electrode pair included in the transmitting unit EMU, and at least one second light-emitting element LD2 connected between the second electrode EL2b and the third electrode EL3a. For example, the second series group SET2 may include the second electrode EL2b connected to the first driving power supply VDD via the pixel circuit 144 and the first series group SET1, the third electrode EL3a connected to the second driving power supply VSS, and a plurality of second light-emitting elements LD2 connected between the second electrode EL2b and the third electrode EL3a. One end of each second light-emitting element LD2 (e.g., the second semiconductor layer) may be electrically connected to the second electrode EL2b of the second series group SET2, and the other end (e.g., the first semiconductor layer) may be electrically connected to the third electrode EL3a of the second series group SET2. The second light-emitting element LD2 can be connected in parallel between the 2b electrode EL2b and the 3a electrode EL3a of the second series group SET2, and connected between the first driving power supply VDD and the second driving power supply VSS through the 2b electrode EL2b and the 3a electrode EL3a in the same direction (e.g., forward direction). In an embodiment, at least one reverse light-emitting element (reference) Figure 6e The LDr can also be connected to the 2b electrode EL2b and the 3a electrode EL3a. The reverse light-emitting element LDr, together with the second light-emitting element LD2 that forms an effective light source, can be connected in parallel between the 2b electrode EL2b and the 3a electrode EL3a. The reverse light-emitting element LDr can be connected between the 2b electrode EL2b and the 3a electrode EL3a in a direction opposite to that of the second light-emitting element LD2.

[0157] In embodiments of this disclosure, the second a electrode EL2a of the first series group SET1 and the second b electrode EL2b of the second series group SET2 can be integrally disposed and connected to each other. In other words, the second a electrode EL2a of the first series group SET1 and the second b electrode EL2b of the second series group SET2 can form a second electrode EL2 that electrically connects the first series group SET1 and the second series group SET2. As described above, when the second a electrode EL2a of the first series group SET1 and the second b electrode EL2b of the second series group SET2 are integrally disposed, the second a electrode EL2a and the second b electrode EL2b can be different regions of the second electrode EL2.

[0158] The third series group SET3 may include at least one third light-emitting element LD3 connected between the third electrode EL3b and the fourth electrode EL4 of the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 of the electrode pairs comprising the transmitting unit EMU. For example, the third series group SET3 may include a third electrode EL3b connected to a first driving power supply VDD via pixel circuit 144 and a previous series group (e.g., first series group SET1 and second series group SET2), a fourth electrode EL4 connected to a second driving power supply VSS, and a plurality of third light-emitting elements LD3 connected between the third electrode EL3b and the fourth electrode EL4. One end (e.g., the second semiconductor layer) of each third light-emitting element LD3 may be electrically connected to the third electrode EL3b of the third series group SET3, and the other end (e.g., the first semiconductor layer) may be electrically connected to the fourth electrode EL4 of the third series group SET3. The third light-emitting elements LD3 may be connected in parallel with each other between the third electrode EL3b and the fourth electrode EL4 of the third series group SET3. The third light-emitting element LD3 can be connected in the same direction (e.g., in the forward direction) between the first driving power supply VDD and the second driving power supply VSS via the third electrode EL3b and the fourth electrode EL4. In an embodiment, at least one reverse light-emitting element (reference) Figure 6e The LDr can also be connected between the 3b electrode EL3b and the fourth electrode EL4. The reverse light-emitting element LDr, together with the third light-emitting element LD3 that forms an effective light source, can be connected in parallel between the 3b electrode EL3b and the fourth electrode EL4. The reverse light-emitting element LDr can be connected between the 3b electrode EL3b and the fourth electrode EL4 in the opposite direction to that of the third light-emitting element LD3.

[0159] In embodiments of this disclosure, the third electrode EL3a of the second series group SET2 and the third electrode EL3b of the third series group SET3 can be integrally disposed and connected to each other. In other words, the third electrode EL3a of the second series group SET2 and the third electrode EL3b of the third series group SET3 can form a third electrode EL3 that electrically connects the second series group SET2 and the third series group SET3. As described above, when the third electrode EL3a of the second series group SET2 and the third electrode EL3b of the third series group SET3 are integrally disposed, the third electrode EL3a and the third electrode EL3b can be different regions of the third electrode EL3.

[0160] In the aforementioned embodiments, the first electrode EL1 of the first tandem group SET1 can be the anode electrode of the emitter unit EMU of each pixel PXL. The fourth electrode EL4 of the third tandem group SET3 can be the cathode electrode of the emitter unit EMU.

[0161] As described above, in the emitter unit EMU of the pixel PXL, which includes light-emitting elements LD connected to each other in a series / parallel combination structure, the drive current / voltage conditions can be easily adjusted in response to the specifications of the product to which the emitter unit EMU is applied.

[0162] Specifically, the driving current in an emitter unit EMU comprising light-emitting elements (LDs) connected in parallel can be reduced compared to the driving current in an emitter unit EMU comprising LDs connected in series / parallel configurations. Furthermore, the driving voltage applied to opposite ends of the emitter unit EMU comprising LDs connected in series / parallel configurations can be reduced compared to the driving voltage in an emitter unit EMU comprising all LDs connected in series. When all LDs are connected in series, if at least one of the LDs connected in series is not properly oriented in the forward direction (or includes a reverse-emitting element LDr), dark spot defects may occur when the driving current can be blocked along its flow path in the pixel PXL. On the other hand, when the LDs are connected in series / parallel configurations, even if some LDs in each series group are not correctly connected in the forward direction (or include a reverse-emitting element LDr) or defects occur in some LDs, the driving current is allowed to flow through the other LDs in the corresponding series group. Therefore, defects in pixel PXL can be prevented or reduced.

[0163] Figure 8 It is shown schematically. Figure 5 A planar view of one pixel in the pixel diagram shown.

[0164] Figure 9 It is shown schematically. Figure 8 The pixel includes a plan view of components other than the first embankment pattern. Figure 10 It is along Figure 8 A sectional view taken from line I-I'. Figure 11 yes Figure 10 An enlarged sectional view of part EA. Figure 12a and Figure 12b It shows Figure 11 Different implementations of the optical pattern shown, and are related to Figure 10 The enlarged sectional view corresponding to part EA. Figure 13 It is along Figure 8 The sectional view taken from line II-II'. Figure 14 It shows Figure 13 Another embodiment of the first dike pattern shown, and is related to Figure 8 The sectional view corresponding to line II-II'. Figure 15 It is along Figure 8 The sectional view taken from line III-III'.

[0165] Figure 8 The pixel PXL shown can be in Figures 6a to 6e , Figure 7a and Figure 7b Any one of the pixels PXL shown. For example, Figure 8 The pixel PXL shown can be Figure 6a The pixel PXL shown in the image.

[0166] For the sake of explanation, in Figure 8 The diagram omits the transistor connected to the light-emitting element LD and the signal lines connected to the transistor.

[0167] although Figures 8 to 15 The structure of the pixel PXL is simply illustrated, for example, showing that each electrode is formed by a single electrode layer and each insulating layer is formed by a single insulating layer, but this disclosure is not limited thereto.

[0168] Furthermore, in the description of the embodiments of this disclosure, "components are disposed and / or formed on the same layer" may mean that the components are formed by the same process, and "components are disposed and / or formed on different layers" may mean that the components are formed by different processes.

[0169] refer to Figures 1a to 5 , Figure 6a as well as Figures 8 to 15 The display device according to embodiments of the present disclosure may include a substrate SUB, a line assembly, and a plurality of pixels PXL.

[0170] The substrate SUB may include a transparent insulating material that allows light to pass through. The substrate SUB may be a rigid substrate or a flexible substrate.

[0171] For example, a rigid substrate can be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate. A flexible substrate can be a film substrate or a plastic substrate comprising a polymeric organic material. For example, a flexible substrate can include at least one of the following: polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0172] However, the materials constituting the substrate SUB can be varied and include, for example, fiber-reinforced plastic (FRP). During the manufacturing process of the display device, the materials applied to the substrate SUB can be resistant to high processing temperatures (heat resistance).

[0173] The substrate SUB may include a display area DA and a non-display area NDA disposed around the display area DA, wherein the display area DA includes at least one pixel area PXA in which a pixel PXL is disposed.

[0174] In one embodiment, the pixel PXL may be arranged in a matrix shape and / or a stripe shape in the display area DA along a plurality of pixel rows extending along a first direction DR1 and a plurality of pixel columns extending along a second direction DR2 intersecting the first direction DR1, but this disclosure is not limited thereto. In another embodiment, the pixel PXL may be disposed on the substrate SUB in the display area DA in various arrangements.

[0175] The pixel region PXA that sets (or provides) each pixel PXL may include an emission region EMA that emits light and a peripheral region surrounding the emission region EMA. In embodiments of this disclosure, the term "peripheral region" may include a non-emission region from which no light is emitted.

[0176] Each pixel PXL may include a pixel circuit layer PCL disposed on a substrate SUB and including pixel circuitry 144, and a display element layer DPL including multiple light-emitting elements LDs. The light-emitting elements LDs may be disposed in the emission region EMA of the pixel region PXA of each pixel PXL.

[0177] For simplicity, the pixel circuit layer PCL will be described first, and then the display element layer DPL will be described.

[0178] The pixel circuit layer PCL may include pixel circuit 144 and passivation layer PSV. Pixel circuit 144 includes buffer layer BFL, at least one transistor T, storage capacitor Cst, driving voltage line DVL, etc.

[0179] The buffer layer (BFL) prevents impurities from diffusing into the transistor (T). While the buffer layer (BFL) can be a single-layer structure, it can also be a multilayer structure with two or more layers. In the case of a multilayer buffer layer (BFL), the layers can be formed from the same material or different materials. Depending on the material of the substrate (SUB) or the processing conditions, the buffer layer (BFL) can be omitted.

[0180] Transistor T may include a first transistor T1 and a second transistor T2. The first transistor T1 is a driving transistor used to control the amount of driving current supplied to the light-emitting element (LD), and the second transistor T2 is a switching transistor. In embodiments of this disclosure, the first transistor T1 may be a reference transistor. Figure 6a The second transistor T2 of the pixel circuit 144 described or referenced Figure 6c The pixel circuit 144 is described with a first transistor T1. The second transistor T2 can be a reference. Figure 6a The first transistor T1 or reference of the pixel circuit 144 described Figure 6c The second transistor T2 of the pixel circuit 144 is described. In the following embodiments, the term "transistor T" or "a plurality of transistors T" will be used to refer to either the first transistor T1 or the second transistor T2, or to refer to both the first transistor T1 and the second transistor T2 together.

[0181] Each of the first transistor T1 and the second transistor T2 may include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be a source electrode or a drain electrode, and the second terminal DE may be another electrode. For example, if the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

[0182] A transistor semiconductor pattern SCL can be disposed and / or formed on a buffer layer BFL. The transistor semiconductor pattern SCL may include a first contact region contacting a first terminal SE and a second contact region contacting a second terminal DE. The region between the first and second contact regions may be a channel region. The transistor semiconductor pattern SCL may be a semiconductor panel formed of polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The channel region may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the first and second contact regions may be a doped semiconductor pattern.

[0183] The gate electrode GE can be disposed and / or formed on the transistor semiconductor pattern SCL, and the gate insulating layer GI is interposed between the gate electrode GE and the transistor semiconductor pattern SCL.

[0184] The first terminal SE and the second terminal DE can contact the first contact area and the second contact area of ​​the transistor semiconductor pattern SCL respectively through the corresponding contact holes passing through the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the gate insulating layer GI.

[0185] Although in the foregoing embodiments, the first terminal SE and the second terminal DE of each of the first transistor T1 and the second transistor T2 have each been described as separate electrodes electrically connected to the transistor semiconductor pattern SCL through contact holes passing through the gate insulating layer GI and the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, this disclosure is not limited thereto. In embodiments, the first terminal SE of each of the first transistor T1 and the second transistor T2 may be a contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL in the first contact region and the second contact region. The second terminal DE of each of the first transistor T1 and the second transistor T2 may be another contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL in the first contact region and the second contact region. In this case, the second terminal DE of each of the first transistor T1 and the second transistor T2 may be electrically connected to the light-emitting element LD of the corresponding pixel PXL through bridge electrodes, contact electrodes, etc.

[0186] In embodiments of this disclosure, each of the transistors T included in the pixel circuit 144 may be formed of an LTPS thin-film transistor, but this disclosure is not limited thereto. In one or more embodiments, each transistor T may be formed of an oxide semiconductor thin-film transistor. Furthermore, cases have been shown in which each of the transistors T is a thin-film transistor having a top-gate structure, but this disclosure is not limited thereto. In embodiments, each of the transistors T may be a thin-film transistor having a bottom-gate structure.

[0187] In an implementation, the transistor T included in the pixel circuit layer PCL may include not only the first transistor T1 and the second transistor T2, but may also include additional transistors, such as a transistor for compensating the threshold voltage of the first transistor T1 and a transistor for controlling the emission time of each of the light-emitting elements LD.

[0188] The storage capacitor Cst may include a lower electrode LE disposed on the gate insulating layer GI and an upper electrode UE disposed on the first interlayer insulating layer ILD1 and overlapping the lower electrode LE.

[0189] The lower electrode LE can be disposed on the same layer as the gate electrode GE of the first transistor T1, and includes the same material as the gate electrode GE. In an embodiment, the lower electrode LE can be integrally disposed with the gate electrode GE of the first transistor T1, or it can be disposed as a component separate from the gate electrode GE.

[0190] The upper electrode UE can overlap with and cover the lower electrode LE. The capacity of the storage capacitor Cst can be increased by increasing the overlap area between the upper electrode UE and the lower electrode LE. The upper electrode UE can be connected to the first electric field line (reference). Figure 6a The first drive power supply VDD applied to the first electric field line PL1 is electrically connected. Therefore, the voltage of the first drive power supply VDD applied to the first electric field line PL1 can be transmitted to the upper electrode UE. A second interlayer insulating layer ILD2 can be disposed on the upper electrode UE. The second interlayer insulating layer ILD2 can be an inorganic insulating layer including inorganic materials or an organic insulating layer including organic materials.

[0191] The drive voltage line DVL can be set on the second interlayer insulation layer ILD2. Figure 6a In the pixel PXL shown, the driving voltage line DVL can be the second power line PL2 to which the voltage of the second driving power supply VSS is applied.

[0192] The passivation layer PSV can be disposed and / or formed on the drive voltage line DVL and the transistor T.

[0193] The passivation layer PSV can be in the form of an organic insulating layer, an inorganic insulating layer, or a structure including an organic insulating layer disposed on an inorganic insulating layer. The inorganic insulating layer may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiON) and metal oxides (such as AlO) x At least one of the following: . The organic insulating layer may include an organic insulating material that allows light to pass through. The organic insulating layer may include at least one of, for example, polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0194] Next, the display element layer DPL for each of the pixels PXL will be described.

[0195] The display element layer (DPL) may include a first dam pattern (BNK1) and a second dam pattern (BNK2), a first electrode (EL1) and a second electrode (EL2), a first connecting line (CNL1) and a second connecting line (CNL2), a light-emitting element (LD), and contact electrodes (CNE1 and CNE2).

[0196] The first embankment pattern BNK1 can be a support component that supports each of the first electrode EL1 and the second electrode EL2 in order to change the surface profile of each of the first electrode EL1 and the second electrode EL2, so that the light emitted from the light-emitting element LD can travel more effectively in the image display direction of the display device.

[0197] The first dam pattern BNK1 may be disposed and / or formed between the passivation layer PSV and the first electrode EL1 and the second electrode EL2 in the emission region EMA of each pixel PXL. For example, the first dam pattern BNK1 may be disposed and / or formed between the passivation layer PSV and the first electrode EL1, and between the passivation layer PSV and the second electrode EL2. The first dam pattern BNK1 may include an inorganic insulating layer formed of an inorganic material, or an organic insulating layer formed of an organic material. In embodiments, the first dam pattern BNK1 may include an organic insulating layer having a single-layer structure and / or an inorganic insulating layer having a single-layer structure, but this disclosure is not limited thereto. In embodiments, the first dam pattern BNK1 may be provided in the form of a multilayer structure formed by stacking at least one organic insulating layer and at least one inorganic insulating layer. However, the material of the first dam pattern BNK1 is not limited to the foregoing embodiments. In embodiments, the first dam pattern BNK1 may include a conductive material.

[0198] The first embankment pattern BNK1 may have a trapezoidal cross-section whose width decreases upward from one surface of the passivation layer PSV, but this disclosure is not limited thereto. In embodiments, the first embankment pattern BNK1 may include a curved surface having a cross-section with a semi-elliptical shape, a semi-circular shape (or a hemispherical shape), etc., whose width decreases upward from one surface of the passivation layer PSV, such as... Figure 14 As shown in the diagram. In the cross-sectional view, the shape of the first dam pattern BNK1 is not limited to the aforementioned embodiment and can be varied in various ways to improve the efficiency of light emitted from each of the light-emitting elements LD. The first dam patterns BNK1 adjacent to each other can be disposed on the same plane on the passivation layer PSV and have the same height (or thickness).

[0199] Although the first embankment pattern BNK1 in the plan view may have a rod-like shape extending in one direction (e.g., the second direction DR2 (vertical direction)), this disclosure is not limited thereto, and its shape may be changed to various shapes.

[0200] The second dam pattern BNK2 may surround at least one side of the peripheral region of each pixel PXL. The second dam pattern BNK2 may be a structure configured to define (or divide) a corresponding emission region EMA of each pixel PXL and its neighboring pixels PXL, and may be, for example, a pixel defining layer. The second dam pattern BNK2 may include at least one light-blocking material and / or a reflective material to prevent light (or rays) leakage defects between each pixel PXL and its neighboring pixels PXL. In embodiments, a reflective material layer may be formed on the second dam pattern BNK2 to further improve the efficiency of light emitted from each pixel PXL. Although the second dam pattern BNK2 may be formed and / or disposed on a layer different from the layer of the first dam pattern BNK1, this disclosure is not limited thereto. In embodiments, the second dam pattern BNK2 may be formed and / or disposed on the same layer as the first dam pattern BNK1. In embodiments of this disclosure, the second dam pattern BNK2 may be formed on a layer different from the layer of the first dam pattern BNK1 and disposed on the first insulating layer INS1.

[0201] The first connection line CNL1 may extend in a first direction DR1 (e.g., "horizontal direction") in each of the pixels PXL. The first connection line CNL1 may be configured and / or formed to drive each pixel PXL independently or separately from neighboring pixels PXL only in each pixel PXL, and is electrically and / or physically separated from the first connection line CNL1 configured and / or formed in each of the neighboring pixels PXL. The first connection line CNL1 configured in each pixel PXL may be electrically connected to a component (e.g., a first transistor T1) included in the pixel circuit layer PCL of the corresponding pixel PXL through a first contact hole CH1 through the passivation layer PSV.

[0202] The second connection line CNL2 can extend in a direction parallel to the direction in which the first connection line CNL1 extends. For example, the second connection line CNL2 can extend in the first direction DR1. The second connection line CNL2 can be shared for each pixel PXL and its neighboring pixels PXL. Therefore, multiple pixels PXL disposed on the same pixel row in the first direction DR1 can be jointly connected to the second connection line CNL2. The second connection line CNL2 disposed in each pixel PXL can be electrically connected to a component (e.g., a drive voltage line DVL) included in the pixel circuit layer PCL of the corresponding pixel PXL through a second contact hole CH2 passing through the passivation layer PSV. Therefore, the voltage of the second drive power supply VSS applied to the drive voltage line DVL can be transmitted to the second connection line CNL2.

[0203] Each of the first electrode EL1 and the second electrode EL2 can be disposed in the emission region EMA of each pixel PXL and extend in one direction (e.g., the second direction DR2). The first electrode EL1 and the second electrode EL2 can be disposed on the same surface and spaced apart from each other.

[0204] The first electrode EL1 may include a first-1 electrode EL1_1 and a first-2 electrode EL1_2 branching off from the first connecting line CNL1 in the second direction DR2. The first-1 electrode EL1_1, the first-2 electrode EL1_2, and the first connecting line CNL1 may be integrally formed and electrically and / or physically connected to each other. When the first electrode EL1 and the first connecting line CNL1 are integrally formed, the first connecting line CNL1 may be a region of the first electrode EL1, or the first electrode EL1 may be a region of the first connecting line CNL1. This disclosure is not limited thereto. In one or more embodiments, the first electrode EL1 and the first connecting line CNL1 may be formed separately and electrically connected to each other via contact holes, connectors, etc. (not shown).

[0205] The second electrode EL2 may branch off from the second connecting line CNL2 in the second direction DR2. The second electrode EL2 and the second connecting line CNL2 may be integrally formed and electrically and / or physically connected to each other. When the second electrode EL2 and the second connecting line CNL2 are integrally formed, the second connecting line CNL2 may be a region of the second electrode EL2, or the second electrode EL2 may be a region of the second connecting line CNL2. However, this disclosure is not limited thereto. In one or more embodiments, the second electrode EL2 and the second connecting line CNL2 may be formed separately and electrically connected to each other via contacts, connectors, etc., not shown.

[0206] The second electrode EL2 can be disposed between the first electrode EL1_1 and the first electrode EL1_2. The first electrode EL1_1 and the second electrode EL2 can be separated from each other by a predetermined distance. The second electrode EL2 and the first electrode EL1_2 can be separated from each other by a predetermined distance. In the emission region EMA of each pixel PXL, the distance between the first electrode EL1_1 and the second electrode EL2, and the distance between the second electrode EL2 and the first electrode EL1_2, can be the same. Therefore, the light-emitting element LD can be arranged more uniformly in the emission region EMA of each pixel PXL. However, this disclosure is not limited thereto. In embodiments, the distance between the first electrode EL1_1 and the second electrode EL2, and the distance between the second electrode EL2 and the first electrode EL1_2, can be different from each other.

[0207] Each of the first electrode EL1 and the second electrode EL2 may be disposed and / or formed on the first embankment pattern BNK1 and have a surface profile corresponding to the shape of the first embankment pattern BNK1. For example, each of the first electrode EL1 and the second electrode EL2 may include a protrusion corresponding to the first embankment pattern BNK1 and a planar portion corresponding to the passivation layer PSV. Each of the first electrode EL1 and the second electrode EL2 may be formed of a material having a predetermined reflectivity to allow light emitted from each of the light-emitting elements LD to travel in the image display direction of the display device.

[0208] Each of the first electrode EL1 and the second electrode EL2 can be made of a conductive material having a predetermined reflectivity. The conductive material can include an opaque metal, which has the advantage of reflecting light emitted from the light-emitting element LD in the image display direction of the display device. The opaque metal can include, for example, metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and alloys thereof. In embodiments, each of the first electrode EL1 and the second electrode EL2 can include a transparent conductive material. The transparent conductive material can include conductive oxides (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO)) or conductive polymers (such as PEDOT). When each of the first electrode EL1 and the second electrode EL2 includes a transparent conductive material, a separate conductive layer formed of an opaque metal may also be included for reflecting light emitted from the light-emitting element LD in the image display direction of the display device. However, the material of each of the first electrode EL1 and the second electrode EL2 is not limited to the aforementioned materials.

[0209] Although each of the first electrode EL1 and the second electrode EL2 can be configured and / or formed as a single-layer structure, this disclosure is not limited thereto. In embodiments, each of the first electrode EL1 and the second electrode EL2 can be configured and / or formed as a multilayer structure by stacking at least two materials selected from metals, alloys, conductive oxides, and conductive polymers. Each of the first electrode EL1 and the second electrode EL2 can have a multilayer structure comprising at least two layers to minimize distortion caused by signal delay when a signal (or voltage) is transmitted to opposite ends of each of the light-emitting elements LD. For example, each of the first electrode EL1 and the second electrode EL2 can have a multilayer structure in which the layers are stacked in the order of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0210] When the first connecting line CNL1 is integrally formed with the first electrode EL1, the first connecting line CNL1 may contain the same material as the first electrode EL1. When the second connecting line CNL2 is integrally formed with the second electrode EL2, the second connecting line CNL2 may contain the same material as the second electrode EL2.

[0211] As described above, since each of the first electrode EL1 and the second electrode EL2 has a surface profile corresponding to the shape of the first embankment pattern BNK1 disposed below it, light emitted from each of the light-emitting elements LD can be reflected by each of the first electrode EL1 and the second electrode EL2, and travel more efficiently in the image display direction of the display device. Therefore, the efficiency of light emitted from each of the light-emitting elements LD can also be improved.

[0212] The first dam pattern BNK1, the first electrode EL1, and the second electrode EL2 can each be used as a reflective component configured to guide light emitted from the light-emitting element LD in a desired direction, thereby improving the optical efficiency of the display device. In other words, the first dam pattern BNK1, the first electrode EL1, and the second electrode EL2 can each be used as a reflective component configured to allow light emitted from the light-emitting element LD to travel in the image display direction of the display device, thereby improving the light output efficiency of the light-emitting element LD.

[0213] Either the first electrode EL1 or the second electrode EL2 can be an anode electrode, and the other electrode can be a cathode electrode. In embodiments of this disclosure, the first electrode EL1 can be an anode electrode, and the second electrode EL2 can be a cathode electrode.

[0214] Each of the light-emitting elements (LDs) can be formed from a material having an inorganic crystal structure and having an ultra-small size, for example, from the nanometer to the micrometer scale. For example, each of the light-emitting elements (LDs) can be an ultra-small light-emitting element manufactured by an etching process or an ultra-small light-emitting element manufactured by a growth process. For example, such as... Figure 11 As shown, each of the light-emitting elements (LDs) can be a light-emitting element manufactured by an etching process, and includes an emission stack pattern formed by continuously stacking a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13 in the longitudinal direction, and an insulating layer 14 configured to surround the outer peripheral surface (or surface) of the emission stack pattern. The type, size, shape, etc. of the light-emitting elements (LDs) can be varied in various ways.

[0215] Although at least two to dozens of light-emitting elements (LDs) can be aligned and / or arranged in the emission region EMA of each pixel PXL, the number of LDs is not limited to this. In implementations, the number of LDs aligned and / or arranged in the emission region EMA of each pixel PXL can be varied in various ways.

[0216] In embodiments of this disclosure, each of the light-emitting elements (LDs) can emit light of any color and / or white light. Each of the LDs can be aligned between a first electrode EL1 and a second electrode EL2 such that the longitudinal direction is parallel to the first direction DR1. The LDs can be diffused in a solution and provided to the emission region EMA of each pixel PXL.

[0217] In embodiments of this disclosure, the light-emitting element (LD) can be provided to the emitting region EMA of each pixel PXL via inkjet printing, slot coating, or various other methods. For example, the LD can be mixed with a volatile solvent and then provided to the emitting region EMA of each pixel PXL via inkjet printing or slot coating. Here, if corresponding alignment signals (or alignment voltages) are provided to the first electrode EL1 and the second electrode EL2 disposed in the emitting region EMA of each pixel PXL, an electric field can be formed between the first electrode EL1 and the second electrode EL2. Therefore, the LD can be aligned between the first electrode EL1 and the second electrode EL2.

[0218] After the light-emitting element (LD) is aligned, the solvent can be removed by evaporation or other methods. As a result, the LD can be finally aligned and / or positioned in the emission region EMA of each pixel PXL.

[0219] When the light-emitting element LD is aligned in the emission region EMA of pixel PXL, each of the first electrode EL1 and the second electrode EL2 can be used as an alignment electrode (or alignment line), and a predetermined alignment signal (or alignment voltage) is applied to the alignment electrode (or alignment line) to align the light-emitting element LD. For example, the first electrode EL1 can be a first alignment electrode (or first alignment line) configured to receive a first alignment signal (or first alignment voltage) from a first connection line CNL1. The second electrode EL2 can be a second alignment electrode (or second alignment line) configured to receive a second alignment signal (or second alignment voltage) from a second connection line CNL2. The first alignment signal and the second alignment signal can have different voltage levels. The first alignment signal and the second alignment signal can be signals having a voltage difference and / or phase difference that enables the light-emitting element LD to align between the first electrode EL1 and the second electrode EL2. For example, the first alignment signal can be a ground voltage, and the second alignment signal can be an alternating current (AC) signal, but this disclosure is not limited thereto. In embodiments, both the first alignment signal and the second alignment signal can be AC ​​signals.

[0220] After the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the first electrode EL1 and the second electrode EL2 can be used as driving electrodes for driving the light-emitting element LD.

[0221] When the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the light-emitting element LD provided to the emission region EMA can be controlled to be relatively biased and aligned by controlling the alignment signal (or alignment voltage) applied to the first electrode EL1 and the second electrode EL2 respectively or by forming a magnetic field.

[0222] Each of the light-emitting elements (LDs) may include a first end EP1 electrically connected to one of two adjacent electrodes in the emission region EMA of each pixel PXL, and a second end EP2 electrically connected to the other of the two adjacent electrodes. In embodiments of this disclosure, the first end EP1 of each LD may be a first semiconductor layer 11 including an n-type semiconductor layer, and its second end EP2 may be a second semiconductor layer 13 including a p-type semiconductor layer. In other words, in the emission region EMA of each pixel PXL, each LD may be connected in a forward direction between two adjacent electrodes, which are spaced at a predetermined distance. As described above, the LDs connected in a forward direction between two adjacent electrodes can form an effective light source for the emission unit EMU of each pixel PXL.

[0223] The light-emitting element (LD) may include a first light-emitting element (LD1) and a second light-emitting element (LD2). For example, the light-emitting element (LD) may include a plurality of first light-emitting elements (LD1) disposed between the first-1 electrode EL1_1 and the second electrode EL2, and a plurality of second light-emitting elements (LD2) disposed between the second electrode EL2 and the first-2 electrode EL1_2.

[0224] The light-emitting element LD can be set in the emission area EMA of each pixel PXL and / or formed on the first insulating layer INS1.

[0225] A first insulating layer INS1 may be disposed in and / or formed beneath each of the emitting regions EMA of each pixel PXL. The first insulating layer INS1 may fill the space between each of the emitting elements LD and the passivation layer PSV to stably support the emitting element LD and prevent the emitting element LD from being removed from the passivation layer PSV.

[0226] Furthermore, in the emission region EMA of each pixel PXL, the first insulating layer INS1 can expose one area of ​​each of the first electrode EL1 and the second electrode EL2, and cover the remaining area except for that one area. Here, contact electrodes CNE1 and CNE2 can be respectively disposed and / or formed on the exposed areas of the first electrode EL1 and the second electrode EL2, such that the first electrode EL1 and the second electrode EL2 can be electrically connected and / or physically connected to the contact electrodes CNE1 and CNE2.

[0227] The first insulating layer INS1 can be formed of an inorganic insulating layer comprising inorganic materials or an organic insulating layer comprising organic materials. Although in embodiments of this disclosure, the first insulating layer INS1 can be formed of an inorganic insulating layer suitable for protecting the light-emitting element LD from the influence of the pixel circuit layer PCL of each pixel PXL, this disclosure is not limited thereto. In embodiments, the first insulating layer INS1 can be formed of an organic insulating layer suitable for planarizing the support surface of the light-emitting element LD.

[0228] A second insulating layer INS2 may be disposed and / or formed on the light-emitting element LD. The second insulating layer INS2 may be disposed and / or formed on each of the light-emitting elements LD to cover a portion of the upper surface of each of the light-emitting elements LD, and to expose the opposite ends EP1 and EP2 of each of the light-emitting elements LD to the outside. The second insulating layer INS2 may be formed in the emission region EMA of each pixel PXL as an independent insulating pattern, but this disclosure is not limited thereto.

[0229] The second insulating layer INS2 can have a single-layer or multi-layer structure, and includes an inorganic insulating layer comprising at least one inorganic material or an organic insulating layer comprising at least one organic material. The second insulating layer INS2 can more reliably fix each of the light-emitting elements LDs aligned in the emission region EMA of each pixel PXL. In embodiments of this disclosure, the second insulating layer INS2 may include an inorganic insulating layer suitable for protecting the active layer 12 of each of the light-emitting elements LDs from external oxygen, water, etc. However, this disclosure is not limited thereto. The second insulating layer INS2 may be formed of an organic insulating layer comprising organic materials, depending on the design conditions of the display device using the light-emitting elements LDs.

[0230] In embodiments of this disclosure, after the alignment of the light-emitting elements (LDs) in the emission regions (EMAs) of each pixel PXL has been completed, a second insulating layer INS2 is formed on the light-emitting elements LDs to prevent the light-emitting elements LDs from being removed from the alignment position. If a gap (or space) exists between the first insulating layer INS1 and the light-emitting element LD before the formation of the second insulating layer INS2, the gap can be filled using the second insulating layer INS2 during the process of forming the second insulating layer INS2. Therefore, the light-emitting element LD can be formed of an organic insulating layer suitable for filling the gap between the first insulating layer INS1 and the light-emitting element LD.

[0231] In embodiments of this disclosure, a second insulating layer INS2 may be formed on each of the light-emitting elements LD, thereby preventing the active layer 12 of each of the light-emitting elements LD from contacting external conductive material. The second insulating layer INS2 may cover only a portion of the surface of each of the light-emitting elements LD, such that opposite ends EP1 and EP2 of each of the light-emitting elements LD may be exposed to the outside.

[0232] Contact electrodes may be disposed on each of the first electrode EL1 and the second electrode EL2. The contact electrodes may be components configured to more reliably electrically connect each of the first electrode EL1 and the second electrode EL2 to the corresponding light-emitting element LD.

[0233] The contact electrodes may include a first contact electrode CNE1 disposed on a first electrode EL1 and a second contact electrode CNE2 disposed on a second electrode EL2. The first contact electrode CNE1 and the second contact electrode CNE2 may be formed of various transparent conductive materials. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may include at least one of various transparent conductive materials including ITO, IZO, and ITZO, and may be substantially transparent or translucent to meet a predetermined transmittance. However, the materials of the first contact electrode CNE1 and the second contact electrode CNE2 are not limited to the foregoing embodiments. In embodiments, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed of various opaque conductive materials.

[0234] The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same plane at locations spaced apart from each other. The first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the same layer and comprise the same material. However, this disclosure is not limited thereto. In one or more embodiments, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on different layers and comprise different materials.

[0235] In embodiments of this disclosure, the first contact electrode CNE1 may be formed of a transparent conductive material to allow light emitted from each of the light-emitting elements LD and reflected by the first electrode EL1 to travel losslessly in the image display direction of the display device. The first contact electrode CNE1 may be disposed on and overlap with the first electrode EL1. The first contact electrode CNE1 may be directly disposed on a region of the first electrode EL1 exposed from the first insulating layer INS1 and may be electrically and / or physically connected to the first electrode EL1. Furthermore, the first contact electrode CNE1 may be directly disposed on one end of each of the opposing ends of the light-emitting elements LD and overlap with that end of each of the light-emitting elements LD. The first contact electrode CNE1 can reliably connect the first electrode EL1 to one end of each of the opposing ends of the light-emitting elements LD. The first contact electrode CNE1 may include a first-1 contact electrode CNE1_1 disposed on the first-1 electrode EL1_1 and a first-2 contact electrode CNE1_2 disposed on the first-2 electrode EL1_2.

[0236] The second contact electrode CNE2 can be disposed on and overlap with the second electrode EL2. The second contact electrode CNE2 can be directly disposed on a region of the second electrode EL2 exposed from the first insulating layer INS1, and can be electrically and / or physically connected to the second electrode EL2. Furthermore, the second contact electrode CNE2 can be directly disposed on the other end of each of the light-emitting elements LD, and overlap with the other end of each of the light-emitting elements LD. The second contact electrode CNE2 can reliably connect the second electrode EL2 to the other end of each of the light-emitting elements LD. In embodiments of this disclosure, the second contact electrode CNE2 can be disposed on the same layer as the first contact electrode CNE1, and can comprise the same material as the first contact electrode CNE1.

[0237] The encapsulation layer ENC can be disposed and / or formed on the first contact electrode CNE1 and the second contact electrode CNE2. The encapsulation layer ENC can be an inorganic insulating layer comprising inorganic materials or an organic insulating layer comprising organic materials. For example, the encapsulation layer ENC can have a structure formed by alternately stacking at least one inorganic insulating layer and at least one organic insulating layer. The encapsulation layer ENC can cover the entire display element layer DPL and prevent water or moisture from being drawn into the display element layer DPL, including the light-emitting element LD, from the outside.

[0238] A capping layer (not shown) may be disposed and / or formed in the emitting region EMA of each pixel PXL. The capping layer may be disposed and / or formed between each of the first electrode EL1 and the second electrode EL2 and a contact electrode. For example, the capping layer may be disposed and / or formed between the first electrode EL1 and the first contact electrode CNE1, and between the second electrode EL2 and the second contact electrode CNE2. The capping layer can prevent damage to each of the first electrode EL1 and the second electrode EL2 caused by defects or the like during the manufacturing process of the display device, and enhance the adhesion between each of the first electrode EL1 and the second electrode EL2 and the passivation layer PSV. The capping layer may be formed of a transparent conductive material (such as indium zinc oxide (IZO)) to minimize the loss of light emitted from each of the light-emitting elements LD and reflected by each of the first electrode EL1 and the second electrode EL2 in the image display direction of the display device.

[0239] The display element layer DPL for each pixel PXL can also include an optical pattern OTP.

[0240] An optical pattern OTP can be disposed on each of the light-emitting elements (LDs) and cover the entirety of each LD. The optical pattern OTP can be disposed below the encapsulation layer ENC and cover both the second insulating layer INS2 disposed on the upper surface of each LD and a portion of each of the first contact electrodes CNE1 and the second contact electrodes CNE2 spaced apart from each other on the second insulating layer INS2. The optical pattern OTP can diffuse and / or scatter light emitted from the LD, or focus (or converge) light, thereby improving light extraction efficiency. Furthermore, the optical pattern OTP can be disposed on the LD and serve as a light control component for controlling the travel path of light emitted from the LD.

[0241] The optical pattern OTP can have a polygonal shape (e.g., a trapezoidal shape) whose width decreases upward from the surface that contacts a portion of each of the first contact electrodes CNE1 and the second contact electrodes CNE2 spaced apart from each other on the second insulating layer INS2, but this disclosure is not limited thereto. In embodiments, the optical pattern OTP can have a lens-like shape, having a semi-circular (or hemispherical) shape with an upwardly decreasing width, or a semi-elliptical cross-section, such as... Figure 12b As shown in the diagram, when the optical pattern OTP has the aforementioned shape, light emitted from the light-emitting element LD and incident on the optical pattern OTP, as well as light reflected by the first electrode EL1 and the second electrode EL2 and incident on the optical pattern OTP, can be diffused and / or scattered in various directions, or focused in a specific direction. The degree to which light emitted from the light-emitting element LD is diffused and / or scattered or focused can be controlled by changing the shape of the optical pattern OTP.

[0242] The optical pattern OTP can overlap with each of the light-emitting elements (LDs), the second insulating layer INS2, and a portion of each of the first contact electrode CNE1 and the second contact electrode CNE2. In a plan view, the optical pattern OTP can have a rod-like shape extending in the second direction DR2 and covering the entire surface of the light-emitting elements (LDs) disposed between the first electrode EL1 and the second electrode EL2. In other words, the optical pattern OTP can be a light output pattern configured to extract light emitted from each of the light-emitting elements (LDs) (hereinafter referred to as "first light") and light emitted from each of the light-emitting elements (LDs) and reflected by the first electrode EL1 and the second electrode EL2 in the image display direction of the display device (hereinafter referred to as "second light"). For example, the optical pattern OTP can diffuse and / or scatter or concentrate the first light and the second light, such that the first light and the second light can be emitted more densely in the image display direction of the display device. Furthermore, the optical pattern OTP can increase the light output angle of light emitted from the light-emitting elements (LDs) at a narrow light output angle, thereby improving the light output efficiency of the light-emitting elements (LDs).

[0243] The optical pattern OTP can be formed from a diffusion ink having a predetermined level or higher reflectivity. For example, the diffusion ink may include polystyrene (PS) or polymethyl methacrylate (PMMA) microspheres, a solvent, a polystyrene (PS) or polymethyl methacrylate (PMMA) copolymer, and additives, but this disclosure is not limited thereto. In embodiments, the optical pattern OTP may include a light-transmitting polymer material. For example, the polymer material may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, and polymethyl methacrylate. However, the material for the optical pattern OTP is not limited to the foregoing embodiments. Various materials may be selectively used, as long as these materials can diffuse and / or scatter or concentrate light emitted from the light-emitting element LD and light emitted from the light-emitting element LD and reflected by the first electrode EL1 and the second electrode EL2.

[0244] In embodiments of this disclosure, optical patterned OTPs can be formed using a mask process. Furthermore, optical patterned OTPs can be formed using methods such as inkjet printing, screen printing, lamination, spin coating, sputtering, or chemical vapor deposition (CVD). Additionally, optical patterned OTPs can be formed by coating a second insulating layer INS2 with portions of a first contact electrode CNE1 and a second contact electrode CNE2 spaced apart from each other on the second insulating layer INS2 using a medium comprising fine particles, and then curing the medium through a thermal curing operation and / or an optical curing operation. For example, an optical patterned OTP can be formed by dropping diffused ink onto the second insulating layer INS2 on a light-emitting element LD and curing the dropped ink through a thermal curing operation and / or an optical curing operation.

[0245] In the implementation method, such as Figure 12a As shown, an optical patterned OTP may include fine-particle DFPs. In this case, the optical patterned OTP may include fine-particle DFPs dispersed in a transparent medium (such as a transparent adhesive) for light diffusion and / or light scattering. In embodiments of this disclosure, the fine-particle DFPs may be referred to as diffuse particles, scattering particles, etc. Each fine-particle DFP may have a size ranging from tens of nanometers to several micrometers, but this disclosure is not limited thereto. The adhesive may include a transparent material, such as acrylic, urethane, or epoxy resin. Transparent or white particles may be used as fine-particle DFPs.

[0246] Transparent particles can be, for example, transparent organic or inorganic particles. Organic particles may include acrylic-based particles of homopolymers or copolymers of methyl methacrylate, acrylic acid, glycidyl methacrylate, ethyl acrylate, isobutyl acrylate, n-butyl acrylate, and 2-ethylhexyl acrylate; olefin-based particles such as polyethylene, polystyrene, or polypropylene; acrylic acid and olefin-based copolymer particles; and multilayer and multicomponent particles formed by forming a layer comprising homopolymer particles and then covering the layer with different types of monomers. Inorganic particles may include, for example, synthetic silica, glass microspheres, and diamond. Titanium oxide, zinc oxide, barium sulfate, calcium carbonate, magnesium carbonate, aluminum hydroxide, clay, etc., can be used as white particles. Furthermore, transparent or white particles can be used alone or in combination of two or more types as fine particles (DFP).

[0247] Although the aforementioned fine-particle DFPs have the same size, this disclosure is not limited thereto. In embodiments, the fine-particle DFPs may have different sizes. Furthermore, although the fine-particle DFPs are shown as regularly distributed in an optical pattern OTP, this disclosure is not limited thereto. In embodiments, the fine-particle DFPs may be irregularly distributed, and for example, their distribution may be biased to one side.

[0248] The first light emitted from the light-emitting element (LD) and incident on the optical pattern OTP can be diffused and / or scattered or focused in a specific direction by the fine particles (DFP), allowing the first light to travel more reliably outside the optical pattern OTP, for example, more reliably outside the optical pattern OTP in the image display direction of the display device. Furthermore, the second light emitted from the light-emitting element (LD), reflected by the first electrode (EL1) and the second electrode (EL2), and then incident on the optical pattern OTP can also be diffused and / or scattered or focused in a specific direction by the fine particles (DFP), allowing the second light to travel more reliably in the image display direction of the display device.

[0249] As described above, when the optical pattern OTP is set on the light-emitting element LD, the light emitted from the light-emitting element LD and the light reflected by the first electrode EL1 and the second electrode EL2 can be diffused and / or scattered, focused, refracted and reflected in various directions (or at different angles) through the optical pattern OTP, thereby increasing the amount (or intensity) of light traveling in the image display direction of the display device. Therefore, the light output efficiency of each pixel PXL can also be improved.

[0250] Although the foregoing embodiments have described the case where the optical pattern OTP covers the entire surface of the second insulating layer INS2 disposed on the corresponding upper surface of the light-emitting element LD, this disclosure is not limited thereto. In embodiments, the optical pattern OTP may be configured to cover only a portion of the second insulating layer INS2 or to cover the entire surface of the display element layer DPL of each pixel PXL.

[0251] Another implementation of optical pattern OTP will be described in detail below.

[0252] Figure 16 It shows Figure 10 Another embodiment of the encapsulation layer shown, and is related to Figure 8 The sectional view corresponding to line I-I'.

[0253] Therefore, for Figure 16 The following description of this embodiment will focus on the differences from the foregoing embodiments to avoid redundant explanations. Components not separately explained in the following description of this embodiment are the same as those in the foregoing embodiments. The same reference numerals will be used to denote the same components, and similar reference numerals will be used to denote similar components.

[0254] refer to Figures 1a to 5 , Figure 6a , Figure 8 and Figure 16 Each pixel PXL may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL.

[0255] The display element layer (DPL) may include a first dam pattern (BNK1) and a second dam pattern (BNK2), a first electrode (EL1) and a second electrode (EL2), a first connecting line (CNL1) and a second connecting line (CNL2), a light-emitting element (LD), a first contact electrode (CNE1) and a second contact electrode (CNE2), a first insulating layer (INS1) and a second insulating layer (INS2), and an encapsulation layer (ENC).

[0256] The encapsulation layer ENC can completely cover the components included in the display element layer DPL. The encapsulation layer ENC can be made of a transparent insulating material to minimize the loss of light emitted from the light-emitting element LD. For example, the encapsulation layer ENC can be formed of an inorganic insulating layer including inorganic materials or an organic insulating layer including organic materials, but this disclosure is not limited thereto.

[0257] To improve the light extraction efficiency from the light-emitting element (LD), the height (or thickness) of each corresponding portion of the encapsulation layer ENC in the LD can be greater than the height (or thickness) of the portions of the encapsulation layer ENC that are not corresponding to each portion of the LD. Here, each corresponding portion of the encapsulation layer ENC in the LD can have a shape that protrudes upwards at its highest point. To allow each corresponding portion of the encapsulation layer ENC in the LD to have a shape that protrudes upwards at its highest point, the encapsulation layer ENC can be formed using a method such as a halftone mask. In embodiments of this disclosure, an optical pattern OTP can be formed such that the portion of the encapsulation layer ENC with the most prominent shape can be used as a light control component that diffuses and / or scatters or focuses light emitted from the LD, and thus controls the path of the light.

[0258] The optical pattern OTP can be included in the encapsulation layer ENC and corresponds to the second insulating layer INS2 on the light-emitting element LD. In other words, the optical pattern OTP can be integrally formed with the encapsulation layer ENC. When the optical pattern OTP is integral with the encapsulation layer ENC, the optical pattern OTP can be considered as a region of the encapsulation layer ENC.

[0259] Although not directly shown in the accompanying drawings, the encapsulation layer ENC including the optical pattern OTP may include scattering particles configured to further improve the light extraction efficiency of light emitted from the light-emitting element LD. The scattering particles may have the same characteristics as the reference. Figure 12a The fine particles described (reference) Figure 12a The configuration is the same as that of the DFP.

[0260] Figures 17a to 17c It is shown Figure 8 Schematic plan view of different implementations of pixels.

[0261] Figures 17a to 17c The description of each pixel PXL in this embodiment will focus on the differences from the above embodiments in order to avoid redundant descriptions. Components not separately explained in the following description of this embodiment are consistent with the components of the aforementioned embodiments. The same reference numerals will be used to indicate the same components, and similar reference numerals will be used to indicate similar components.

[0262] For the sake of explanation, Figures 17a to 17c Some components included in the display element layer DPL for each pixel PXL are shown only schematically.

[0263] First, refer to Figures 1a to 4b , Figure 5 , Figure 6a , Figure 10 and Figure 17aEach pixel PXL's display element layer DPL may include a first connection line CNL1 and a second connection line CNL2, a first electrode EL1 and a second electrode EL2, a light-emitting element LD, and a first contact electrode CNE1 and a second contact electrode CNE2.

[0264] The second insulating layer INS2 can be disposed on the light-emitting element LD. The second insulating layer INS2 can have the same characteristics as the reference layer. Figure 10 The configuration of the second insulating layer INS2 described is the same. An optical pattern OTP can be set and / or formed on the second insulating layer INS2 on the light-emitting element LD. An encapsulation layer ENC can be set on the optical pattern OTP.

[0265] In embodiments of this disclosure, an optical pattern OTP may include multiple sub-optical patterns. For example, an optical pattern OTP may include first sub-optical patterns OTP1 to sixth sub-optical patterns OTP6. Each of the first sub-optical patterns OTP1 to sixth sub-optical patterns OTP6 may be configured to group a specific number of light-emitting elements LD in the light-emitting elements LD into a sub-emitting unit, and cover only that one sub-emitting unit.

[0266] For example, assuming that the light-emitting elements LDs set in the emission region EMA of each pixel PXL include nine first light-emitting elements LD1 and nine second light-emitting elements LD2, the first sub-optical pattern OTP1 can be configured to group three of the nine first light-emitting elements LD1 into a first sub-emission unit, and cover only the first sub-emission unit. The second sub-optical pattern OTP2 can be configured to group three other first light-emitting elements LD1 into a second sub-emission unit, and cover only the second sub-emission unit. The third sub-optical pattern OTP3 can be configured to group the other three first light-emitting elements LD1 into a third sub-emission unit, and cover only the third sub-emission unit. The fourth sub-optical pattern OTP4 can be configured to group three second light-emitting elements LD2 into a fourth sub-emission unit, and cover only the fourth sub-emission unit. The fifth sub-optical pattern OTP5 can be configured to group three other second light-emitting elements LD2 into a fifth sub-emission unit, and cover only the fifth sub-emission unit. The sixth sub-optical pattern OTP6 can be configured to group the other three of the nine second light-emitting elements LD2 into a sixth sub-emitting unit, and only cover the sixth sub-emitting unit.

[0267] In the planar view, each of the first sub-optical patterns OTP1 to the sixth sub-optical pattern OTP6 may have a rod-like shape extending in the second direction DR2. Each of the first sub-optical pattern OTP1, the second sub-optical pattern OTP2, and the third sub-optical pattern OTP3 may overlap with the second insulating layer INS2 on the corresponding first light-emitting element LD1 between the first-1 electrode EL1_1 and the second electrode EL2. Each of the fourth sub-optical pattern OTP4, the fifth sub-optical pattern OTP5, and the sixth sub-optical pattern OTP6 may overlap with the second insulating layer INS2 on the corresponding second light-emitting element LD2 between the second electrode EL2 and the first-2 electrode EL1_2.

[0268] Furthermore, the first sub-optical pattern OTP1, the second sub-optical pattern OTP2, and the third sub-optical pattern OTP3 may overlap with at least a portion of each of the first-1 contact electrode CNE1_1 and the second contact electrode CNE2, which are spaced apart from each other on the second insulating layer INS2. The fourth sub-optical pattern OTP4, the fifth sub-optical pattern OTP5, and the sixth sub-optical pattern OTP6 may overlap with at least a portion of each of the second contact electrode CNE2 and the first-2 contact electrode CNE1_2, which are spaced apart from each other on the second insulating layer INS2.

[0269] In embodiments of this disclosure, the first sub-optical patterns OTP1 to the sixth sub-optical patterns OTP6 may have the same size and the same shape, but this disclosure is not limited thereto. In embodiments, the first sub-optical patterns OTP1 to the third sub-optical patterns OTP3 corresponding to the first light-emitting element LD1 may have the same size and the same shape. The fourth sub-optical patterns OTP4 to the sixth sub-optical patterns OTP6 corresponding to the second light-emitting element LD2 may have the same size and the same shape. Furthermore, in embodiments, the first sub-optical patterns OTP1 to the sixth sub-optical patterns OTP6 may have different sizes and different shapes.

[0270] Each of the first sub-optical patterns OTP1 to the sixth sub-optical pattern OTP6 can diffuse and / or scatter or concentrate light emitted from and incident on the light-emitting element LD included in the corresponding sub-emitting unit, as well as light reflected by the first electrode EL1 and the second electrode EL2 and incident on it, thereby increasing the amount (or intensity) of light traveling in the image display direction of the display device. Therefore, the light output efficiency of each pixel PXL can be improved.

[0271] Next, refer to Figures 1a to 6a , Figure 10 , Figure 17b and Figure 17c The optical pattern OTP can include the first sub-optical pattern OTP1 to the eighth sub-optical pattern OTP8.

[0272] The first sub-optical pattern OTP1 to the fourth sub-optical pattern OTP4 in the first sub-optical pattern OTP1 to the eighth sub-optical pattern OTP8 can cover the first light-emitting element LD1 and the second insulating layer INS2 on the first light-emitting element LD1. The fifth sub-optical pattern OTP5 to the eighth sub-optical pattern OTP8 can cover the second light-emitting element LD2 and the second insulating layer INS2 on the second light-emitting element LD2.

[0273] The first sub-optical pattern OTP1 and the fifth sub-optical pattern OTP5 can have the same shape and the same or different dimensions (or surface area). For example, in a planar view, the first sub-optical pattern OTP1 and the fifth sub-optical pattern OTP5 can each have an elliptical shape. The first sub-optical pattern OTP1 can cover only the first sub-emitting unit, which includes two of the nine first light-emitting elements LD1. The fifth sub-optical pattern OTP5 can cover only the fifth sub-emitting unit, which includes two of the nine second light-emitting elements LD2.

[0274] The second sub-optical pattern OTP2 and the sixth sub-optical pattern OTP6 can have the same shape and the same or different dimensions (or surface area). For example, in a planar view, the second sub-optical pattern OTP2 and the sixth sub-optical pattern OTP6 can each have a circular shape. The second sub-optical pattern OTP2 can cover only the second sub-emitting unit, which includes two of the nine first light-emitting elements LD1. The sixth sub-optical pattern OTP6 can cover only the sixth sub-emitting unit, which includes two of the nine second light-emitting elements LD2.

[0275] The third sub-optical pattern OTP3 and the seventh sub-optical pattern OTP7 can have the same shape and the same or different dimensions (or surface area). For example, in a planar view, the third sub-optical pattern OTP3 and the seventh sub-optical pattern OTP7 can each have an elliptical shape. The third sub-optical pattern OTP3 can cover only the third sub-emitting unit, which includes two of the nine first light-emitting elements LD1. The seventh sub-optical pattern OTP7 can cover only the seventh sub-emitting unit, which includes two of the nine second light-emitting elements LD2.

[0276] The fourth sub-optical pattern OTP4 and the eighth sub-optical pattern OTP8 can have the same shape and the same or different dimensions (or surface area). For example, in a planar view, the fourth sub-optical pattern OTP4 and the eighth sub-optical pattern OTP8 can each have a rectangular shape. The fourth sub-optical pattern OTP4 can cover only the fourth sub-emitting unit, which includes the other three of the nine first light-emitting elements LD1. The eighth sub-optical pattern OTP8 can cover only the eighth sub-emitting unit, which includes the other three of the nine second light-emitting elements LD2.

[0277] In the implementation method, such as Figure 17c As shown, the first sub-optical pattern OTP1 to the fourth sub-optical pattern OTP4 can have the same shape but different dimensions (or surface areas). Similarly, the fifth sub-optical pattern OTP5 to the eighth sub-optical pattern OTP8 can have the same shape but different dimensions (or surface areas).

[0278] Figure 18 This is a schematic plan view of pixels according to an embodiment of the present disclosure. Figure 19 It is along Figure 18 A sectional view taken from line IV-IV'. Figure 20 It is along Figure 18 A sectional view taken by line V-V'.

[0279] To avoid redundant explanations, Figures 18 to 20 The description of the pixel PXL will focus on the differences from the foregoing embodiments. Components not separately explained in the following description of this embodiment are the same as those in the foregoing embodiments. The same reference numerals will be used to denote the same components, and similar reference numerals will be used to denote similar components.

[0280] refer to Figures 1a to 5 , Figure 6a as well as Figures 18 to 20 Each pixel PXL may include a substrate SUB, a pixel circuit layer PCL disposed on the substrate SUB, and a display element layer DPL disposed on the pixel circuit layer PCL. Here, the substrate SUB and the pixel circuit layer PCL may each have a reference [missing information]. Figure 10 The substrate SUB and pixel circuit layer PCL are described as having the same configuration.

[0281] The display element layer DPL may include a first dam pattern BNK1 and a second dam pattern BNK2, a first connecting line CNL1 and a second connecting line CNL2, a first electrode EL1 and a second electrode EL2, a light-emitting element LD, a first contact electrode CNE1 and a second contact electrode CNE2, and an encapsulation layer ENC. Furthermore, the display element layer DPL may include a second insulating layer INS2, which is configured to cover a portion of the upper surface of each of the light-emitting elements LD and allow opposite ends EP1 and EP2 of each of the light-emitting elements LD to be exposed.

[0282] A second insulating layer INS2 may be disposed on the upper surface of each of the light-emitting elements LD, thereby preventing the active layer 12 of each of the light-emitting elements LD from contacting external conductive material. The second insulating layer INS2 may fill the gap between the first insulating layer INS1 and each light-emitting element LD. In embodiments of this disclosure, the second insulating layer INS2 may be an organic insulating layer comprising organic materials.

[0283] The second insulating layer INS2 can be formed by an exposure process using a mask, and its shape can be changed in response to the light (or ray) used during the exposure process. For example, the second insulating layer INS2 can be formed into a lens-like shape, including a semi-elliptical or semi-circular (or hemispherical) shape, which expands upward in response to the light used during the exposure process. The intensity of the light (or ray) used when forming the second insulating layer INS2 and / or the exposure time can be adjusted, thereby changing the second insulating layer INS2 into a shape that maximizes the light extraction efficiency of the light emitted from the light-emitting element LD and the light reflected by the first electrode EL1 and the second electrode EL2.

[0284] When the second insulating layer INS2 disposed on the upper surface of each of the light-emitting elements (LDs) has a lens-like shape in cross-section, the light emitted from the LDs and the light reflected by the first electrode EL1 and the second electrode EL2 can be diffused and / or scattered as it passes through the second insulating layer INS2. Therefore, the light extraction efficiency of the light emitted from the emission region EMA of each pixel PXL can be improved. The second insulating layer INS2 with a lens-like shape can be used as a light output pattern for extracting the light emitted from the LDs and the light reflected by the first electrode EL1 and the second electrode EL2 in the image display direction of the display device. For example, the second insulating layer INS2 can diffuse and / or scatter or concentrate the light emitted from the LDs and the light reflected by the first electrode EL1 and the second electrode EL2, and emit light more concentratedly in the image display direction of the display device.

[0285] In embodiments of this disclosure, the second insulating layer INS2 disposed on the upper surface of each of the light-emitting elements LD can be used as an optical insulating component configured to stably support each of the light-emitting elements LD, protect the active layer 12 of each light-emitting element LD, and diffuse and / or scatter or concentrate light emitted from the light-emitting elements LD and light reflected by the first electrode EL1 and the second electrode EL2.

[0286] In an embodiment, the second insulating layer INS2 may include diffuse particles DFP', which are used to further improve the light extraction efficiency of light emitted from the light-emitting element LD. The diffuse particles DFP' may be regularly or irregularly dispersed in the second insulating layer INS2 to diffuse and / or scatter the light emitted from the light-emitting element LD. Transparent or white particles may be used as the diffuse particles DFP'. The diffuse particles DFP' may have the same characteristics as the reference... Figure 12a The configuration described is the same as that of the fine-grained DFP.

[0287] Figure 21 The image shows pixels according to an embodiment of the present disclosure, and is related to... Figure 18 The sectional view corresponding to line IV-IV'. Figures 22a to 22d It is shown Figure 21 Cross-sectional views of different implementations of pixels.

[0288] To avoid redundant explanation, Figure 21 , Figures 22a to 22d The description of the pixel PXL will focus on the differences from the foregoing embodiments. Components not separately explained in the following description of this embodiment are the same as those in the foregoing embodiments. The same reference numerals will be used to denote the same components, and similar reference numerals will be used to denote similar components.

[0289] refer to Figures 1a to 5 , Figure 6a , Figure 18 , Figure 21 as well as Figures 22a to 22d Each pixel PXL may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL.

[0290] The display element layer (DPL) may include a first dam pattern (BNK1) and a second dam pattern (BNK2), a first connecting line (CNL1) and a second connecting line (CNL2), a first electrode (EL1) and a second electrode (EL2), a light-emitting element (LD), a first contact electrode (CNE1) and a second contact electrode (CNE2), a first insulating layer (INS1) and a second insulating layer (INS2), and an encapsulation layer (ENC).

[0291] In addition, the display element layer DPL may also include an optical layer OTL disposed on the encapsulation layer ENC.

[0292] The optical layer OTL can be an optical component disposed on the encapsulation layer ENC and configured to diffuse and / or scatter or concentrate light passing through the encapsulation layer ENC, thereby increasing the amount (or intensity) of light traveling in the image display direction of the display device. The optical layer OTL can be configured to cover the entire encapsulation layer ENC and correspond to the outermost layer of the display element layer DPL. In embodiments of this disclosure, the optical layer OTL may include a material capable of diffuse and / or scatter or concentrate light passing through the encapsulation layer ENC and allowing light to pass through therethrough. For example, the optical layer OTL may be made of a transparent resin.

[0293] The optical layer OTL can include multiple embossed patterns RCP formed by an imprinting process. For example, the optical layer OTL can be formed to include multiple embossed patterns RCP on its upper surface by applying a transparent resin to the encapsulation layer ENC, performing an imprinting process using a mold, and then applying ultraviolet light to it. Furthermore, the optical layer OTL can include a planar portion FP disposed between two adjacent embossed patterns RCP. The embossed patterns RCP can be disposed on the upper surface of the optical layer OTL to correspond to the emission area EMA of each pixel PXL.

[0294] Each of the embossed patterns RCP can have a lens-like shape with its width decreasing upwards, having a semi-elliptical shape, a semi-circular shape (or a hemispherical shape). In other words, each of the embossed patterns RCP can have an upwardly convex shape. Each of the embossed patterns RCP can be disposed on a surface of the optical layer OTL and spaced apart from adjacent embossed patterns RCP, with a planar portion FP interposed between them. Although the distance between the embossed patterns RCP can be uniform, this disclosure is not limited thereto. In embodiments, the embossed patterns RCP can be disposed on the upper surface of the optical layer OTL such that, based on any given point, the distance between adjacent embossed patterns RCP decreases or increases in the direction toward or away from that point.

[0295] Each of the embossed patterns RCP can have a dimension equal to or substantially similar to the length L of each of the light-emitting elements LD, but this disclosure is not limited thereto. In embodiments, such as Figure 22a As shown, each of the embossed patterns RCP can have a dimension larger than the length L of each of the light-emitting elements LD, and is sufficient to cover each of the light-emitting elements LD. Furthermore, in embodiments, each of the embossed patterns RCP can have a dimension smaller than the length L of each of the light-emitting elements LD. The embossed patterns RCP can have the same size and the same width, but this disclosure is not limited thereto. In embodiments, the embossed patterns RCP can have different sizes and widths. Figure 22bAs shown, only some of the embossed patterns in the RCP can have the same size and width, or they can have different sizes and widths.

[0296] The embossed pattern RCP can be a light control device used to diffuse and / or scatter or concentrate light passing through the encapsulation layer ENC and to change the light's path toward the image display direction of the display device. Furthermore, the embossed pattern RCP can increase the emission angle of light passing through the encapsulation layer ENC and improve the light output efficiency of light emitted from the emission region EMA of each pixel PXL. The optical layer OTL including the embossed pattern RCP may also include diffuser particles (not shown) for diffuser and / or scatterer of light passing through the encapsulation layer ENC. Here, the diffuser particles may have the same characteristics as the reference... Figure 12a The fine-grained DFP described has the same configuration.

[0297] The optical layer OTL, which includes the embossed pattern RCP and the planar portion FP, can have a structure that causes a portion of its upper (or outer) surface to bend.

[0298] Although the foregoing embodiments have described cases where the optical layer OTL includes embossed patterns RCP each having an upwardly convex lens-like shape, this disclosure is not limited thereto. In embodiments, such as Figure 22c As shown, the optical layer OTL can be configured with recessed patterns CCPs instead of embossed patterns RCPs. The recessed patterns CCPs can have the same size and width, but this disclosure is not limited thereto. In embodiments, each of the recessed patterns CCPs can have a different size and width than the adjacent recessed patterns CCPs, and a planar portion FP is interposed between them. The optical layer OTL including the recessed patterns CCPs and the planar portion FP can be formed by an imprinting process.

[0299] The recessed pattern CCP can be a light control device used to diffuse and / or scatter or focus light passing through the encapsulation layer ENC and change the path of the light toward the image display direction of the display device.

[0300] Although the foregoing embodiments have described the case where the optical layer OTL includes a downwardly recessed pattern CCP, this disclosure is not limited thereto. In embodiments, such as Figure 22dAs shown, the optical layer OTL can be configured with a prism pattern PRP instead of a recessed pattern CCP, the prism pattern PRP having a prism mountain shape. The prism pattern PRPs can have the same size and width, but this disclosure is not limited thereto. In embodiments, each of the prism pattern PRPs can have a different size and width than adjacent prism pattern PRPs, and a planar portion FP is interposed between them. In embodiments of this disclosure, the vertical angle of each of the prism pattern PRPs and the size and / or width of each of the prism pattern PRPs can be adjusted such that light passing through the encapsulation layer ENC can be diffused and / or scattered or focused, thereby allowing the light to travel more densely in the image display direction of the display device.

[0301] While various implementations have been described above, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope of this disclosure.

[0302] Therefore, the embodiments disclosed in this specification are for illustrative purposes only and are not intended to limit the technical scope of this disclosure. The scope of this disclosure may be defined by the appended claims.

Claims

1. A display device, including: A substrate includes a display area and a non-display area, the display area including a plurality of pixel areas, each of the plurality of pixel areas including an emission area, and the non-display area being located at least one side of the display area; as well as A pixel, set in each of the plurality of pixel regions. The pixels include: The first electrode and the second electrode are spaced apart from each other on the substrate; Multiple light-emitting elements are connected between the first electrode and the second electrode. Each of the multiple light-emitting elements includes a first semiconductor layer, an active layer, a second semiconductor layer, and an element insulating layer covering the first semiconductor layer, the active layer, and the second semiconductor layer. An optical pattern is disposed on the plurality of light-emitting elements and overlaps with at least some of the plurality of light-emitting elements. The first contact electrode is electrically connected to each of the light-emitting elements and the first electrode; The second contact electrode is electrically connected to each of the light-emitting elements and the second electrode; An electrode insulating layer continuously covers the first electrode and the second electrode; and An insulating layer is directly disposed on the upper surface of each of the plurality of light-emitting elements, and is disposed between each of the first contact electrode and the second contact electrode and the element insulating layer; The optical pattern is configured to focus the light emitted from the plurality of light-emitting elements. Wherein, at least a portion of the optical pattern is disposed on the first contact electrode and the second contact electrode. The first contact electrode and the second contact electrode are formed of a transparent conductive material. Wherein, a first portion of the electrode insulating layer is disposed between the first electrode and the first contact electrode, and a second portion of the electrode insulating layer is disposed between the second electrode and the second contact electrode, and The optical pattern covers the entirety of each of the plurality of light-emitting elements.

2. The display device according to claim 1, wherein, The optical pattern includes lenses.

3. The display device according to claim 2 further includes an encapsulation layer disposed on the first electrode, the second electrode, and the light-emitting element.

4. The display device according to claim 3, wherein, The optical pattern is integrated with the encapsulation layer.

5. The display device according to claim 3, wherein, The encapsulation layer is disposed on the optical pattern.

6. The display device according to claim 3, in, The optical pattern includes multiple sub-optical patterns, and Each of the plurality of sub-optical patterns groups a specific number of light-emitting elements from the plurality of light-emitting elements into a unit and is located on the unit.

7. The display device according to claim 6, wherein, The multiple sub-optical patterns have different shapes from each other.

8. The display device according to claim 6, wherein, The multiple sub-optical patterns have the same shape.

9. The display device according to claim 3, in, The first contact electrode is disposed on the insulating layer; Wherein, the second contact electrode is spaced apart from the first contact electrode on the insulating layer, and The optical pattern covers a portion of the first contact electrode and a portion of the second contact electrode.

10. A display device, including: A substrate includes a display area and a non-display area, the display area including a plurality of pixel areas, each of the plurality of pixel areas including an emission area, and the non-display area being located at least one side of the display area; as well as A pixel, set in each of the plurality of pixel regions. The pixels include: The first electrode and the second electrode are spaced apart from each other on the substrate; Multiple light-emitting elements are connected between the first electrode and the second electrode. Each of the multiple light-emitting elements includes a first semiconductor layer, an active layer, a second semiconductor layer, and an element insulating layer covering the first semiconductor layer, the active layer, and the second semiconductor layer. An insulating optical pattern is disposed on the upper surface of each of the plurality of light-emitting elements and configured to extract light emitted from the plurality of light-emitting elements; The first contact electrode and the second contact electrode are spaced apart from each other on the insulating optical pattern; An insulating layer is directly disposed on the upper surface of each of the plurality of light-emitting elements, and is disposed between each of the first contact electrode and the second contact electrode and the element insulating layer; An electrode insulating layer continuously covers the first electrode and the second electrode; and An encapsulation layer is disposed on the first contact electrode and the second contact electrode. The insulating optical pattern includes optically diffused particles. Wherein, a first portion of the electrode insulating layer is disposed between the first electrode and the first contact electrode, and a second portion of the electrode insulating layer is disposed between the second electrode and the second contact electrode, and The first contact electrode and the second contact electrode overlap with the insulating optical pattern in the plan view and are formed of a transparent conductive material.

11. The display device according to claim 10, wherein, The insulating optical pattern has an upwardly projecting shape, and The optically diffused particles are dispersed in the insulating optical pattern.

12. The display device according to claim 11, wherein, The insulating optical pattern comprises organic insulating materials.

13. A display device, including: A substrate includes a display area and a non-display area, the display area including a plurality of pixel areas, each of the plurality of pixel areas including an emission area, and the non-display area being located at least one side of the display area; as well as A pixel, set in each of the plurality of pixel regions. The pixels include: The first electrode and the second electrode are spaced apart from each other on the substrate; Multiple light-emitting elements are connected between the first electrode and the second electrode; An insulating layer is directly disposed on the upper surface of each of the plurality of light-emitting elements; The first contact electrode and the second contact electrode are spaced apart from each other on the insulating layer and are formed of a transparent conductive material; An encapsulation layer is disposed on the first contact electrode and the second contact electrode; An electrode insulating layer continuously covers the first electrode and the second electrode; and An optical layer is disposed on the encapsulation layer, and The optical layer is configured to focus the light emitted from the plurality of light-emitting elements. Each of the light-emitting elements includes a first semiconductor layer, a second semiconductor layer, an active layer between the first semiconductor layer and the second semiconductor layer, and an insulating layer, wherein the insulating layer covers the first semiconductor layer, the second semiconductor layer, and the active layer. Wherein, a first portion of the electrode insulating layer is disposed between the first electrode and the first contact electrode, and a second portion of the electrode insulating layer is disposed between the second electrode and the second contact electrode. Wherein, the insulating layer is disposed between each of the first contact electrode and the second contact electrode and the insulating layer of the element, and The optical layer covers the entire light-emitting element in a planar view.

14. The display device according to claim 13, wherein, The optical layer comprises multiple optical patterns.

15. The display device according to claim 14, wherein, Each of the plurality of optical patterns has an upwardly projecting shape.

16. The display device according to claim 14, wherein, Each of the plurality of optical patterns has a concave shape.

17. The display device according to claim 14, wherein, The multiple optical patterns have the same size.

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