Programmable gain amplifier with programmable resistance

Abstract

A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE, 310) having an AFE input and an AFE output. The AFE output is coupled to an input of the ADC. The AFE includes a programmable gain amplifier (PGA, 115) having a first PGA input and a second PGA input. The PGA (115) includes a first operational amplifier (OP AMP, OP1) having first and second OP AMP inputs. The AFE (310) also includes a programmable resistance circuit (320) having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit (320) includes a resistor network having first and second balancing resistances. The first balancing resistance is coupled to the first and second OP AMP inputs, and the second balancing resistance is coupled to the first and second OP AMP inputs.

Description

Background Technology

[0001] An analog-to-digital converter (ADC) converts an analog signal into a digital representation of that signal. ADCs are used in a variety of applications. One of the characterizing parameters of an analog signal chain (such as an analog signal chain that includes an ADC) is the common-mode rejection ratio (CMRR). CMRR is a measure of a signal chain's ability to suppress common-mode signals present at the two input terminals of the signal chain. Some applications may benefit from a higher CMRR. Summary of the Invention

[0002] In one example, a circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front-end (AFE) having an AFE input and an AFE output. The AFE output is coupled to the input of the ADC. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) having first and second OPAMP inputs. The AFE also includes a programmable resistor circuit having a first programmable resistor circuit input and first and second programmable resistor circuit outputs. The first programmable resistor circuit input is coupled to the first and second PGA inputs. The programmable resistor circuit includes a resistor network having first and second balancing resistors. The first balancing resistor is coupled to the first and second OP AMP inputs, and the second balancing resistor is coupled to the first and second OP AMP inputs. Attached Figure Description

[0003] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0004] Figure 1 The diagram illustrates a circuit signal chain that includes an analog front-end (AFE) with a programmable gain amplifier (PGA) coupled to an analog-to-digital converter (ADC).

[0005] Figure 2 The diagram shows Figure 1 The AFE, which has additional details of the PGA.

[0006] Figure 3 An example of an AFE is shown, which includes a programmable resistor circuit for compensating for resistor mismatch within the AFE.

[0007] Figure 4 An example implementation of a programmable resistor circuit is shown, which includes a resistor network (hybrid R-2R network) with a pair of balanced resistors and also includes a Δ-Σ (delta sigma) modulator.

[0008] Figure 5An example of a programmable resistor circuit is shown, which includes a two-tap finite impulse response (FIR) filter for attenuating noise above the audio frequency band.

[0009] Figure 6 The use of two resistor networks with an AFE is shown, where one resistor network operates under an inverting input voltage, compared to the other resistor network.

[0010] Figure 7 Another example of an AFE including two resistor networks is shown. Detailed Implementation

[0011] The signal chain described herein includes an analog front-end (AFE) coupled to the ADC. The AFE receives the input analog signal. The AFE may include amplifiers, such as programmable gain amplifiers (PGAs), to modify the amplitude of the input analog signal before it is provided to the ADC for conversion to a digital representation. The AFE described herein provides a relatively high CMRR.

[0012] Figure 1 An example of circuitry 100 including an AFE 110 coupled to an ADC 150 is shown. In this example, the AFE 110 and ADC 150 are formed on the same semiconductor die 105 and are therefore provided on the same chip. The output of the AFE 110 is coupled to the input of the ADC 150. The AFE 110 has inputs designated as positive input (INP) and negative input (INM). The INP and INM inputs receive analog input signals (e.g., differential analog signals), which are then processed by the AFE 110. The processed analog signal from the AFE 110 is converted into a digital representation (digital output 151) by the ADC 150.

[0013] In this example, AFE 110 adjusts the amplitude of the input analog signal. AFE 110 includes a programmable gain amplifier (PGA) 115 with a positive input 116, a negative input 117, a positive output (OUTP) 118, and a negative output (OUTM) 119. OUTP 118 and OUTM 119 are coupled to the corresponding inputs 153 and 154 of ADC 150. AFE 110 also includes resistors R1P, R2P, R1M, and R2M. One terminal of R1P provides the INP input, while the other terminal of R1P is coupled to the positive input 116 of PGA 115 and one terminal of R2P at node NP. The other terminal of R2P is coupled to ground node 130 (or a power supply voltage node). Similarly, one terminal of R1M provides the INM input, while the other terminal of R1M is coupled to the negative input 117 of PGA 115 and one terminal of R2M at node NM. The other terminal of R2M is coupled to ground node 131 (or another fixed voltage). Resistors R1P and R2P include resistive voltage dividers for attenuating the positive input signal INP before being adjusted (e.g., programmable attenuation) by the PGA 115. The voltage at node NP is labeled ATTN_OUTP. Similarly, resistors R1M and R2M include resistive voltage dividers for attenuating the negative input signal INP before being adjusted by the PGA 115. The voltage at node NM is labeled ATTN_OUTM. ADC 150 can include any suitable type of ADC. In one example, ADC 150 includes a third-order continuous-time Δ-Σ ADC.

[0014] Figure 2An AFE 110 with additional example details of a PGA 115 is shown. The PGA 115 in this example includes operational amplifiers (OP AMP) OP1 and OP2, and resistors RINP, RINM, RCM1, RCM2, R3, R4, RFB1, and RFB2. OP1 has a positive input 201 (positive virtual ground, VGP), a negative input 202 (negative virtual ground, VGM), a positive output (OUTP) 118, and a negative output (OUTM) 119. OP2 has a negative input 203 and a positive input 204. RINP is coupled between R1P (positive input 116 of the PGA 115) and the positive input 201 of OP1. RINM is coupled between R1M (negative input 117 of the PGA 115) and the negative input 202 of OP2. RFB1 is coupled between the positive input 201 and OUTM 119, and RFB2 is coupled between the negative input 202 and OUTP 118. R4 is coupled between the positive input 201 of OP1 and the negative input 203 of OP2. R3 is coupled between the negative input 202 of OP1 and the negative input 203 of OP2. The common-mode voltage (VCM) is a reference voltage (e.g., generated by a bandgap reference) and is provided to the positive input 204 of OP2. The VCM voltage is selected so that all nodes within the circuit remain within the effective bias condition on the input signal swing. The output of OP2 provides a signal labeled OP2_OUT and is coupled to RCM1 and RCM2. RCM1 is coupled to the positive input 201 of OP1, and RCM2 is coupled to the negative input 202 of OP1. The PGA 115 has an input common-mode rejection loop (CMSL) partially formed by RCM1, RCM12, OP2, R3, and R4. This loop ensures that the common-mode of the virtual ground VGP and VGM at the positive input 201 and negative input 202 of OP1 remains at the desired level of VCM.

[0015] The CMRR of circuit 100 is at least partially determined by the CMRR of AFE 110. The CMRR of AFE 110 is determined by the degree of mismatch between the resistors on the positive side (i.e., R1P, R2P, RINP, and RCM1) and their corresponding resistors on the negative side (i.e., R1M, R2M, RINM, and RCM2). Due to their lower cost, many semiconductor devices implement resistors as polysilicon resistors. However, polysilicon resistors are characterized by relatively poor matching. Therefore, it is difficult, if not impossible, to achieve a high CMRR using polysilicon to implement the resistors of AFE 110. Some applications may benefit from CMRRs of 80dB, 90dB, or even higher. For example, for... Figure 2 The resistors shown in the AFE architecture may not be able to achieve 90dB CMRR using polysilicon.

[0016] Figure 3 The implementation ratio is shown Figure 1and Figure 2 An example of the AFE 310 with a higher CMRR (e.g., 90dB) than the AFE 110, also using polysilicon resistors, but with a different architecture. Figure 2 The architecture shown is different. (And) Figure 2 The architecture is the same as that of the AFE 110. Figure 3 The AFE 310 includes OP1, OP2 and resistors RINP, RINM, RCM1, RCM2, R3, R4, RFB1 and RFB2 connected together in a manner substantially the same as described above. Figure 3 The AFE 310 also includes a programmable resistor circuit 320 and resistors Rx1 and Rx2. Rx1 and Rx2 are connected in series between the positive input 116 and the negative input 117 of the PGA, and therefore also in series between voltages ATTN_OUTP and ATTN_OUTM. In some examples, the nominal resistance of Rx1 is equal to the nominal resistance of Rx2 (i.e., Rx1 = Rx2, ignoring resistor mismatch). Node 340 between Rx1 and Rx2 is coupled to the input terminal (VIN) of the programmable resistor circuit 320. When Rx1 equals Rx2, the voltage at node 340 is half that between ATTN_OUTM and ATTN_OUTP.

[0017] The output terminals of the programmable resistor circuit 320 include outputs 350 and 351. Output 350 is coupled to the positive input 201 of OP1 at VGP, and output 351 is coupled to the negative input 202 of OP1 at VGM. The programmable resistor circuit 320 is adjustable to provide programmable resistors coupled between inputs 116 and 117 of PGA 115 and inputs 201 and 202 of OP1. The programmable resistors balance the AFE 310 to address mismatches between the positive-side resistors (RINP, RINP, RCM1, and RFB1) and negative-side resistors (RINM, RINM, RCM2, and RFB2). All other things being equal, the CMRR of the AFE 310 is higher due to the use of the programmable resistor circuit 320. Figure 2 Possible values ​​for AFE 110.

[0018] Figure 4An example implementation of a programmable resistor circuit 320 is shown. In this example, the programmable resistor circuit 320 includes a resistor network 410 coupled to a Δ-Σ modulator 472. The programmable resistor circuit 320 also includes a storage device 490 (e.g., a memory device, register, etc.). The resistor network 410 is a hybrid “R-2R” resistor network. A conventional R-2R network includes repeating units (“branches”), each of which includes a unit resistor (R) coupled to a 2R resistor, and also includes balancing resistors to help ensure binary weighting of the individual branches of the R-2R network. However, Figure 4 The resistor network 410 shown includes two balancing resistors (resistors 429 and 430), instead of just one as in a conventional R-2R network. Each balancing resistor 429, 430 can be implemented as a combination of one or more unit resistors (R). Each of the balancing resistors 429 and 430 can also be referred to as a balancing “resistor” to recognize that each balancing resistor 429, 430 can include more than one resistor. The additional balancing resistor 430 (in addition to balancing resistor 429) helps to cover the residual error generated by the resistor network 410 using the coarse CMRR trimming code 470. The residual error generated by the resistor network 410 may be higher than that of a single balancing resistor (due to resistor mismatch in the resistor network 410). The two balancing resistors adequately account for the residual error.

[0019] Resistor network 410 includes resistors 420-430 and 440-443. Each resistor includes one or more resistors having the nominal effective resistance shown. These resistors may include one or more unit resistors (R) coupled together to form the resistors shown. Each of resistors 420, 422, 424, 426, 428-430, 440, 442, and 443 is a 2R resistor. Each of resistors 421, 423, and 425 is an R / 2 resistor (half a unit resistor). Resistor 441 is a 4R / 3 resistor.

[0020] Switch 450 selectively couples each 2R resistor 420, 422, 424, 426, and 428 to one of the following nodes: VGP, VCM, or VGM. Coarse CMRR trimming code 470 controls switch 450 to allow current to selectively flow through the corresponding 2R resistors 420, 422, 424, 426, and 428 to the VGP node, VCM node, or VGM node. Coarse CMRR trimming code 470 is stored in storage device 490. In one example, coarse CMRR trimming code 470 is implemented in sign magnitude form, but it can be implemented in other forms such as two's complement. Figure 4In the example, five resistors (resistors 420, 422, 424, 426, and 428) are controlled by the coarse CMRR trim code 470. In the sign amplitude form, one bit of the trim code indicates the correction direction, while the other bits indicate the amplitude. To control the five resistors, the coarse trim code 470 consists of six bits. The most significant bit controls the application direction, meaning whether resistors (420 to 428) should be connected to VGP or VGM. The remaining five bits of the trim code control whether each corresponding resistor is connected to VCM (when this bit is 0) or to VGP / VGM (when this bit is 1 and depends on the direction of the sign bit (MSB bit)). For example, when the coarse CMRR trim code 470 is “000000” or “100000”, all resistors are connected to VCM. When the coarse trim code 470 is “011111”, resistors 420-428 are connected to VGP. When the coarse / fine adjustment code 470 is "111111", the resistor is connected to VGM.

[0021] The Δ-Σ modulator 472 receives a fine CMRR tuning code 471 (also stored in storage device 490). The Δ-Σ modulator 472 may include a second-order Δ-Σ modulator. The Δ-Σ modulator generates an output bit sequence Q (and its complement QZ) to control the on / off states of switches SW1, SW2, SW3, and SW4. Using a Δ-Σ modulator helps ensure relatively little noise is injected into the AFE310 over the audio frequency range. SW1 is coupled between resistor 430 and VGP. SW2 is coupled between resistor 430 and VGM. SW3 is coupled between resistor 429 and VGP. SW1 is coupled between resistor 429 and VGM. The Q signal controls SW1 and SW3, while QZ controls SW2 and SW4. Therefore, SW1 and SW2 will not be on simultaneously, and similarly, SW3 and SW4 will not be on simultaneously. The Q signal causes SW1 and SW3 to be on simultaneously (and SW2 and SW4 to be off due to QZ). The QZ signal causes SW2 and SW4 to conduct simultaneously (and SW1 and SW3 to deactivate due to Q). When SW1 and SW3 are on (and SW2 and SW4 are off), current (i) flows to VGP through each of the balancing resistors 429 and 430. Then, when SW2 and SW4 are on (and SW1 and SW3 are off), current i flows to VGM through each of the balancing resistors 429 and 430.

[0022] If switches SW1-SW4 operate with an average duty cycle of 50%, zero differential current is effectively added to the input of OP1. However, by controlling the duty cycle to a value different from 50%, sub-LSB (least significant bit) correction current is added to the input of OP1. Therefore, by using dual-balanced resistors 429 and 430 and switching them between the VGP and VGM virtual ground nodes, the balanced portion of the resistor network helps improve the resolution of resistor network 410, thus allowing the resulting AFE 310 to have a higher CMRR.

[0023] Because two balancing resistors 429 and 430 are used (to increase the correction range of the balancing stage of resistor network 410 to correct the full range of residual errors as described above), with current i flowing through each of resistors 429 and 430, the current flowing through the combined balancing resistors of resistor network 410 is twice that of a conventional R-2R network with a single balancing resistor. However, the additional balancing resistors reduce linearity compared to a conventional R-2R resistor network. To increase the correction range of the balancing stage of resistor network 410 while maintaining the linearity of the resistor network, an additional (compared to a conventional R-2R network) compensation resistor 440 is coupled in parallel across the unit resistor 427. To ensure that the binary weighting ratio of the resistor network is maintained, resistors 441-443 are added (relative to a conventional R-2R network). Figure 4 The relative current magnitudes through the various branches of the resistor network are shown. Resistor 4R / 3 allows a current of 3i to flow through it, thus maintaining the two currents through resistor 425 as integer powers (e.g., 8i). Resistor 442 is a 2R resistor, allowing a current of 4i to flow through it, thus making the current through resistor 423 the next higher integer power of the two currents compared to the current through resistor 425. That is, the current through resistor 423 is 16i. The reason for including resistor 443 is roughly the same as for resistor 442. Resistors 421, 423, and 425 include R / 2 resistors, instead of a unit resistance R as in the case of an R-2R trapezoidal resistor.

[0024] Δ-Σ modulator 472 in Figure 4The example uses signals to generate control switches SW1-SW4. While a pulse width modulation (PWM) clock could be used to control switches SW1-SW4, using a clock could result in noise being injected into the AFE 310 in the audio frequency range. However, the Δ-Σ modulator 472 injects noise above the audio frequency range, while injecting relatively less noise in the audio frequency range. [In one example, the Δ-Σ modulator 472 includes a quantizer (noise injector) 489 coupled to integrators 481 and 482 (depending on the modulator order) to form a loop. Integrators 481 / 482 form the first stage of the loop, while quantizer 489 forms the last stage. Because integrators 481 / 482 have considerable gain at low frequencies, noise injected by quantizer 489 will be suppressed at frequencies where the integrator gain is high (at low frequencies). At higher frequencies (where integrators 481 / 482 do not have high gain), the noise from quantizer 489 is not suppressed. In this way, the Δ-Σ modulator adds low noise at low frequencies.] Because the audio frequency band is at a relatively low frequency (e.g., 20 Hz to 20 kHz), the Δ-Σ modulator 472 advantageously adds low-level noise to the audio frequency band. However, this higher-frequency noise (above the audio frequency band) may still intermodulate with other high-frequency noise within the system, resulting in some added noise within the audio frequency band.

[0025] Figure 5 It shows the relationship with Figure 4 A similar example, but including a resistor network with a finite impulse response (FIR) filter. The FIR filter includes a delay unit 520 and dual-switch balancing resistors 429 and 430, and corresponding switches SW1-SW4. The delay unit 520 delays the switching control signals Q and QZ of SW3 and SW4 relative to SW1 and SW2. The FIR filter in this example includes a two-tap FIR filter. The two-tap FIR filter is a notch filter and advantageously attenuates noise at frequencies within the notch—frequency ranges above the audio frequency band.

[0026] To mitigate charge injection caused by the switching of the two balancing resistors 429 and 430, in Figure 6In the example, the programmable resistor circuit is implemented as a pair of resistor networks 410P (for the P-side of AFE 310) and 410M (for the M-side of AFE 310). As shown, the VGP outputs of resistor networks 410P and 410M are coupled together, and the VGM outputs are also coupled together. This circuit architecture ensures that the number of components switched between VGP and VGM is the same, regardless of the order. Therefore, symmetry between VGP and VGM is maintained. However, in order to operate the M-side resistor network 410M, the input VIN to resistor network 410M should be the negative version of the input common-mode voltage to resistor network 410P. In one implementation, an inverting amplifier 610 may be included to invert the input voltage of node 340 to VIN of resistor network 410M.

[0027] Figure 7 Another example implementation of the AFE 710 is shown, very similar to those already shown and described above. Two resistor networks 410P and 410M and a Δ-Σ modulator 472 are shown (which may include a two-tap FIR filter as described above). Figure 7 The example AFE 710 does not include an inverting amplifier (such as...). Figure 6 Instead of generating an input voltage (VIN) for the resistor network 410M (as shown), a normalizer 718 is included. The normalizer 718 has an input (IN) 719 and an output (OUT) 720. The input 719 of the normalizer is coupled to the output of OP2. The output 720 of the normalizer is coupled to VIN of the resistor network 410M. The normalizer 718 normalizes the output voltage (OP2_OUT) from OP2 to an appropriate level relative to the voltage at node 340 between resistors Rx1 and Rx2. In one example, the normalizer 718 includes a resistor divider. The signal (OP2_OUT) at the output of OP2 may differ from the voltage at node 340 between resistors Rx1 and Rx2. The normalizer 718 receives the voltage OP2_OUT and outputs a different voltage that is equal to or approximately equal to the voltage at node 340.

[0028] The term "coupled" is used throughout this specification. This term can encompass a connection, communication, or signaling path that achieves a functional relationship consistent with the description of this disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example, device A is coupled to device B; or in a second example, if intermediate component C does not significantly alter the functional relationship between device A and device B, device A is coupled to device B via intermediate component C, such that control signals generated by device B via device A are controlled by device A.

[0029] Modifications may be made to the described embodiments.

Claims

1. A circuit comprising: An analog-to-digital converter, or ADC, has an ADC input. The analog front-end (AFE) has an AFE input and an AFE output. The AFE output is coupled to the ADC input. The AFE includes a programmable gain amplifier (PGA) with a first PGA input and a second PGA input. The PGA also includes a first operational amplifier (OPAMP) with a first OPAMP input and a second OPAMP input. The AFE further includes a programmable resistor circuit. The programmable resistor circuit has a first programmable resistor circuit input, a first programmable resistor circuit output, and a second programmable resistor circuit output, wherein the first programmable resistor circuit input is coupled to the first PGA input and the second PGA input; as well as The programmable resistor circuit includes a resistor network with a first balancing resistor and a second balancing resistor, the first balancing resistor being coupled to the first OP AMP input and the second OP AMP input, and the second balancing resistor being coupled to the first OP AMP input and the second OP AMP input. The circuit further includes a Δ-Σ modulator configured to control a switch to selectively couple the first balancing resistor and the second balancing resistor to the first OP AMP input or to the second OP AMP input.

2. The circuit of claim 1 further includes a filter coupled to the output of the Δ-Σ modulator.

3. The circuit of claim 1 further includes a delay unit coupled between the Δ-Σ modulator and one of the first balancing resistor and the second balancing resistor.

4. The circuit according to claim 1, wherein the programmable resistor circuit comprises: A first switch having a control input, and the first switch being coupled between the first balancing resistor and the first OPAMP input; A second switch has a control input, and the second switch is coupled between the first balancing resistor and the second OPAMP input; A third switch has a control input, and the third switch is coupled between the second balancing resistor and the first OPAMP input; as well as A fourth switch has a control input, and the fourth switch is coupled between the second balancing resistor and the second OPAMP input; The Δ-Σ modulator includes corresponding control outputs coupled to the control inputs of the first switch, the second switch, the third switch, and the fourth switch.

5. The circuit of claim 1, wherein the programmable resistor circuit is a first programmable resistor circuit and the AFE includes a second programmable resistor circuit, wherein the second programmable resistor circuit includes a resistor network having a first balancing resistor and a second balancing resistor, the first balancing resistor of the second programmable resistor circuit being coupled to the first OP AMP input and the second OP AMP input, and the second balancing resistor of the second programmable resistor circuit being coupled to the first OP AMP input and the second OP AMP input.

6. The circuit of claim 5, wherein the AFE includes a second OP AMP having a second OP AMP output, and wherein the second programmable resistor circuit includes a second programmable resistor input coupled to the second OP AMP output.

7. The circuit of claim 5 further includes a voltage level shifter circuit coupled between the second OP AMP output and the second programmable resistor input.

8. A circuit comprising: The first operational amplifier, also known as the first OP AMP, has a first OP AMP input and a second OP AMP input; A first resistor coupled to the input of the first OP AMP, the first resistor providing a positive input; A second resistor coupled to the input of the second OP AMP, the second resistor providing a negative input; A programmable resistor circuit having a programmable resistor input, a first programmable resistor output, and a second programmable resistor output, wherein the programmable resistor input is coupled to the positive input and the negative input, the first programmable resistor output is coupled to the first OP AMP input, and the second programmable resistor output is coupled to the second OP AMP input; and The programmable resistor circuit includes a resistor network with a first balancing resistor and a second balancing resistor, the first balancing resistor being coupled to the first OP AMP input and the second OP AMP input, and the second balancing resistor being coupled to the first OP AMP input and the second OP AMP input. The circuit further includes a Δ-Σ modulator configured to control a switch to selectively couple the first balancing resistor and the second balancing resistor to the first OP AMP input or to the second OP AMP input.

9. The circuit of claim 8, wherein the first OP AMP includes an output, and the circuit further includes an analog-to-digital converter, i.e., an ADC, coupled to the output of the first OP AMP.

10. The circuit of claim 8 further includes a filter coupled to the output of the Δ-Σ modulator.

11. The circuit of claim 8 further includes a delay unit coupled between the Δ-Σ modulator and one of the first balancing resistor and the second balancing resistor.

12. The circuit of claim 8 further includes a storage device configured to store fine-tuning code to be provided to the Δ-Σ modulator.

13. The circuit of claim 8, wherein the programmable resistor circuit comprises: A first switch having a control input, and the first switch being coupled between the first balancing resistor and the first OPAMP input; A second switch has a control input, and the second switch is coupled between the first balancing resistor and the second OPAMP input; A third switch has a control input, and the third switch is coupled between the second balancing resistor and the first OPAMP input; as well as A fourth switch has a control input, and the fourth switch is coupled between the second balancing resistor and the second OPAMP input.

14. The circuit of claim 8, wherein the programmable resistor circuit is a first programmable resistor circuit and the circuit includes a second programmable resistor circuit, wherein the second programmable resistor circuit includes a resistor network having a first balancing resistor and a second balancing resistor, the first balancing resistor of the second programmable resistor circuit being coupled to the first OP AMP input and the second OP AMP input, and the second balancing resistor of the second programmable resistor circuit being coupled to the first OP AMP input and the second OP AMP input.

15. A circuit comprising: The first operational amplifier, also known as the first OP AMP, has a first OP AMP input, a second OP AMP input, and a first OP AMP output; A second OP AMP having a first OP AMP input, a second OP AMP input, and an OP AMP output, wherein the first OP AMP input of the second OP AMP is coupled to the first OP AMP output of the first OP AMP; A first resistor coupled to the input of the first OP AMP, the first resistor providing a positive input; A second resistor coupled to the input of the second OP AMP of the first OP AMP, the second resistor providing a negative input; A first programmable resistor circuit having a programmable resistor input, a first programmable resistor output, and a second programmable resistor output, wherein the programmable resistor input of the first programmable resistor circuit is coupled to the positive input and the negative input, the first programmable resistor output of the first programmable resistor circuit is coupled to the first OP AMP input of the first OP AMP, and the second programmable resistor output of the first programmable resistor circuit is coupled to the second OP AMP input of the first OP AMP. as well as A second programmable resistor circuit having a programmable resistor input, a first programmable resistor output, and a second programmable resistor output, wherein the programmable resistor input of the second programmable resistor circuit is coupled to the OPAMP output of the second OP AMP, the first programmable resistor output of the second programmable resistor circuit is coupled to the first OPAMP input of the first OP AMP, and the second programmable resistor output of the second programmable resistor circuit is coupled to the second OPAMP input of the first OP AMP.

16. The circuit of claim 15, further comprising a normalizer circuit coupled between the first OP AMP output of the second OP AMP and the programmable resistor input of the second programmable resistor circuit, the normalizer circuit being configured to adjust the voltage on the first OP AMP output of the second OP AMP to be supplied to the programmable resistor input of the second programmable resistor circuit.

17. The circuit of claim 15, wherein the first programmable resistor circuit includes a resistor network, and the second programmable resistor circuit includes a resistor network, and the circuit further includes a Δ-Σ modulator coupled to the first programmable resistor circuit and the second programmable resistor circuit.

18. The circuit of claim 17 further includes a finite impulse response filter, i.e., an FIR filter, coupled to the Δ-Σ modulator.

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