Display device

Abstract

A display device according to an embodiment includes: a substrate; a first insulating layer; a first pixel electrode disposed in a pixel; a second pixel electrode disposed in a dummy pixel; a second insulating layer having an opening; a first organic layer that is in contact with the first pixel electrode through the opening; a second organic layer disposed in the dummy pixel; first and second power supply lines disposed on the second insulating layer; first and second partition walls disposed on the first and second power supply lines; and a common electrode including first and second portions that cover the first and second organic layers. The first organic layer is located between the first and second partition walls and is separated from the first and second partition walls. The second power supply line and the second partition wall are located between the first organic layer and the second organic layer. The first and second partition walls have a shape in which the width of the upper portion is larger than the width of the lower portion. The first portion is in contact with the first power supply line between the first partition wall and the first organic layer.

Description

[0001] Cross - reference to related applications

[0002] This application is based on and claims the priority of Japanese Application No. 2020 - 190930 filed on November 17, 2020, the entire content of which is incorporated herein by reference. Technical field

[0003] Embodiments of the present invention relate to a display device. Background art

[0004] In recent years, a display device using an organic light - emitting diode (OLED) as a display element has been put into practical use. The display element includes a pixel electrode, a common electrode, and an organic layer disposed between the pixel electrode and the common electrode.

[0005] When patterning elements such as electrodes and wirings repeatedly arranged in a display area, sometimes the shape of the outermost - peripheral element among these elements is not formed as designed. For example, when patterning the pixel electrodes of each pixel by etching, the outermost - peripheral pixel electrodes are eroded excessively. If such a shape defect occurs, the display quality of the display device deteriorates. Summary of the invention

[0006] A display device according to an embodiment includes a substrate, a first insulating layer, a first pixel electrode, a second pixel electrode, a second insulating layer, a first organic layer, a second organic layer, a first power supply line, a second power supply line, a second partition wall, and a common electrode. The first insulating layer is disposed on the substrate. The first pixel electrode is disposed on the first insulating layer in pixels located in a display area. The second pixel electrode is disposed on the first insulating layer in dummy pixels located in a peripheral area outside the display area. The second insulating layer is disposed on the first insulating layer and has an opening overlapping with the first pixel electrode. The first organic layer is disposed on the pixels and is in contact with the first pixel electrode through the opening. The second organic layer is disposed on the dummy pixels. The first power supply line and the second power supply line are disposed on the second insulating layer. The first partition wall is disposed on the first power supply line. The second partition wall is disposed on the second power supply line. The common electrode includes a first portion covering the first organic layer and a second portion covering the second organic layer. The first organic layer is located between the first partition wall and the second partition wall and is separated from the first partition wall and the second partition wall. The second power supply line and the second partition wall are located between the first organic layer and the second organic layer. The first partition wall and the second partition wall have a shape in which the width of the upper part is larger than the width of the lower part. The first portion is in contact with the first power supply line between the first partition wall and the first organic layer.

[0007] According to the above configuration, a display device capable of improving display quality can be provided. Description of the Drawings

[0008] Figure 1 FIG. is a diagram showing a configuration example of a display device according to the first embodiment.

[0009] Figure 2 FIG. is a diagram showing an example of the layout of sub-pixels and dummy sub-pixels.

[0010] Figure 3 is along Figure 2 A schematic cross-sectional view of the display device along line III-III.

[0011] Figure 4 FIG. is a cross-sectional view showing an example of a layer configuration applicable to an organic layer.

[0012] Figure 5 is Figure 3 A schematic top view of the pixel electrode and the organic layer shown.

[0013] Figure 6 is Figure 3 A schematic top view of the power supply line, the partition wall, the common electrode, and the conductive layer shown.

[0014] Figure 7 FIG. is a schematic cross-sectional view of the display device according to the second embodiment. Detailed Embodiments

[0015] Hereinafter, embodiments of the present invention will be described with reference to the accompanying Figure 1 drawings.

[0016] In addition, the disclosure is only an example, and appropriate changes that can be easily conceived by those skilled in the art while maintaining the gist of the invention are of course included in the scope of the present invention. In addition, for the sake of clarity of explanation, the drawings may schematically show the widths, thicknesses, shapes, etc. of each part compared with the actual mode, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each drawing, sometimes constituent elements that perform the same or similar functions as those described in the drawings that have already appeared are denoted by the same reference numerals, and repeated detailed descriptions are appropriately omitted.

[0017] In addition, in the drawings, as needed, the X-axis, Y-axis, and Z-axis orthogonal to each other are described for easy understanding. The direction along the X-axis is called the X direction or the first direction, the direction along the Y-axis is called the Y direction or the second direction, and the direction along the Z-axis is called the Z direction or the third direction. The plane defined by the X-axis and the Y-axis is called the X-Y plane, and the plane defined by the X-axis and the Z-axis is called the X-Z plane. Looking at the X-Y plane is called a top view.

[0018] The display device DSP of the present embodiment is an organic electroluminescent display device having an organic light-emitting diode (OLED) as a display element, and is mounted on a television, a personal computer, a vehicle-mounted device, a portable terminal, a mobile phone, etc.

[0019] [First Embodiment]

[0020] Figure 1 It is a diagram showing a configuration example of the display device DSP of the first embodiment. The display device DSP has a display area DA for displaying an image and a peripheral area SA outside the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0021] The display area DA includes a plurality of pixels PX arranged in a matrix along a first direction X and a second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. In addition, the pixel PX may also include four or more sub-pixels including sub-pixels of other colors such as white in addition to the above three-color sub-pixels.

[0022] The sub-pixel SP includes a pixel circuit 1 and a display element 20 driven and controlled by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements formed of thin film transistors, for example.

[0023] In the pixel switch 2, the gate electrode is connected to the scan line GL, the source electrode is connected to the signal line SL, and the drain electrode is connected to one electrode of the capacitor 4 and the gate electrode of the driving transistor 3. In the driving transistor 3, the source electrode is connected to the other electrode of the capacitor 4 and the power supply line PL, and the drain electrode is connected to the anode of the display element 20. The cathode of the display element 20 is connected to a power supply line FL (auxiliary wiring) for supplying a common voltage. In addition, the configuration of the pixel circuit 1 is not limited to the example shown in the figure.

[0024] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element. For example, the sub-pixel SP1 includes a display element that emits light corresponding to a red wavelength, the sub-pixel SP2 includes a display element that emits light corresponding to a green wavelength, and the sub-pixel SP3 includes a display element that emits light corresponding to a blue wavelength. The configuration of the display element 20 will be described later.

[0025] The peripheral area SA includes a plurality of dummy pixels DP that do not display an image. For example, the plurality of dummy pixels DP surround the display area DA. That is, the dummy pixels DP are located between the outermost pixels PX and the respective sides of the substrate 10.

[0026] Dummy pixel DP includes a plurality of dummy sub-pixels DS. In one example, dummy pixel DP includes: a dummy sub-pixel DS1 having a structure similar to that of sub-pixel SP1; a dummy sub-pixel DS2 having a structure similar to that of sub-pixel SP2; and a dummy sub-pixel DS3 having a structure similar to that of sub-pixel SP3.

[0027] Figure 2 It is a diagram showing an example of the layout of sub-pixels SP1, SP2, SP3 and dummy sub-pixels DS1, DS2, DS3. Here, focusing on Figure 1 the four pixels PX surrounded by the dashed box and the five dummy pixels DP around them.

[0028] In each pixel PX, sub-pixel SP1 and sub-pixel SP2 are arranged along the second direction Y, sub-pixel SP1 and sub-pixel SP3 are arranged along the first direction X, and sub-pixel SP2 and sub-pixel SP3 are arranged along the first direction X. Sub-pixel SP1 is formed in a substantially rectangular shape extending along the first direction X, and sub-pixels SP2 and SP3 are formed in a substantially rectangular shape extending along the second direction Y. The area of sub-pixel SP2 is larger than the area of sub-pixel SP1, and the area of sub-pixel SP3 is larger than the area of sub-pixel SP2. In addition, the area of sub-pixel SP1 may be the same as the area of sub-pixel SP2.

[0029] If we focus on the plurality of pixels PX arranged in the display area DA, sub-pixel SP1 and sub-pixel SP3 are alternately arranged in the first direction X. Sub-pixel SP2 and sub-pixel SP3 are also alternately arranged in the first direction X. In addition, sub-pixel SP1 and sub-pixel SP2 are alternately arranged in the second direction Y. Sub-pixel SP3 is arranged in the second direction Y without being separated by sub-pixels SP1 and SP2.

[0030] Dummy sub-pixel DS1 has the same shape as sub-pixel SP1, dummy sub-pixel DS2 has the same shape as sub-pixel SP2, and dummy sub-pixel DS3 has the same shape as sub-pixel SP3. The arrangement of dummy sub-pixels DS1, DS2, DS3 in dummy pixel DP is the same as the arrangement of sub-pixels SP1, SP2, SP3 in pixel PX.

[0031] In addition, Figure 2 The outer shapes of the sub-pixels SP1, SP2, SP3 and the dummy sub-pixels DS1, DS2, DS3 shown are equivalent to the pixel electrodes of the display element or the outer shapes of the light-emitting regions of the display element, but are simplified and do not necessarily reflect the actual shape. In addition, the shape of each of the dummy sub-pixels DS1, DS2, DS3 only needs to be a shape similar to the shape of each of the sub-pixels SP1, SP2, SP3, and is not necessarily limited to the same shape.

[0032] Figure 3 is along Figure 2 a schematic cross-sectional view of a display device DSP along line III-III. The display device DSP includes an insulating layer 11 (first insulating layer) disposed on a substrate 10 and an insulating layer 12 (second insulating layer) disposed on the insulating layer 11. Figure 1 The pixel circuit 1, scanning line GL, signal line SL, and power line PL shown in the figure are disposed on the substrate 10 and covered by the insulating layer 11, but the illustration is omitted here. The insulating layers 11 and 12 are, for example, organic insulating layers. The insulating layer 11 may be a base layer of a display element 20. The insulating layer 12 is formed to divide the display element 20 or sub-pixel SP, and may be called ribs, partitions, etc.

[0033] As Figure 3 shown by the sub-pixel SP3, the display element 20 of each sub-pixel SP includes a pixel electrode PE1 (first pixel electrode), an organic layer OR1 (first organic layer), and a common electrode CE. The pixel electrode PE1 is an electrode arranged for each sub-pixel SP or each display element 20, and may be called a lower electrode or an anode, etc. The common electrode CE is an electrode commonly arranged for a plurality of sub-pixels SP or a plurality of display elements 20, and may be called a counter electrode, an upper electrode, or a cathode, etc.

[0034] The pixel electrode PE1 is disposed on the insulating layer 11, and its peripheral portion is covered by the insulating layer 12. The pixel electrode PE1 is electrically connected to Figure 1 the driving transistor 3 shown in the figure. The pixel electrode PE1 is, for example, a transparent electrode formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). In addition, the pixel electrode PE1 may also be a metal electrode formed of a metal material such as silver or aluminum. In addition, the pixel electrode PE1 may also be a laminate of a transparent electrode and a metal electrode. For example, the pixel electrode PE1 may be configured as a laminate formed by sequentially laminating a transparent electrode, a metal electrode, and a transparent electrode, or may be configured as a laminate of three or more layers.

[0035] The insulating layer 12 has an opening OP that overlaps with the pixel electrode PE1 in each sub-pixel SP. The organic layer OR1 is disposed on the insulating layer 12 and is in contact with the pixel electrode PE1 through the opening OP.

[0036] Figure 4It is a cross-sectional view showing an example of the layer structure applicable to the organic layer OR1. For example, the organic layer OR1 includes a functional layer F1, a light-emitting layer EL, and a functional layer F2 that are sequentially stacked from the pixel electrode PE1 toward the common electrode CE. The functional layers F1 and F2 are, for example, a hole injection layer, a hole transport layer, a hole blocking layer, an electron injection layer, an electron transport layer, or an electron blocking layer, but they can also be other functional layers. Each of the functional layers F1 and F2 is not limited to a single layer, and can also be a laminate in which multiple functional layers are stacked. In addition, at least one of the functional layers F1 and F2 can be omitted.

[0037] As Figure 3 and Figure 4 shown, the common electrode CE covers the organic layer OR1. The common electrode CE is, for example, a transparent electrode formed of a transparent conductive material such as ITO or IZO. In addition, the common electrode CE can be covered with a transparent protective film (including at least one of an inorganic insulating film and an organic insulating film).

[0038] When the potential of the pixel electrode PE1 is relatively higher than the potential of the common electrode CE, the pixel electrode PE1 serves as an anode and the common electrode CE serves as a cathode. In addition, when the potential of the common electrode CE is relatively higher than the potential of the pixel electrode PE1, the common electrode CE serves as an anode and the pixel electrode PE1 serves as a cathode.

[0039] As an example, when the pixel electrode PE1 serves as an anode, the functional layer F1 includes at least one of a hole injection layer and a hole transport layer, and the functional layer F2 includes at least one of an electron transport layer and an electron injection layer.

[0040] As Figure 3 shown by the dummy sub-pixels DS1 and DS3, the dummy sub-pixel DS includes a pixel electrode PE2 (second pixel electrode) and an organic layer OR2 (second organic layer). The pixel electrode PE2 is disposed on the insulating layer 11 in the same manner as the pixel electrode PE1 and is covered by the insulating layer 12. The pixel electrode PE2 is formed of the same material as the pixel electrode PE1 through the same process as the pixel electrode PE1. The organic layer OR2 is disposed on the insulating layer 12 in the same manner as the organic layer OR1 and is covered by the common electrode CE. The organic layer OR2 has the same structure as the organic layer OR1 and, in one example, includes a light-emitting layer EL and functional layers F1 and F2.

[0041] In Figure 3 the example, the insulating layer 12 does not have an opening in the dummy sub-pixel DS. Thus, the pixel electrode PE2 of each dummy sub-pixel DS faces the organic layer OR2 with the insulating layer 12 therebetween. In the dummy sub-pixel DS having such a structure, even if a potential difference is assumed to be formed between the pixel electrode PE2 and the common electrode CE, the organic layer OR2 does not emit light.

[0042] The dummy sub-pixel DS may also have the same pixel circuit 1 as the sub-pixel SP. The pixel circuit 1 may be connected to the pixel electrode PE2 or may not be connected to the pixel electrode PE2. When the dummy sub-pixel DS has the pixel circuit 1, the pixel circuit 1 of the sub-pixel SP can be protected from electrostatic discharge generated during the manufacturing process of the display device DSP and the like by using the pixel circuit 1.

[0043] A power supply line FL and a partition wall PT are disposed between the organic layers OR1 of two adjacent sub-pixels SP, between the organic layer OR1 of the sub-pixel SP and the organic layer OR2 of the dummy sub-pixel DS adjacent to the sub-pixel SP, and between the organic layers OR2 of two adjacent dummy sub-pixels DS. In Figure 3 the example of, a partition wall PT is also disposed to the right of the dummy sub-pixel DS3. The power supply line FL is formed of a metal material. The partition wall PT is, for example, an organic insulating layer.

[0044] In the following description, the three power supply lines FL shown in Figure 3 may sometimes be referred to as a power supply line FL1 (first power supply line), a power supply line FL2 (second power supply line), and a power supply line FL3 (third power supply line) in order from the left. In addition, the four partition walls PT shown in Figure 3 may sometimes be referred to as a partition wall PT1 (first partition wall), a partition wall PT2 (second partition wall), a partition wall PT3 (third partition wall), and a partition wall PT4 (fourth partition wall) in order from the left.

[0045] The partition wall PT1 is disposed on the power supply line FL1. The partition wall PT2 is disposed on the power supply line FL2. The partition wall PT3 is disposed on the power supply line FL3. The partition wall PT4 is disposed on the conductive layer CL1 (first conductive layer). The conductive layer CL1 is disposed on the insulating layer 12 and is formed of the same metal material as each power supply line FL by the same process as each power supply line FL.

[0046] Each partition wall PT has an inverted cone shape. Here, the inverted cone shape means a shape in which the width W1 at the upper part is larger than the width W2 at the lower part as shown by the partition wall PT1 in Figure 3 . The side surface of the partition wall PT may be a plane inclined with respect to the third direction Z or may be a curved surface. In addition, the partition wall PT may be composed of a plurality of parts whose widths gradually decrease from the upper part to the lower part.

[0047] The organic layer OR1 of the sub-pixel SP3 is located between the adjacent walls PT1 and PT2, and is separated from the adjacent walls PT1 and PT2. The organic layer OR2 of the dummy sub-pixel DS1 is located between the adjacent walls PT2 and PT3, and is separated from the adjacent walls PT2 and PT3. The organic layer OR2 of the dummy sub-pixel DS3 is located between the adjacent walls PT3 and PT4, and is separated from the adjacent walls PT3 and PT4.

[0048] The width of the power supply line FL is larger than the width W2 of the lower part of the adjacent wall PT. Moreover, in the Figure 3 example, the width of the power supply line FL is larger than the width W1 of the upper part of the adjacent wall PT. Both ends of the power supply line FL protrude from the adjacent wall PT disposed above the power supply line FL. That is, for example, when focusing on the second power supply line FL2, the second power supply line FL2 has a first end E11 on the organic layer OR1 side of the sub-pixel SP3 and a second end E12 on the organic layer OR2 side of the dummy sub-pixel DS1. The first end E11 protrudes more toward the organic layer OR1 side than the adjacent wall PT2 and is not covered by the adjacent wall PT2. The second end E12 protrudes more toward the organic layer OR2 side than the adjacent wall PT2 and is not covered by the adjacent wall PT2. The first end E11 is covered by the organic layer OR1. The second end E12 is covered by the organic layer OR2. A gap is formed between the first end E11 and the organic layer OR1. A gap is formed between the second end E12 and the organic layer OR2. Additionally, depending on the conditions of the width W1 and height of the upper part of the adjacent wall PT and the width of the power supply line FL, the organic layer OR may not cover the ends of the power supply line FL.

[0049] The conductive layer CL1 has a first end E21 disposed on the organic layer OR2 side of the dummy sub-pixel DS3 and a second end E22 on the opposite side thereof. These ends E21, E22 are not covered by the adjacent wall PT4.

[0050] The common electrode CE is formed integrally over the region including the sub-pixel SP and the dummy sub-pixel DS by, for example, evaporation. At this time, the organic layers OR1, OR2, and the upper part of the adjacent wall PT are covered by the common electrode CE. In the Figure 3 example, the conductive layer CL1 is also covered by the common electrode CE. On the other hand, since the adjacent wall PT has the above-described inverted cone shape, almost no common electrode CE is formed on the side surface of the adjacent wall PT. Thus, the common electrode CE is divided at the position of the adjacent wall PT.

[0051] Here, in the common electrode CE, the part covering the organic layer OR1 is referred to as the first part P1, the part covering the organic layer OR2 is referred to as the second part P2, the part covering the upper part of the adjacent wall PT is referred to as the third part P3, and the part covering the conductive layer CL1 is referred to as the fourth part P4. The third part P3 is separated from one of the first part P1, the second part P2, and the fourth part P4.

[0052] As Figure 3 shown, the first portion P1 of the organic layer OR1 covering the sub-pixel SP3 is connected to the power supply line FL1 through the gap between the partition wall PT1 and the organic layer OR1. Moreover, the first portion P1 is connected to the power supply line FL2 through the gap between the partition wall PT2 and the organic layer OR1. The other sub-pixels SP also have the same structure as the Figure 3 sub-pixel SP3 shown

[0053] The second portion P2 of the organic layer OR2 covering the dummy sub-pixel DS1 is connected to the power supply line FL2 through the gap between the partition wall PT2 and the organic layer OR2. Moreover, the second portion P2 is connected to the power supply line FL3 through the gap between the partition wall PT3 and the organic layer OR2. The second portion P2 of the organic layer OR2 covering the dummy sub-pixel DS3 is connected to the power supply line FL3 through the gap between the partition wall PT3 and the organic layer OR2. Moreover, the second portion P2 is connected to the conductive layer CL1 through the gap between the partition wall PT4 and the organic layer OR2. The other dummy sub-pixels DS also have the same structure as the Figure 3 dummy sub-pixel DS1 or dummy sub-pixel DS3 shown

[0054] The display device DSP further includes a conductive layer CL2 (second conductive layer) disposed between the insulating layers 11 and 12 and a conductive layer CL3 (third conductive layer) disposed between the substrate 10 and the insulating layer 11. In the peripheral region SA, the insulating layer 12 has a contact hole CH1 (first contact hole), and the insulating layer 11 has a contact hole CH2 (second contact hole). For example, the conductive layer CL2 is formed of the same material as the pixel electrodes PE1 and PE2 by the same process as the pixel electrodes PE1 and PE2.

[0055] The conductive layer CL1 is connected to the conductive layer CL2 through the contact hole CH1. The conductive layer CL2 is connected to the conductive layer CL3 through the contact hole CH2. A common voltage is supplied to the conductive layer CL3. The common voltage is supplied to the first portion P1, the second portion P2, and the fourth portion P4 of the common electrode CE via the conductive layer CL2, the conductive layer CL1, and the power supply line FL.

[0056] In Figure 3In the example, an organic layer OR3 is disposed over the conductive layer CL1. The organic layer OR3 is covered by the fourth part P4. For example, the above-mentioned light-emitting layer EL in the organic layers OR1 and OR2 is separately formed for each color of the sub-pixel SP and the dummy sub-pixel DS. On the other hand, at least a part of the layers included in the above-mentioned functional layers F1 and F2 is simultaneously formed for the entire region including the sub-pixel SP and the dummy sub-pixel DS. For example, the organic layer OR3 is a part of the layer (shared layer) that is simultaneously formed for each sub-pixel SP and each dummy sub-pixel DS and is divided by the partition wall PT4. In this case, the organic layer OR3 may not include the light-emitting layer EL.

[0057] In addition, at least a part of the layers constituting the organic layers OR1 and OR2 may be disposed on the upper part of the partition wall PT. For example, when the light-emitting layer EL and the functional layers F1 and F2 are formed within the range overlapping with the partition wall PT, a part of the light-emitting layer EL and the functional layers F1 and F2 is disposed between the upper part of the partition wall PT and the third part P3. Since the partition wall PT has an inverted conical shape, this part is separated from the organic layers OR1 and OR2.

[0058] Figure 5 It is a schematic plan view of the pixel electrodes PE1 and PE2 and the organic layers OR1, OR2, and OR3. The pixel electrode PE1 is disposed separately for each of the sub-pixels SP1, SP2, and SP3. These pixel electrodes PE1 overlap with the above-mentioned opening OP. The pixel electrode PE2 is disposed separately for each of the dummy sub-pixels DS1, DS2, and DS3.

[0059] The organic layer OR1 overlaps with the pixel electrode PE1 in each of the sub-pixels SP1, SP2, and SP3. In Figure 5 the example, a continuous organic layer OR1 is disposed for a plurality of sub-pixels SP3 arranged along the second direction Y.

[0060] The organic layer OR2 overlaps with the pixel electrode PE2 in each of the dummy sub-pixels DS1, DS2, and DS3. In Figure 5 the example, a continuous organic layer OR2 is disposed for a plurality of dummy sub-pixels DS3 arranged along the second direction Y. The organic layer OR2 of the dummy sub-pixel DS3 adjacent to the sub-pixel SP3 in the second direction Y is connected to the organic layer OR1 of the sub-pixel SP3.

[0061] The organic layer OR3 has a portion extending along the first direction X and a portion extending along the second direction Y. For example, the organic layer OR3 is formed in a ring shape in the peripheral area SA. The dummy sub-pixels DS1, DS2, and DS3 are located between the display area DA and the organic layer OR3.

[0062] Figure 6It is a schematic top view of the power supply line FL, the partition wall PT, the common electrode CE, and the conductive layers CL1, CL2, and CL3. The power supply line FL includes a power supply line FLx extending in the first direction X and a power supply line Fly extending in the second direction Y.

[0063] The power supply lines FLx and Fly are arranged between two adjacent sub-pixels SP, between two adjacent dummy sub-pixels DS, and between an adjacent sub-pixel SP and a dummy sub-pixel DS, and are integrally formed in a lattice shape. Figure 3 The shown power supply lines FL1, FL2, and FL3 are all power supply lines Fly.

[0064] The partition wall PT corresponds to the area with dots added in the figure. The partition wall PT includes a partition wall PTx extending in the first direction X and a partition wall PTy extending in the second direction Y. Figure 3 The shown partition walls PT1, PT2, PT3, and PT4 are all partition walls PTy.

[0065] The partition wall PTy is arranged above the power supply line Fly. The outermost partition wall Pty in the first direction X overlaps with the conductive layer CL1. The partition wall PTx is arranged above the power supply line FLx and is connected to the adjacent partition wall PTy between the sub-pixels SP1 and SP2 arranged in the second direction Y and between the dummy sub-pixels DS1 and DS2 arranged in the second direction Y. The partition wall PTx is not arranged between the sub-pixels SP3 arranged in the second direction Y and between the dummy sub-pixels DS3 arranged in the second direction Y. In addition, the outermost partition wall PTx in the second direction Y overlaps with the conductive layer CL1, extends longer than other partition walls PTx, and is connected to all partition walls PTy.

[0066] For example, the conductive layers CL1, CL2, and CL3 are formed in a ring shape in the peripheral area SA. The dummy sub-pixels DS1, DS2, and DS3 are located between the display area DA and the conductive layers CL1, CL2, and CL3. The power supply lines FLx and Fly are connected to the conductive layer CL1.

[0067] In Figure 6 's example, a plurality of contact holes CH1 and CH2 are formed around the dummy sub-pixels DS1, DS2, and DS3. The contact hole CH1 is located on the side closer to the display area DA than the contact hole CH2. As another example, the contact hole CH1 may also have a long strip shape that connects a plurality of contact holes CH1 arranged in the first direction X in Figure 6 and a plurality of contact holes CH1 arranged in the second direction Y into one. Similarly, the contact hole CH2 may also have a long strip shape that connects a plurality of contact holes CH2 arranged in the first direction X in Figure 6 and a plurality of contact holes CH2 arranged in the second direction Y into one.

[0068] AsFigure 6 As shown by the dashed line in the figure, the common electrode CE is disposed in a region including sub-pixels SP1, SP2, SP3 and dummy sub-pixels DS1, DS2, DS3. The end edge of the common electrode CE is located between the contact holes CH1 and CH2.

[0069] Figure 3 The cross-sectional structure along the first direction X of the sub-pixel SP3 and the dummy sub-pixels DS1 and DS3 is shown, but the cross-sectional structure along the first direction X of the sub-pixels SP1 and SP2 is the same as that of the sub-pixel SP3, and the cross-sectional structure along the first direction X of the dummy sub-pixel DS2 is the same as that of the dummy sub-pixel DS1. In addition, the cross-sectional structure along the second direction Y of the sub-pixels SP1 and SP2 is also the same as Figure 3 the cross-sectional structure of the sub-pixel SP3 in Figure 3 and the cross-sectional structures along the second direction Y of the dummy sub-pixels DS1 and DS2 are also the same as

[0070] Among the elements disposed in each sub-pixel SP in the display area DA, for example, the pixel electrode PE1 is patterned by etching. When forming a plurality of elements simultaneously by etching in this way, the outermost peripheral portion of these elements may be over-etched. Therefore, when there is no conductive layer the same as the pixel electrode PE1 outside the outermost peripheral pixel electrode PE1 in the display area DA, the pixel PX including the outermost peripheral pixel electrode PE1 cannot obtain the designed configuration, and the display quality may be reduced.

[0071] In contrast, in the present embodiment, a dummy pixel DP including a pixel electrode PE2 having the same shape as the pixel electrode PE1 is disposed outside the outermost peripheral pixel PX in the display area DA. Therefore, excessive erosion is not likely to occur in the pixel electrode PE1 of the outermost peripheral pixel PX, and as a result, the display quality of the display device DSP can be improved.

[0072] In addition, when Figure 3 a partition wall PT having an inverted cone shape as shown is disposed between the sub-pixel SP and the dummy sub-pixel DS, since the common electrode CE is divided by the partition wall PT, it is necessary to study the structure related to the power supply to the common electrode CE disposed in the sub-pixel SP. Regarding this point, as described using Figure 3 and Figure 6 , if the power supply line FL is disposed under the partition wall PT and the power supply line FL is connected to the common electrode CE, a voltage can be appropriately applied to the common electrode CE of each sub-pixel SP.

[0073] In addition to this, various preferable effects can also be obtained according to the present embodiment.

[0074] [Second Embodiment]

[0075] The second embodiment will be described. Components not particularly mentioned are the same as those in the first embodiment.

[0076] The figure is a schematic cross-sectional view of the display device DSP of the seventh embodiment. In the example of this figure, one end of the power supply line FL is covered by the partition wall PT. That is, for example, if we focus on the second power supply line FL2, its first end E11 is covered by the partition wall PT2, and the second end E12 is not covered by the partition wall PT2. The relationship between the power supply line FL1 and the partition wall PT1, and the relationship between the power supply line FL3 and the partition wall PT3 are the same. Also, in Figure 7 the example, the first end E21 of the conductive layer CL1 is covered by the partition wall PT4, and the second end E22 is not covered by the partition wall PT4.

[0077] The first part P1 of the organic layer OR1 covering the sub-pixel SP3 in the common electrode CE is connected to the power supply line FL1 through the gap between the partition wall PT1 and the organic layer OR1. Since the first end E11 of the power supply line FL2 is covered by the partition wall PT2, this first part P1 is not connected to the power supply line FL2. Other sub-pixels SP also have the same structure as Figure 7 the sub-pixel SP3 shown.

[0078] The second part P2 of the organic layer OR2 covering the dummy sub-pixel DS1 in the common electrode CE is connected to the power supply line FL2 through the gap between the partition wall PT2 and the organic layer OR2, but is not connected to the power supply line FL3. Also, the second part P2 of the organic layer OR2 covering the dummy sub-pixel DS3 is connected to the power supply line FL3 through the gap between the partition wall PT3 and the organic layer OR2, but is not connected to the conductive layer CL1. Other dummy sub-pixels DS also have the same structure as Figure 7 the dummy sub-pixel DS1 or the dummy sub-pixel DS3 shown.

[0079] Thus, in this embodiment, the two first parts P1 respectively disposed in adjacent sub-pixels SP are not connected via the power supply line FL therebetween. Similarly, the first part P1 and the second part P2 respectively disposed in adjacent sub-pixels SP and dummy sub-pixels DS, and the two second parts P2 respectively disposed in adjacent dummy sub-pixels DS are also not connected via the power supply line FL therebetween. In Figure 7 the cross-section along the first direction X has been described, but the cross-section along the second direction Y is the same.

[0080] As described above Figure 3As in the example of , when the first parts P1 respectively arranged in adjacent sub-pixels SP are connected via the power supply line FL, there is a possibility that the current flowing through the display element 20 of one sub-pixel SP leaks to the display element 20 of the other sub-pixel SP. If such leakage between sub-pixels SP occurs, it may cause display defects and be one of the reasons for the increase in the driving power of the display device DSP. On the contrary, with the structure of the present embodiment, the leakage of current between the display elements 20 of adjacent sub-pixels SP can be suppressed.

[0081] In the above embodiments, the layout and configuration of the pixel PX and the dummy pixel DP are not limited to Figure 1 and Figure 2 the layout and configuration shown. For example, in each pixel PX, sub-pixels SP (SP1, SP2, SP3) of the same shape may be arranged along the first direction X. Similarly, in the dummy pixel DP, dummy sub-pixels DS (DS1, DS2, DS3) of the same shape may be arranged along the first direction X. In Figure 1 and Figure 2 , the dummy pixel DP is arranged only once around the display area DA, but it may also be arranged two or more times.

[0082] In Figure 7 , a configuration is illustrated in which the first end portion E11 of the power supply line FL2 is covered by the partition wall PT2 and the second end portion E12 is not covered by the partition wall PT2. As another example, the first end portion E11 may not be covered by the partition wall PT2 and the second end portion E12 may be covered by the partition wall PT2. The relationship between the other power supply lines FL and the partition wall PT can also be changed in the same way.

[0083] In Figure 3 and Figure 7 , a configuration is illustrated in which the second part P2 arranged in the dummy sub-pixel DS is connected to a certain power supply line FL. As another example, the second part P2 may not be connected to any power supply line FL. In this case, the second part P2 floats.

[0084] All display devices that can be appropriately designed and modified by those skilled in the art based on the display device described as an embodiment of the present invention, as long as they include the gist of the present invention, also belong to the scope of the present invention.

[0085] Within the scope of the idea of the present invention, various variations can be conceived by those skilled in the art, and these variations should also be understood to belong to the scope of the present invention. For example, the ways in which those skilled in the art appropriately add, delete, or modify the components of the above embodiments, or the ways in which they add, omit, or change the conditions of the processes, as long as they have the gist of the present invention, are also included in the scope of the present invention.

[0086] In addition, with regard to other effects brought about by the methods described in the above-described embodiments, the content made clear according to the description of this specification or the content that can be appropriately conceived by those skilled in the art is of course considered to be brought about by the present invention.

Claims

1. A display device, characterized in that, Comprising: A substrate; A first insulating layer disposed on the substrate; A first pixel electrode disposed on the first insulating layer in pixels located in the display area; A second pixel electrode disposed on the first insulating layer in dummy pixels located in the peripheral area outside the display area; A second insulating layer disposed on the first insulating layer and having an opening overlapping with the first pixel electrode; A first organic layer disposed on the pixel and contacting the first pixel electrode through the opening; A second organic layer disposed on the dummy pixel and on the second insulating layer; A first power supply line and a second power supply line disposed on the second insulating layer; A first partition disposed on the first power supply line; A second partition disposed on the second power supply line; And A common electrode including a first portion covering the first organic layer and a second portion covering the second organic layer, The first organic layer is located between the first partition and the second partition and is separated from the first partition and the second partition, The second power supply line and the second partition are located between the first organic layer and the second organic layer, The first partition and the second partition have a shape with a width at the upper part larger than that at the lower part, The first portion contacts the first power supply line between the first partition and the first organic layer and does not contact the second power supply line.

2. The display device according to claim 1, wherein The second organic layer is separated from the second partition, The second portion contacts the second power supply line between the second partition and the second organic layer.

3. The display device according to claim 1, wherein The second power supply line has a first end on the side of the first organic layer and a second end on the side of the second organic layer, The first end is covered by the second partition, The second end is not covered by the second partition.

4. The display device according to any one of claims 1 to 3, wherein The common electrode further includes a third portion respectively disposed on the upper parts of the first partition and the second partition, The third portion is separated from the first portion and the second portion.

5. The display device according to any one of claims 1 to 3, wherein The display device further comprises: A first conductive layer disposed on the second insulating layer in the peripheral area and connected to the first power supply line and the second power supply line; and A second conductive layer disposed between the first insulating layer and the second insulating layer in the peripheral area, The second insulating layer has a first contact hole in the peripheral area, The first conductive layer contacts the second conductive layer through the first contact hole.

6. The display device according to claim 5, wherein The display device further comprises a third conductive layer disposed between the substrate and the first insulating layer in the peripheral area, The first insulating layer has a second contact hole in the peripheral area, The second conductive layer contacts the third conductive layer through the second contact hole.

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