Processing device, processing system and processing method

Abstract

The application discloses a processing device, a processing system, a processing method and a computer readable medium related to interrupt processing and exception processing. The processing device comprises: a plurality of registers for storing information; a decision maker for providing decision data corresponding to an interrupt request, the decision data representing a register save list for designating one or more registers of the plurality of registers as live save registers corresponding to the interrupt request; and an interrupt processing module for receiving the interrupt request and the corresponding decision data, and providing a corresponding interrupt service in response to the interrupt request, wherein the decision maker designates the one or more registers designated by the list as the live save registers corresponding to the interrupt request based on a list of registers operated in the process of response. The processing device, system and method provided by the application do not need to cache all the registers of the caller attributes in the live protection stage, which is beneficial to reduce the response time.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processors, and in particular, to a processing device, a processing system, a processing method and a computer readable medium related to interrupt processing and exception processing. BACKGROUND

[0002] In the process of executing a main program by a processor, when an emergency or an abnormal event occurs, the processor suspends the execution of the main program, processes the event, and after processing the event, returns to the breakpoint (usually refers to the address of the first instruction to be executed when returning to the main program) to continue executing the main program that was just suspended. This process is called an interrupt, and the event that triggers the interrupt can be referred to as an interrupt source. In order to respond to the interrupt request initiated by the interrupt source, the processor needs to call an interrupt service routine (ISR) corresponding to the interrupt request by executing an interrupt handler, so as to realize the corresponding interrupt service content.

[0003] Since the running of the main program and the interrupt service routine both depend on the register resources of the processor, in order to avoid the processor from destroying the content written in the registers by the main program when running the interrupt service routine, the interrupt handler needs to save the content of each register at the breakpoint before calling the interrupt service routine (this process can be referred to as context protection). Then, the processor executes the interrupt service routine corresponding to the interrupt request based on each register. In this way, after the running of the interrupt service routine ends, the processor can restore the value of each register saved in the context protection stage to each register, so as to continue executing the main program from the breakpoint based on the content of the restored registers.

[0004] The time period from triggering the interrupt to actually starting to process the interrupt service routine can be used to characterize the response time and real-time performance of the interrupt. In industrial control, microprocessor, embedded, Internet of Things and other application scenarios, various applications are very sensitive to the response time and real-time performance of the interrupt, and the frequency of occurrence of the interrupt in these application scenarios is also high, which further highlights the importance of improving the real-time performance of the interrupt and reducing the response time. SUMMARY

[0005] The present disclosure aims to cache the content of some specified registers during the context protection stage in the interrupt response process based on a preset register saving list, without indiscriminately caching all general registers or all general registers with caller attributes during the context protection stage, so as to optimize the response time of the interrupt and improve the real-time performance of the interrupt response.

[0006] According to a first aspect of embodiments of the present disclosure, there is provided a processing apparatus comprising: a plurality of registers configured to store information; a decision maker configured to provide decision data corresponding to an interrupt request, the decision data characterizing a register save list configured to designate one or more registers of the plurality of registers as live save registers corresponding to the interrupt request; and an interrupt handling module configured to receive the interrupt request and the corresponding decision data, and to provide a corresponding interrupt service in response to the interrupt request, wherein the decision maker is configured to designate one or more registers of the register save list as live save registers corresponding to the interrupt request based on a list of registers operated during the response.

[0007] In some embodiments, the interrupt handling module is adapted to perform, during the response to the interrupt request: cache information of each live save register designated by the decision data to a storage unit before the interrupt service is started; during the interrupt service, if an operation on one of the plurality of registers is required and information of the register is not cached by the storage unit, cache information stored in the register to the storage unit before the operation is performed; and restore the plurality of registers to a state before the interrupt service using the storage unit after the interrupt service is completed.

[0008] In some embodiments, the decision maker is configured to collect training data corresponding to the interrupt service, and to adjust the decision data corresponding to the interrupt service according to the training data, the training data comprising information of: a list of registers required to be restored at completion of the interrupt service, and / or a list of registers operated during the interrupt service, such that the adjusted decision data designates each register indicated by the training data as a live save register corresponding to the interrupt service.

[0009] In some embodiments, the decision maker comprises: a first storage unit configured to store the training data collected; a second storage unit configured to store the decision data corresponding to a current interrupt service; a logic unit configured to adjust the decision data according to the training data; and a transmission unit configured to obtain the corresponding decision data from the storage unit according to the interrupt request, and to provide the adjusted decision data provided by the second storage unit to the storage unit.

[0010] In some embodiments, the decision maker is further adapted to remove, from the register save list designated by the decision data, live save registers not operated during the interrupt service and / or live save registers not required to be restored at completion of the interrupt service according to the training data.

[0011] In some embodiments, corresponding to the current interrupt service, in the case that the decision maker does not collect the training data, the decision data is an initial state, in which the number of live save registers specified by the decision data is zero or less than the total number of the plurality of registers.

[0012] In some embodiments, during the interrupt service in response to the current interrupt request, if the interrupt handling module needs to handle another interrupt request with a higher priority than the current interrupt request, the decision maker provides the decision data corresponding to the other interrupt request to the interrupt handling module, so that the interrupt handling module executes the response process for the other interrupt request based on the decision data in the response process of the current interrupt request.

[0013] In some embodiments, the processing device further comprises a judgment module, in the case that the current interrupt service has ended and the plurality of registers have not been completely restored to the state before the interrupt service, if the judgment module determines that the next interrupt service needs to be continued to be handled, the interrupt handling module does not restore and cache the contents of each of the registers before providing the next interrupt service, so that the interrupt handling module uses the storage unit to restore the plurality of registers to the state before the start of the current interrupt service after the end of the next interrupt service.

[0014] In some embodiments, the interrupt handling module stores the information to be cached into a first storage area of the storage unit before the start of the interrupt service, and stores the information to be cached into a second storage area of the storage unit during the interrupt service, the first storage area and the second storage area are distributed non-overlappingly in the storage unit.

[0015] In some embodiments, the plurality of registers are respectively general registers configured as caller-save attributes.

[0016] In a second aspect, the embodiments of the present disclosure provide a processing system, comprising the processing device according to any of the embodiments of the present disclosure; and a memory coupled to the processing device, adapted to provide the storage unit and at least one interrupt service routine, the processing device implements the corresponding interrupt service by running one of the at least one interrupt service routine.

[0017] In some embodiments, the memory is further adapted to provide one or more decision data, each of the decision data is associated with a corresponding interrupt service and / or application program, so that the processing device obtains the corresponding decision data according to the interrupt request to be responded.

[0018] In some embodiments, the processing system is implemented in a system on chip.

[0019] In a third aspect, the embodiments of the present disclosure provide a processing method, comprising: providing decision data corresponding to an interrupt request, the decision data representing a register save list for specifying one or more registers of a plurality of registers as live save registers corresponding to the interrupt request; responding to the interrupt request to provide a corresponding interrupt service; and based on a list of registers operated in the responding, specifying one or more registers of the list as live save registers corresponding to the interrupt request.

[0020] In some embodiments, the step of responding to the interrupt request to provide a corresponding interrupt service comprises: before the interrupt service starts, caching information of each live save register specified by the decision data; during the interrupt service, if one of the plurality of registers needs to be operated and information of the register is not cached, caching information stored in the register before the operation is performed; and after the interrupt service is completed, restoring the plurality of registers to a state before the interrupt service using the cached information.

[0021] In some embodiments, the step of based on a list of registers operated in the responding, specifying one or more registers of the list as live save registers corresponding to the interrupt request comprises: collecting training data corresponding to the interrupt service; and adjusting the decision data corresponding to the interrupt service according to the training data, the training data including information of a list of registers that need to be restored when the interrupt service is completed, and / or a list of registers operated during the interrupt service, so that the adjusted decision data specifies each register indicated by the training data as a live save register corresponding to the interrupt service.

[0022] In some embodiments, the step of adjusting the decision data corresponding to the interrupt service according to the training data comprises: according to the training data, deleting from the register save list specified by the decision data, live save registers that are not operated during the interrupt service and / or live registers that do not need to be restored at the end of the interrupt service.

[0023] In some embodiments, the step of responding to the interrupt request to provide a corresponding interrupt service further comprises: corresponding to a current interrupt service, in the case that the training data is not collected, the decision data is in an initial state, in which the number of live save registers specified by the decision data is zero or less than the total number of the plurality of registers.

[0024] In some embodiments, the step of responding to the interrupt request to provide a corresponding interrupt service further comprises: during the interrupt service responding to the current interrupt request, if the interrupt processing module needs to process another interrupt request with a higher priority than the current interrupt request, providing the decision data corresponding to the another interrupt request so as to perform a response process for the another interrupt request based on the decision data in a nested manner in the response process of the current interrupt request.

[0025] In some embodiments, the step of responding to the interrupt request to provide a corresponding interrupt service further comprises: in the case that the current interrupt service has ended and the plurality of registers have not been completely restored to the state before the interrupt service, if it is needed to continue processing a next interrupt service, not restoring and caching the content of each of the registers before providing the next interrupt service so as to restore the plurality of registers to the state before the current interrupt service starts by using the information cached before the current interrupt service starts after the next interrupt service ends.

[0026] In a fourth aspect, the embodiments of the present disclosure further provide a computer readable medium, which stores computer instructions, and the computer instructions, when executed, implement the processing method in any of the embodiments of the present disclosure.

[0027] The embodiments of the present disclosure can cache the content of some registers specified according to the register save list represented by the decision data in the live protection stage, and can also dynamically cache other registers needed to be used by the interrupt service during the interrupt service, without unconditionally caching all general registers with the caller attribute in the live protection stage. Therefore, on the premise of ensuring the accuracy of the register storage information, the number of registers needing to be protected in the live protection stage is reduced, which is conducive to reducing the interrupt response time and improving the interrupt real-time performance, and also saves the storage space occupied by the interrupt.

[0028] In some optional embodiments, training data can also be collected in the actual interrupt processing process, and the decision data can be dynamically optimized and corrected based on the training data, so that the register save list represented by the decision data can be consistent with the register list actually involved in the interrupt service as much as possible, thereby avoiding live protection and restoration of unnecessary registers in the interrupt processing process as much as possible. Through the training mechanism, the real-time performance of the interrupt response is further optimized, which is also conducive to reducing the live restoration time and the time of the entire interrupt processing process.

[0029] In some embodiments, the register save list adapted to different interrupt services / applications can be set respectively, so that the matched register save list is provided according to different interrupt requests, and the register live protection is more flexible and accurate, so as to further improve the real-time performance of interrupt response.

[0030] In some embodiments, in the case of continuously processing multiple interrupt requests, the register live protection and / or recovery can not be performed between the execution processes of two adjacent interrupt service routines, but the register cache information (in the storage unit) of the previous interrupt service is directly inherited by the subsequent interrupt service, so that after the series of continuous interrupt services are completed, the cache information in the storage unit can be directly used to restore each register to the state before the first interrupt service starts, further shortening the interrupt response process and saving the time for live protection and live recovery in the case of continuously processing interrupt requests.

[0031] In the embodiment with a large number of general registers, the technical solution of the present disclosure can greatly reduce the interrupt response delay time caused by the caller-save attribute general registers, and significantly improve the real-time performance of interrupt response. BRIEF DESCRIPTION OF DRAWINGS

[0032] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 a schematic block diagram of a computer system in one embodiment of the present disclosure is shown;

[0034] Figure 2 a schematic block diagram of a processor in one embodiment of the present disclosure is shown;

[0035] Figure 3 a flowchart of an interrupt processing method in one embodiment of the present disclosure is shown;

[0036] Figure 4 an exemplary interrupt processing flow in one embodiment of the present disclosure is shown;

[0037] Figure 5 a schematic diagram of a processing device in one embodiment of the present disclosure is shown;

[0038] Figure 6 a schematic diagram of one or more stack structures in one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0039] The present application is described in detail below with reference to Examples. However, the present application is not limited to these Examples. In the following detailed description of the present application, some specific details are described in detail. The present application can be understood without these details, which are set forth to provide what is believed to be the most useful and readily understood description of the present application. In order to avoid obscuring the present application, well-known methods, procedures, and protocols are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0040] The following terms are used herein.

[0041] Computer system: an embedded system, a desktop computer, a server, or other system with information processing capability.

[0042] Memory: a physical structure in a computer system for storing information. According to different uses, memory can be divided into main memory (also referred to as internal memory, or simply memory / main memory) and auxiliary memory (also referred to as external memory, or simply auxiliary storage / external storage). Memory is used to store instruction information and / or data information represented by data signals, for example, to store data provided by a processor, and can also be used to exchange information between a processor and external storage. The information provided by external storage needs to be called into main memory before it can be accessed by a processor, so the memory referred to herein is generally the memory, and the storage device referred to herein is generally the external storage.

[0043] Interrupt handler: after determining that an interrupt request needs to be responded to, the processor executes the interrupt handler to call the interrupt service routine corresponding to the interrupt request, thereby processing the interrupt. Different interrupt requests can correspond to different interrupt service routines, and the processor can execute the corresponding service content according to the entry address of the interrupt service routine (which can also be referred to as an interrupt vector). It should be noted that the main program described herein is relative to the interrupt service routine, and the name is not used to limit the essential type of the main program, for example, the main program can be a program called by another program or an interrupt handler interrupted by another interrupt request.

[0044] Interrupt nesting: when the processor is processing an interrupt, if another interrupt source with a higher priority raises an interrupt request, it means that interrupt nesting occurs, at which time the processor can interrupt the interrupt handler being executed with a lower priority to respond to the interrupt request with a higher priority, and then return to the interrupted interrupt handler to continue execution.

[0045] Stack structure: refers to one or more contiguous memory regions used to store temporary data. For example, during the context saving phase, the values ​​of registers that need to be protected can be backed up in the stack structure so that these values ​​can be restored to their original registers during the subsequent context restoration phase, allowing the main program running before the interrupt to continue running correctly after the interrupt. In addition, the stack structure can also be used to store other data. Stack operations can be performed using the PUSH and POP instructions, for example.

[0046] System overview

[0047] Figure 1 A schematic block diagram of a computer system according to an embodiment of the present invention is shown. This computer system 10 is an example of a "centralized" system architecture. Computer system 10 can be built based on various processors currently available on the market and powered by Windows. TM Operating system versions, UNIX operating systems, Linux operating systems, and other operating system drivers. Furthermore, computer system 10 can be implemented in hardware and / or software such as PCs, desktops, laptops, servers, and mobile communication devices.

[0048] like Figure 1 As shown, the computer system 10 of this embodiment may include one or more processors 12 and a memory 11. The processors 12 and the memory 11 may be wholly or partially integrated in the same system-on-a-chip / processor chip, or they may be located in different chips / modules.

[0049] The memory 11 in the computer system 10 can be used as RAM. In some embodiments, the memory 11 can be one or more different memory devices and / or one or more different types of memory. For example, the memory 11 may include dynamic random access memory (DRAM), and may also include other types of random access memory.

[0050] The memory 11 can include one or more application modules, such as for running image processing programs, audio processing programs, screen wake-up programs, drawing programs, e-mail programs, and the like. The memory 11 can also include an operating system module for running an operating system required for the computer system 10, which supports and manages the running of various programs. The operating system module can include an interrupt handling unit 111 for storing instruction information of an interrupt handling program that can invoke an interrupt service routine stored in one or more interrupt routine units 112 according to information provided by an interrupt request, thereby providing a corresponding service content. The memory 11 can include a single operating system module, or optionally two or more operating system modules. In an embodiment not shown, the memory 11 can also optionally include a virtual machine manager module, a hypervisor module, and the like.

[0051] The memory 11 also has one or more stack structures 113. The stack structure 113 can be used to store information about a program (e.g., a field protection stage stores parameter values, addresses, and the like of a specified program for restoring a field). The stack structure is sometimes also referred to as a call stack structure, an execution stack structure, a runtime stack structure, a machine stack mechanism, or simply a stack, which can be a storage area accessed according to a last-in first-out rule, or a fixed storage area inside or outside the operating system module, for implementing interrupt nesting and / or parameter values and breakpoints of subprogram calls.

[0052] The processor 12 can include a pipeline structure 120, a memory management unit 130, a register bank 140, and the like.

[0053] The pipeline structure 120 includes, for example, a decoder, an instruction execution unit, and the like, and a program (e.g., a main program, an interrupt handling program, an interrupt service routine, and the like) to be executed on the processor 12 can include one or more instructions loaded from the memory 11 (e.g., from an operating system module and / or an application module) and executed by the pipeline structure 120.

[0054] During the execution of a program by the processor, relevant information can be recorded using the register bank 140. The registers in the register bank 140 can be distributed, for example, within the processor 12 and / or within a chip / system-on-a-chip in which the processor 12 is located.

[0055] The processor 12 needs to access the memory 11 to obtain instruction information / data information in the memory 11, and can also modify information in the memory 11, so the processor can also include a memory management unit 130 to manage the exchange of information between the processor 12 and the memory 11, such as for implementing translation between a virtual address and a physical address.

[0056] In order to alleviate the speed gap between the processor 12 and the memory 11 due to the slower access speed of the memory 11, the computer system 10 further comprises a cache memory 14 coupled with the bus 13, which is configured to cache some data in the memory 11 that can be repeatedly invoked, such as program data or message data. The cache memory 14 is implemented by a type of storage device such as static random access memory (SRAM). The cache memory 14 can be a multi-level structure, such as a three-level cache structure with a level one cache (L1 Cache), a level two cache (L2 Cache) and a level three cache (L3 Cache), or a cache structure with more than three levels or other types of cache structure. In some embodiments, a part of the cache memory 14 (e.g., the level one cache, or the level one cache and the level two cache) can be integrated inside the processor 12 or in the same system on chip as the processor 12.

[0057] In order to avoid confusion in the description, a relatively simple processor has been shown and described. However, the processor can also optionally include other well-known processor components. Possible examples of such components include, but are not limited to, a prefetch buffer, an address translation buffer, a branch prediction unit, a register renaming and / or allocation unit, an instruction dispatch unit, a bus interface unit, an address generation unit, a debug unit, a performance monitor unit, a power management unit, external pins, other components that can be included in a processor, and various combinations thereof. Such components can be coupled together in various different suitable combinations and / or configurations known in the art. The embodiments are not limited to any known such combinations or configurations. Moreover, the embodiments can be included in a processor having multiple cores, at least one of which is configured to perform the embodiments of interrupt processing described herein.

[0058] In addition, the computer system 10 can further comprise a storage device 18, a display device 15, an audio device 16, a mouse / keyboard 17 and other input / output devices. The storage device 18 is, for example, a hard disk, an optical disk, a flash memory and other devices for information access coupled with the bus 13 through a corresponding interface. The display device 15 is coupled with the bus 13 through a corresponding display card, for example, to display according to the display signal provided by the bus 13.

[0059] Computer system 10 also typically includes a communication device 19 so that it can communicate with a network or other devices. Communication device 19 can include, for example, one or more communication modules, such as a wireless communication module adapted for a particular wireless communication protocol, as an example. For instance, communication device 19 can include a WLAN module for implementing Wi-Fi™ communication in accordance with the 802.11 standard promulgated by the Institute of Electrical and Electronics Engineers (IEEE); communication device 19 can also include a WW AN module for implementing wireless wide area communications in accordance with a cellular or other wireless wide area protocol; communication device 19 can also include a Bluetooth module or other communication module employing other protocols, or other custom types of communication modules; and communication device 19 can also be a port for serial transmission of data.

[0060] Of course, different computer systems can vary in structure according to the motherboard, operating system, and instruction set architecture. For example, many computer systems now have an input / output control hub connected between bus 13 and various input / output devices, which can be integrated within processor 12 or independent of processor 12.

[0061] Processor

[0062] Figure 2 is a schematic block diagram of processor 12 in embodiments of the present invention.

[0063] In some embodiments, each processor 12 can include one or more processor cores 12A for processing instructions, which processing and execution of instructions can be controlled by a user (e.g., through an application) and / or a system platform. In some embodiments, each processor core 12A can be configured to process a particular instruction set. In some embodiments, an instruction set can support a Complex Instruction Set Computing (CISC), a Reduced Instruction Set Computing (RISC), or a Very Long Instruction Word (VLIW) computing architectures. Different processor cores 12A can each process a different or same instruction set. In some embodiments, processor core 12A can also include other processing modules, such as a Digital Signal Processor (DSP) core, etc. As an example, Figure 2 Processors cores 1 through m, m being a natural number non-zero, are shown in FIG. 1.

[0064] In some embodiments, Figure 1The cache memory 14 shown can be wholly or partially integrated into the processor 12. Depending on the architecture, the cache memory 14 can be a single or multiple levels of internal high-speed cache memory located within and / or outside each processor core 120A (e.g., ...). Figure 2 The three-level high-speed cache memory L1 to L3 are shown. Figure 2 The cache, uniformly identified as 14), may also include an instruction-oriented cache and a data-oriented cache. In some embodiments, the various components in the processor 12 may share at least a portion of the cache memory, such as... Figure 2 As shown, processor cores 1 to m share a common level 3 cache memory L3. Processor 12 may also include an external cache (not shown), and other cache structures may also serve as external caches for processor 12.

[0065] In some embodiments, such as Figure 2 As shown, processor 12 may include register file 140, which may include multiple registers for storing different types of data and / or instructions. These registers may be of different types. For example, register file 140 may include integer registers, floating-point registers, status registers, instruction registers, and pointer registers. The registers in register file 140 may be implemented using general-purpose registers, or a specific design may be adopted according to the actual needs of processor 12. Examples will be provided later.

[0066] The pipeline structure 120 of processor 12 is used to execute instruction sequences (i.e., programs). The process of processor 12 executing each instruction includes: fetching the instruction from memory 11 where the instructions are stored, decoding the fetched instruction, executing the decoded instruction, and saving the instruction execution result, etc., and so on, until all instructions in the instruction sequence have been executed or an instruction that needs to stop or terminate the execution of the current instruction sequence is encountered (e.g., an interrupt instruction, a halt instruction, etc.).

[0067] To achieve the above process, the pipeline structure 120 may include an instruction fetch unit 124, an instruction decode unit 125, an instruction issue unit (not shown), an instruction execution unit 121, and an instruction de-initialization unit (not shown), etc.

[0068] The instruction fetch unit 124 serves as the boot engine of the processor 12, used to move instructions from memory 11 to the instruction register (which may be...). Register set and stack structure The instruction is stored in one of the registers in register group 140 shown, and the next fetch address is received or calculated according to the fetch algorithm, which may include, for example, incrementing or decrementing the address based on the instruction length.

[0069] After fetching the instruction, the processor 12 enters the instruction decode stage, and the instruction decode unit 125 decodes the fetched instruction according to a predetermined instruction format to obtain the operand acquisition information required by the fetched instruction, so as to prepare for the operation of the instruction execution unit 121. The operand acquisition information is, for example, a pointer to an immediate number, a register, or other software / hardware capable of providing a source operand.

[0070] The instruction issue unit is usually present in a high-performance processor 12 between the instruction decode unit 125 and the instruction execution unit, and is used for scheduling and control of instructions to efficiently allocate individual instructions to different instruction execution units 121, so that parallel operation of multiple instructions is possible. After the instruction is fetched, decoded, and scheduled to the corresponding instruction execution unit 121, the corresponding instruction execution unit 121 begins to execute the instruction, i.e., performs the operation indicated by the instruction and implements the corresponding function.

[0071] The instruction retirement unit (or instruction write-back unit) is mainly responsible for writing the execution result generated by the instruction execution unit 121 back to the corresponding storage location (e.g., a register in the processor 12), so that subsequent instructions can quickly obtain the corresponding execution result from the storage location.

[0072] For different categories of instructions, different instruction execution units 121 can be correspondingly provided in the processor 12. The instruction execution unit 121 can be an arithmetic unit (e.g., including an arithmetic logic unit, a vector operation unit, etc., for performing operations on operands and outputting the operation result), a memory execution unit (e.g., for accessing memory according to instructions to read data in the memory or write specified data to the memory, etc.), a coprocessor, etc. In the processor 12, each instruction execution unit 121 can run in parallel and output the corresponding execution result.

[0073] When executing a certain type of instruction (e.g., a memory access instruction), the instruction execution unit 121 needs to access the memory 11 to obtain the information stored in the memory 11 or provide the data to be written into the memory 11.

[0074] It should be noted that the instruction execution unit 121 for executing the memory access instruction can also be referred to as a memory execution unit, which is, for example, a load store unit (LSU) and / or other units for memory access.

[0075] General purpose registers with caller-save attributes

[0076] The register file of a processor can include a plurality of general purpose registers and special purpose registers, each register in the register file having an identification code (e.g., part or all of the binary code of the register address / identity tag) that is distinct from other registers.

[0077] Special purpose registers are registers that are set up for performing some special operations. For example, to support interrupt handling, a RISC-V based processor core defines a set of control / status registers and interrupt registers to support interrupt handling, listed as follows:

[0078] Processor status registers are used to store values related to the state of the processor, such as various status information (e.g., whether there is a carry, whether there is an overflow, whether the result number is positive or negative, whether the result number is even or odd, etc.) of the current instruction execution result, various control information (e.g., whether to allow interrupts, etc.), or other information.

[0079] Instruction address registers are used to temporarily store the address of the instruction that is ready to be executed or is not yet completed. It is also commonly referred to as a program counter (PC), instruction address counter, etc. Before the program starts to execute, the address of the first instruction of the program needs to be sent to the PC, and during the program execution, the address in the PC points to the address of the next instruction to be executed.

[0080] In the register file, there can also be some recovery registers for interrupt / exception handling process. For example, the processor can store the state values saved in the processor status registers and / or the instruction address stored in the PC into the corresponding recovery registers before running the interrupt service routine in response to the interrupt request, so that the values of the recovery registers can be restored to the processor status registers and the PC before returning to the main program. In some other embodiments, the processor can also write the values of the special purpose registers such as the processor status registers and the PC into the corresponding stack structure in the memory during the live save stage.

[0081] In some embodiments, the special purpose registers can also include power control registers PCON and other registers, and the type and number of special purpose registers are not limited in the present disclosure.

[0082] In addition to the special purpose registers, the register file also includes general purpose registers (GPRs) for transferring and temporarily storing data (e.g., difference, product, divisor, quotient, port address, target address, etc.), participating in arithmetic logic operations and holding the operation results, such as including accumulation registers, base registers, count registers, data registers, etc. In some embodiments, the general purpose registers can be divided into fixed point general purpose registers and floating point general purpose registers to protect the register operands and operation results of different numerical types in the instructions.

[0083] Interrupt handling flow

[0084] Considering the cost, volume and other factors, the number of general registers in a processor is limited, in order to facilitate management (for example, to avoid information coverage) and improve the utilization of registers, part of the general registers in the processor is configured as "caller save attribute", and another part of the general registers is configured as "callee save attribute".

[0085] For example, if function Q needs to be called during the running of function P, and the intermediate values and / or result values during the running of function P are saved in the general registers configured as callee save attribute, the called function Q (for example, interrupt service routine) can not affect these values, or temporarily store these values in the stack structure, so as to ensure that these values are the same before and after the running of function Q, so that the processor can continue to run function P based on these values after the end of function Q.

[0086] If one or some intermediate values and / or result values of function P are saved in the general registers with caller save attribute, in the prior technical solution, the values of the registers with caller save attribute related to function P need to be unconditionally stored in the stack structure in the live-in protection stage before the execution of function Q starts, and then function Q can be called.

[0087] As a specific example, for a certain general register (or a certain special register supporting backup in the stack structure) that needs to be backed up, in the live-in protection stage, the pipeline structure 120 first writes the value of the general register into the corresponding stack structure based on the memory load, storage instructions and other instructions; in the live-in recovery stage, the pipeline structure will restore the backup value in the stack structure to the corresponding register based on the corresponding instructions.

[0088] In some processors, the number of general registers is large. For example, in some RISC-based processors, the operands of the processor operations can all or partially come from general registers, rather than being obtained by directly accessing memory, so more general registers are provided in RISC-based processors than in traditional architecture processors, especially in the case of floating-point general registers, the number of general registers is large. In the conventional scheme, all general registers with caller-save attributes are saved and restored at process switching, and the process of saving and restoring the registers requires a large number of memory loading, storing and other instructions, resulting in an increase in the delay of process switching. Generally, the called process usually does not use some or some of the registers with caller-save attributes, so the process of unconditionally storing the values of these registers with caller-save attributes in the stack structure and then restoring them from the stack structure to the corresponding registers requires a large amount of storage space resources and consumes too much time, affecting the interrupt real-time performance, which is not conducive to improving the interrupt response speed, and frequent handling of the saving and restoring of the registers also increases the overall power consumption of the processor.

[0089] The embodiments of the present disclosure aim to cache the contents of some specified registers in the register saving list during the context protection phase, and also cache the registers that need to be protected but are not protected in the interrupt service phase, without unconditionally caching all general registers with caller attributes in the context protection phase, thereby reducing the number of registers that need to be protected in the context protection phase, which is conducive to reducing the interrupt response time and improving the interrupt real-time performance, and also saves the storage space occupied by the interrupt.

[0090] Figure 3

[0091] The processor implements interrupt processing processes such as interrupt response by running an interrupt handling program. In the interrupt response process, the interrupt handling program first saves the context of the currently executed main program, then obtains the entry address of the corresponding interrupt service routine according to the information provided by the interrupt request, and calls the corresponding interrupt service routine based on the entry address, so as to implement the interrupt service required by the interrupt source; after the interrupt service routine ends, the interrupt handling program restores the context, so that the processor can continue to run the main program from the breakpoint based on the restored context, and implement interrupt return.

[0092] If another interrupt request R0 initiated by an interrupt source with higher priority is received or queried by the processor in the process of responding to the interrupt request R1 initiated by a certain interrupt source, it means that interrupt nesting occurs, and the processor needs to suspend the response to the interrupt request R1 and start responding to the interrupt request R0; after the interrupt service required by the interrupt request R0 ends, the processor returns to the previous interrupt processing program to continue the interrupt processing process for the interrupt request R1.

[0093] The interrupt processing method of the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0094] Figure 4 A flowchart of the interrupt processing method of the embodiments of the present disclosure is shown. For ease of illustration, Figure 4 An exemplary interrupt processing flow of the embodiments of the present disclosure is shown.

[0095] In step S410, first, the interrupt request currently required to be responded to is determined. The interrupt request can come from a hardware interrupt source or a software interrupt source, and can be an interrupt request passively received by the processor or an interrupt request actively queried by the processor.

[0096] The processor has the opportunity to receive multiple interrupt requests at the same time, so in step S410, the interrupt request currently required to be responded to needs to be determined from multiple interrupt requests, for example, the interrupt request initiated by the interrupt source with the highest priority among the interrupt sources can be responded to first. The interrupt request itself can contain the priority information of the interrupt source corresponding thereto.

[0097] On the premise of allowing the interrupt to be responded to, the current process (for example, corresponding to the main program or the interrupt processing program nested by the interrupt) can be suspended, and the interrupt request determined in step S410 can be responded to. In some examples, the processor can return an interrupt response signal to the interrupt source corresponding to the interrupt request after confirming the interrupt request currently required to be processed.

[0098] In step S420, the context information of the current process is saved according to the register save list. The context information can include the values of each register specified by the register save list at the breakpoint. The processor temporarily stores the context information in the corresponding recovery register and / or stack structure in the context protection stage, for example, by executing a PUSH instruction and / or other instructions.

[0099] Step S240 can be implemented by a plurality of sub-steps. For example, in some examples, the value of the instruction address register and the value in the processor status register can be temporarily stored in a stack structure for recording the processor status; in addition, the values of the registers specified by the register save list (referring to registers other than the instruction address register and the processor status register) can be temporarily stored in the corresponding stack structure. The present disclosure does not limit the order of these sub-steps.

[0100] In some embodiments, the registers specified by the register save list can include the instruction address register, the processor status register, and one or more general-purpose registers with caller-save attribute, and can also include other special-purpose registers. In other embodiments, the register save list can only be used to specify one or more general-purpose registers with caller-save attribute that need to be backed up in the live protection phase, and the processor can automatically cache the values of the instruction address register, the processor status register, and other special-purpose registers into the corresponding recovery registers and / or stack structure in the live protection phase.

[0101] In some embodiments, different registers in the processor correspond to different identification codes, and the register save list is, for example, a set of identification codes or a set of encoded identification codes of the registers that need to be backed up in the live protection phase.

[0102] In the initial state, the register save list is not updated, and the initial value of the register save list can specify a small number of general-purpose registers or even no general-purpose registers. In subsequent steps, the register save list can be continuously optimized by the training data collected in the interrupt processing process.

[0103] In some embodiments, the register save list can be set separately for different interrupt services / applications, so as to provide a matching register save list according to different interrupt requests, and more flexibly and accurately implement the live protection of the registers, so as to optimize the interrupt response time of different interrupt sources and further improve the real-time performance of the interrupt response.

[0104] In step S430, the entry address of the interrupt service routine is obtained according to the interrupt request, and the corresponding interrupt service routine is located based on the entry address, so as to start executing the instructions corresponding to the interrupt service required by the interrupt request.

[0105] During this period, before executing each instruction of the interrupt service routine, if it is detected that the instruction needs to use a register (for example, a general-purpose register not specified by the register save list) that has not been backed up, the processor automatically temporarily stores the content of the register in the stack structure, and then executes the corresponding instruction based on the register.

[0106] In some embodiments, the interrupt service stage (step S430) and the context protection stage (step S420) can operate on different stack structures. For example, in the context protection stage, the processor can save the values of the specified registers to a first stack structure; while in the interrupt service stage, the processor can save the values of the detected registers that need to be cached to a second stack structure, which can be different from the first stack structure, so as to prevent the values cached in the context protection stage from being overwritten by the values cached in the interrupt service stage. In other embodiments, the interrupt service stage and the context protection stage can operate on the same stack structure, and only need to properly arrange the stack pointer to prevent information from being overwritten.

[0107] In some embodiments, the identification codes of the registers that are backed up by the hardware in the interrupt service stage are recorded as the first training information, which can be used to optimize the register save list. In other embodiments, the identification codes of the registers that are backed up by the hardware in the interrupt service stage are recorded in association with the interrupt source corresponding to the interrupt request as the first training information, so that the first training information can correspond to the relevant interrupt source, and the register save list corresponding to different interrupt sources can be more accurately optimized.

[0108] After the interrupt service corresponding to each interrupt request is completed, step S440 is performed to determine whether another interrupt request needs to be processed. If no other interrupt request needs to be processed, step S450, i.e., the interrupt return step, is performed; if another interrupt request needs to be processed, step S430 is returned to be performed.

[0109] Step S450 is used to prepare for the resumption of the interrupted process before the interrupt processing. In step S450, the information previously saved in the stack structure and / or the restoration registers needs to be stored back into the corresponding registers, so as to restore the register context to the state corresponding to the breakpoint, and enable the processor to resume the interrupted process using the values of the registers.

[0110] The interrupt return step can be implemented by the processor executing one or more POP instructions and / or an interrupt return instruction IRET, for example.

[0111] The interrupt return step can include a plurality of sub-steps, for example. In some examples, the information in the restoration registers used to record the instruction addresses can be restored and stored into the instruction address registers, and the information in the restoration registers used to record the register states can be restored and stored into the processor state registers; in addition, according to the saved data in the stack structure, the values of the registers updated in the interrupt processing stage can be restored to the values before the interrupt processing. The present disclosure does not limit the order of these sub-steps.

[0112] In some examples, it is also necessary to record the list of registers that are restored / need to be restored during the interrupt return step (referred to as the register restoration list). This list can serve as secondary training information to optimize the register save list.

[0113] In some embodiments, the interrupt handling process may further include optimization of the register save list. The processor can optimize the register save list based on training data (including first training information and / or second training information), thereby optimizing the interrupt response time by continuously collecting training data generated during the interrupt handling process.

[0114] As an example, such as Figure 4 As shown, after the interrupt service corresponding to the first interrupt request is completed, if it is necessary to continue processing the second interrupt request, the process returns to step S430 to implement the interrupt service required by the second interrupt request. Among the multiple interrupt requests received by the processor simultaneously, the priority of the second interrupt request is, for example, second only to the priority of the first interrupt request.

[0115] Before processing the second interrupt request, there is no need to restore the register context saved during the first interrupt request. Instead, the context information saved during the first interrupt handling can be directly used as the context information for the second interrupt request. Furthermore, this context information can be supplemented during the second interrupt request processing, thus saving time for context restoration and re-saving, further improving interrupt response speed. As an example, a fixed context information register is set up corresponding to the current interrupt handling process, so the contents of the context information register (the context information of the first interrupt request) can be directly used as the context information for the second interrupt request without data transfer.

[0116] During the on-site protection phase, if a terminal request is received / queried and has a higher priority than the currently processed interrupt request, the higher priority interrupt request will be responded to first after the on-site protection phase is completed.

[0117] During a service interruption, if a received / queried interruption request has a higher priority than the currently being processed interruption request, for example... Figure 6The priority of the third interrupt request is higher than the priority of the second interrupt request, which means that interrupt nesting occurs, and the current process (the interrupt service stage or the field protection stage corresponding to the second interrupt request) needs to be suspended, and steps S420 and S430 are re-executed to execute the interrupt service corresponding to the third interrupt request after the field protection (for example, based on the register saving list corresponding to the third interrupt request) of the nested interrupt handler. In the case of interrupt nesting, the field information includes, for example, the register record information (for example, the result number and / or the operand for the second interrupt service) generated by the interrupt handler of the second interrupt request and the stack position information (for example, the next position of the stack structure to be cached at the time of interrupt nesting, used to restore the breakpoint information at the time of the second interrupt service being nested), which can be temporarily stored in the corresponding stack structure in step S420.

[0118] As an example, as shown in Processing device To prevent useful information in the stack structure from being overwritten, multiple independent storage spaces can be provided in the stack structure for storing the cache information of the field protection stage, the cache information of the interrupt service stage, and the cache information of the interrupt nesting stage, respectively.

[0119] Figure 5

[0120] Figure 5 A schematic diagram of a processing device according to an embodiment of the present disclosure is shown. As shown in Figure 5 The processing device 200 can be implemented by a processor or a computer system described in the present disclosure, or can be designed as a special device independent of the above architecture.

[0121] As an example, the processing device can include: a plurality of registers for storing information; a decision maker for providing decision data corresponding to an interrupt request, the decision data indicating a register saving list for designating one or more registers in the plurality of registers as field saving registers corresponding to the interrupt request; and an interrupt handling module (for example, including an interrupt response module, a register saving module, a register restoring module, etc.) for receiving the interrupt request and the corresponding decision data, and providing a corresponding interrupt service in response to the interrupt request. Wherein, the interrupt handling module is further adapted to, during the response to the interrupt request: before the start of the interrupt service, cache the information of each field saving register designated by the decision data to a storage unit; during the interrupt service, if one of the plurality of registers needs to be operated and the information of the register is not cached by the storage unit, cache the information stored in the register to the storage unit before performing the operation; and after the completion of the interrupt service, restore the plurality of registers to the state before the interrupt service by using the storage unit.

[0122] The following will be described with reference to Figure 5 Further description will be made. As an example, the processing device 200 for implementing the interrupt processing method of the embodiments of the present disclosure can include the following several parts.

[0123] The interrupt response module 210 is configured to respond to the interrupt request that needs to be processed. When the interrupt response module 210 receives / queries multiple interrupt requests at the same time, the interrupt request with the highest priority can be determined as the interrupt request that needs to be processed currently according to the priority order, and a response signal can be sent to the corresponding interrupt source. During the interrupt processing process, the interrupt response module 210 can also serve as a judgment module for judging whether another interrupt request needs to be responded to after the current interrupt service, and can also be used for judging whether another interrupt request with a higher priority than the current interrupt request needs to trigger interrupt nesting.

[0124] The register group 220 is configured to provide a plurality of registers 1 to N for supporting the program running, wherein, Figure 6 The register i shown is used to represent one or more registers involved in the interrupt service, one or more registers specified by the register save list, and / or one or more registers that need to be restored in the field recovery stage. In some embodiments, the register i can be one or more general-purpose registers provided in the above-mentioned processor with the caller-save attribute.

[0125] The register saving module 240 is configured to save the context information that needs to be saved into the corresponding recovery register and / or stack structure. The context information can include breakpoint information (for example, the address of the next instruction that needs to be executed by the main program) and processor state information (for example, stored in the CPU state register) of the main program, and other information that needs to be saved in the field, and can also include part or all of the information stored in the general-purpose register. The register saving module can be a software module or a software and hardware combined module implemented by the processor based on a series of PUSH instructions.

[0126] The storage unit 230 is configured to provide one or more interrupt service routines 232, and one or more stack structures 231 for caching register information. In some embodiments, referring to ​ The schematic diagram of one or more stack structures in the embodiments of the present disclosure is shown. The stack structure 231 can be divided into a plurality of non-overlapping storage spaces (which can be continuously, alternately or intermittently distributed in the storage unit 230) for caching the register cache information provided by the register saving module 240 in the field protection stage, the register cache information provided by the register saving module 240 in the interrupt service stage, the register cache information provided by the register saving module 240 in the interrupt nesting process, etc., so as to prevent the cache information in different stages or the useful cache information corresponding to different sources from being mistakenly overwritten.

[0127] The decision maker 270 is configured to save and provide a register save list, which can be characterized by decision data provided by the decision maker 270. The decision maker 270 can be stored in a designated storage area of the memory or in a register that is not affected by the process.

[0128] As an example, the decision maker can include a first register unit, a second register unit, a logic unit, a transmission unit, and the like. The first register unit is configured to store the training data obtained; the second register unit is configured to store the decision data corresponding to the current interrupt service; the logic unit is configured to adjust the decision data stored in the second register unit according to the training data; and the transmission unit is configured to obtain the corresponding decision data from the storage unit according to the interrupt request, and provide the adjusted decision data provided by the second register unit to the storage unit.

[0129] In the embodiments of the present disclosure, the register save module 240 receives the decision data output by the decision maker, so as to cache the information stored in each live save register (i.e., the register specified by the decision data) to the storage unit 230 during the live protection phase corresponding to the current interrupt service; during the interrupt service phase corresponding to the current interrupt service: if an operation needs to be performed on a certain register and the information stored in the register has not been cached by the storage unit, the register save module 240 caches the information stored in the register to the storage unit before performing the operation.

[0130] In the initial state, the decision maker 270 defaults to set the decision data to an initial value, so as to preliminarily select a small number of register lists to be saved in the case that the decision maker is not trained, so that the register save module can determine a small number of live save registers to be backed up according to the output value of the decision maker, instead of unconditionally performing live save on all general-purpose registers with caller-save attributes. In some other examples, the initial value of the decision maker 270 can not specify any general-purpose register or only specify one / two general-purpose registers with a higher usage frequency.

[0131] In some examples, the decision data of the decision maker 270 corresponds to the number / identity tag of each special-purpose register and / or general-purpose register that needs to be saved during the live protection phase. In some other examples, the decision data provided by the decision maker can only correspond to the number / identity tag of the general-purpose register with the caller-save attribute that needs to be saved, and the register save module defaults to perform live protection on various special-purpose registers during the live protection phase.

[0132] In some examples, the decision maker 270 can provide a corresponding register save list for different interrupt service routines, or can provide a register save list required by an interrupt process for different application programs respectively.

[0133] In some optional embodiments, the decision maker 270 collects training data during the live recovery phase and / or the service interrupt phase, and the decision maker 270 can adjust the corresponding decision data according to the collected training data. The training data can include information such as a list of registers that need to be recovered in the live recovery phase, and / or a list of registers that are operated in the service interrupt phase, so that the adjusted decision data specifies the registers that need to be recovered in the live recovery phase and / or the registers that are operated in the service interrupt phase as live save registers.

[0134] In some embodiments, the decision maker 270 can also delete live save registers that are not operated in the service interrupt phase from the register save list according to the collected training data.

[0135] In some embodiments, multiple decision data are provided in the decision maker 270, and the decision maker 270 can select decision data matching the current interrupt request from the multiple decision data according to the interrupt request corresponding to the current interrupt service, and output the decision data to the register save module 240, so that the register save module 240 implements live protection for the current interrupt service based on the decision data. Further, in some embodiments, the decision maker 270 can adjust the decision data corresponding to the current interrupt service based on training data generated by the current interrupt service, and the decision maker 270 can also set different initial values for the corresponding decision data for different interrupt services, so that the decision data can better match the corresponding interrupt service. In these cases, in the decision maker 270, the interrupt service and the corresponding decision data can be associated in various ways.

[0136] The interrupt service module 250 is configured to implement the interrupt service corresponding to the interrupt request. The interrupt service routines 232 corresponding to different interrupt sources can be pre-stored in the memory or other storage space, and when the interrupt response module determines the interrupt request that needs to be responded to, the interrupt service module can determine the entry address of the interrupt service routine corresponding to the interrupt request, and then execute the corresponding interrupt service routine based on the entry address to implement the corresponding interrupt service.

[0137] The register recovery module 260 is configured to, after the interrupt service is completed, store the information previously saved in the stack structure back into the corresponding registers, so as to recover the live registers to the state corresponding to the breakpoint. The register recovery module can write the cached information in the stack structure 231 back to the original registers in the order in which the information is stored in the live protection phase, that is, recover the original values of the registers at the breakpoint of the main program. The live recovery process can be implemented by the processor by executing one or more POP instructions (for outputting information in the stack structure to a specified location in a first-in, first-out order), for example.

[0138] During the interrupt service in response to the current interrupt request, if the interrupt handling module needs to handle another interrupt request with a higher priority than the current interrupt request, the decision maker provides the register saving module with decision data corresponding to the other interrupt request, so that the register saving module can perform a nested response process for the other interrupt request based on the decision data during the response process of the current interrupt request. If interrupt nesting occurs, the register saving module 240 can cache the information stored in each register and / or the information of the registers modified by the current interrupt service to the storage unit 230 before the interrupt service corresponding to the interrupt nesting, and the register restoring module 260 can restore the corresponding registers according to the cached information in the storage unit after the interrupt service required by the interrupt nesting.

[0139] Before the context recovery phase corresponding to the current interrupt service, if the judging module (the interrupt response module) determines that the next interrupt service needs to be processed after the current interrupt service ends, the judging module disables the register restoring module 260 and the register saving module 240 after the current interrupt service is completed and before the next interrupt service starts, so that the information cached in the storage unit and / or the decision data provided by the decision maker 270 for the current interrupt service can be used for the next interrupt service. For example, in the case where the current interrupt service has ended and each register in the register group has not been completely restored to the state before the current interrupt service, if the judging module determines that the next interrupt service needs to be processed, the processing device does not restore and cache the contents of each register before providing the next interrupt service, so that each register can be restored to the state before the current interrupt service starts by using the storage unit after the next interrupt service ends.

[0140] In some embodiments, the processing device is provided with a return module (not shown) for switching the process to the main program, so as to continue to execute the main program interrupted before based on the restored context from the breakpoint. The return module is implemented by, for example, using the processor to execute an interrupt return instruction IRET, by executing the instruction, the values saved in the stack structure can be popped to the corresponding registers, not only the instruction address register can be restored to point to the instruction address at the breakpoint (for example, the address corresponding to the next instruction to be executed by the main program), but also the contents of the processor state register can be restored to the value before the interrupt handling, so that the processor starts to continue to execute the main program based on the instruction address. In some embodiments, the register restoring module can be part of the return module or coupled with the return module.

[0141] The embodiments of the present disclosure can cache the content of some registers designated according to the register save list represented by the decision data in the live protection stage, and can also dynamically cache other registers needed to be used by the interrupt service during the interrupt service, without unconditionally caching all general registers with the caller attribute in the live protection stage. Therefore, the number of registers needing to be protected in the live protection stage is reduced under the premise of ensuring the accuracy of the register storage information, which is conducive to reducing the interrupt response time and improving the interrupt real-time performance, and also saves the storage space occupied by the interrupt.

[0142] In some optional embodiments, training data can also be collected in the actual interrupt processing process, and the decision data can be dynamically optimized and corrected based on the training data, so that the register save list represented by the decision data can be consistent with the register list actually involved in the interrupt service as much as possible, thereby avoiding live protection and recovery of unnecessary registers in the interrupt processing process as much as possible. Through the training mechanism, the real-time performance of the interrupt response is further optimized, which is also conducive to reducing the live recovery time and the time of the entire interrupt processing process.

[0143] In some embodiments, the register save list can be set for different interrupt services / application programs respectively, so as to provide a matching register save list according to different interrupt requests, and to more flexibly and accurately implement live protection of registers, thereby further improving the real-time performance of the interrupt response.

[0144] In some embodiments, in the case of needing to continuously process multiple interrupt requests, live protection and / or recovery of registers can no longer be performed between the execution processes of adjacent two interrupt service routines, but the register cache information (located in the storage unit) of the preceding interrupt service can be directly inherited by the subsequent interrupt service, so that after the series of continuous interrupt services are completed, the cache information in the storage unit can be directly used to restore each register to the state before the first interrupt service starts, thereby further shortening the interrupt response process and saving the time for live protection and live recovery in the case of continuously processing interrupt requests.

[0145] In the embodiments with a large number of general registers, the technical solution of the present disclosure can greatly reduce the interrupt response delay time caused by the general registers with the caller save attribute, and significantly improve the real-time performance of the interrupt response.

[0146] The present application also discloses a computer-readable storage medium including computer-executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the method of each embodiment described herein.

[0147] In addition, the present application also discloses a system comprising the apparatus for implementing the method of each embodiment described herein.

[0148] The present application also discloses a processing apparatus comprising the processor, the processor core or the system on chip integrated with the processor or the processor core.

[0149] It should be noted that although the present disclosure is described by taking the interrupt processing process as an example, the technical solutions provided by the present disclosure are also applicable to the abnormal processing process and the switching / calling process of the program.

[0150] It should be understood that the above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, there are many variations of the embodiments of the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0151] It should be understood that each embodiment in the present specification is described in a progressive manner, and the same or similar parts of each embodiment can be referred to each other, and each embodiment focuses on the difference from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the device and system embodiments, the description is relatively simple, and the relevant parts can refer to the part of the description of other embodiments.

[0152] It should be understood that the above describes specific embodiments of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multi-task processing and parallel processing are possible or can be advantageous.

[0153] It should be understood that the elements described herein in singular form or only shown in one in the drawings do not represent the number of the elements limited to one. In addition, the modules or elements described or shown herein as separate can be combined into a single module or element, and the modules or elements described or shown herein as single can be split into multiple modules or elements.

[0154] It should also be understood that the terms and expressions used herein are only used for description, and one or more embodiments of the present specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean the exclusion of any equivalent features described (or part thereof). It should be recognized that various modifications can exist and should be included in the scope of the claims. Other modifications, changes and replacements can also exist. Accordingly, the claims should be considered to cover all these equivalents.

Claims

1. A processing device for interrupt processing, characterized by: The application comprises: a plurality of registers for storing information; a decision maker for providing decision data corresponding to an interrupt request, the decision data representing a register save list for designating one or more registers of the plurality of registers as live save registers corresponding to the interrupt request, the register save list being respectively set for different interrupt services; an interrupt handling module for receiving the interrupt request and the corresponding decision data, and providing a corresponding interrupt service in response to the interrupt request, wherein the decision maker designates one or more registers of the plurality of registers designated by the register save list as live save registers corresponding to the interrupt request based on a list of registers operated in the response process; the interrupt handling module is adapted to perform, in the response process to the interrupt request: during the interrupt service, if an operation is required on one of the plurality of registers and the information stored in the register is not cached by a storage unit, caching the information stored in the register to the storage unit before performing the operation, and further comprising, in the case of requiring to continuously handle a plurality of interrupt requests, between the execution processes of two adjacent interrupt service routines, the interrupt service after directly inheriting the register cache information of the interrupt service before.

2. The processing device of claim 1, wherein, the interrupt handling module is further adapted to perform, in the response process to the interrupt request: before the interrupt service starts, caching the information of each live save register designated by the decision data to a storage unit; after the interrupt service is completed, restoring the plurality of registers to the state before the interrupt service by using the storage unit.

3. The processing device of claim 2, wherein, the decision maker collects training data corresponding to the interrupt service, and adjusts the decision data corresponding to the interrupt service according to the training data, the training data includes information of a list of registers required to be restored at the completion of the interrupt service, and / or a list of registers operated during the interrupt service, so that the adjusted decision data designates each register indicated by the training data as a live save register corresponding to the interrupt service.

4. The processing device of claim 3, wherein, the decision maker comprises: a first storage unit for storing the collected training data; a second storage unit for storing the decision data corresponding to the current interrupt service; a logic unit for adjusting the decision data according to the training data; and a transmission unit for obtaining the corresponding decision data from the storage unit according to the interrupt request, and providing the adjusted decision data provided by the second storage unit to the storage unit.

5. The processing device of claim 3, wherein, the decision maker is further adapted to delete, according to the training data, live save registers not operated during the interrupt service and / or live registers not required to be restored at the end of the interrupt service from the register save list designated by the decision data.

6. The processing device of claim 3, wherein, corresponding to the current interrupt service, in the case that the decision maker does not collect the training data, the decision data is in an initial state, in the initial state, the number of live save registers designated by the decision data is zero, or less than the total number of the plurality of registers.

7. The processing device of claim 2, wherein, In response to the current interrupt request, if the interrupt processing module needs to process another interrupt request with a higher priority than the current interrupt request, the decision maker provides the interrupt processing module with the decision data corresponding to the other interrupt request, so that the interrupt processing module executes the response process for the other interrupt request based on the decision data in the response process of the current interrupt request.

8. The processing device of claim 2, wherein, If the judgment module determines that the next interrupt service needs to be processed after the current interrupt service has ended and the plurality of registers have not been completely restored to the state before the interrupt service, the interrupt processing module does not restore and cache the contents of the registers before providing the next interrupt service, so that the interrupt processing module uses the storage unit to restore the plurality of registers to the state before the current interrupt service starts after the next interrupt service ends.

9. The processing device of claim 2, wherein, The interrupt processing module stores the information that needs to be cached into a first storage area of the storage unit before the interrupt service starts, and stores the information that needs to be cached into a second storage area of the storage unit during the interrupt service, The first storage area and the second storage area are distributed in the storage unit without overlapping.

10. The processing device according to any one of claims 1 to 9, characterized in that, The plurality of registers are general registers configured as caller-save attributes.

11. A processing system for interrupt handling, characterized by The processing device comprises: The processing device according to any one of claims 1 to 10; And The memory is coupled to the processing device and is adapted to provide the storage unit and at least one interrupt service routine, and the processing device implements the corresponding interrupt service by running one of the at least one interrupt service routine.

12. The processing system of claim 11, wherein, The memory is further adapted to provide one or more decision data, each of which is associated with a corresponding interrupt service and / or application, so that the processing device obtains the corresponding decision data according to the interrupt request that needs to be responded.

13. The processing system of claim 12, wherein, The processing system is implemented in a system on chip.

14. A processing method for interrupt processing, characterized by, The processing device comprises: Providing decision data corresponding to an interrupt request, the register save list represented by the decision data is used to designate one or more registers of a plurality of registers as live registers corresponding to the interrupt request, and the register save list is set respectively for different interrupt services; Responding to the interrupt request to provide a corresponding interrupt service; And Based on the list of registers operated in the response process, one or more registers designated by the list are designated as live registers corresponding to the interrupt request; The step of responding to the interrupt request to provide a corresponding interrupt service comprises: During the interrupt service, if one of the plurality of registers needs to be operated and the information stored in the register is not cached, the information stored in the register is cached before the operation is performed, and if a plurality of interrupt requests need to be processed continuously, the register cache information of the previous interrupt service is directly inherited by the subsequent interrupt service between the execution processes of adjacent two interrupt service routines.

15. The processing method according to claim 14, characterized in that, The step of responding to the interrupt request to provide a corresponding interrupt service further comprises: storing information of each live save register designated by the decision data before the interrupt service starts; restoring the plurality of registers to a state before the interrupt service using the stored information after the interrupt service is completed.

16. The processing method according to claim 15, wherein The step of designating one or more registers of the list of registers operated during the responding as live save registers corresponding to the interrupt request comprises: collecting training data corresponding to the interrupt service; and adjusting the decision data corresponding to the interrupt service according to the training data, The training data comprises information of a list of registers to be restored when the interrupt service is completed, and / or a list of registers operated during the interrupt service, so that the adjusted decision data designates each register indicated by the training data as a live save register corresponding to the interrupt service.

17. The treatment method of claim 16, wherein, The step of adjusting the decision data corresponding to the interrupt service according to the training data comprises: deleting from the list of registers designated by the decision data live save registers not operated during the interrupt service and / or live registers not to be restored when the interrupt service is completed according to the training data.

18. The processing method of claim 16, wherein, The step of responding to the interrupt request to provide a corresponding interrupt service further comprises: corresponding to a current interrupt service, the decision data is in an initial state without collecting the training data, In the initial state, the number of live save registers designated by the decision data is zero or less than the total number of the plurality of registers.

19. The processing method of claim 15, wherein, The step of responding to the interrupt request to provide a corresponding interrupt service further comprises: During the interrupt service responding to the current interrupt request, if the interrupt handling module needs to handle another interrupt request with a higher priority than the current interrupt request, the decision data corresponding to the another interrupt request is provided so that a responding process for the another interrupt request is nested executed based on the decision data during the responding process of the current interrupt request.

20. The processing method of claim 15, wherein, The step of responding to the interrupt request to provide a corresponding interrupt service further comprises: In a case that the current interrupt service has ended and the plurality of registers are not completely restored to a state before the interrupt service, if a next interrupt service needs to be processed, the contents of the registers are not restored and stored before the next interrupt service is provided, so that the plurality of registers are restored to a state before the current interrupt service starts using information stored before the current interrupt service starts after the next interrupt service ends.

21. A computer readable medium storing computer instructions, which when executed, implement the processing method of any one of claims 14 to 20.

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