Clock tree correction device and correction method thereof

Abstract

A clock tree correction device and a correction method thereof are provided. The clock tree correction method includes: performing a frequency signal path tracing operation on a network link list of a circuit according to time limit information to obtain a clock tree circuit structure; identifying a bus state of the clock tree circuit structure to find at least one frequency bus point, and setting one of a plurality of frequency signals on the frequency bus point as a selected frequency signal; performing a correction point identification operation on the clock tree circuit structure based on the selected frequency signal to obtain a plurality of candidate correction points; and respectively calculating a plurality of weight values of the candidate correction points, and obtaining a plurality of selected correction points according to the weight values.

Description

Technical Field

[0001] The present invention relates to a clock tree correction device and a correction method thereof, and more particularly to a correction device that can automatically execute a clock tree correction method. Background Art

[0002] In the field of circuit design, the pre-correction action (clock prefix) of the clock tree is a necessary operation for using the functional clock signal as a scan clock signal to perform the clock scan action. In a circuit with a complex clock structure, this pre-correction action will take a lot of time for the designer and reduce the design efficiency.

[0003] Existing Electronic Design Automation (EDA) software often inserts multiple multiplexers into the circuit so that the clock signal can be transmitted to the inside of the circuit through these externally inserted multiplexers. Such a method often causes a burden when performing Clock Tree Synthesis (CTS) and significantly increases the area of the circuit. Summary of the Invention

[0004] The present invention is directed to a clock tree correction method device and a correction method, which can automatically and quickly perform a pre-correction (prefix) action on the clock tree.

[0005] According to an embodiment of the present invention, the clock tree correction method includes: performing a clock signal path tracing action on the network connection list of the circuit according to time limit information to obtain a clock tree circuit structure; identifying the convergence state of the clock tree circuit structure to find at least one clock convergence point, and setting one of the multiple clock signals on the clock convergence point as the selected clock signal; based on the selected clock signal, performing a correction point identification action on the clock tree circuit structure to obtain a plurality of candidate correction points; and respectively calculating a plurality of weight values of the candidate correction points, and obtaining a plurality of selected correction points according to the weight values.

[0006] According to an embodiment of the present invention, a clock tree correction device for a circuit includes a storage element and a controller. The storage element stores time limit information and the network connection list of the circuit. The controller is coupled to the storage element for executing the clock tree correction method as described above.

[0007] According to the above, the clock tree correction method of the present invention obtains a clock tree circuit structure through a clock signal path tracing action, identifies candidate correction points in the clock tree circuit structure, sets a plurality of weight values for the candidate correction points, and obtains a plurality of selected correction points according to the weight values. In this way, the selected correction points can be generated quickly and automatically, improving the efficiency of design analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0009] Figure 1 A flowchart showing a method for correcting a clock tree according to an embodiment of the present invention;

[0010] Figure 2 A flowchart showing a method for correcting a clock tree according to another embodiment of the present invention;

[0011] Figure 3 A schematic diagram showing the circuit structure of a clock tree according to an embodiment of the present invention;

[0012] Figure 4 A schematic diagram showing a clock sink point according to an embodiment of the present invention;

[0013] Figure 5 A schematic diagram showing the circuit structure of a clock tree and its correction points according to an embodiment of the present invention;

[0014] Figure 6 A schematic diagram showing a method for generating multiple candidate correction points according to an embodiment of the present invention;

[0015] Figures 7A to 7C A schematic diagram showing a method for setting the weights of candidate correction points;

[0016] Figure 8A 、 Figure 8B A schematic diagram showing a method for selecting a selected correction point;

[0017] Figure 9 A schematic diagram showing a clock tree correction device according to an embodiment of the present invention.

[0018] REFERENCE NUMERAL DESCRIPTION

[0019] 300, 400, 500: Clock tree circuit structure;

[0020] 610, 620, 630: Solution meaning tree structure;

[0021] 900: Clock tree correction device;

[0022] 910: Controller;

[0023] 920: Storage element;

[0024] AN1, AN2, AN3, AN4, AN41, AN42: AND gate;

[0025] CL11, CL12, CL21, CL22, CL23: combinational logic circuits;

[0026] clk, clk1, clk2: clock signals;

[0027] ICG1, ICG2, ICG: clock isolation gates;

[0028] IE1 to IE3, P1 to P3, A, B, C, D, E, F, G, H, I, J1, J2, J3, K, L: input terminals;

[0029] IF1: network link list;

[0030] IF2: time limit information;

[0031] J, M, N, O: output terminals;

[0032] LC1: logic component;

[0033] MUX1, MUX41: multiplexers;

[0034] ND11 to ND39: candidate correction points;

[0035] OR1, OR2: OR gates;

[0036] S110 to S140, S210 to S250: correction steps of clock tree;

[0037] SE: source;

[0038] W11 to W39: weight values. Detailed implementation manners

[0039] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0040] Please refer to Figure 1 , Figure 1Flowchart showing a method for correcting a clock tree according to an embodiment of the present invention. In step S110, a clock signal path tracing operation is performed on the netlist of the circuit according to the timing constraint information, and a clock tree circuit structure is obtained through the clock signal path tracing operation. Then, in step S120, the convergence state of the clock tree circuit structure obtained in step S110 can be identified to find one or more clock convergence points, and one of the multiple clock signals on the clock convergence point is set as the selected clock signal. Here, it should be noted that in circuit design, there may be multiple clock signals in a clock tree circuit structure. Step S120 is used to identify the clock convergence points of these clock signals. Here, the designer can select one of the above multiple clock signals as the selected clock signal.

[0041] Incidentally, in this embodiment, the clock convergence point of the clock signal often occurs on a circuit component that is a multiplexer.

[0042] In step S130, based on the above selected clock signal, a correction point identification operation is performed on the clock tree circuit structure, and a plurality of candidate correction points are obtained. Here, this embodiment can analyze a plurality of circuit components associated with the selected clock signal in the clock tree circuit structure, and set these circuit elements (logic gates) as a plurality of candidate correction points.

[0043] In step S140, weight values are set and calculated for the above plurality of candidate correction points, and a plurality of selected correction points are obtained based on the weight values of the candidate correction points. Corresponding to the selected correction points, the designer can modify the logical expression so that the logical value on the selected correction point is sufficient to enable the selected clock signal to be successfully transmitted in the clock tree circuit structure, and the functional clock path can be used as the scan clock path.

[0044] Please refer to the following Figure 2 , Figure 2 Flowchart showing a method for correcting a clock tree according to another embodiment of the present invention. In step S210, the netlist IF1 of the circuit and the timing constraint information IF2 are received, and a clock path tracing operation is performed accordingly. Please refer to Figure 2 and Figure 3 simultaneously, where Figure 3Schematic diagram showing the clock tree circuit structure according to an embodiment of the present invention. Among them, when performing the action of clock path tracing, the clock signal clk in the circuit can be found, and the tracing action can be performed according to the transmission direction of the clock signal clk. During the tracing action, the circuit components between the transmission paths of the clock signal clk can be recorded. In Figure 3 , the clock signal clk is received by the AND gate AN1 and sequentially transmitted along the multiplexer MUX1, the AND gate AN2, and the logic component LC1. It should be noted that the action of clock path tracing of the clock signal clk starts from the source SE of the clock signal clk and ends at the isolation clock gates (ICG) ICG1 and ICG2 in the path. In this embodiment, the isolation clock gates ICG1 and ICG2 can be D-type flip-flops. In Figure 3 , by recording the connection relationship of the AND gate AN1, the multiplexer MUX1, the AND gate AN2, and the logic component LC1, the clock tree circuit structure 300 corresponding to the clock signal clk can be established.

[0045] It is worth mentioning that in the embodiment of the present invention, the input logic values can be recorded in multiple circuit components of the clock tree circuit structure 300 so that the clock signal clk can be transmitted smoothly. Taking the embodiment of Figure 3 as an example, one input terminal of the AND gate AN1 receives the clock signal clk, and the other input terminal of the AND gate AN1 must be set to the logic value 1 so that the clock signal clk can be transmitted to the output terminal of the AND gate AN1. Similarly, based on the input terminal of the multiplexer MUX1 corresponding to the selection signal being the logic value 0 being coupled to the output terminal of the AND gate AN1, the input terminal of the multiplexer MUX1 should be set to the logic value. The first input terminal of the AND gate AN2 is coupled to the output terminal of the multiplexer MUX1. Therefore, the second input terminal of the AND gate AN2 must be set to the logic value.

[0046] Of course, Figure 3 the components and structures included in the clock tree circuit structure 300 in

[0047] are only illustrative examples and are not used to limit the scope of the present invention. Figure 2 Please refer back to Figure 2 and Figure 4 . Then, in step S220, the action of identifying the clock convergence point of the clock tree circuit structure is performed. Please synchronously refer to Figure 4 and Figure 4 which shows the schematic diagram of the clock convergence point according to an embodiment of the present invention. In the embodiment of the present invention, the clock convergence point often occurs in the multiplexer in the clock tree circuit structure. In Figure 4In the clock tree circuit structure 400, there are multiple clock signals clk1 and clk2. Moreover, the multiplexer MUX41 receives the clock signals clk1 and clk2 through the AND gates AN41 and AN42 respectively. Here, the multiplexer MUX41 can be recognized as a clock convergence point. When the clock convergence point (multiplexer MUX41) is recognized, the designer can select one of the clock signals clk1 and clk2 as the selected clock signal. In this embodiment, taking the clock signal clk1 being selected as the selected clock signal as an example, the selection terminal of the multiplexer MUX can be set to the logical value 0 so that the clock signal clk1 can be smoothly transmitted. In other parts, the input terminal of the AND gate AN41 that does not receive the clock signal clk1 is set to the logical value 1; the input terminal of the AND gate AN42 that does not receive the clock signal clk2 is set to the logical value 1, and the input terminal of the AND gate AN43 that is not coupled to the input terminal of the multiplexer MUX41 can be set to the logical value 1. In addition, the clock isolation gate ICG can be the termination point of the clock tree circuit structure 400.

[0048] Refer back to Figure 2 , after the logical values of the clock tree circuit structure and all input terminals are set, the correction point identification operation of the clock tree circuit structure can be performed. Please refer to Figure 5 , Figure 5 FIG. shows the clock tree circuit structure of an embodiment of the present invention and a schematic diagram of its correction points. The clock tree circuit structure 500 is generated based on Figure 3 the clock tree circuit structure 300 and multiple surrounding control logic circuits thereof. The clock tree circuit structure 500 has multiple input terminals IE1 to IE3 for controlling the clock signal clk1. The input terminals IE1 to IE3 respectively correspond to the AND gate AN1, the multiplexer MUX1, and the AND gate AN2. The logical values set for the input terminals IE1 to IE3 are the logical values 1, 0, and 1 respectively.

[0049] In addition, the input terminal IE1 is controlled by the OR gate OR1 and the combinational logic circuits CL11 and CL12; the input terminal IE2 is controlled by the AND gate AN3 and the combinational logic circuits CL21 and CL22; the input terminal IE3 is controlled by the combinational logic circuit CL23. In this embodiment, multiple input terminals and output terminals of the above OR gate OR1, combinational logic circuits CL11, CL12, AND gate AN3, combinational logic circuits CL21, CL22, and combinational logic circuit CL23 can be respectively set as multiple candidate correction points.

[0050] Next, refer back to Figure 2, in step S230, a fixed value is set in the node, that is, a logical value that can effectively transmit the clock signal clk is set on the above-mentioned multiple circuit components set as candidate correction points. Specifically, the output terminal of the OR gate OR1 is set to the logical value 1 (equal to the logical value of the input terminal IE1), and at least one of the two input terminals of the OR gate OR1 is set to the logical value 1. The output terminal of the AND gate AN3 is set to the logical value 0 (equal to the logical value of the input terminal IE2), and at least one of the input terminals of the AND gate AN3 needs to be set to the logical value 0. The output terminal of the combinational logic circuit CL3 needs to be set to the logical value 1 (equal to the logical value of the input terminal IE3).

[0051] Next, in step S240, a plurality of weight values are respectively set for the candidate correction points, and in step S250, a plurality of selected correction points are selected from the plurality of candidate correction points according to the weight values.

[0052] For the implementation details of steps S240 and S250, please refer to Figures 6 to 8B . Among them, Figure 6 A schematic diagram showing the generation method of a plurality of candidate correction points according to an embodiment of the present invention, Figures 7A to 7C A schematic diagram showing the weight setting method of the candidate correction points, Figure 8A , Figure 8B Then it shows a schematic diagram of the selection method of the selected correction points.

[0053] In Figure 6 , the clock tree circuit structure 600 corresponds to the clock signal clk and includes AND gates AN1, AN2, and multiplexer MUX1. The input terminals P1, P2, and P3 of the AND gates AN1, multiplexer MUX1, and AND gate AN2 are respectively set to the logical values 1, 0, and 1. Corresponding to the input terminal P1, the OR gate OR1, AND gates AN3, and AN4 serve as control logic circuits and can be used to control the logical value of the input terminal P1. Based on the input terminal P1 being set to the logical value 1, the output terminal M of the OR gate OR1 is set to the logical value 1; the input terminals I, J1 (equivalent to the output terminal J of the AND gate AN4) of the OR gate OR1 can both be set to the logical value 1; the input terminals A, B of the AND gate AN3 are both set to the logical value 1; the input terminals C, D of the AND gate AN4 are both set to the logical value 1.

[0054] In addition, based on the input terminal P2 being set to the logical value 0, the output terminal N of the OR gate OR2 is set to the logical value 0; the input terminals J2 (equivalent to the output terminal J of the AND gate AN4), K (equivalent to the output terminal of the AND gate AN5) of the OR gate OR2 can both be set to the logical value 0; the input terminals E, F of the AND gate AN5 can both be set to the logical value 0; the input terminals C, D of the AND gate AN4 are both set to the logical value 0.

[0055] Based on the input terminal P3 being set to the logical value 1, the output terminal O of the OR gate OR3 is set to the logical value 1; the input terminals J3 (equivalent to the output terminal J of the AND gate AN4) and L (equivalent to the output terminal of the AND gate AN6) of the OR gate OR3 can both be set to the logical value 1; the input terminals G and H of the AND gate AN6 can both be set to the logical value 1; the input terminals C and D of the AND gate AN4 are both set to the logical value 1.

[0056] According to the settings of the logical values of the above endpoints, the solution meaning tree structures 610, 620, and 630 can be respectively established corresponding to the input terminals P1, P2, and P3. The solution meaning tree structures 610, 620, and 630 include tree-like structures formed by multiple candidate correction points corresponding to the input terminals P1, P2, and P3 respectively.

[0057] Here, it should be noted that in the embodiment of the present invention, binary integer linear programming or a heuristic algorithm can be applied to obtain the selected correction points from the solution meaning tree structures 610, 620, and 630. The following presents an implementation example to illustrate the method of obtaining the selected correction points.

[0058] In Figure 7A , for the solution meaning tree structure 610, the multiple endpoints therein and the corresponding set logical values can be analyzed, and weight values are applied to each candidate correction point in the solution meaning tree structure 610. In terms of the weight value setting method, a candidate correction point in the solution meaning tree structure 610 can be selected as the parent node, and based on the type of logic circuit corresponding to this parent node and the weight value of this parent node, the weight values of the multiple child nodes of this parent node are set. First, the candidate correction point ND11 can be set as the parent node, and the weight value W11 of the candidate correction point ND11 is set to 1. Since the candidate correction point ND11 has only one child node (the candidate correction point ND12), the weight value W12 of the candidate correction point ND12 is the same as the weight value W11 of the candidate correction point ND11 (=1). Then, since the candidate correction point ND12 corresponds to the output terminal M of the OR gate OR1, when the candidate correction point ND12 is the parent node, the weight values W13 and W14 of its child nodes (the candidate correction points ND13 and ND14) can be the same as the weight value W12 of the candidate correction point ND2 (=1). In addition, when the candidate correction point ND13 is the parent node, based on the candidate correction point ND13 corresponding to the output terminal I of the AND gate AN3. Therefore, the weight value W13 of the candidate correction point ND13 can be evenly distributed to its child nodes (the candidate correction points ND15 and ND16), and the weight values W15 and W16 of the candidate correction points ND15 and ND16 are both equal to 0.5.

[0059] By analogy with the above method, the weight values W11 to W19 of all candidate correction points ND11 to ND19 can be calculated.

[0060] In addition, in Figure 7B , according to the same method as Figure 7A , the weight values W21 to W29 can be respectively set for the candidate correction points ND21 to ND29 in the solution meaning tree structure 620. Similarly, in Figure 7C , the weight values W31 to W39 can also be effectively set for the candidate correction points ND31 to ND39 in the solution meaning tree structure 630.

[0061] Next, in the embodiment of the present invention, the weight values W11 to W39 corresponding to all candidate correction points ND11 to ND39 can be sorted out, and the candidate correction points with the same end points and the same set logical values are subjected to the operation of adding the weight values, and Figure 8A can be obtained. It should be noted here that Figure 7A the candidate correction point ND17 in and Figure 7C the candidate correction point ND37 in correspond to the same output terminal J and are set with the same logical value 1. Therefore, the weight values W17 and W37 of the candidate correction point ND17 and the candidate correction point ND37 can be added, and a weight value (=2) corresponding to J = 1 is generated.

[0062] From Figure 8A it can be found that the candidate correction points corresponding to J = 1 have the highest weight value. Therefore, the candidate correction points of J = 1 can be selected first as the first selected correction points.

[0063] Next, in Figure 8B , based on the fact that the candidate correction points of J = 1 have been selected, all candidate correction points related to the solution meaning tree structures 610 and 630 are deleted. At this time, the candidate correction points corresponding to N = 0 have the highest weight value (=1). Therefore, the candidate correction points corresponding to N = 0 are selected as the second selected correction points.

[0064] Furthermore, it can be known through the clock tree correction method of the embodiment of the present invention that only by controlling the output of the output terminal J of the AND gate AN4 in the clock tree circuit structure 600 of Figure 6 to be logic 1, the inputs P1 and P3 can be controlled to be logic 1, and by controlling the output terminal N of the OR gate OR2 in the clock tree circuit structure 600 of Figure 6 to generate logic 0, the input P2 can be controlled to be logic 0. In this way, the clock signal clk can be effectively transmitted. The embodiment of the present invention completes the clock tree correction action through an automatic and fast method.

[0065] Please refer to Figure 9 below.Figure 9 Schematic diagram showing a clock tree correction device according to an embodiment of the present invention. The clock tree correction device 900 includes a controller 910 and a storage element 920. The controller 910 and the storage element 920 are coupled to each other. Among them, the storage element 920 can be used to store the time limit information of the circuit and the network link table. The controller 910 can read the time limit information of the circuit and the network link table from the storage element 920, and execute as follows according to the time limit information of the circuit and the network link table Figure 1 , Figure 2 the clock tree correction method shown.

[0066] Regarding the execution details of the clock tree correction method, they have been described in detail in the foregoing embodiments, and will not be elaborated here.

[0067] In this embodiment, the storage element 920 can also be used to store the temporary data generated during the calculation process of the controller 910. In terms of the hardware architecture, the controller 910 can be a processor with computing capabilities. Alternatively, the controller 910 can be designed by a hardware description language (HDL) or any other design method of digital circuits well-known to those skilled in the art, and implemented in the form of a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or an application-specific integrated circuit (ASIC). In addition, the storage component 920 can be various random access memories (RAMs), read-only memories (ROMs), etc., but not limited thereto.

[0068] In summary, the present invention identifies multiple candidate correction points in the clock tree circuit structure, sets multiple weight values for the candidate correction points, and then finds the selected correction points according to the weight values. In this way, the correction action of the clock tree of the circuit can be quickly and automatically found, improving the efficiency of circuit design.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for correcting a clock tree, comprising: Performing a clock signal path tracing operation on a network link list of a circuit according to time limit information to obtain a clock tree circuit structure; Identifying a bus state of the clock tree circuit structure to find at least one clock bus point, and setting one of a plurality of clock signals on the at least one clock bus point as a selected clock signal; Based on the selected clock signal, performing a correction point identification operation on the clock tree circuit structure to obtain a plurality of candidate correction points; And Respectively calculating a plurality of weight values of the plurality of candidate correction points, and obtaining a plurality of selected correction points according to the plurality of weight values.

2. The method for correcting a clock tree according to claim 1, wherein the step of respectively calculating a plurality of weight values of the plurality of candidate correction points and obtaining the plurality of selected correction points according to the plurality of weight values comprises: Respectively establishing a plurality of solution meaning tree structures for the plurality of candidate correction points; And Performing a binary integer tree linear programming or a heuristic algorithm on the plurality of solution meaning tree structures to obtain the plurality of selected correction points.

3. The method for correcting a clock tree according to claim 2, wherein the step of respectively calculating the plurality of weight values of the plurality of candidate correction points comprises: Setting each of the candidate correction points as a parent node, and setting weight values of a plurality of child nodes of the parent node according to a logic circuit type corresponding to the parent node and a weight value of the parent node.

4. The method for correcting a clock tree according to claim 3, wherein when the logic circuit corresponding to the parent node is an AND gate, a sum of the weight values of the plurality of child nodes is equal to the weight value of the parent node, and when the logic circuit corresponding to the parent node is an OR gate or a buffer, the weight value of each child node is equal to the weight value of the parent node.

5. The method for correcting a clock tree according to claim 1, wherein the step of obtaining the plurality of selected correction points according to the plurality of weight values comprises: Selecting the largest one of the plurality of weight values to generate a selected weight value, and setting a candidate correction point corresponding to the selected weight value as a first selected node; And Removing at least one associated candidate correction point associated with the first selected node, and selecting the one with the largest weight value among the remaining plurality of candidate correction points as a second selected node.

6. The method for correcting a clock tree according to claim 1, wherein in the step of performing the clock signal path tracing operation on the network link list of the circuit according to the time limit information to obtain the clock tree circuit structure, it includes: Based on a clock signal, finding a plurality of circuit components on a transmission path of the clock signal; And Marking a plurality of logic signals on the plurality of circuit components that can enable the clock signal to be transmitted smoothly.

7. The method for correcting a clock tree according to claim 1, wherein after the step of setting one of the plurality of clock signals on the at least one clock bus point as the selected clock signal, it further includes: Marking a logic signal on the at least one clock bus point that can enable the selected clock signal to be transmitted.

8. A correction device for a clock tree of a circuit, comprising: A storage element, a storage time limit information needle, and a network link table of the circuit; And A controller, coupled to the storage element, for: Performing a clock signal path tracing operation on the network link table according to the time limit information to obtain the clock tree circuit structure; Identifying the convergence state of the clock tree circuit structure to find at least one clock convergence point, and setting one of the multiple clock signals on the at least one clock convergence point as a selected clock signal; Based on the selected clock signal, performing a correction point identification operation on the clock tree circuit structure to obtain multiple candidate correction points; And Calculating the weight values of the multiple candidate correction points respectively, and obtaining multiple selected correction points according to the multiple weight values.

9. The clock tree correction device according to claim 8, wherein the controller respectively establishes multiple solution meaning tree structures for the multiple candidate correction points, and performs binary integer tree linear programming or a heuristic algorithm on the multiple solution meaning tree structures to obtain the multiple selected correction points.

10. The clock tree correction device according to claim 8, wherein the controller is used for: Setting each of the candidate correction points as a parent node, and setting the weight values of the multiple child nodes of the parent node according to the type of the logic circuit corresponding to the parent node and the weight value of the parent node; Selecting the one with the largest of the multiple weight values to generate a selected weight value, and setting the candidate correction point corresponding to the selected weight value as a first selected node; And Removing at least one associated candidate correction point associated with the first selected node, and selecting the one with the largest weight value among the multiple remaining candidate correction points as a second selected node.

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